Non-operational amplifier band-gap reference for high-order temperature compensation of power supply chip

Abstract

The invention discloses an operational amplifier-free band-gap reference for high-order temperature compensation of a power supply chip, which belongs to the field of integrated circuits and comprises a band-gap reference core circuit, a high-order compensation circuit and a pre-adjustment circuit. The clamping effect of emitter junctions of the NPN triodes Q1 and Q3 is adopted to realize equal voltage drop of the resistors R3 and R4, and the clamping precision of the emitter junctions of the triodes is improved by adopting a feedback system and a self-biasing circuit technology, so that a first-order band-gap reference voltage is generated; temperature nonlinearity of first-order band-gap reference voltage is compensated by temperature nonlinearity current provided by PMOS (P-channel Metal Oxide Semiconductor) tubes M14 and M16 working in a sub-threshold region, low-temperature-drift band-gap reference voltage is realized, and a working power supply is provided for a band-gap reference core circuit and a high-order compensation circuit by a PMOS tube M23 of a pre-adjusting circuit. Therefore, the band-gap reference voltage with high power supply rejection ratio and low temperature drift is obtained, and the operational amplifier-free band-gap reference for high-order temperature compensation of a power supply chip is realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an op-amp-free bandgap reference for high-order temperature compensation of power supply chips. Background Technology

[0002] With the rapid development of portable electronic products, power supply chips are gradually evolving towards higher efficiency and lower power consumption. As one of the key circuits in a power supply chip, the bandgap reference provides a precise bias signal for the chip's functional modules, and its performance characteristics directly affect the overall performance of the power supply chip. With the advancement of integrated circuit technology, the performance requirements for the internal bandgap reference circuit of power supply chips are becoming increasingly stringent.

[0003] Figure 1 This is a traditional bandgap reference circuit structure. PMOS transistors M1, M2, and M3 are identical. The low-frequency gain A of amplifier A1 is... d There is A d >>1. The emitter area of ​​PNP transistor Q2 is N times that of PNP transistor Q1. Resistors R1 and R2 are made of the same material. Then the output voltage V of the bandgap reference circuit is... ref for Among them, V EB3 This is the emitter-base voltage of the PNP transistor Q3. R1 is the impedance of resistor R1, R2 is the impedance of resistor R2, q is the electron charge, k is the Boltzmann constant, and T is the absolute temperature. By optimizing the values ​​of resistors R1 and R2 and parameter N, a voltage with low temperature drift can be obtained. However, this reference voltage VREF is a first-order bandgap reference voltage, exhibiting high temperature drift characteristics, which limits the application of bandgap reference source circuits in high-performance power supply chips. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above, and proposes an op-amp-free bandgap reference for high-order temperature compensation in power supply chips. The technical solution of this invention is as follows:

[0005] An op-amp-less bandgap reference for high-order temperature compensation in power supply chips includes: a bandgap reference core circuit, a high-order compensation circuit, and a pre-adjustment circuit. The signal output terminal of the bandgap reference core circuit is connected to the signal input terminals of both the high-order compensation circuit and the pre-adjustment circuit. The signal output terminal of the high-order compensation circuit is connected to the signal input terminal of the bandgap reference core circuit. The signal output terminal of the pre-adjustment circuit is also connected to both the signal input terminals of the bandgap reference core circuit and the high-order compensation circuit. The bandgap reference core circuit uses the clamping effect of the emitter junctions of two NPN transistors to achieve equal voltages at the two nodes. A feedback system and a self-biasing circuit are used to improve the clamping accuracy of the NPN transistor emitter junctions, thereby providing a first-order bandgap reference voltage V at the circuit output. REF1 The higher-order compensation circuit utilizes the higher-order temperature nonlinear current I provided by PMOS transistors M14 and M16. 14 and I 16 For the first-order bandgap reference voltage V REF1 The high-order temperature nonlinearity is compensated by the pre-adjustment circuit, which provides the operating power supply voltage for the bandgap reference core circuit and the high-order compensation circuit, thereby obtaining a bandgap reference voltage with high power supply rejection ratio and low temperature drift.

[0006] Furthermore, the core circuit of the bandgap reference includes: NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9; NPN transistors Q1, Q2, Q3, Q4, and Q5; resistors R1, R2, R3, R4, R5, R6, and R7; and capacitor C1. The source of PMOS transistor M8 is connected to the source of PMOS transistor M9, the source of PMOS transistor M4, the drain of NMOS transistor M1, the source of PMOS transistor M5, the source of PMOS transistor M10, and P... The source of MOSFET M11, the source of PMOS transistor M18, the drain of PMOS transistor M23, and the drain of NMOS transistor M19 are connected. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M6, the gate of NMOS transistor M6, and the gate of NMOS transistor M7. The source of NMOS transistor M6 is connected to the source of NMOS transistor M7, one end of resistor R6, the emitter of NPN transistor Q1, one end of resistor R2, the emitter of NPN transistor Q3, and external ground GND. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M12, the gate of PMOS transistor M13, and the drain of NMOS transistor M19. The drain of OS transistor M7 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M2. The drain of PMOS transistor M2 is connected to the collector of NPN transistor Q4, the gate of PMOS transistor M8, the gate of PMOS transistor M4, the gate of PMOS transistor M5, the gate of PMOS transistor M10, the gate of PMOS transistor M11, and the drain of NMOS transistor M36. The emitter of NPN transistor Q4 is connected to the other end of resistor R6, the gate of PMOS transistor M15, and the gate of PMOS transistor M16. The source of NMOS transistor M1 is connected to one end of resistor R5, one end of resistor R10, the gate of PMOS transistor M18, the gate of NMOS transistor M34, and the circuit output terminal VREF. The resistors are connected in series: the other end of resistor R5 is connected to the base of NPN transistor Q4, one end of resistor R3, one end of resistor R4, the base of NPN transistor Q5, the drain of PMOS transistor M14, and the drain of PMOS transistor M16; the other end of resistor R3 is connected to one end of resistor R1 and the base of NPN transistor Q1; the other end of resistor R1 is connected to the base of NPN transistor Q2 and the collector of NPN transistor Q1; the other end of resistor R4 is connected to the base of NPN transistor Q3, one end of capacitor C1, and the collector of NPN transistor Q2; the emitter of NPN transistor Q2 is connected to the other end of resistor R2; and the drain of PMOS transistor M5 is connected to the source of PMOS transistor M3.The drain of PMOS transistor M3 is connected to the gate of NMOS transistor M1, the other end of capacitor C1, and the collector of NPN transistor Q5. The emitter of NPN transistor Q5 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the collector of NPN transistor Q3.

[0007] Furthermore, the higher-order compensation circuit includes: PMOS transistors M10, M11, M12, M13, M14, M15, M16, and M17; resistors R8, R9, and R10; wherein the drain of PMOS transistor M10 is connected to the source of PMOS transistor M12; the drain of PMOS transistor M12 is connected to the sources of PMOS transistors M14 and M15, respectively; and PMOS transistor M17... The gate of S-MOSFET M14 is connected to the other end of resistor R10 and one end of resistor R9. The other end of resistor R9 is connected to one end of resistor R8 and the gate of PMOS transistor M17. The other end of resistor R8 is connected to the drain of PMOS transistor M15, the drain of PMOS transistor M17, and external ground GND. The drain of PMOS transistor M11 is connected to the source of PMOS transistor M13. The drain of PMOS transistor M13 is connected to the source of PMOS transistor M16 and the source of PMOS transistor M17.

[0008] Furthermore, the pre-adjustment circuit includes: PMOS transistors M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, and M36, and resistor R11, wherein the source of PMOS transistor M23 is connected to the source of PMOS transistor M24, P19, M20, M21, M22, M33, M34, M35, and M36, respectively, and resistor R11. The source of transistor M25, the source of PMOS transistors M26, M27, and M32, and the external power supply VDD are connected. The drain of PMOS transistor M18 is connected to the gate of NMOS transistor M19 and the drain of NMOS transistor M20. The source of NMOS transistor M20 is connected to the sources of NMOS transistors M19, M21, and M22, one end of resistor R11, the sources of NMOS transistors M31, M36, M35, and M34, and the external ground GND. PMOS transistor M24... The drain of PMOS transistor M25 is connected to the gates of PMOS transistors M24, M23, and M21, respectively. The drain of PMOS transistor M25 is connected to the gates of NMOS transistors M20, M21, M22, and M22, respectively. The drain of PMOS transistor M26 is connected to the gates of PMOS transistors M25, M26, M27, M35, and M28, respectively. The source of NMOS transistor M28 is connected to the drain of NMOS transistor M30, and the source of NMOS transistor M30 is connected to... The other end of resistor R11 is connected to the drain of PMOS transistor M27, which is connected to the gate of NMOS transistor M28, the gate of NMOS transistor M29, and the drain of NMOS transistor M29. The source of NMOS transistor M29 is connected to the gate of NMOS transistor M30, the gate of NMOS transistor M31, and the drain of NMOS transistor M31. The gate of PMOS transistor M32 is connected to the drain of PMOS transistor M32 and the source of PMOS transistor M33. The drain of PMOS transistor M33 is connected to the gate of PMOS transistor M33, the gate of NMOS transistor M35, the gate of NMOS transistor M36, and the drain of NMOS transistor M34.

[0009] Furthermore, in the core bandgap reference circuit, the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 ensures that the voltage drops of resistors R3 and R4 are equal. A feedback system composed of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a self-biasing circuit composed of resistor R6, NPN transistor Q4, PMOS transistors M2, M4, M9, M8, NMOS transistors M6, and M7 are used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without operational amplifiers. Resistors R3, R4, and R6 are identical, as are NPN transistors Q1, Q3, and Q4. The current amplification factor β of all NPN transistors is much greater than 1, and the base current of all NPN transistors is negligible. Therefore, the base-emitter voltage V of NPN transistor Q1 is... BE1 The base-emitter voltage V of NPN transistor Q4 BE4 have Among them, I S V is the saturation current of the transistor. T Let V be the thermal voltage, R3 be the resistance of resistor R3, and R6 be the resistance of resistor R6. Since resistors R3 and R6 have the same resistance, then by optimizing the circuit, V = ... BE1 =V BE4 The current I flowing through resistor R3 is thus increased. R3 With the current I flowing through resistor R6 R6 There is I R3 =I R6 PMOS transistors M2, M3, M4, and M5 form a common-source, common-gate current mirror. PMOS transistors M4 and M5 are identical, and PMOS transistors M2 and M3 are identical. Therefore, NPN transistors Q3 and Q4 have the same collector current, and consequently, the base-emitter voltage V of NPN transistor Q3 is the same. BE3 V BE3 =V BE4 =V BE1 Resistors R3 and R4 are identical. The emitter area of ​​NPN transistor Q2 is m times that of NPN transistor Q1. Then the current I flowing through resistor R3 is... R3 With the current I flowing through resistor R4 R4 The voltage V generated at the circuit output terminal VREF REF1 for Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, R5 is the resistance of resistor R5, k is Boltzmann's constant, q is the electron charge, T is the absolute temperature, and the factor VBE1 It has negative temperature characteristics, factor It has a positive temperature characteristic, therefore, by optimizing the circuit parameters, the voltage V can be made... REF1 This is the reference voltage for first-order temperature compensation.

[0010] Furthermore, in the higher-order compensation circuit, PMOS transistors M14, M15, M16, and M17 all operate in the subthreshold region, and the gate voltage V of PMOS transistor M15... G15 The gate voltage V of PMOS transistor M16 G16 And the voltage drop V across resistor R6 R6 V G15 =V G16 =V R6 And the gate voltage V of PMOS transistor M15 G15 With the gate voltage V of PMOS transistor M16 G16 Increases with increasing temperature; Gate voltage V of PMOS transistor M14 G14 The gate voltage V of PMOS transistor M17 G17 Provided by the circuit output terminal VREF, the gate voltage V of PMOS transistor M14 is... G14 With the gate voltage V of PMOS transistor M17 G17 The voltage is independent of temperature T. The gate voltage V of PMOS transistor M14. G14 With the gate voltage V of PMOS transistor M17 G17 V G14 >>V R6 >>V G17 Then the drain current I of PMOS transistor M14 14 and the current I of PMOS transistor M16 16 They are respectively and Among them, I 10 I is the drain current of PMOS transistor M10, η is the non-ideal factor for the MOS transistor operating in the subthreshold region, and I 11 This represents the drain current of PMOS transistor M11. Current I 14 With current I 16 The first-order temperature-compensated bandgap reference voltage V provided to the core circuit of the bandgap reference. REF1 Perform high-order temperature compensation to improve the output voltage V provided by the op-amp-free bandgap reference for high-order temperature compensation of power chips. REF For V REF =V REF1 -(I 14 +I 16 R5, where the output voltage V REF Inclusion factor V REF1 and (I)14 +I 16 R5, factor (I) 14 +I 16 R5 exhibits high-order temperature nonlinearity and is affected by the factor V. REF1 The higher-order temperature nonlinearity is compensated for to obtain the bandgap reference voltage V with low temperature drift. REF .

[0011] Furthermore, in the pre-adjustment circuit, PMOS transistors M26, M27, M28, M29, M30, and M31, along with resistor R11, form a self-biasing circuit and provide a bias signal for the pre-adjustment circuit. PMOS transistors M32, M33, M34, M35, and M36 form a startup circuit, causing the self-biasing circuit of the pre-adjustment circuit and the bandgap reference core circuit to leave the degenerate state and enter the normal operating state. PMOS transistor M23 provides power to the bandgap reference core circuit and the higher-order compensation circuit. Simultaneously, PMOS transistors M18, M19, M20, and M23 form a negative feedback system. When the external power supply VDD experiences an increase in fluctuation, the drain potential of PMOS transistor M23 increases, which in turn increases the gate potential of NMOS transistor M19 via PMOS transistor M18. This increases the drain current of NMOS transistor M19, thereby suppressing the increase in the drain potential of PMOS transistor M23. In other words, it suppresses the influence of external power supply VDD fluctuations on the power supply of the bandgap reference core circuit and the higher-order compensation circuit, thus achieving a high power supply rejection ratio and low temperature drift bandgap reference voltage V. REF The advantages and beneficial effects of this invention are as follows:

[0012] This invention provides an op-amp-free bandgap reference for high-order temperature compensation in power supply chips. It achieves equal voltages at the two nodes by clamping the emitter junctions of NPN transistors Q1 and Q3. A feedback system consisting of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a self-biasing circuit consisting of resistor R6, NPN transistor Q4, PMOS transistors M2, M4, M9, M8, NMOS transistors M6, and M7 are used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without an op-amp. Furthermore, PMOS transistors M14, M15, M16, and M17 operate in the subthreshold region to generate a high-order temperature nonlinear current I. 14 and I 16Furthermore, the high-order temperature nonlinearity of the first-order bandgap reference voltage is compensated. A pre-adjustment circuit is used to provide operating power to the core circuit of the bandgap reference and the high-order compensation circuit, thereby realizing a bandgap reference voltage with high power supply rejection ratio and low temperature drift, and thus realizing an op-amp-free bandgap reference for high-order temperature compensation of power chips. Attached Figure Description

[0013] Figure 1 It is a schematic diagram of a traditional first-order bandgap reference circuit;

[0014] Figure 2 An op-amp-free bandgap reference for high-order temperature compensation of power chips is provided as a preferred embodiment of the present invention.

[0015] Figure 3 The simulation diagram shows the output voltage temperature characteristics of a high-order temperature-compensated op-amp bandgap reference for power chips, according to a preferred embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0017] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0018] In this embodiment, the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 is used to achieve equal voltages at the two nodes. A feedback system consisting of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a self-biasing circuit consisting of resistor R6, NPN transistor Q4, PMOS transistors M2, M4, M9, M8, M6, and M7 are used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without operational amplifiers. PMOS transistors M14, M15, M16, and M17 operate in the subthreshold region to generate a high-order temperature nonlinear current I. 14 and I 16 Furthermore, the high-order temperature nonlinearity of the first-order bandgap reference voltage is compensated. A pre-adjustment circuit is used to provide operating power to the core circuit of the bandgap reference and the high-order compensation circuit, thereby realizing a bandgap reference voltage with high power supply rejection ratio and low temperature drift, and thus realizing an op-amp-free bandgap reference for high-order temperature compensation of power chips.

[0019] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0020] Example

[0021] An op-amp-free bandgap reference for high-order temperature compensation in power supply chips, such as Figure 2 As shown, it includes a bandgap reference core circuit 1, a high-order compensation circuit 2, and a pre-adjustment circuit 3;

[0022] In this circuit, the signal output terminal of the bandgap reference core circuit 1 is connected to the signal input terminal of the higher-order compensation circuit 2 and the signal input terminal of the pre-adjustment circuit 3, respectively. The signal output terminal of the higher-order compensation circuit 2 is connected to the signal input terminal of the bandgap reference core circuit 1, and the signal output terminal of the pre-adjustment circuit 3 is connected to the signal input terminals of the bandgap reference core circuit 1 and the higher-order compensation circuit 2, respectively. The bandgap reference core circuit 1 uses the clamping effect of the emitter junctions of two NPN transistors to achieve equal voltages at the two nodes. A feedback system and a self-biasing circuit are used to improve the clamping accuracy of the emitter junctions of the NPN transistors, thereby providing a first-order bandgap reference voltage V at the circuit output terminal. REF1 The higher-order compensation circuit 2 utilizes the higher-order temperature nonlinear current I provided by PMOS transistors M14 and M16. 14 and I 16 For the first-order bandgap reference voltage V REF1 The high-order temperature nonlinearity is compensated by the pre-adjustment circuit 3, which provides the working power supply voltage for the bandgap reference core circuit 1 and the high-order compensation circuit 2, thereby obtaining a bandgap reference voltage with high power supply rejection ratio and low temperature drift.

[0023] As a preferred technical solution, such as Figure 2As shown, the bandgap reference core circuit 1 includes: NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9; NPN transistors Q1, Q2, Q3, Q4, and Q5; resistors R1, R2, R3, R4, R5, R6, and R7; and capacitor C1. The source of PMOS transistor M8 is connected to the source of PMOS transistor M9, the source of PMOS transistor M4, the drain of NMOS transistor M1, the source of PMOS transistor M5, the source of PMOS transistor M10, and the PMOS transistor M9. The source of transistor M11, the source of PMOS transistor M18, the drain of PMOS transistor M23, and the drain of NMOS transistor M19 are connected. The drain of PMOS transistor M8 is connected to the drain and gate of NMOS transistor M6, and the gate of NMOS transistor M7. The source of NMOS transistor M6 is connected to the source of NMOS transistor M7, one end of resistor R6, the emitter of NPN transistor Q1, one end of resistor R2, the emitter of NPN transistor Q3, and external ground GND. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M12, the gate of PMOS transistor M13, and the drain of NMOS transistor M19. The drain of S-MOSFET M7 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M2. The drain of PMOS transistor M2 is connected to the collector of NPN transistor Q4, the gate of PMOS transistor M8, the gate of PMOS transistor M4, the gate of PMOS transistor M5, the gate of PMOS transistor M10, the gate of PMOS transistor M11, and the drain of NMOS transistor M36. The emitter of NPN transistor Q4 is connected to the other end of resistor R6, the gate of PMOS transistor M15, and the gate of PMOS transistor M16. The source of NMOS transistor M1 is connected to one end of resistor R5, one end of resistor R10, the gate of PMOS transistor M18, the gate of NMOS transistor M34, and the output terminal VREF. The other end of resistor R5 is connected to the base of NPN transistor Q4, one end of resistor R3, one end of resistor R4, the base of NPN transistor Q5, the drain of PMOS transistor M14, and the drain of PMOS transistor M16. The other end of resistor R3 is connected to one end of resistor R1 and the base of NPN transistor Q1. The other end of resistor R1 is connected to the base of NPN transistor Q2 and the collector of NPN transistor Q1. The other end of resistor R4 is connected to the base of NPN transistor Q3, one end of capacitor C1, and the collector of NPN transistor Q2. The emitter of NPN transistor Q2 is connected to the other end of resistor R2. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M3.The drain of PMOS transistor M3 is connected to the gate of NMOS transistor M1, the other end of capacitor C1, and the collector of NPN transistor Q5. The emitter of NPN transistor Q5 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the collector of NPN transistor Q3.

[0024] The high-order compensation circuit 2 includes: PMOS transistors M10, M11, M12, M13, M14, M15, M16, and M17; resistors R8, R9, and R10. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M12. The drain of PMOS transistor M12 is connected to the sources of both PMOS transistors M14 and M15. The gate of M14 is connected to the other end of resistor R10 and one end of resistor R9. The other end of resistor R9 is connected to one end of resistor R8 and the gate of PMOS transistor M17. The other end of resistor R8 is connected to the drain of PMOS transistor M15, the drain of PMOS transistor M17 and external ground GND. The drain of PMOS transistor M11 is connected to the source of PMOS transistor M13. The drain of PMOS transistor M13 is connected to the source of PMOS transistor M16 and the source of PMOS transistor M17.

[0025] The pre-adjustment circuit 3 includes: PMOS transistors M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, and M36, and resistor R11. The source of PMOS transistor M23 is connected to the source of PMOS transistor M24, and the source of PMOS transistor M36 is connected to the source of PMOS transistor M27. The source of transistor M25, the source of PMOS transistors M26, M27, and M32, as well as the external power supply VDD, are connected. The drain of PMOS transistor M18 is connected to the gate of NMOS transistor M19 and the drain of NMOS transistor M20. The source of NMOS transistor M20 is connected to the sources of NMOS transistors M19, M21, and M22, one end of resistor R11, the sources of NMOS transistors M31, M36, M35, and M34, as well as the external ground GND. The drain of PMOS transistor M24... The gates of PMOS transistors M24, M23, and M21 are connected to each other respectively. The drain of PMOS transistor M25 is connected to the gates of NMOS transistors M20, M21, M22, and M22 respectively. The drain of PMOS transistor M26 is connected to the gates of PMOS transistors M25, M26, M27, M35, and M28 respectively. The source of NMOS transistor M28 is connected to the drain of NMOS transistor M30. The source of NMOS transistor M30 is connected to the drain of NMOS transistor M30. The other end of resistor R11 is connected to the drain of PMOS transistor M27, which is connected to the gate of NMOS transistor M28, the gate of NMOS transistor M29, and the drain of NMOS transistor M29. The source of NMOS transistor M29 is connected to the gate of NMOS transistor M30, the gate of NMOS transistor M31, and the drain of NMOS transistor M31. The gate of PMOS transistor M32 is connected to the drain of PMOS transistor M32 and the source of PMOS transistor M33. The drain of PMOS transistor M33 is connected to the gate of PMOS transistor M33, the gate of NMOS transistor M35, the gate of NMOS transistor M36, and the drain of NMOS transistor M34.

[0026] In the core circuit 1 of the bandgap reference, the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 makes the voltage drops of resistors R3 and R4 equal. A feedback system composed of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a self-biasing circuit composed of resistor R6, NPN transistor Q4, PMOS transistors M2, M4, M9, M8, NMOS transistors M6, and M7 are used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without operational amplifiers. Resistors R3, R4, and R6 are identical, as are NPN transistors Q1, Q3, and Q4. The current amplification factor β of all NPN transistors is much greater than 1, and the base current of all NPN transistors is negligible. Therefore, the base-emitter voltage V of NPN transistor Q1 is... BE1 The base-emitter voltage V of NPN transistor Q4 BE4 have

[0027]

[0028] In equation (1), I S V is the saturation current of the transistor. T Let R3 be the thermal voltage, R6 be the resistance of resistor R3, and R6 be the resistance of resistor R6. Resistors R3 and R6 have the same resistance value, and NPN transistors Q4 and Q1 have the same emitter area. Then, by optimizing the circuit, we have V. BE1 =V BE4 The current I flowing through resistor R3 is thus increased. R3 With the current I flowing through resistor R6 R6 There is I R3 =I R6 PMOS transistors M2, M3, M4, and M5 form a common-source, common-gate current mirror. PMOS transistors M4 and M5 are identical, and PMOS transistors M2 and M3 are identical. Therefore, NPN transistors Q3 and Q4 have the same collector current, and consequently, the base-emitter voltage V of NPN transistor Q3 is the same. BE3 V BE3 =V BE4 =V BE1 Resistors R3 and R4 are identical. The emitter area of ​​NPN transistor Q2 is m times that of NPN transistor Q1. Then the current I flowing through resistor R3 is... R3 With the current I flowing through resistor R4 R4 have

[0029]

[0030] In equation (2), R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, k is Boltzmann's constant, q is the electron charge, and T is the absolute temperature. Therefore, the current I flowing through resistor R3... R3 With the current I flowing through resistor R4 R4 The voltage V generated at the circuit output terminal VREF REF1 for

[0031]

[0032] In equation (3), R5 is the resistance value of resistor R5, and the factor V BE1 It has negative temperature characteristics, factor It has a positive temperature characteristic, therefore, by optimizing the circuit parameters, the voltage V can be made... REF1 This is the reference voltage for first-order temperature compensation.

[0033] In the higher-order compensation circuit 2, PMOS transistors M14, M15, M16, and M17 all operate in the subthreshold region, and the gate voltage V of PMOS transistor M15 is... G15 The gate voltage V of PMOS transistor M16 G16 And the voltage drop V across resistor R6 R6 V G15 =V G16 =V R6 And the gate voltage V of PMOS transistor M15 G15 With the gate voltage V of PMOS transistor M16 G16 Increases with increasing temperature; Gate voltage V of PMOS transistor M14 G14 The gate voltage V of PMOS transistor M17 G17 Provided by the circuit output terminal VREF, the gate voltage V of PMOS transistor M14 is... G14 With the gate voltage V of PMOS transistor M17 G17 The voltage is independent of temperature T. The gate voltage V of PMOS transistor M14. G14 V G14 >>V G15 =V R6 Then the drain current I of PMOS transistor M14 14 for

[0034]

[0035] In equation (4), I 10 Let be the drain current of PMOS transistor M10, and η be the non-ideal factor for the MOS transistor operating in the subthreshold region. Vgate of PMOS transistor M17. G17 VG17 < <V R6 The current I of PMOS transistor M16 16 for

[0036]

[0037] In equation (5), I 11 This represents the drain current of PMOS transistor M11. Current I 14 With current I 16 The first-order temperature-compensated bandgap reference voltage V provided by the bandgap reference core circuit 1 REF1 Perform high-order temperature compensation to improve the output voltage V provided by the op-amp-free bandgap reference for high-order temperature compensation of power chips. REF for

[0038] V REF =V REF1 -(I 14 +I 16 R5 (6)

[0039] As can be seen from equation (6), the output voltage V of the high-order temperature-compensated op-amp-free bandgap reference for power chips is... REF Inclusion factor V REF1 and (I) 14 +I 16 R5, where the factor (I) 14 +I 16 R5 exhibits high-order temperature nonlinearity and is affected by the factor V. REF1 The higher-order temperature nonlinearity is compensated for to obtain the bandgap reference voltage V with low temperature drift. REF .

[0040] In the pre-adjustment circuit 3, PMOS transistors M26, M27, M28, M29, M30, and M31, along with resistor R11, form a self-biasing circuit and provide a bias signal to the pre-adjustment circuit 3. PMOS transistors M32, M33, M34, M35, and M36 form a startup circuit, causing the self-biasing circuit of the pre-adjustment circuit 3 and the bandgap reference core circuit 1 to leave the degenerate state and enter the normal operating state. PMOS transistor M23 provides power to the bandgap reference core circuit 1 and the high-order compensation circuit 2. Simultaneously, PMOS transistors M18, M19, M20, and M23 form a negative feedback system. When the external power supply VDD experiences an increase in fluctuation, the drain potential of PMOS transistor M23 increases, which in turn increases the gate potential of NMOS transistor M19 via PMOS transistor M18. This increases the drain current of NMOS transistor M19, thereby suppressing the increase in the drain potential of PMOS transistor M23. In other words, it suppresses the influence of external power supply VDD fluctuations on the power supply of the bandgap reference core circuit 1 and the high-order compensation circuit 2, thus achieving a high power supply rejection ratio and low temperature drift bandgap reference voltage V. REF .

[0041] Figure 3 The present invention provides an output voltage V of an op-amp-less bandgap reference for high-order temperature compensation in power supply chips. REF The simulation curves show that the horizontal axis represents temperature T and the vertical axis represents the output voltage V of the bandgap reference. REF Simulation results show that, within a temperature range of -40℃ to 125℃, the temperature coefficient of the output voltage of the op-amp-free bandgap reference for high-order temperature compensation in power supply chips is 0.821ppm / ℃.

[0042] In the above embodiments of this application, an op-amp-free bandgap reference for high-order temperature compensation of power chips includes a bandgap reference core circuit, a high-order compensation circuit, and a pre-adjustment circuit. This embodiment employs the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 to achieve equal voltages at the two nodes. A feedback system consisting of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a self-biasing circuit consisting of resistor R6, NPN transistor Q4, PMOS transistors M2, M4, M9, M8, M6, and M7, are used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without operational amplifiers. High-order temperature nonlinear current I is generated by PMOS transistors M14, M15, M16, and M17 operating in the subthreshold region. 14 and I 16 Furthermore, the high-order temperature nonlinearity of the first-order bandgap reference voltage is compensated. A pre-adjustment circuit is used to provide operating power to the core circuit of the bandgap reference and the high-order compensation circuit, thereby realizing a bandgap reference voltage with high power supply rejection ratio and low temperature drift, and thus realizing an op-amp-free bandgap reference for high-order temperature compensation of power chips.

[0043] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0044] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. An op-amp-free bandgap reference for high-order temperature compensation in power supply chips, characterized in that, include: The bandgap reference core circuit (1), the high-order compensation circuit (2), and the pre-adjustment circuit (3) are configured such that the signal output terminal of the bandgap reference core circuit (1) is connected to the signal input terminal of the high-order compensation circuit (2) and the signal input terminal of the pre-adjustment circuit (3), respectively; the signal output terminal of the high-order compensation circuit (2) is connected to the signal input terminal of the bandgap reference core circuit (1), and the signal output terminal of the pre-adjustment circuit (3) is connected to the signal input terminal of the bandgap reference core circuit (1) and the signal input terminal of the high-order compensation circuit (2), respectively; the bandgap reference core circuit (1) uses the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 to achieve equal voltage drops between resistors R3 and R4, and uses a feedback system and self-biasing circuit technology to improve the clamping accuracy of the emitter junctions of NPN transistors Q1 and Q3, thereby providing a first-order bandgap reference voltage V at the circuit output terminal. REF1 The higher-order compensation circuit (2) uses the higher-order temperature nonlinear current provided by PMOS transistors M14 and M16 to adjust the first-order bandgap reference voltage V. REF1 The high-order temperature nonlinearity is compensated by the pre-adjustment circuit (3), which provides the working power supply voltage to the bandgap reference core circuit (1) and the high-order compensation circuit (2) through the PMOS transistor M23, thereby obtaining a bandgap reference voltage with high power supply rejection ratio and low temperature drift.

2. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 1, characterized in that, The bandgap reference core circuit (1) includes: NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9; NPN transistors Q1, Q2, Q3, Q4, and Q5; resistors R1, R2, R3, R4, R5, R6, and R7; and capacitor C1. The source of PMOS transistor M8 is connected to the source of PMOS transistor M9, the source of PMOS transistor M4, the drain of NMOS transistor M1, the source of PMOS transistor M5, the source of PMOS transistor M10, and PM10. The source of transistor M11, the source of PMOS transistor M18, the drain of PMOS transistor M23, and the drain of NMOS transistor M19 are connected. The drain of PMOS transistor M8 is connected to the drain and gate of NMOS transistor M6, and the gate of NMOS transistor M7. The source of NMOS transistor M6 is connected to the source of NMOS transistor M7, one end of resistor R6, the emitter of NPN transistor Q1, one end of resistor R2, the emitter of NPN transistor Q3, and external ground GND. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M12, the gate of PMOS transistor M13, and the drain of NMOS transistor M19. The drain of S-MOSFET M7 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M2. The drain of PMOS transistor M2 is connected to the collector of NPN transistor Q4, the gate of PMOS transistor M8, the gate of PMOS transistor M4, the gate of PMOS transistor M5, the gate of PMOS transistor M10, the gate of PMOS transistor M11, and the drain of NMOS transistor M36. The emitter of NPN transistor Q4 is connected to the other end of resistor R6, the gate of PMOS transistor M15, and the gate of PMOS transistor M16. The source of NMOS transistor M1 is connected to one end of resistor R5, one end of resistor R10, the gate of PMOS transistor M18, the gate of NMOS transistor M34, and the output terminal VREF. The other end of resistor R5 is connected to the base of NPN transistor Q4, one end of resistor R3, one end of resistor R4, the base of NPN transistor Q5, the drain of PMOS transistor M14, and the drain of PMOS transistor M16. The other end of resistor R3 is connected to one end of resistor R1 and the base of NPN transistor Q1. The other end of resistor R1 is connected to the base of NPN transistor Q2 and the collector of NPN transistor Q1. The other end of resistor R4 is connected to the base of NPN transistor Q3, one end of capacitor C1, and the collector of NPN transistor Q2. The emitter of NPN transistor Q2 is connected to the other end of resistor R2. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M3.The drain of PMOS transistor M3 is connected to the gate of NMOS transistor M1, the other end of capacitor C1, and the collector of NPN transistor Q5. The emitter of NPN transistor Q5 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the collector of NPN transistor Q3.

3. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 1, characterized in that, The high-order compensation circuit (2) includes: PMOS transistors M10, M11, M12, M13, M14, M15, M16, and M17; resistors R8, R9, and R10. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M12. The drain of PMOS transistor M12 is connected to the sources of PMOS transistors M14 and M15, respectively. The gate of transistor M14 is connected to the other end of resistor R10 and one end of resistor R9. The other end of resistor R9 is connected to one end of resistor R8 and the gate of PMOS transistor M17. The other end of resistor R8 is connected to the drain of PMOS transistor M15, the drain of PMOS transistor M17 and external ground GND. The drain of PMOS transistor M11 is connected to the source of PMOS transistor M13. The drain of PMOS transistor M13 is connected to the source of PMOS transistor M16 and the source of PMOS transistor M17.

4. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 1, characterized in that, The pre-adjustment circuit (3) includes: PMOS transistors M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, and M36, and resistor R11. The source of PMOS transistor M23 is connected to the source of PMOS transistor M24, and the source of PMOS transistor M26 is connected to the source of PMOS transistor M27. The source of transistor M25, the source of PMOS transistors M26, M27, and M32, and the external power supply VDD are connected. The drain of PMOS transistor M18 is connected to the gate of NMOS transistor M19 and the drain of NMOS transistor M20. The source of NMOS transistor M20 is connected to the sources of NMOS transistors M19, M21, and M22, one end of resistor R11, the sources of NMOS transistors M31, M36, M35, and M34, and the external ground GND. The drain of PMOS transistor M24... The source of PMOS transistor M25 is connected to the gate of PMOS transistor M24, the gate of PMOS transistor M23, and the drain of NMOS transistor M21, respectively. The drain of PMOS transistor M25 is connected to the gate of NMOS transistor M20, the gate of NMOS transistor M21, the gate of NMOS transistor M22, and the drain of NMOS transistor M22, respectively. The drain of PMOS transistor M26 is connected to the gate of PMOS transistor M25, the gate of PMOS transistor M26, the gate of PMOS transistor M27, the drain of NMOS transistor M35, and the drain of NMOS transistor M28, respectively. The source of NMOS transistor M28 is connected to the drain of NMOS transistor M30, and the source of NMOS transistor M30 is connected to... The other end of resistor R11 is connected to the drain of PMOS transistor M27, which is connected to the gate of NMOS transistor M28, the gate of NMOS transistor M29, and the drain of NMOS transistor M29. The source of NMOS transistor M29 is connected to the gate of NMOS transistor M30, the gate of NMOS transistor M31, and the drain of NMOS transistor M31. The gate of PMOS transistor M32 is connected to the drain of PMOS transistor M32 and the source of PMOS transistor M33. The drain of PMOS transistor M33 is connected to the gate of PMOS transistor M33, the gate of NMOS transistor M35, the gate of NMOS transistor M36, and the drain of NMOS transistor M34.

5. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 4, characterized in that, In the pre-adjustment circuit (3), PMOS transistors M26, M27, M28, M29, M30, and M31, along with resistor R11, form a self-biasing circuit and provide a bias signal to the pre-adjustment circuit (3). PMOS transistors M32, M33, M34, M35, and M36 form a startup circuit, causing the self-biasing circuit of the pre-adjustment circuit (3) and the bandgap reference core circuit (1) to leave the degenerate state and enter the normal working state. PMOS transistor M23 is the bias signal for the bandgap reference core circuit (1) and the higher-order... The compensation circuit (2) provides the working power supply. At the same time, PMOS transistors M18, M19, M20 and M23 form a negative feedback system. When the external power supply VDD has an increasing fluctuation signal, the drain potential of PMOS transistor M23 increases and through PMOS transistor M18, the gate potential of NMOS transistor M19 increases, the drain current of NMOS transistor M19 increases, thereby suppressing the increase of the drain potential of PMOS transistor M23. That is, suppressing the influence of external power supply VDD fluctuation on the working power supply of the bandgap reference core circuit (1) and the high-order compensation circuit (2), thereby realizing a bandgap reference voltage with a high power supply rejection ratio.

6. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 2, characterized in that, In the bandgap reference core circuit (1), the clamping effect of the emitter junctions of NPN transistors Q1 and Q3 makes the voltage drops of resistors R3 and R4 equal. A feedback system composed of NPN transistor Q3, resistor R7, NPN transistor Q5, NMOS transistor M1, resistor R4, and resistor R5, and a system composed of resistor R6, NPN transistor Q4, PMOS transistor M2, PMOS transistor M4, PMOS transistor M9, PMOS transistor M8, and NMOS transistor M1 are used. A self-biasing circuit composed of OS transistor M6 and NMOS transistor M7 is used to improve the clamping accuracy of the emitter junctions of NPN transistors Q3 and Q1, thereby achieving a high-precision first-order bandgap reference voltage without operational amplifiers. Resistors R3 and R4 are identical to resistor R6, and NPN transistors Q1, Q3, and Q4 are identical. The current amplification factor β of all NPN transistors is much greater than 1. The base-emitter voltage V of NPN transistor Q1 is... BE1 The base-emitter voltage V of NPN transistor Q4 BE4 have Among them, I S V is the saturation current of the transistor. T Let V be the thermal voltage, R3 be the resistance of resistor R3, and R6 be the resistance of resistor R6. Since resistors R3 and R6 have the same resistance, then by optimizing the circuit, V = ... BE1 =V BE4 The current I flowing through resistor R3 is thus increased. R3 With the current I flowing through resistor R6 R6 There is I R3 =I R6 PMOS transistors M2, M3, M4, and M5 form a common-source, common-gate current mirror. PMOS transistors M4 and M5 are identical, and PMOS transistors M2 and M3 are identical. Therefore, NPN transistors Q3 and Q4 have the same collector current, and thus the base-emitter voltage V of NPN transistor Q3 is... BE3 V BE3 =V BE4 =V BE1 Resistors R3 and R4 are identical. The emitter area of ​​NPN transistor Q2 is m times that of NPN transistor Q1. Then the current I flowing through resistor R3 is... R3 With the current I flowing through resistor R4 R4 The voltage V generated at the circuit output terminal VREF REF1 for Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, R5 is the resistance of resistor R5, k is Boltzmann's constant, q is the electron charge, T is the absolute temperature, and the factor V BE1 It has negative temperature characteristics, factor It has a positive temperature characteristic, and the voltage V is made possible by optimizing the circuit parameters. REF1 This is the first-order temperature-compensated bandgap reference voltage.

7. The op-amp-free bandgap reference for high-order temperature compensation of power chips according to claim 3, characterized in that, In the higher-order compensation circuit (2), PMOS transistors M14, M15, M16, and M17 all operate in the subthreshold region, and the gate voltage V of PMOS transistor M15 is... G15 The gate voltage V of PMOS transistor M16 G16 And the voltage drop V across resistor R6 R6 V G15 =V G16 =V R6 The gate voltage V of PMOS transistor M15 G15 With the gate voltage V of PMOS transistor M16 G16 Increases with increasing temperature; Gate voltage V of PMOS transistor M14 G14 The gate voltage V of PMOS transistor M17 G17 Provided by the circuit output terminal VREF, the gate voltage V of PMOS transistor M14 is... G14 With the gate voltage V of PMOS transistor M17 G17 The gate voltage V of PMOS transistor M14 is a voltage independent of temperature T. G14 With the gate voltage V of PMOS transistor M17 G17 V G14 >>V R6 >>V G17 Then the drain current I of PMOS transistor M14 14 and the current I of PMOS transistor M16 16 for and Among them, I 10 I is the drain current of PMOS transistor M10, η is the non-ideal factor for the MOS transistor operating in the subthreshold region, and I 11 V is the drain current of PMOS transistor M11. T This is thermal voltage.

8. A high-order temperature compensation op-amp-free bandgap reference for power supply chips according to any one of claims 5-7, characterized in that, The drain current I of PMOS transistor M14 14 The drain current I of PMOS transistor M16 16 It exhibits high-order temperature nonlinearity, and current I 14 With current I 16 The first-order temperature-compensated bandgap reference voltage V provided by the bandgap reference core circuit (1) REF1 Perform high-order temperature compensation to improve the output voltage V of the op-amp-free bandgap reference for high-order temperature compensation in power supply chips. REF For V REF =V REF1 -(I 14 +I 16 R5, where R5 is the resistance value of resistor R5, and the output voltage V REF Inclusion factor V REF1 and (I) 14 +I 16 R5, factor (I) 14 +I 16 R5 exhibits high-order temperature nonlinearity and is affected by the factor V REF1 The higher-order temperature nonlinearity is compensated for to obtain the bandgap reference voltage V with low temperature drift. REF This leads to the realization of an op-amp-free bandgap reference for high-order temperature compensation in power chips.

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