A multi-channel partition light source high-speed switching method under a light source control system

Abstract

The application discloses a kind of multi-channel partition light source high-speed switching method under light source control system, it is related to light source control technical field, including between different light source controllers by configuring fixed pulse width END signal output and to END signal carry out edge sampling identification, establish the cascade notice mechanism of process completion, and in the light source controller of later stage, setting is used to absorb link delay Fixed synchronization waiting window;When the camera trigger request occurs concurrently in different processes, set the process level photograph request flag bit and aggregate to the camera trigger buffer uniformly, and when judging that the photograph request is valid, output a single fixed pulse width camera trigger pulse signal to the camera trigger channel;Adjustable filter module is set at the input interface of light source controller, select multiple filter capacitors by physical dial code to suppress the jitter of external START frame signal of DC 5-24V, while controlling the response delay of frame signal.

Description

Technical Field

[0001] This invention relates to the field of light source control technology, specifically to a method for high-speed switching of multi-channel zoned light sources in a light source control system. Background Technology

[0002] In recent years, machine vision inspection, industrial automation equipment, and high-speed production lines have placed increasingly higher demands on the performance of light source control systems. Especially in complex working environments, multi-channel zoned light sources need to switch rapidly according to different workstations, inspection steps, and imaging requirements to cooperate with industrial cameras for accurate shooting and high-speed recognition. Simultaneously, systems often employ a multi-controller cascade approach to coordinate the scheduling of multiple light sources, requiring strict timing consistency and real-time response capabilities across different processes. Furthermore, frame synchronization signals from cameras or external control systems exhibit characteristics such as high frequency, edge-triggered sensitivity, and high anti-interference requirements. Therefore, light source control equipment not only needs to achieve stable light source illumination control but also needs to undertake multiple functions including trigger management, signal filtering, and system collaborative operation.

[0003] However, existing light source control technologies still have significant shortcomings in multi-controller collaborative synchronization, high-speed concurrent trigger fusion processing, and frame signal anti-interference capabilities. Under multi-controller cascading conditions, existing solutions typically only transmit simple trigger signals to complete process notification, lacking fixed pulse width and edge sampling judgment mechanisms. This leads to accumulated transmission link differences in process synchronization between different controllers, making it difficult to achieve stable and reliable cascading synchronization. When multiple light source processes simultaneously issue camera trigger requests, traditional systems mostly use independent channels or simple priority arbitration methods, failing to achieve unified aggregation output of trigger requests under concurrent conditions. This may result in camera trigger signal loss, trigger conflicts, or duplicate triggers, failing to meet the requirement of providing only a single trigger channel while still ensuring reliable image capture control. External START frame signals are susceptible to electromagnetic interference and jitter in industrial environments. Existing technologies often use fixed filtering or software delay methods, failing to achieve adjustable filtering and response delay control for different interference environments, easily leading to false triggers or trigger hysteresis, thus affecting the overall timing stability of the system. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is that the existing multi-channel partitioned light source control method has the following problems: the lack of a reliable process cascading synchronization mechanism between multiple controllers, the inability to safely aggregate concurrent requests for camera photo capture triggering which easily leads to trigger conflicts or loss, insufficient anti-interference capability of external frame signals and lack of adjustable filtering capability, and how to achieve stable synchronous control, reliable single-channel trigger output and frame signal jitter suppression under high-speed light source switching conditions.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a high-speed switching method for multi-channel partitioned light sources under a light source control system, comprising: establishing a cascading notification mechanism for process completion by configuring a fixed pulse width END signal output and performing edge sampling and identification on the END signal between different light source controllers; setting a fixed synchronization waiting window in the subsequent light source controller to absorb link delay; when camera trigger requests occur concurrently in different processes, setting a process-level photo capture request flag bit and aggregating them to the camera trigger buffer; and outputting a single fixed pulse width camera trigger pulse signal to the camera trigger channel when the photo capture request is determined to be valid; setting an adjustable filtering module at the input interface of the light source controller, and selecting multiple filter capacitors through physical DIP switches to suppress jitter of the external START frame signal of DC 5-24V, while simultaneously controlling the frame signal response delay.

[0007] As a preferred embodiment of the high-speed switching method for multi-channel zoned light sources under the light source control system described in this invention, the END signal output includes: the light source controller automatically outputting a high-level pulse signal after each complete lighting process, the voltage value of the high-level pulse signal being 24V and the pulse width being fixed at 2ms; the END signal being output to the input interface of the next-level light source controller through the positive and negative terminals of END, the output action being bound to the process end status flag in the process control module inside the light source controller, and the END signal being generated by the timing module inside the light source controller at fixed intervals; the END signal adopts standard TTL compatible level logic, directly triggering the light source lighting process configured in the subsequent light source controller; before executing each process, the light source controller determines whether it has received a valid END signal edge from the previous-level light source controller by checking the status of the process buffer; if the END signal is not received within the set timeout period, the light source controller will enter a waiting mode or execute a safety process.

[0008] As a preferred embodiment of the high-speed switching method for multi-channel zoned light sources under the light source control system described in this invention, the fixed synchronous waiting window includes a time period set in the internal logic of the light source controller for delaying the triggering process after waiting for the END signal response. The time period is fixed at 5μs to 20μs and does not exceed the minimum process cycle unit of 100μs supported by the light source controller. The fixed synchronous waiting window does not affect the light source output delay setting and brightness control, and is decoupled from the process logic control module. After the light source controller receives the rising edge of the END signal, the timer is started immediately. After the timer expires, the process logic control module is activated to load the next process task, and a mark is recorded in the process configuration file. Each process can independently define whether to enable the synchronous waiting window.

[0009] As a preferred embodiment of the high-speed switching method for multi-channel partitioned light sources under the light source control system described in this invention, the following is included: The photo-taking request flag bit includes the following: Within the light source controller process, whenever a light source process defines a field that needs to be output to trigger a camera, the light source controller registers the field in the process parsing module, generating a valid flag bit. The valid flag bit is written into the camera trigger buffer table, which is updated cyclically on a periodic basis. Within a control cycle, if one or more processes generate camera trigger flag bits, they are aggregated into a single valid trigger request. Within each process cycle, the light source controller sequentially checks the status of each trigger flag bit in the camera trigger buffer table. If any flag bit is in a valid state, a valid photo-taking request is confirmed within the current cycle. The single trigger output module is then invoked to send a set of high-level control signals with a pulse width of 2ms and 24V to the configured camera trigger output port. After completing a single output, the light source controller locks the status of the single trigger output module, prohibiting it from triggering again within the current cycle. Only when the process cycle ends and the next cycle's status is re-entered, is it allowed to re-evaluate whether to trigger the output based on the new trigger conditions.

[0010] As a preferred embodiment of the high-speed switching method for multi-channel partitioned light sources under the light source control system described in this invention, the camera trigger buffer includes: before the start of each process cycle, the light source controller polls and traverses the camera trigger flag bit to establish a binary aggregation register; if the register value is not 0, a trigger signal with a fixed 2ms pulse width is output; the light source controller latches the trigger event through software logic and writes the trigger status into the cycle end flag; the buffer mechanism is configured as edge triggering or level triggering mode, and the external device is status-sensing or fault-judgment is performed by querying the trigger status in the last 8 cycles through system parameter selection.

[0011] As a preferred embodiment of the high-speed switching method for multi-channel zoned light sources under the light source control system described in this invention, the adjustable filtering module includes a four-position DIP switch installed on the external panel of the light source controller. Each DIP switch corresponds to a set of parallel capacitor values: the first position corresponds to a capacitor value of 0.001uF, the second position to 0.01uF, the third position to 0.1uF, and the fourth position to 1uF. The light source controller selects the filter capacitor through the DIP switch to adjust the response sensitivity of the input frame signal. The frame signal is a DC 5-24V edge-triggered signal. The light source controller performs filtering and amplification processing on the frame signal through an internal signal shaping circuit. The filtering circuit consists of a limiting clamping circuit and an RC low-pass filter network. The configuration interface of the light source controller allows querying the current filter value status and manually adjusting the capacitor combination according to the interference level. The dynamic response frequency is within 50Hz.

[0012] As a preferred embodiment of the high-speed switching method for multi-channel zoned light sources under the light source control system described in this invention, the frame signal response delay control includes: the light source controller's signal response delay not exceeding 15μs; employing a digital sampling window strategy, combined with the amplitude of the input signal after RC filtering, performing single sampling confirmation and signal validity judgment; if the sampled value appears more than three times within the set fluctuation tolerance, it is considered a valid trigger signal; if the frame signal input level change frequency exceeds the system limit, the light source controller will trigger the input protection mechanism and suspend the process operation, allowing triggering again after the input stabilizes.

[0013] Another objective of this invention is to provide a high-speed switching system for multi-channel zoned light sources under a light source control system.

[0014] As a preferred embodiment of the high-speed switching system for multi-channel partitioned light sources under the light source control system described in this invention, the system includes: a cascaded notification module, a buffer module, and a switching module; the cascaded notification module is used to establish a cascaded notification mechanism for process completion by configuring a fixed-width END signal output and performing edge sampling and identification on the END signal between different light source controllers, and setting a fixed synchronization waiting window in the subsequent light source controller to absorb link delay; the buffer module is used to set a process-level photo capture request flag bit and uniformly aggregate it to the camera trigger buffer when concurrent camera trigger requests occur in different processes, and output a single fixed-width camera trigger pulse signal to the camera trigger channel when the photo capture request is determined to be valid; the switching module is used to set an adjustable filtering module at the input interface of the light source controller, and select multiple filter capacitors through physical DIP switches to suppress jitter of the external START frame signal of DC 5-24V, while controlling the frame signal response delay.

[0015] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a method for high-speed switching of multi-channel zoned light sources under a light source control system.

[0016] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a high-speed switching method for multi-channel zoned light sources under a light source control system.

[0017] The beneficial effects of this invention are as follows: The high-speed switching method for multi-channel partitioned light sources under a light source control system provided by this invention achieves high-speed switching control of multi-channel partitioned light sources under a light source control system by constructing a fixed pulse width END signal mechanism with cascade synchronization capability, a unified camera trigger management logic based on process-level trigger flag bits, and a frame signal anti-interference input module with adjustable filtering capability. This improves the synchronization accuracy between controllers, the reliability of trigger logic, and the system's adaptability to complex interference environments. The edge triggering of the END signal and the synchronization waiting window work together to solve the problem of asynchronous process completion times in cascade control. The camera trigger buffer mechanism achieves safe integration of multiple concurrent trigger requests under a single output channel through flag bit aggregation and periodic latching control, avoiding signal loss or false triggering. The adjustable filtering module, through DIP switch selection of capacitor values ​​and sampling confirmation mechanism, achieves adaptive suppression of electromagnetic interference of different intensities, effectively ensuring the accuracy of frame signal recognition. This improves the overall timing consistency, trigger stability, and operational robustness of the system, solving key problems that existing light source control systems struggle to overcome in high-speed, complex environments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an overall flowchart of a high-speed switching method for multi-channel zoned light sources in a light source control system provided in Embodiment 1 of the present invention. Detailed Implementation

[0020] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0021] Example 1, referring to Figure 1 As an embodiment of the present invention, a method for high-speed switching of multi-channel zoned light sources under a light source control system is provided, comprising:

[0022] S1: By configuring a fixed pulse width END signal output between different light source controllers and performing edge sampling and identification on the END signal, a cascading notification mechanism for process completion is established, and a fixed synchronization waiting window is set in the subsequent light source controller to absorb link delay.

[0023] Furthermore, the END signal output includes: the light source controller automatically outputting a high-level pulse signal after each complete lighting process, with a voltage value of 24V and a fixed pulse width of 2ms; the END signal is output to the input interface of the next-level light source controller through the positive and negative terminals of END; the output action is bound to the process end status flag in the process control module inside the light source controller, and the END signal is generated by the timing module inside the light source controller at fixed intervals; the END signal adopts standard TTL compatible level logic and directly triggers the light source lighting process configured in the subsequent light source controller; before executing each process, the light source controller determines whether it has received a valid END signal edge from the previous-level light source controller by checking the status of the process buffer; if the END signal is not received within the set timeout period, the light source controller will enter a waiting mode or execute a safety process.

[0024] It should also be noted that a preferred scheme for configuring a fixed-width END signal output and performing edge sampling and identification on the END signal between different light source controllers specifically includes, assuming the complete lighting process of each light source controller is defined as:

[0025]

[0026] in, Indicates the first The single-light-up process of a light source controller; Indicates the start time of the process; This indicates the end time of the process, automatically recorded by the controller's internal process control module based on the task completion status. This is recorded each time a process is detected... After a certain time, the controller will generate an END signal:

[0027]

[0028] in, Indicates the first Each controller in time Output the END signal; This indicates a fixed pulse width for the END signal; the output interfaces are: positive terminal (END_P) and negative terminal (END_N), and the output level is a 24VTL compatible high-level signal. Next-level controller. Received from the previous level controller After the END signal, edge detection is required. The sampling mechanism is as follows: The signal acquired by the receiver is defined as:

[0029]

[0030] in, This indicates the sampled signal received by the next-level controller; This indicates the delay time of the signal during its propagation through the cable. The controller performs rising edge detection on the signal.

[0031]

[0032] in, Indicates the first The rising edge event flag bit of the END signal detected by the light source controller This indicates the time point at which the END signal change is detected. Indicates time The actual level value of the END signal received at that moment. Indicates a point in time The value immediately following the last instant. If detected... If so, it means the process end signal is valid.

[0033] It should be noted that the fixed synchronous wait window includes setting a time period in the internal logic of the light source controller to delay the triggering of the process after waiting for the END signal response. The time period is fixed at 5μs to 20μs and does not exceed the minimum process cycle unit of 100μs supported by the light source controller. The fixed synchronous wait window does not affect the light source output delay setting and brightness control. It is decoupled from the process logic control module. The timer is started immediately after the light source controller receives the rising edge of the END signal. After the timer expires, the process logic control module is activated to load the next process task. The timer is marked and recorded in the process configuration file, allowing each process to independently define whether to enable the synchronous wait window.

[0034] It should also be noted that a preferred scheme for establishing a cascading notification mechanism for process completion specifically includes, to avoid differences in line transmission... The resulting controller cascade startup timing offset is addressed by introducing a fixed synchronization wait window after receiving a valid END signal. This window provides a short delay to the startup process, ensuring all controllers start with a consistent baseline. Delay time for:

[0035]

[0036] Limited by the controller's minimum cycle control unit:

[0037]

[0038] in, This is the minimum process scheduling cycle supported by the controller. Upon receiving the rising edge of the END signal, the controller starts a synchronization timer and waits for a specified time. Upon arrival, the process logic control module is invoked to execute the next process. Before the process starts, the status register in the process buffer inside the controller records the process reception status of the previous stage. :

[0039]

[0040] like The controller will enter a safety waiting mode or execute a preset error handling procedure to prevent abnormal start-up of the light source. Whether the synchronization delay mechanism is enabled is determined by a flag in the procedure configuration file. control:

[0041]

[0042] The process flags are read and registered before loading process tasks, forming the ability to customize process configuration.

[0043] It should also be noted that, regarding the engineering challenges of synchronization misalignment and timing drift during multi-controller cascaded operation in multi-light source control systems, most existing multi-controller light source systems simply use cascaded trigger lines for process notification, lacking a clear fixed pulse width output standard and a strict edge recognition mechanism. In high-speed operation and long-link transmission scenarios, this easily leads to unstable pulse recognition, amplified edge jitter, and accumulated link inconsistencies, ultimately causing asynchronous process startup of different controllers, which directly affects the exposure matching and imaging consistency of industrial cameras. This step not only limits the END signal to a fixed pulse width and uses the edge as the sole valid identification criterion, but also introduces a fixed synchronization waiting window to actively absorb link delay differences, essentially constructing a unified timing reference benchmark in a multi-node system. This technical problem is often ignored in traditional light source control systems or only handled through empirical delays, lacking systematization, determinism, and engineering verifiability.

[0044] S2: When camera trigger requests occur concurrently in different processes, a process-level photo capture request flag is set and uniformly aggregated to the camera trigger buffer. When the photo capture request is determined to be valid, a single fixed-width camera trigger pulse signal is output to the camera trigger channel.

[0045] Furthermore, the photo-taking request flag bit includes the following: Within the light source controller process, whenever a light source process defines the need to output a camera trigger identifier field, the light source controller registers the identifier field in the process parsing module, generating a valid flag bit. The valid flag bit is written into the camera trigger buffer table, which is updated cyclically on a periodic basis. Within a control cycle, if one or more processes generate camera trigger flag bits, they are aggregated into a single valid trigger request. Within each process cycle, the light source controller sequentially checks the status of each trigger flag bit in the camera trigger buffer table. If any flag bit is in a valid state, it confirms that a valid photo-taking request exists within this cycle, calls the single trigger output module, and sends a set of high-level control signals with a pulse width of 2ms and 24V to the configured camera trigger output port. After completing a single output, the light source controller locks the status of the single trigger output module, prohibiting it from triggering again within the current cycle, until the process cycle ends and the status judgment of the next cycle is re-entered, at which point it is allowed to re-evaluate whether to trigger the output based on the new trigger conditions.

[0046] It should also be noted that a preferred scheme for setting process-level photo request flags specifically includes executing a set of process definitions for each light source controller cycle. Represented as:

[0047]

[0048] in, Indicates the controller number; Indicates controller Inner Individual light source process; This indicates the maximum number of processes executed within each cycle.

[0049] Whenever a certain process This includes a photo-taking trigger request, which is set via the trigger identifier field in the process configuration. The controller will then register a photo-taking request flag. , is represented as:

[0050]

[0051] all Write to the photo buffer table The buffer table is initialized and rebuilt every cycle, and its contents are:

[0052]

[0053] At the beginning of each control cycle, the controller... Perform a one-time aggregation judgment to generate the photo request aggregation register value. , is represented as:

[0054]

[0055] in, This represents the logical "OR" operation. If This indicates that at least one process generated a valid photo-taking request within this cycle. The controller then invokes the single-trigger output module to send a photo-taking control signal to the configured single output interface (corresponding to physical ports Cam+ and Cam-). , is represented as:

[0056]

[0057] in, Indicates the start time of the trigger signal output within this cycle; It indicates a fixed pulse width for the output signal; the voltage value is 24V, which meets the TTL-compatible triggering standard; the output terminal is a single channel, with a set of physical trigger signals outputting positive and negative terminals.

[0058] To prevent the camera from being repeatedly triggered within the same control cycle, the controller sets a latch flag immediately after executing a valid trigger output. , is represented as:

[0059]

[0060] If before the end of the current control cycle, If this happens, the triggering action will not be executed again, regardless of whether a flag request is generated again in subsequent processes. This locking flag is reset to this value at the start of each new cycle.

[0061]

[0062] This mechanism ensures that even if multiple processes concurrently request to take pictures, the controller will only output a picture signal once per cycle, thus meeting the single-channel camera input requirements.

[0063] It should be noted that the camera trigger buffer includes the following: before the start of each process cycle, the light source controller polls and traverses the camera trigger flag bit to establish a binary aggregation register; if the register value is not 0, a trigger signal with a fixed 2ms pulse width is output; the light source controller latches the trigger event through software logic and writes the trigger status to the cycle end flag; the buffer mechanism is configured to edge trigger or level trigger mode, and the external device is status-aware or fault-detected by querying the trigger status in the last 8 cycles through system parameter selection.

[0064] It should also be noted that a preferred embodiment of the buffering mechanism specifically includes a photo buffer table. In addition to real-time judgment, it also supports mode configuration and status recording functions.

[0065] The trigger buffer mechanism can be configured via system parameters as follows:

[0066]

[0067] in, Indicates the first Camera trigger output mode setting parameters for each light source controller This indicates rising edge triggering, suitable for high-speed edge sensing; This indicates a high-level trigger, suitable for level-sustaining cameras; at the end of each cycle, the controller will change the trigger state of that cycle. Record to the end-of-cycle flag stack Represented as:

[0068]

[0069] in, Records a maximum of the last 8 cycle trigger states; Indicates the index number of the current period.

[0070] External systems can read The state stack is used to sense the activity level of the system triggers, or to determine on the camera side whether there are anomalies such as trigger loss or delayed response.

[0071] It should also be noted that the problem of ensuring safe and reliable execution of concurrent triggering under single-channel output conditions when multiple light sources simultaneously trigger cameras is addressed. Traditional solutions typically involve adding multiple camera trigger channels, employing hardware arbitration, or simple priority overriding mechanisms. However, in high-speed industrial scenarios, these methods either rely on hardware expansion, are costly and complex, or suffer from risks such as trigger loss, duplicate triggering, or unpredictable trigger order, making it difficult to meet the high-reliability shooting requirements under single-camera interface and single-trigger channel conditions. This step proposes a process-level photo-taking request marking mechanism to uniformly aggregate concurrent triggering requests into a trigger buffer, and outputs a single fixed-width trigger signal through a unified judgment and latching strategy. This solves the structural contradiction of how concurrent triggering requests can be transformed into single-channel safe triggering at the logical architecture level. This problem involves not only signal fusion logic design but also systemic technical challenges such as periodic consistency management, trigger reliability assurance, and avoiding camera mis-shooting and missed shooting. Few existing technologies can achieve stable multi-process concurrent triggering management capabilities without adding physical interfaces or changing the overall system structure.

[0072] S3: An adjustable filter module is set at the input interface of the light source controller. Multiple filter capacitors are selected through physical DIP switches to suppress jitter of the external START frame signal of DC5-24V, and at the same time control the frame signal response delay.

[0073] Furthermore, the adjustable filtering module includes a four-position DIP switch mounted on the external panel of the light source controller. Each DIP switch corresponds to a set of parallel capacitor values: the first position corresponds to a capacitor value of 0.001uF, the second position to 0.01uF, the third position to 0.1uF, and the fourth position to 1uF. The light source controller selects the filter capacitor through the DIP switch to adjust the response sensitivity of the input frame signal. The frame signal is a DC 5-24V edge-triggered signal. The light source controller filters and amplifies the frame signal through an internal signal shaping circuit. The filter circuit consists of a limiting clamping circuit and an RC low-pass filter network. The configuration interface of the light source controller allows querying the current filter value status and manually adjusting the capacitor combination according to the interference level. The dynamic response frequency is within 50Hz.

[0074] It should also be noted that a preferred embodiment of the adjustable filtering module includes setting the external synchronization frame signal received by the light source controller as follows:

[0075]

[0076] Its signal characteristics are as follows:

[0077] Level range: , is a DC power supply pulse signal;

[0078] Triggering characteristics: Edge-triggered, mainly identified by the rising edge;

[0079] Maximum input frequency limit: The system allows a maximum frame signal frequency of 50Hz, corresponding to a minimum period of [missing information]. .

[0080] The controller is equipped with a four-position DIP switch. Each DIP switch controls whether the corresponding capacitor branch is connected:

[0081]

[0082] in, , indicating the dial switch number The switch state of the bit; The corresponding capacitance values ​​are as follows: 、 、 、 ， The filtering module essentially consists of a limiting clamping circuit to limit input voltage overshoot and reverse spikes; and an RC low-pass network to suppress high-frequency interference, with controllable response delay. The low-pass filter time constant is:

[0083]

[0084] in: This represents the filter series resistor, a fixed value; It represents the signal response delay time constant and can be used to estimate the signal edge response buffer window.

[0085] Adjust the DIP switch status Users can view the current combined capacitor value in the device interface. And manually adjust the filter strength according to the level of interference on site.

[0086] It should be noted that the frame signal response delay control includes ensuring that the light source controller's signal response delay does not exceed 15μs; employing a digital sampling window strategy, combined with the amplitude of the input signal after RC filtering, to perform single sampling confirmation and signal validity judgment; if the sampled value appears more than three times within the set fluctuation tolerance, it is considered a valid trigger signal; if the frame signal input level change frequency exceeds the system limit, the light source controller will trigger the input protection mechanism and suspend the process operation, allowing triggering again after the input stabilizes.

[0087] It should also be noted that a preferred scheme for frame signal response delay control specifically includes, to ensure that the filtered signal does not cause input misjudgment, employing a digital sampling strategy. Whenever a new frame signal edge is input, the controller will activate the sampling judgment window: the sampling period unit is: Response decision window length: The corresponding maximum number of samplings is The sampled data stream is recorded as follows:

[0088]

[0089] in, Indicates the first The input voltage sequence acquired by each light source controller during the current frame signal sampling period. Represents the input voltage sequence The first in For each voltage value sample, the system is set to allow a fluctuation tolerance of [value]. If the following conditions are met:

[0090]

[0091] If all three sets of sampled values ​​fall within the same amplitude range, the controller will consider the frame signal as a valid trigger signal. Otherwise, the sample is judged as a jitter signal or noise signal and will not enter the triggering process. If the system detects the frequency of the input frame signal within multiple consecutive cycles... Exceeding the allowed limit :

[0092]

[0093] in, During the observation period, the controller will automatically trigger the input protection mechanism and execute the following steps: suspend process task scheduling; record trigger frequency anomaly logs; maintain protection mode until the input recovers to within the allowed frequency. After the frame signal stabilizes, continuously observe for 3 cycles to ensure the frequency limit is met, then the controller will automatically unlock the protection state and re-enable the trigger judgment logic.

[0094] It should also be noted that, addressing the issues of strong interference, frequent jitter, and varying anti-interference requirements in different industrial environments for external START frame signals, this invention proposes an innovative input processing scheme that combines adjustable filtering capabilities with controllable response delay. Traditional technologies typically employ fixed RC filtering or software delay methods. However, fixed filtering cannot adapt to different interference environments; insufficient filtering can lead to false triggering, while excessive filtering can cause response lag or even miss the effective trigger window, making it difficult to achieve a dynamic balance between interference suppression and real-time performance. This step uses a DIP switch to select the filter capacitor level, combining a limiting clamp with an RC network to form a configurable physical filtering path. Simultaneously, it introduces a mechanically meaningful sampling judgment window and a multiple stable sampling confirmation mechanism to achieve signal validity determination and precise control of response delay. This collaborative architecture of hardware-adjustable filtering and software stability judgment can adapt to different electromagnetic environments and frame frequency requirements, representing a system-level anti-interference design approach distinct from traditional fixed filtering or simple delay codes. It solves not only the problem of single filtering capability but also the challenge of maintaining stable and reliable frame synchronization signals while meeting high-speed triggering requirements under harsh industrial interference scenarios.

[0095] Example 2 is an embodiment of the present invention, which provides a high-speed switching system for multi-channel zoned light sources under a light source control system, including a cascaded notification module, a buffer module, and a switching module.

[0096] The cascading notification module is used to establish a cascading notification mechanism for process completion by configuring a fixed-width END signal output and sampling the edge of the END signal between different light source controllers. It also sets a fixed synchronization waiting window in the subsequent light source controller to absorb link delay. The buffer module is used to set a process-level photo capture request flag bit and aggregate it to the camera trigger buffer when concurrent camera trigger requests occur in different processes. When the photo capture request is determined to be valid, it outputs a single fixed-width camera trigger pulse signal to the camera trigger channel. The switching module is used to set an adjustable filter module at the input interface of the light source controller. It selects multiple filter capacitors through physical DIP switches to suppress jitter of the external START frame signal of DC 5-24V and control the frame signal response delay.

Claims

1. A method for high-speed switching of multi-channel zoned light sources under a light source control system, characterized in that, include: By configuring a fixed pulse width END signal output and performing edge sampling and identification on the END signal between different light source controllers, a cascaded notification mechanism for process completion is established, and a fixed synchronization waiting window for absorbing link delay is set in the subsequent light source controller. When camera trigger requests occur concurrently in different processes, a process-level photo capture request flag is set and aggregated into the camera trigger buffer. When a photo capture request is determined to be valid, a single fixed-width camera trigger pulse signal is output to the camera trigger channel. An adjustable filter module is set at the input interface of the light source controller. Multiple filter capacitors are selected through physical DIP switches to suppress jitter of the external START frame signal of DC5-24V, and at the same time control the frame signal response delay. The END signal output includes: After each complete lighting process, the light source controller automatically outputs a high-level pulse signal. The voltage value of the high-level pulse signal is 24V, and the pulse width is fixed at 2ms. The END signal is output to the input interface of the next-level light source controller through the positive and negative terminals of END. The output action is bound to the process end status flag in the process control module inside the light source controller, and the END signal is generated by the timing module inside the light source controller at fixed intervals. The END signal uses standard TTL-compatible level logic to directly trigger the light source lighting process configured in the subsequent light source controller; Before executing each process, the light source controller checks the status of the process buffer to determine whether it has received a valid END signal edge from the previous light source controller. If the END signal is not received within the set timeout period, the light source controller will enter the waiting mode or execute a safety process. Setting process-level photo request flags includes, Within the light source controller process, whenever a light source process definition requires the output of a camera trigger identifier field, the light source controller registers the identifier field in the process parsing module, generates a valid flag bit, and writes the valid flag bit into the camera trigger buffer table. The buffer table is updated cyclically in a periodic unit. Within a control cycle, if one or more processes generate camera trigger flags, they are aggregated into a single valid trigger request. In each process cycle, the light source controller sequentially checks the status of each trigger flag bit in the camera trigger buffer table. If any flag bit is in a valid state, it confirms that there is a valid photo capture request in this cycle, calls the single trigger output module, and sends a set of high-level control signals with a pulse width of 2ms and 24V to the configured camera trigger output port. After completing a single output, the light source controller locks the state of the single triggered output module, prohibiting it from being triggered again in the current cycle. Only when the process cycle ends and the state judgment of the next cycle is re-entered can the trigger output be re-evaluated according to the new trigger conditions.

2. The high-speed switching method for multi-channel zoned light sources under the light source control system as described in claim 1, characterized in that: The fixed synchronization wait window set for absorbing link delay includes, In the internal logic of the light source controller, a time period is set to delay the triggering process after waiting for the END signal response. The time period is fixed at 5μs to 20μs and does not exceed the minimum process cycle unit of 100μs supported by the light source controller. The fixed synchronous waiting window does not affect the light source output delay setting and brightness control. It is decoupled from the process logic control module. The timer is started immediately after the light source controller receives the rising edge of the END signal. After the timer is full, the process logic control module is activated to load the next process task. It is marked and recorded in the process configuration file, allowing each process to independently define whether to enable the synchronous waiting window.

3. The high-speed switching method for multi-channel zoned light sources under the light source control system as described in claim 1, characterized in that: The unified aggregation to the camera trigger buffer includes, Before the start of each process cycle, the light source controller polls and traverses the camera trigger flag bit to establish a binary aggregation register; If the register value is not 0, a trigger signal with a fixed pulse width of 2ms will be output. The light source controller latches the trigger event through software logic and writes the trigger status to the cycle end flag. The buffer mechanism is configured to be edge-triggered or level-triggered. By selecting system parameters, the external device's status can be sensed or fault can be determined by querying the trigger status within the last 8 cycles.

4. The high-speed switching method for multi-channel zoned light sources under the light source control system as described in claim 3, characterized in that: The adjustable filter module includes... The four-position DIP switch installed on the external panel of the light source controller has each DIP switch corresponding to a set of parallel capacitor values. The first position corresponds to a capacitor value of 0.001uF, the second position is 0.01uF, the third position is 0.1uF, and the fourth position is 1uF. The light source controller selects the filter capacitor through the DIP switch to adjust the response sensitivity of the input frame signal. The frame signal is DC 5-24V, an edge-triggered signal. The light source controller filters and amplifies the frame signal through an internal signal shaping circuit. The filtering circuit consists of a limiting clamping circuit and an RC low-pass filter network. The light source controller configuration interface allows users to query the current filter value status and manually adjust the capacitor combination according to the interference level. The dynamic response frequency is within 50Hz.

5. The high-speed switching method for multi-channel zoned light sources under the light source control system as described in claim 4, characterized in that: The frame signal response delay control includes, The light source controller's signal response delay does not exceed 15μs; A digital sampling window strategy is adopted, which combines the amplitude of the input signal after RC filtering to perform single sampling confirmation and signal validity judgment. If the sampled value appears more than three times within the set fluctuation tolerance, it is considered a valid trigger signal. If the frequency of frame signal input level changes exceeds the system limit, the light source controller will trigger the input protection mechanism and suspend the process operation. Triggering will be allowed again after the input stabilizes.

6. A high-speed switching system for multi-channel zoned light sources under a light source control system, employing the high-speed switching method for multi-channel zoned light sources under a light source control system as described in any one of claims 1 to 5, characterized in that: Includes a cascading notification module, a buffer module, and a switching module; The cascading notification module is used to establish a cascading notification mechanism for process completion by configuring a fixed pulse width END signal output and performing edge sampling and identification on the END signal between different light source controllers, and to set a fixed synchronization waiting window in the subsequent light source controller to absorb link delay. The buffer module is used to set a process-level photo capture request flag bit and aggregate it into the camera trigger buffer when camera trigger requests occur concurrently in different processes, and output a single fixed-width camera trigger pulse signal to the camera trigger channel when it is determined that the photo capture request is valid. The switching module is used to set an adjustable filter module at the input interface of the light source controller. It selects multiple filter capacitors through physical DIP switches to suppress jitter of the external START frame signal of DC 5-24V, and at the same time controls the frame signal response delay.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the high-speed switching method for multi-channel zoned light sources under the light source control system according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the high-speed switching method for multi-channel zoned light sources under the light source control system as described in any one of claims 1 to 5.

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