Display substrate and display device

Abstract

The invention provides a display substrate and a display device, and relates to the technical field of display, the display device can improve the problem that a screen turns green due to electrostatic charges, and then the display effect is improved. The display substrate comprises a display area and a non-display area connected with the display area, the non-display area comprises an edge area and a first dam area, and the first dam area is located between the display area and the edge area; the display substrate further comprises a substrate; the anti-static layer is arranged on the substrate; the anti-static layer is at least located in the edge area; the driving unit and the touch unit are arranged on the substrate; wherein the driving unit is located in the display area, and the touch unit is located in the display area and the non-display area and covers the driving unit; wherein the anti-static layer and the touch control unit are arranged on the same layer, or the anti-static layer is arranged on the side, away from the substrate, of the touch control unit.

Description

[0001] This application is a divisional application based on application number 202111137439.5, filed on September 27, 2021, entitled "A display substrate and display device". The technical content of this application is derived from the earlier application with application number 202111137439.5, filed on September 27, 2021, entitled "A display substrate and display device". Technical Field

[0002] This application relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] When a user's finger continuously slides across an OLED (Organic Light-Emitting Diode) touchscreen for a period of time, a large amount of electrostatic charge is generated on the screen surface in contact with the finger. OLED touchscreens include an insulating layer containing a large number of organic polymer molecules, which causes the electrostatic charge to accumulate and undergo a polarization reaction. This leads to some of the charge being conducted to the driving backplane, ultimately causing a shift in the characteristics of the thin-film transistors (TFTs) in the driving backplane. This results in a greenish tinge at the screen edges, thus reducing the display quality. Summary of the Invention

[0004] Embodiments of this application provide a display substrate and a display device that can improve the problem of screen greening caused by electrostatic charge, thereby improving the display effect.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: On one hand, a display substrate is provided, comprising: a display area and a non-display area connected to the display area, the non-display area including an edge area and a first dam area, the first dam area being located between the display area and the edge area; The display substrate further includes: Substrate; An antistatic layer is disposed on the substrate; the antistatic layer is located at least in the edge region; A driving unit and a touch unit are disposed on the substrate; wherein, the driving unit is located in the display area, and the touch unit is located in the display area and the non-display area, and covers the driving unit; The antistatic layer and the touch unit are disposed on the same layer, or the antistatic layer is disposed on the side of the touch unit away from the substrate.

[0006] Optionally, the touch unit includes a first touch layer, a first insulating layer, a second touch layer, and a second insulating layer stacked sequentially on the driving unit; the first touch layer and the second touch layer are both located in the display area, and the first insulating layer and the second insulating layer are located in the display area and the non-display area, respectively. In this design, one of the first touch layer and the second touch layer is a metal mesh electrode layer, and the other is a bridging metal layer.

[0007] Optionally, if the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the first touch layer are disposed on the same layer. Alternatively, if the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the second touch layer are disposed on the same layer.

[0008] Optionally, the second insulating layer covers the first insulating layer, and the boundary of the second insulating layer is farther away from the first dam area than the boundary of the first insulating layer; The second insulating layer located in the non-display area is disposed on the side of the antistatic layer away from the substrate.

[0009] Optionally, the orthographic projection of the antistatic layer on the substrate overlaps with the orthographic projection of the second insulating layer on the substrate; Alternatively, the orthographic projection of the antistatic layer on the substrate lies within the orthographic projection of the second insulating layer on the substrate.

[0010] Optionally, if the antistatic layer is disposed on the side of the touch unit away from the substrate, the second insulating layer located in the non-display area is disposed on the side of the antistatic layer closer to the substrate.

[0011] Optionally, the first dam area is arranged around the display area, and the edge area is arranged around the first dam area.

[0012] Optionally, the edge region includes a cutting transition region, a crack dam region, and a drive circuit region; the crack dam region is disposed around the first dam region and is disconnected in the drive circuit region; the cutting transition region is disposed around the crack dam region and the drive circuit region. The cracked dam area includes at least one groove, which is disposed around the first dam area and disconnected in the drive circuit area; the antistatic layer at least covers a portion of the groove.

[0013] Optionally, the display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer stacked sequentially; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the first dam area, and the crack dam area; The groove at least penetrates the portion of the interlayer medium layer located in the cracked dam area.

[0014] Optionally, the display substrate further includes: a first flat portion and a first protrusion, wherein the first flat portion is located in the cutting transition area and the crack dam area; the first protrusion is located in the crack dam area, is disposed around the first dam area, and is disconnected in the driving circuit area; The first flat portion covers all the grooves, the first protrusion is disposed on the side of the first flat portion away from the substrate, and the antistatic layer covers the first protrusion.

[0015] Optionally, the integral formed by the interlayer dielectric layer, the gate insulating layer, and the buffer layer has at least one step near the edge of the cut transition zone; the first flat portion covers all the steps.

[0016] Optionally, the edge region further includes a crack detection region, which is located between the first dam region and the cracked dam region; The crack detection area includes multiple crack detection lines, and the antistatic layer covers all the crack detection lines and all the grooves.

[0017] Optionally, the antistatic layer is also located in the first dam area; The non-display area also includes a wiring area, which is located between the first dam area and the display area; The display substrate further includes: a power signal line located in the wiring area and the first dam area; the power signal line partially overlaps with the antistatic layer in a direction perpendicular to the substrate.

[0018] Optionally, the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the wiring area and the crack detection area; The first dam area includes at least one first dam, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam includes a second protrusion, a second flat portion, and a third flat portion disposed sequentially; the second flat portion covers the second protrusion, and the third flat portion covers the second flat portion; The second protrusion and the first flat portion are disposed in the same layer, and the second flat portion and the first protrusion are disposed in the same layer.

[0019] Optionally, the first dam area further includes a jumper wire and a third protrusion. The third protrusion is disposed on the side of the first dam closest to the cut transition area, near the crack dam area. The jumper wire is disposed on the side of the interlayer dielectric layer away from the substrate. The third protrusion covers the jumper wire. The third protrusion, the second protrusion, and the first flat portion are disposed in the same layer.

[0020] Optionally, the power signal line includes at least a first power line, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam is disposed on the side of the first power line away from the substrate. The first power line and the jumper are arranged in the same layer and disconnected from each other, and the third protrusion also covers the edge of the first power line near the cutting transition area; The first power line and the antistatic layer partially overlap in a direction perpendicular to the substrate.

[0021] Optionally, the power signal line further includes a second power line and a third power line; the third power line is disposed on the side of the second power line away from the substrate; The second power line is positioned near the edge of the cutting transition zone between the second protrusion and the second flat portion in the first dam closest to the cutting transition zone, and the third power line is positioned near the edge of the cutting transition zone between the second flat portion and the third flat portion in the first dam closest to the cutting transition zone.

[0022] Optionally, the display substrate further includes a plurality of light-emitting units arranged in an array; the light-emitting units are located in the display area and disposed between the driving unit and the touch unit; The light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode; the second electrode is disposed on the side of the light-emitting functional layer away from the driving unit. The driving unit includes an array of transistors, a first flat film, a plurality of transition electrodes, and a second flat film. The first flat film covers the transistors, and the transition electrodes are disposed between the first flat film and the second flat film and are electrically connected to the transistors. The first electrode is disposed on the side of the second flat film away from the substrate and is electrically connected to the transition electrode. In this configuration, the first power line is disposed on the same layer as the source and drain of the transistor; the second power line is disposed on the same layer as the transition electrode; the third power line is disposed on the same layer as the first electrode; the first flat film, the first flat portion, the second protrusion, and the third protrusion are disposed on the same layer; and the second flat film, the second flat portion, and the first protrusion are disposed on the same layer.

[0023] Optionally, the edge region includes an opening region and a transition region; the transition region is disposed around the opening region, and the first dam region is disposed around the transition region; The antistatic layer is located at least in the transition zone.

[0024] Optionally, the transition zone includes at least one second dam, which is disposed on the side of the antistatic layer near the substrate and at least partially overlaps the antistatic layer in a direction perpendicular to the substrate.

[0025] Optionally, the first dam area includes at least one third dam, which is arranged in the same layer as the second dam; The antistatic layer and the third dam do not overlap in a direction perpendicular to the substrate.

[0026] Optionally, the transition zone further includes a barrier wall located between the second dam and the third dam, and surrounding the second dam.

[0027] Optionally, the non-display area further includes an isolation area, which is located between the first dam area and the display area and is disposed around the first dam area; The isolation zone includes isolation columns, which are arranged around the first dam area.

[0028] Optionally, the non-display area further includes a wiring area, which is located between the isolation area and the display area and surrounds the isolation area; The wiring area includes multiple wirings, and the wirings in the wiring area are electrically connected to the wirings corresponding to the display area.

[0029] Optionally, the display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer stacked sequentially; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the wiring area, the isolation area, the first dam area, and the transition area; The second dam, the third dam, and the isolation column are all located on the side of the interlayer dielectric layer away from the substrate.

[0030] Optionally, the display substrate further includes a packaging unit and a plurality of light-emitting units arranged in an array; the packaging unit covers the light-emitting units and is disposed between the light-emitting units and the touch unit; the packaging unit is located in the non-display area and the display area, and the light-emitting units are located in the display area; The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially; the first inorganic encapsulation layer and the second inorganic encapsulation layer are configured to encapsulate the first dam area and the light-emitting unit; the organic encapsulation layer is configured to encapsulate the light-emitting unit and is disconnected in the first dam area.

[0031] On the other hand, embodiments of this application also provide a display device including the above-described display substrate.

[0032] Optionally, the display device further includes a packaging substrate, the packaging substrate and the display substrate being fixed together by an adhesive layer.

[0033] In the display substrate provided in this application embodiment, an anti-static layer is provided to block and release the static charge generated by the friction of fingers on the screen surface, thereby greatly reducing the charge conducted to the driving unit through the non-display area, and thus greatly reducing the probability of characteristic deviation of the transistors in the driving unit, ultimately improving the problem of greening in the edge area and improving the display effect.

[0034] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 2a and Figure 2b Top views of two display substrates provided in embodiments of this application; Figure 3 and Figure 4 For along Figure 2b Two cross-sectional views in the EE direction; Figure 5 and Figure 6 This is a schematic diagram of the structure of two touch units and an antistatic layer provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of a touch unit provided in an embodiment of this application; Figure 8-12 A schematic diagram showing the positional relationship between various first insulating layers, second insulating layers, and antistatic layers provided in embodiments of this application; Figure 13a , Figure 14-16 for Figure 2a Schematic diagrams of various cross-sections along the CC direction; Figure 13b for Figure 13a Top view before cutting; Figure 17 A driving circuit diagram provided for an embodiment of this application; Figure 18 A distribution diagram of drive signal lines provided in an embodiment of this application; Figure 19 A schematic diagram of the structure of a wiring area and a first dam area provided in an embodiment of this application; Figure 20 and Figure 21 For along Figure 2a Two cross-sectional views in the AA direction; Figure 22-25 For along Figure 2a Multiple cross-sectional views in the BB direction; Figure 26 This is a schematic diagram of a barrier wall provided in an embodiment of this application; Figure 27 This is a schematic diagram of the structure of an isolation column provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0039] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0040] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] refer to Figure 1 As shown, when a user's finger continuously slides on an OLED touchscreen for a period of time, a large amount of electrostatic charge 11 is generated on the screen surface in contact with the finger. Because the glass cover 12, the OCA (Optically Clear Adhesive) layer 13, and the POL (Polarize) layer 14 contain a large number of organic polymer molecules, the electrostatic charge accumulates and undergoes a polarization reaction, leading to the charge spreading along... Figure 1 The direction shown (indicated by dashed lines with arrows) sequentially passes through the touch layer 15, the second CVD layer 16, the IJP (Ink Jet Printing) layer 17, and the first CVD layer 18, and is conducted to the drive backplate 11. When the charge 11 travels along... Figure 1 When the charge is conducted to the CTD layer 19 in the indicated direction, some of the charge is released through the CTD layer; the other part of the charge is conducted from the edge of the CTD layer 19 to the driving backplane 10, which eventually causes the thin film transistor (TFT) 20 of the driving backplane 10 to shift, resulting in a greening phenomenon at the edge of the screen, thereby reducing the display effect. Figure 1 In the diagram, the organic light-emitting layer (EL) is labeled as 21.

[0042] Based on the above, this application provides a display substrate, including: a display area and a non-display area connected to the display area, the non-display area including an edge area and a first dam area, the first dam area being located between the display area and the edge area.

[0043] The aforementioned display area refers to the area used for display. Non-display areas are generally used for setting up driving traces and driving circuits, such as GOA (Gate Driver on Array) driving circuits, or for setting up in-screen cameras, earpieces, or speakers. This non-display area may consist of only one region; for example, it may only include... Figure 2a The A0 area shown includes an edge area A3 and a first dam area A2. The first dam area A2 surrounds the display area A1, and the edge area A3 surrounds the first dam area A2. Alternatively, the aforementioned non-display area may also include only... Figure 2aThe B0 area shown includes an edge area B6 and a first dam area B2. The edge area B6 includes an opening area B1 and a transition area B3. The transition area B3 surrounds the opening area B1, and the first dam area B2 surrounds the transition area B3. Of course, the aforementioned non-display area can also include two independent areas simultaneously. For example, the non-display area can simultaneously include... Figure 2a The A0 and B0 areas are shown; this application does not limit them. It should be noted that, for the sake of clarity in the following explanation, the A0 area can be referred to as the first non-display area, and the B0 area as the second non-display area.

[0044] The aforementioned first dam area may include at least one dam (also known as DAM) to address the problem of water and oxygen intrusion caused by ink overflow during the formation of organic encapsulation layers using inkjet printing. The number of such dams is not limited. Figure 2a In the first non-display area A0, the first dam area A2 includes two dams ( Figure 2a The following diagram illustrates the dam, labeled 38a and 38 respectively. Figure 2a The enclosure can be set around the entire display area, or it can be set around a portion of the display area; there is no limitation here, but the former is preferred for better encapsulation. The dam can include one or more layers of structure, which is not limited here.

[0045] Combination Figure 2b , Figure 3 and Figure 4 As shown, the display substrate also includes: Substrate 101; the material of the substrate is not limited, for example it may be a rigid material such as glass, or a flexible material such as PI (polyimide).

[0046] An antistatic layer 1 is disposed on the substrate 101; the antistatic layer 1 is located at least in the edge region ( Figure 3 and Figure 4 (Area A3 within the first non-display area A0).

[0047] A driving unit 3 and a touch unit 2 are disposed on a substrate 101; wherein, the driving unit 3 is located in the display area A1, and the touch unit 2 is located in the display area A1 and the non-display area (…). Figure 3 and Figure 4 The first non-display area A0 is covered by the driving unit 3.

[0048] Among them, reference Figure 4 As shown, the antistatic layer 1 and the touch unit 2 are disposed on the same layer, or, refer to Figure 3 As shown, the antistatic layer 1 is disposed on the side of the touch unit 2 away from the substrate 101.

[0049] It should be noted that, Figure 3 and Figure 4 The illustration is given using an example where the antistatic layer 1 is located in the edge area A3 of the first non-display area A0. This antistatic layer 1 can be illustrated as follows: Figure 2b The image shows a ring-shaped metal layer. The shape of the ring can be circular, rectangular, or irregular; no limitation is made here. The material of this antistatic layer can include metals or metal oxides. For example, the material of the antistatic layer can include metals such as silver, molybdenum, aluminum, or titanium, or it can also include metal oxides such as ITO (Indium Tin Oxide).

[0050] refer to Figure 3 and Figure 4 As shown, the display substrate may further include multiple light-emitting units 1d arranged in an array; the light-emitting units 1d are located in the display area A1 and disposed between the driving unit 3 and the touch unit 2. The driving unit may include multiple driving circuits, each driving circuit being used to provide a driving current to a corresponding light-emitting unit, so that the light-emitting unit emits light. (Reference) Figure 3 and Figure 4 As shown, the driving circuit may include at least one transistor 22, which may be a polysilicon transistor, such as an LTPS (Low Temperature Poly-silicon) transistor; or an oxide transistor, such as an IGZO (Indium Gallium Zinc Oxide) transistor, etc., without limitation.

[0051] The structure of the aforementioned touch unit is not limited. For example, the touch unit can adopt a mutual capacitive touch structure or a self-capacitive touch structure. The mutual capacitive touch structure or the self-capacitive touch structure can be obtained from relevant technologies, which will not be described in detail here.

[0052] The aforementioned single-layer setup refers to a process using a single patterning process. A single patterning process refers to the process of forming the required layer structure through a single exposure. A single patterning process includes processes such as masking, exposure, development, etching, and stripping.

[0053] The aforementioned antistatic layer can be disposed on the same layer as the touch unit. In this way, the antistatic layer can be formed at the same time as the touch unit, which can reduce the number of patterning processes and reduce costs. Alternatively, the antistatic layer can also be disposed on the side of the touch unit away from the substrate. That is, the touch unit can be formed first and then the antistatic layer can be formed. This can prevent the edge film layer of the touch unit from bulging, thereby preventing it from peeling and improving the performance of the display substrate.

[0054] In the display substrate provided in this application embodiment, an anti-static layer is provided to block and release the electrostatic charge generated by friction between fingers and the screen surface, thereby significantly reducing the charge conducted to the driving unit through the non-display area. This significantly reduces the probability of transistor characteristic shift in the driving unit, ultimately improving the green tint problem at the edges and enhancing the display effect. Figure 3 and Figure 4 The structure shown is used as an example for detailed explanation. (Refer to...) Figure 3 and Figure 4 As shown, when the static charge 11 generated by the friction of the finger on the screen surface is conducted to the antistatic layer 1, the antistatic layer 1 can block and release the charge, thereby greatly reducing the charge conducted to the driving unit through the non-display area, and thus greatly reducing the probability of the transistor of the driving unit experiencing characteristic deviation, ultimately improving the display effect.

[0055] In one or more embodiments, reference is made to Figure 5 and Figure 6 As shown, the touch unit 2 includes a first touch layer 25, a first insulating layer 26, a second touch layer 27, and a second insulating layer 28 stacked sequentially on the driving unit; the first touch layer 25 and the second touch layer 27 are both located in the display area, and the first insulating layer 26 and the second insulating layer 28 are located in the display area and the non-display area; wherein, one of the first touch layer and the second touch layer is a metal mesh electrode layer, and the other is a bridging metal layer.

[0056] The first touch layer can be a metal mesh electrode layer, and the second touch layer can be a bridging metal layer; alternatively, the first touch layer can be a bridging metal layer, and the second touch layer can be a metal mesh electrode layer. The latter is preferable to achieve better touch performance.

[0057] refer to Figure 7 As shown, the metal mesh electrode layer 24 may include driving electrodes (TX electrodes) 241 and sensing electrodes (RX electrodes) 242. Each row of driving electrodes 241 is directly connected and electrically connected to the touch driving unit 23 via TX lines. Each row of sensing electrodes 242 is electrically connected to the bridging metal layer through vias penetrating the first insulating layer and electrically connected to the touch driving unit 23 via RX lines. The metal mesh electrode layer 24 can be located in the display area, while the TX lines, RX lines, and touch driving unit can be located in the non-display area. The structure of this touch unit belongs to the FMLOC (Flexible Multi-Layer On Cell) touch structure. This touch structure can reduce screen thickness, thus facilitating folding; it also eliminates bonding tolerances, reducing bezel width; furthermore, it reduces the risk of cracking.

[0058] The materials of the first and second insulating layers can be any one of silicon nitride, silicon oxide, or silicon oxynitride.

[0059] To better form the first touch layer, the aforementioned touch unit may further include, for example: Figure 5 and Figure 6 The isolation layer 29 shown is disposed on the side of the first touch layer 25 away from the first insulating layer 26.

[0060] Optionally, to simplify the process and reduce manufacturing difficulty, the anti-static layer and the touch unit can be placed on the same layer, referring to... Figure 6 As shown, the antistatic layer 1 and the first touch layer 25 are disposed on the same layer, that is, the antistatic layer and the first touch layer can be formed simultaneously through a single patterning process.

[0061] Alternatively, if the anti-static layer and the touch unit are installed on the same layer, refer to... Figure 5 As shown, the antistatic layer 1 and the second touch layer 27 are disposed in the same layer, that is, the antistatic layer and the second touch layer can be formed simultaneously through a single patterning process.

[0062] Further optional, see reference Figure 8-11 As shown, the second insulating layer 28 covers the first insulating layer 27, and the boundary of the second insulating layer 28 is farther away from the first dam area than the boundary of the first insulating layer 27; the second insulating layer 28 located in the non-display area is disposed on the side of the antistatic layer 1 away from the substrate 101.

[0063] Optional, see reference Figure 8 , Figure 9 , Figure 11 As shown, the orthographic projection S1 of the antistatic layer 1 on the substrate 101 partially overlaps with the orthographic projection S2 of the second insulating layer 28 on the substrate 101; or, referring to Figure 10 As shown, the orthographic projection S1 of the antistatic layer 1 on the substrate 101 is located within the orthographic projection S2 of the second insulating layer 28 on the substrate 101.

[0064] The distance between the edge of the antistatic layer furthest from the display area and the edge of the edge area furthest from the display area is not limited. For example, see reference. Figure 8 , Figure 10 , Figure 11 As shown, a certain distance D can exist between the edge of the antistatic layer away from the display area and the edge of the edge area away from the display area. The size of this distance is not limited, for example: Figure 8 and Figure 11 D in the figure can be 50 μm. Figure 10 D in the figure can be 80 μm; or, refer to Figure 9As shown, the edge of the antistatic layer away from the display area roughly coincides with the edge of the edge area away from the display area. "Roughly coincident" here includes both actual coincidence and coincidence within the range of manufacturing tolerances.

[0065] Figure 9 In the structure shown, the antistatic layer has a large area, which allows it to absorb and release static charge more quickly and effectively.

[0066] Optionally, if the antistatic layer is disposed on the side of the touch unit away from the substrate, refer to Figure 12 As shown, the second insulating layer 28 located in the non-display area is disposed on the side of the antistatic layer 1 near the substrate 101.

[0067] It should be noted that, Figure 7-12 Only the positional relationship between the first insulating layer, the second insulating layer, and the antistatic layer is shown; other structures are not shown.

[0068] The structure when the anti-static layer is set in the first non-display area A0 is described in detail below.

[0069] In one or more embodiments, reference is made to Figure 2a As shown, within the first non-display area A0, the first dam area A2 surrounds the display area A1, and the edge area A3 surrounds the first dam area A2.

[0070] refer to Figure 2a As shown, within the first non-display area A0, the edge area A3 includes a cutting transition area A4, a crack dam area A5, and a driving circuit area A6; the crack dam area A5 surrounds the first dam area A2 and is disconnected in the driving circuit area A6; the cutting transition area A4 surrounds the crack dam area A5 and the driving circuit area A6.

[0071] Combination Figure 2a and Figure 13a , Figure 14-16 The cracked dam area A5 includes at least one groove 33, which is arranged around the first dam area A2 and disconnected in the drive circuit area A6; the antistatic layer 1 covers at least part of the groove.

[0072] The number of the aforementioned grooves is not limited. Figure 13a , Figure 14-16 The illustration uses five consecutively spaced grooves as an example. These grooves reduce and disperse the stress generated during cutting, thereby lowering the risk of cracks. Therefore, these grooves can also be called crack dams. The depth of these grooves perpendicular to the substrate is not limited and can be determined based on the specific circumstances.

[0073] It should be noted that if the driving circuit area A6 adopts a pad bending structure (that is, bending the pad area to the non-display surface of the substrate), the break position of the groove corresponds to the lead area (fanout area) on the bending area; if the driving circuit area A6 adopts a non-pad bending structure, the break position of the groove corresponds to the pad area (bonding area).

[0074] Optional, see reference Figure 13a , Figure 14-16 As shown, the display substrate also includes: a buffer layer 102, a gate insulating layer 100 and an interlayer dielectric layer 103 stacked sequentially; the interlayer dielectric layer 103, the gate insulating layer 100 and the buffer layer 102 are all located in the display area, the first dam area and the crack dam area; the groove 33 at least penetrates the portion of the interlayer dielectric layer 103 located in the crack dam area A5.

[0075] It should be noted that groove 33 can be as follows: Figure 13a , Figure 14-16 The groove can be shown to penetrate only the portion of the interlayer dielectric layer 103 located in the crack dam region A5; or, the groove can also penetrate the portions of both the interlayer dielectric layer and the grid insulation layer located in the crack dam region; or, the groove can also penetrate the portions of the interlayer dielectric layer, the grid insulation layer, and the buffer layer located in the crack dam region, which is not limited here.

[0076] In addition, the display substrate may also include: an isolation layer located between the substrate and the buffer layer, the isolation layer being located in the display area, the first dam area and the crack dam area; the aforementioned groove may also penetrate the portions of the interlayer dielectric layer, the gate insulating layer, the buffer layer and the isolation layer located in the crack dam area.

[0077] Optional, see reference Figure 13a , Figure 14-16 As shown, the display substrate further includes: a first flat portion 41 and a first protrusion 34, wherein the first flat portion 41 is located in the cutting transition region A4 and the crack dam region A5; Reference Figure 2a As shown, the first protrusion 34 is located in the cracked dam area A5, is arranged around the first dam area A2, and is disconnected in the drive circuit area A6.

[0078] refer to Figure 13a , Figure 14-16 As shown, the first flat portion 41 covers all the grooves 33, the first protrusion 34 is disposed on the side of the first flat portion 41 away from the substrate 101, and the antistatic layer 1 covers the first protrusion 34.

[0079] It should be noted that if the driving circuit area A6 adopts a pad bending structure (that is, bending the pad area to the non-display surface of the substrate), the break position of the first protrusion corresponds to the lead area (fanout area) on the bending area; if the driving circuit area A6 adopts a non-pad bending structure, the break position of the first protrusion corresponds to the pad area (bonding area).

[0080] The aforementioned first flat portion covers and fills all the grooves, which can further reduce the risk of cracks generated during cutting, and at the same time facilitates the deposition of the antistatic layer.

[0081] refer to Figure 13a , Figure 14-16 As shown, the integral formed by the interlayer dielectric layer 103, the gate insulating layer 100, and the buffer layer 102 has at least one step 35 near the edge of the cutting transition region A4; the first flat portion 41 covers all steps 35.

[0082] The aforementioned interlayer dielectric layer, grid insulating layer, and buffer layer are mostly made of inorganic materials. When patterned using a dry engraving process, residues are easily generated, forming the aforementioned steps. The aforementioned first flat portion covers all steps, which can provide better protection.

[0083] Optional, see reference Figure 13a , Figure 14-16 As shown, the edge region also includes crack detection zone A7, which is located between the first dam zone A2 and the cracked dam zone A5; Reference Figure 13a , Figure 14-15 As shown, the crack detection area A7 includes multiple crack detection lines 36, and the antistatic layer 1 covers all crack detection lines 36 and all grooves 33.

[0084] The number of crack detection lines mentioned above is not limited. Figure 13a , Figure 14-16 The illustration is based on four examples.

[0085] The aforementioned crack detection area is mainly used for crack detection to improve product yield and reduce production costs.

[0086] It should be noted that the reference Figure 16 As shown, the antistatic layer 1 may only cover part of the groove 33, without covering the crack detection line 36.

[0087] Optional, see reference Figure 13a , Figure 14-15 As shown, antistatic layer 1 is also located in area A2 of the first dam area; Reference Figure 2a As shown, the non-display area also includes the wiring area A8, which is located between the first dam area A2 and the display area A1.

[0088] refer to Figure 13a , Figure 14-15 As shown, the display substrate also includes: a power signal line 37, which is located in wiring area A8 and first dam area A2; Reference Figure 13a , Figure 14-15 As shown, the power signal line 37 and the antistatic layer 1 partially overlap in the direction perpendicular to the substrate 101; thus, the static charge generated by the finger rubbing against the screen surface can be absorbed and released through the power signal line and the antistatic layer respectively. The partial overlap of the power signal line and the antistatic layer in the direction perpendicular to the substrate can further ensure the effect of absorbing and releasing static charge.

[0089] It should be noted that the reference Figure 16 As shown, if the antistatic layer 1 is only located in the cutting transition area A4 and the crack dam area A5, then the antistatic layer 1 and the power signal line 37 do not overlap in the direction perpendicular to the substrate 101.

[0090] The aforementioned wiring area A8 can be used to house power signal lines, ELVSS, and other signal lines. This display substrate can be adopted as follows: Figure 17 The 7T1C driver circuit shown (the driving principle of this circuit can be obtained from relevant technologies and will not be elaborated here) includes seven thin-film transistors (T1-T7), capacitor C1, and an OLED. Except for driver transistor T3, each transistor is controlled by a different drive signal, such as: ELVSS power signal, Vdata signal, gate signal, EM signal, Vinit signal, ELVDD signal, and reset signal. These drive signals are provided by corresponding drive signal lines. The ELVSS power signal line, Vinit signal line, etc., can be found in [reference needed]. Figure 18 The setup is as shown. The ELVSS power signal line can be electrically connected to the cathode located in the display area via a via, and the cathode is typically a single layer in the display area. There is no limit to the number of layers included in the ELVSS power signal line; for example, it can include two layers (a single SD structure) or three layers (a dual SD structure), for example... Figure 13a , Figure 14-15 The first power line 371, the second power line 372, and the third power line 373 shown are provided in the following ways: the third power line 373 can be disposed on the same layer as the first electrode (used as an anode) located in the display area to prevent the circuit below from being interfered with by light or electrostatic discharge; the first power line 371 can be disposed on the same layer as the source and drain of the transistor located in the display area; and the second power line 372 can be disposed on the same layer as the transition electrode located in the display area.

[0091] Optional, see reference Figure 13a , Figure 14-16As shown, the interlayer dielectric layer 103, the gate insulating layer 100, and the buffer layer 102 are all located in the wiring area ( Figure 13a , Figure 14-16 (Not shown) and crack detection area A7.

[0092] The first dam area A2 includes at least one first dam 38, which is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101. The first dam 38 includes a second protrusion 381, a second flat portion 382 and a third flat portion 383 arranged sequentially. The second flat portion 382 covers the second protrusion 381 and the third flat portion 383 covers the second flat portion 382. The second protrusion 381 and the first flat portion 41 are disposed on the same layer, and the second flat portion 382 and the first protrusion 34 are disposed on the same layer.

[0093] There is no limit to the number of first-level dikes here. For example, to improve ink spill prevention, two first-level dikes can be used. The structure of two first-level dikes can be referenced. Figure 19 As shown, the substrate includes two first dams, labeled 38a and 38, respectively. The height of the first dam 38a near the wiring area A8 in a direction perpendicular to the substrate 101 is lower than the height of the first dam 38 away from the wiring area A8 in a direction perpendicular to the substrate 101. The first dam 38a near the wiring area A8 blocks the organic encapsulation layer 118b.

[0094] Optional, see reference Figure 13a , Figure 14-16 As shown, the first dam area A7 also includes a jumper 39 and a third protrusion 40. The third protrusion 40 is disposed on the side of the first dam 38 closest to the cut transition area A4, near the crack dam area A5. The jumper 39 is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101. The third protrusion 40 covers the jumper 39. The third protrusion 40, the second protrusion 381, and the first flat portion 41 are disposed in the same layer.

[0095] The jumpers mentioned above can discharge static electricity and reduce its impact on the signal lines. Optional, see reference Figure 13a , Figure 14-16 As shown, the power signal line 37 includes at least a first power line 371, which is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101; a first dam 38 is disposed on the side of the first power line 371 away from the substrate 101. The first power line 371 and the jumper 39 are disposed in the same layer and disconnected from each other, and the third protrusion 40 also covers the edge of the first power line 371 near the cutting transition region A4.

[0096] refer to Figure 13a , Figure 13b , Figure 14 , Figure 15 As shown, the first power line 371 and the antistatic layer 1 partially overlap in a direction perpendicular to the substrate 101. Figure 13b Cutting along the cutting line can form Figure 13a The structure shown. Figure 13b This is a top view of the substrate. (Reference) Figure 13b As shown, the antistatic layer 1 extends 50 μm beyond the cutting line along the C1C2 direction. Therefore, after cutting, the antistatic layer roughly coincides with the edge of the edge region. The width of the cut antistatic layer along the C1C2 direction is 335 μm, and the width of the portion where the first power line 371 overlaps with the antistatic layer 1 in a direction perpendicular to the substrate is 5 μm. Of course, the width of the antistatic layer along the C1C2 direction and the width of the overlapping portion of the antistatic layer and the first power line along the C1C2 direction can be selected according to the actual design. Here, only the above width values ​​are used as an example for explanation. Figure 13a The relative positional relationship between the first power line and the antistatic layer is explained in the corresponding uncut structure. Figure 14-16 The situation is similar, so I won't go into details here.

[0097] The aforementioned first power line can be disposed on the same layer as the source and drain terminals of the transistor located in the display area. The aforementioned first power line and the anti-static layer can simultaneously absorb and release static charges, further mitigating the adverse effects of static charges.

[0098] Optional, see reference Figure 13a , Figure 13b , Figure 14-16 As shown, the power signal line 37 also includes a second power line 372 and a third power line 373; the third power line 373 is disposed on the side of the second power line 372 away from the substrate 101.

[0099] The second power line 372 is positioned between the second protrusion 381 and the second flat portion 382 in the first dam 38 closest to the cutting transition zone A4, and the third power line 373 is positioned between the second flat portion 382 and the third flat portion 383 in the first dam 38 closest to the cutting transition zone A4, near the edge of the cutting transition zone A4.

[0100] Figure 13a , Figure 14-16In this configuration, the power signal line 37 includes a first power line 371, a second power line 372, and a third power line 373, forming a dual SD structure. The third power line 373 can be disposed on the same layer as the first electrode (used as the anode) located in the display area to prevent interference from light or electrostatic discharge to the circuitry below. The first power line 371 can be disposed on the same layer as the source and drain electrodes of the transistor located in the display area. The second power line 372 can be disposed on the same layer as the transition electrode located in the display area. The power signal line can be electrically connected to the cathode located in the display area via a via.

[0101] In one or more embodiments, reference is made to Figure 3 and Figure 4 As shown, the display substrate may also include multiple light-emitting units 1d arranged in an array; the light-emitting units 1d are located in the display area A1 and are disposed between the driving unit 3 and the touch unit 2.

[0102] refer to Figure 20 and Figure 21 As shown, the light-emitting unit 1d includes a first electrode 112, a light-emitting functional layer 114a, and a second electrode 115; the second electrode 115 is disposed on the side of the light-emitting functional layer 114a away from the driving unit.

[0103] refer to Figure 21 As shown, the driving unit includes multiple transistors T arranged in an array, multiple transition electrodes 133, and a planarization layer 116. The planarization layer 116 includes a first planarization film 116a and a second planarization film 116b. The first planarization film 116a covers the transistors T. The transition electrodes 133 are disposed between the first planarization film 116a and the second planarization film 116b and are electrically connected to the transistors T. The first electrode 112 is disposed on the side of the second planarization film 116b away from the substrate 101 and is electrically connected to the transition electrodes 133.

[0104] In this configuration, the first power line is disposed on the same layer as the source and drain of the transistor; the second power line is disposed on the same layer as the transition electrode; the third power line is disposed on the same layer as the first electrode; the first planarization film, the first planar portion, the second protrusion, and the third protrusion are disposed on the same layer; and the second planarization film, the second planar portion, and the first protrusion are disposed on the same layer.

[0105] Figure 20 and Figure 21In this transistor T, a first electrode 110, a second electrode 111, a control electrode 106, and an active layer 104 are included. Either the first electrode 110 or the second electrode 111 is used as the source, and the other is used as the drain. The control electrode 106 can be used as the gate. The type of transistor is not limited here; it can be a top-gate thin-film transistor or a bottom-gate thin-film transistor. Based on the positional relationship of the three electrodes, transistors can be divided into two categories: one where the gate is located below the source and drain (bottom-gate transistor); and another where the gate is located above the source and drain (top-gate transistor). Figure 20 and Figure 21 The diagram is illustrated using a top-gate type. The material of the active layer is not limited here; it can be an oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), etc.; it can also be LTPS (Low Temperature Poly-silicon); and of course, it can also be single-crystal silicon, etc.

[0106] refer to Figure 20 and Figure 21 As shown, the substrate may further include a first gate insulator layer 105, a second gate insulator layer 108, an interlayer dielectric layer 103, a passivation layer 134, and a capacitor unit. The capacitor unit may include a first electrode 130 and a second electrode 131. The first electrode 130 is disposed on the same layer as the gate 106, and the second electrode 131 is located between the second gate insulator layer 108 and the interlayer dielectric layer 103, and is disposed opposite to the first electrode 130.

[0107] It should be noted that if no capacitor unit is provided, only one gate insulator layer is needed. The aforementioned first and second gate insulator layers can also be placed in the non-display area to form a gate insulating layer.

[0108] The materials for the aforementioned gate, first electrode, and second electrode can include metallic or alloy materials, such as molybdenum, aluminum, or titanium. The materials for the first and second electrodes can also include metallic or alloy materials, such as single-layer or multi-layer metal structures formed from molybdenum, aluminum, or titanium. For example, the multi-layer structure is a multi-metal stack, such as a titanium, aluminum, and titanium three-layer stack (Al / Ti / Al). The aforementioned planarization layer is typically made of organic materials, such as photoresist, acrylic polymers, or silicon polymers.

[0109] The first electrode described above can be used as the anode, which can be made of materials such as ITO (indium tin oxide), indium zinc oxide (IZO), or zinc oxide (ZnO); (See reference) Figure 20 and Figure 21 As shown, the substrate also includes a pixel defining portion 113, which is disposed on the side of the planarization layer 116 away from the substrate 101. The pixel defining portion 113 can be made of organic materials, such as photoresist, and the portion of the pixel defining portion 113 located in the display area A1 has a pixel opening that exposes the first electrode 112. The light-emitting functional layer 114a is located in the pixel opening and formed on the first electrode 112. The light-emitting functional layer can include small molecule organic materials or polymer molecule organic materials, or it can also be a fluorescent light-emitting material or a phosphorescent light-emitting material, which can emit red light, green light, or blue light, etc. In addition, depending on the actual needs, in different examples, the light-emitting functional layer can further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. The second electrode covers the light-emitting functional layer. This second electrode 115 can be used as a cathode, and its material can be a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag).

[0110] It should be noted that, as Figure 20 and Figure 21 As shown, the first electrode 112, the light-emitting functional layer 114a, and the second electrode 115 can constitute a light-emitting unit 1d. The portion of this substrate located in the display area may include multiple light-emitting units arranged in an array. Furthermore, it should be noted that the first electrode of each light-emitting unit is independent, while the second electrode of each light-emitting unit is an integral structure and can be disposed as a single layer.

[0111] In one or more embodiments, reference is made to Figure 20 and Figure 21 As shown, a support portion 132 may also be provided on the side of the pixel defining portion 113 away from the substrate 101. This support portion 132 can support the protective film layer. Figure 20 and Figure 21 The protective film (not shown) serves to prevent the first electrode 112 or other traces from coming into contact with each other, thus avoiding potential damage to the first electrode 112 or other traces. It should be noted that this protective film is primarily used during the transfer of semi-finished products to prevent damage during this process. Specifically, a protective film can be applied during the transfer of the substrate with the support portion 132 to the evaporation line. This protective film is removed when the luminescent material needs to be deposited.

[0112] For example, the material of the support portion 132 may be the same as the material of the pixel defining portion 113, and the support portion 132 and the pixel defining portion 113 may be formed using the same patterning process. However, it is not limited to this. The material of the support portion 132 may also be different from the material of the pixel defining portion 113, and the support portion 132 and the pixel defining portion 113 may also be formed using different patterning processes.

[0113] In one or more embodiments, reference is made to Figure 20 As shown, the first electrode 112 can be directly electrically connected to the second electrode 111 through the vias in the planarization layer 116. Figure 3 The structure shown is a single SD structure. In this case, the power signal line located in the non-display area can include a two-layer structure. For example, the power signal line can include two power lines. One power line is set on the same layer as the first and second electrodes (i.e., source and drain electrodes) of the transistor; the other power line is set on the same layer as the first electrode.

[0114] In one or more embodiments, reference is made to Figure 21 As shown, the first electrode 112 can also be electrically connected to the second electrode 111 via a transfer electrode 133. When the first electrode 112 is electrically connected to the second electrode 111 via the transfer electrode 133, the planarization layer 116 can be a double-layer structure, specifically including a first planarization film 116a and a second planarization film 116b formed sequentially. In addition, a passivation layer 134 can be formed between the first planarization film layer 116a and the interlayer dielectric layer 103. The passivation layer 134 can be formed of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The passivation layer 134 covers the first electrode 110 and the second electrode 111. It should be noted that... When the planarization layer 116 is a single layer, a passivation layer 134 can also be formed between the planarization layer 116 and the interlayer dielectric layer 103; the transition electrode 133 is formed between the first planarization film 116a and the second planarization film 116b, and is electrically connected to the second electrode 111 through vias (e.g., metal vias) on the first planarization film 116a and the passivation layer 134; and the first electrode 112 can be electrically connected to the transition electrode 133 through vias (e.g., metal vias) on the second planarization film 116b, such as... Figure 4 As shown. However, it is not limited to this, the transfer electrode 133 may also be formed between the first planar film 116a and the passivation layer 134.

[0115] Figure 21 The structure shown is a dual SD structure. In this case, the power signal lines located in the non-display area can include a three-layer structure. For example, the power signal lines can include, as shown below: Figure 13a , Figure 14-15 The first power line 371, the second power line 372, and the third power line 373 shown are configured such that the first power line is on the same layer as the first and second electrodes (i.e., source and drain) of the transistor; the second power line is on the same layer as the transition electrode; and the third power line is on the same layer as the first electrode. (Combined with...) Figure 21 and Figure 13a , Figure 14-16 The first flat film 116a, the first flat portion 41, the second protrusion 381 and the third protrusion 40 are arranged in the same layer; the second flat film 116b, the second flat portion 382 and the first protrusion 34 are arranged in the same layer. This can reduce the number of patterning processes and reduce the manufacturing cost.

[0116] In one or more embodiments, reference is made to Figure 3 and Figure 4 As shown, the display substrate also includes a packaging unit 118 and a plurality of light-emitting units 1d arranged in an array; the packaging unit 118 covers the light-emitting units 1d and is disposed between the light-emitting units 1d and the touch unit 2; the packaging unit 118 is located in the non-display area and the display area, and the light-emitting units are located in the display area.

[0117] refer to Figure 20 and Figure 21 As shown, the encapsulation layer 118 includes a first inorganic encapsulation layer 118a, an organic encapsulation layer 118b, and a second inorganic encapsulation layer 118c, which are stacked sequentially; combined with Figure 20 , Figure 21 and Figure 19 As shown, the first inorganic encapsulation layer 118a and the second inorganic encapsulation layer 118c are configured to encapsulate the first dam region A2 and the light-emitting unit 1d; the organic encapsulation layer 118b is configured to encapsulate the light-emitting unit 1d and is disconnected in the first dam region A2.

[0118] The first and second inorganic encapsulation layers can be formed using chemical vapor deposition (CVD), but are not limited to this process; alternatively, they can also be formed using physical vapor deposition (PVD), etc. The organic encapsulation layer can be formed using inkjet printing, but is not limited to this process; alternatively, it can also be formed using spraying, etc. During the fabrication of the organic encapsulation layer, because the organic encapsulation material has a certain degree of fluidity, a dam needs to be set up in the first dam area to prevent the organic encapsulation material from overflowing, thereby avoiding encapsulation failure.

[0119] The structure when the anti-static layer is set in the second non-display area B0 is described in detail below.

[0120] In one or more embodiments, reference is made to Figure 2a As shown, within the non-display area B0, the edge area B6 includes an opening area B1 and a transition area B3; the transition area B3 surrounds the opening area B1, and the first dam area B2 surrounds the transition area B3; wherein, reference Figure 22-25 As shown, the antistatic layer 1 is located at least in the transition zone B3.

[0121] It should be noted that, after the opening process, the B1 area of ​​the display substrate in this application is used to assemble devices such as cameras, sensors, home buttons, earpieces, or speakers. For the display substrate of this application, it can be as follows... Figure 22 and Figure 24 As shown, area B1, which has no opening, will be opened before assembling the camera and other components. Alternatively, it can be done as follows: Figure 23 and Figure 25 As shown, the aperture area B1 has been opened, and under this condition, the display substrate can be directly assembled.

[0122] The shape of the opening area is not limited here; it can be a racetrack hole or a circular hole, etc. After the opening process, the resulting opening can be, but is not limited to, the following forms: through holes, grooves, and openings. Furthermore, the number of opening areas is not limited; for example, this display substrate can have a single hole or two holes. Figure 2a The illustration is based on a single hole.

[0123] The aforementioned antistatic layer being located at least in the transition zone includes: the antistatic layer being located only in the transition zone; or, the antistatic layer being located in the transition zone and the first dam zone; or, the antistatic layer being located in the transition zone and the opening zone; or, the antistatic layer being located in the transition zone, the opening zone, and the first dam zone, etc., without limitation. Figure 22-25 The illustration is based on a portion of the first dam area where the antistatic layer is located, as well as the entire transition zone and the perforation zone. The aforementioned antistatic layer can block and release static charge, thereby significantly reducing the charge conducted through the transition region, which in turn reduces the probability of transistor characteristic shift in the driving unit, ultimately improving the display effect.

[0124] Optional, see reference Figure 24 and Figure 25 As shown, the transition region B3 includes at least one second dam 1c, which is disposed on the side of the antistatic layer 1 near the substrate 101 and at least partially overlaps with the antistatic layer 1 in a direction perpendicular to the substrate 101.

[0125] The aforementioned overlap of the second dam and the antistatic layer in a direction perpendicular to the substrate includes: the second dam and the antistatic layer partially overlap in a direction perpendicular to the substrate, in which case the orthographic projection of the second dam onto the substrate partially overlaps with the orthographic projection of the antistatic layer onto the substrate. Alternatively, the second dam and the antistatic layer completely overlap in a direction perpendicular to the substrate, in which case the orthographic projection of the second dam onto the substrate is located within the orthographic projection of the antistatic layer onto the substrate. Figure 24 and Figure 25 In the middle, the antistatic layer 1 is located in the entire area of ​​the transition region B3, and the second dam 1c overlaps with the antistatic layer 1 in a direction perpendicular to the substrate 101.

[0126] The specific number of second dikes is not specified here. Figure 24-25 The illustration is based on a second dam.

[0127] refer to Figure 24-25 As shown, the second dam 1c may include a first protective part 140, a first barrier part 141 and a first diaphragm part 142 arranged in sequence.

[0128] In one or more embodiments, combined Figure 21 and Figure 24 As shown, the first protective portion 140 can be disposed in the same layer as the first electrode 112 in the aforementioned display area. Since the first conductive film covers the interlayer dielectric layer 103 located in the transition region B3, the interlayer dielectric layer 103 in the transition region B3 will not be cleaned by the etching solution during the patterning process of forming the first electrode 112. This reduces the number of times the interlayer dielectric layer 103 in the transition region B3 is cleaned by the etching solution, thereby improving the adhesion of the interlayer dielectric layer 103 in the transition region B3. Furthermore, the first protective portion 140 can also be formed simultaneously during the formation of the first electrode 112. Therefore, the first protective portion 140 can continue to protect the interlayer dielectric layer 103 located in the transition region B3, preventing the etching solution in the subsequent patterning process from cleaning the interlayer dielectric layer 103 in the transition region B3. Since the first protective portion 140 and the first electrode 112 are formed in a single patterning process, the number of processing steps and the use of a mask can be reduced, thereby lowering costs.

[0129] In one or more embodiments, combined Figure 21 and Figure 24 As shown, the first protective portion 140 can be disposed in the same layer as the planarization layer 116. Since the planarization film covers the interlayer dielectric layer 103 located in the transition region B3, the interlayer dielectric layer 103 located in the transition region B3 will not be cleaned by the etching solution during the patterning process of forming the planarization layer 116. This reduces the number of times the interlayer dielectric layer 103 in the transition region B3 is cleaned by the etching solution, thereby improving the adhesion of the interlayer dielectric layer 103 located in the transition region B3. Furthermore, since the first protective portion 140 is also formed during the formation of the planarization layer 116, it can continue to protect the interlayer dielectric layer 103 located in the transition region B3, preventing the etching solution in the subsequent patterning process from cleaning the interlayer dielectric layer 103 located in the transition region B3. Because the first protective portion 140 and the planarization layer 116 are formed in a single patterning process, the number of processing steps and the use of a mask can be reduced, thereby lowering costs.

[0130] In one or more embodiments, combined Figure 21 and Figure 24As shown, the first barrier portion 141 can be disposed on the same layer as the pixel defining portion 113 in the aforementioned display area. Therefore, the first barrier portion 141 and the pixel defining portion 113 are made of the same material, which is also an organic material. In this embodiment, the first protective portion 140 is disposed on the same layer as the planarization layer 116, so that the material of the first protective portion 140 is the same as the material of the planarization layer 116, which is also an organic material. The material of the first protective portion 140 can be the same as the material of the first barrier portion 141. This design can improve the bonding force between the first protective portion 140 and the first barrier portion 141, ensure the structural stability of the second encapsulation dam 1c, and prevent the first barrier portion 141 from falling off the first protective portion 140, thereby further reducing the risk of encapsulation failure, improving the encapsulation yield, and ensuring the display effect and product lifespan.

[0131] The first spacer portion can be disposed in the same layer as the support portion 132 in the aforementioned display area. It can increase the thickness of the second dam 1c in the direction perpendicular to the substrate. The first spacer portion can block the organic encapsulation material in the encapsulation unit 118 from flowing to the opening area B1, further improving the restriction on the flow of organic encapsulation material in the encapsulation unit and further improving the reliability of the display substrate encapsulation.

[0132] Of course, the aforementioned second dam may also include a two-layer structure; this is not a limitation here. The specific details can be determined based on the actual situation.

[0133] In this application, by setting up a second dam, the barrier effect can be further improved, so that the transition zone can fully isolate the opening area and the display area, prevent impurities such as water and oxygen from entering the display area from the opening area, and prevent the cracks that may form in the opening area from spreading to the display area.

[0134] It should be noted that, in one or more embodiments, in order to save space, reference is made to... Figure 22-23 As shown, no second dam is set in the transition zone B3, and the dam in the first dam zone can be used to block the organic encapsulation material.

[0135] In one or more embodiments, reference is made to Figure 22-25 As shown, the first dam area B2 includes at least one third dam, which is disposed in the same layer as the second dam; wherein, the antistatic layer 1 and the third dam do not overlap in the direction perpendicular to the substrate.

[0136] The number of the aforementioned third dikes is not limited. Figure 22-25 The diagram is illustrated using the first dam area B2, which includes two third dams, as an example. The two third dams are labeled 1b and 1a, respectively.

[0137] refer to Figure 22-25As shown, the structures of the third dam 1b near the second dam 1c and the third dam 1a far from the second dam 1c are the same as those of the second dam 1c and are arranged on the same layer. The beneficial effects of the corresponding structures are also similar, and will not be described in detail here. Specifically, the third dam 1b near the second dam 1c includes a second protective part 120, a second barrier part 121, and a second diaphragm part 123 arranged in successive layers; the third dam 1a far from the second dam 1c includes a third protective part 119, a third barrier part 117, and a third diaphragm part 122 arranged in successive layers.

[0138] The first protective part, the second protective part, and the third protective part are arranged in the same layer; the first barrier part, the second barrier part, and the third barrier part are arranged in the same layer; the first septum part, the second septum part, and the third septum part are arranged in the same layer.

[0139] The thickness of the third dam 1b, which is closer to the second dam 1c, along the direction perpendicular to the substrate can be greater than the thickness of the third dam 1a, which is farther from the second dam 1c, along the same direction perpendicular to the substrate, to better achieve the barrier effect. For example, the thickness of the second protective portion along the direction perpendicular to the substrate can be greater than the thickness of the third protective portion along the same direction perpendicular to the substrate. The thickness of the second and third barrier portions along the direction perpendicular to the substrate is the same, and the thickness of the second and third spacer portions along the same direction perpendicular to the substrate is also the same. This achieves the effect that the thickness of the third dam 1b, which is closer to the second dam 1c, along the direction perpendicular to the substrate is greater than the thickness of the third dam 1a, which is farther from the second dam 1c, along the same direction perpendicular to the substrate. Of course, the different heights of the two dams can also be achieved in other ways.

[0140] The aforementioned third dam can effectively block organic encapsulation materials, thereby improving the encapsulation and display effects.

[0141] In one or more embodiments, reference is made to Figure 24 and Figure 25 As shown, the transition zone B3 also includes a barrier wall 135, which is located between the second dam 1c and the third dam 1b and is arranged around the second dam 1c.

[0142] The aforementioned barrier wall is disposed on the side of the antistatic layer closest to the substrate; the barrier wall and the antistatic layer may or may not overlap in a direction perpendicular to the substrate, depending on the specific requirements. Figure 24 and Figure 25 The diagram is illustrated by taking the barrier wall and the antistatic layer as completely overlapping in a direction perpendicular to the substrate. In this case, the orthographic projection of the barrier wall on the substrate is located within the orthographic projection of the antistatic layer on the substrate.

[0143] Combination Figure 21 and Figure 26The barrier wall may include a first film layer 136 disposed in the same layer as the control electrode 106 and the first electrode plate 130, a second film layer 137 disposed in the same layer as the second electrode plate 131, a third film layer 138 disposed in the same layer as the first electrode 110 and the second electrode 111, a second gate insulator layer 108 located between the first film layer 136 and the second film layer 137, and an interlayer dielectric layer 103 located between the third film layer 138 and the second film layer 137. That is, the first film layer 136, the control electrode 106, and the first electrode plate 130 have the same structure and include the same material, and can be manufactured by a single patterning process; the second film layer 137 and the second electrode plate 131 have the same structure and include the same material, and can be manufactured by a single patterning process; the third film layer 138 has the same structure as the first electrode 110 and the second electrode 111, and includes the same material, and can be manufactured by a single patterning process.

[0144] In one or more implementations, refer to Figure 24 and Figure 25 As shown, the transition zone B2 may also include an organic insulating encapsulation part 139, which is located between the second dam 1c and the third dam 1b and covers the barrier wall 135. The organic insulating encapsulation part 139 is made of the same material as the organic encapsulation layer 118b of the encapsulation unit 118, and both can be formed by the same inkjet printing process.

[0145] In this application, by setting a second encapsulation dam 1c, a barrier wall 135, and an organic insulating encapsulation part 139, a further barrier effect is provided, so that the transition zone B3 can fully isolate the opening zone B1 and the display zone A1, preventing impurities such as water and oxygen from entering the display zone A1 from the opening zone B1, and preventing cracks that may be formed when the opening zone B1 is formed from extending to the display zone A1.

[0146] Additionally, refer to Figure 24 and Figure 25 As shown, in the transition zone B3, which includes the second dam 1c, the barrier wall 135, and the organic insulating encapsulation part 139, the aforementioned first inorganic encapsulation layer 118a also covers the second dam 1c and the barrier wall 135; the organic encapsulation layer 118b and the organic insulating encapsulation part 139 are formed by inkjet printing; the second inorganic encapsulation layer 118c also covers the second dam 1c, the barrier wall 135, and the organic insulating encapsulation part 139. (Reference) Figure 24 and Figure 25 As shown, when the first dam area B2 includes the third dams 1b and 1a, the first inorganic encapsulation layer 118a and the second inorganic encapsulation layer 118c also cover the third dams 1b and 1a, and the organic encapsulation layer 118b is blocked by the third dams 1b and 1a.

[0147] It should be noted that in this application, if Figure 2aAs shown, when the aperture area B1 is circular, the orthographic projection of the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 on the substrate can also be an annulus; when the aperture area B1 is rectangular, the orthographic projection of the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 on the substrate can also be a rectangular annulus; but not limited to this, the aperture area B1 can also be other regular or irregular shapes, and the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 can be adapted to them.

[0148] In one or more implementations, refer to Figure 22-25 As shown, the non-display area also includes the isolation area B4 area, which is located between the first dam area B2 area and the display area A1 area, and is set around the first dam area B2 area.

[0149] refer to Figure 22-25 As shown, isolation zone B4 includes isolation pillars 124, which are arranged around the first dam zone B2; (Reference) Figure 27 As shown, the side wall of the isolation column 124 is provided with a partition groove 124a.

[0150] The number of the aforementioned isolation columns is not limited to one, or there may be multiple columns.

[0151] In one or more embodiments, the isolation pillar can be disposed in the same layer as the first electrode 110 and the second electrode 111 of the thin-film transistor. If the first electrode 110 and the second electrode 111 are a three-layer metal structure, then the isolation pillar can also be a three-layer metal structure. For example, Figure 27 As shown, the isolation pillar 124 may include a first metal layer 124b, a second metal layer 124c, and a third metal layer 124d stacked sequentially. The outer boundary of the orthogonal projection of the second metal layer 124c onto the substrate is located within the outer boundaries of the orthogonal projections of the first metal layer 124b and the third metal layer 124d onto the substrate, so as to form a partition groove 124a on the sidewall of the isolation pillar 124, making the longitudinal section of the isolation pillar 124 have an "I" shaped structure. In this way, when evaporating the light-emitting material or the cathode material, the light-emitting material layer 114 and the cathode (i.e., the second electrode 115) are interrupted at this partition groove 124a, thereby blocking the path of water and oxygen in the opening area B1 to erode the display area A1, thereby further preventing the display area A1 from being eroded, improving the display effect of the display substrate and extending the product life.

[0152] In one or more implementations, refer to Figure 22-25As shown, the isolation zone B4 includes a first slot 125 and a second slot 126; the first slot 125 is located on the side of the isolation column 124 near the third dam 1a, and the first slot 125 is arranged around the third dam 1a; the second slot 126 is located on the side of the isolation column 124 near the display area A1, and the second slot 126 is arranged around the first slot 125. This design can increase the probability of the luminescent material breaking on the side of the isolation column 124.

[0153] Figure 22-25 In this process, the first and second slots can be created by removing portions of the interlayer dielectric layer 103, the second grid insulator layer 108, and the first grid insulator layer 105 located in the isolation zone B4 where the isolation posts 124 are not installed. Of course, other methods can also be used, which will not be elaborated here.

[0154] In this application, by setting a first slot and a second slot, the probability of the light-emitting material or cathode material breaking off on the side of the isolation pillar is further increased; in addition, when the display substrate is flexible and bent, this design can also relieve some stress and ensure reliability.

[0155] It should be noted that in this application, if Figure 2a As shown, when the aperture region B1 is circular, the orthographic projection of the isolation pillar, the first slot, and the second slot on the substrate can also be an annulus; when the aperture region B1 is rectangular, the orthographic projection of the isolation pillar, the first slot, and the second slot on the substrate can also be a rectangular annulus; but not limited to this, the aperture region B1 can also be other regular or irregular shapes, and the isolation pillar, the first slot, and the second slot can be adapted to them.

[0156] In one or more implementations, refer to Figure 22-25 As shown, the non-display area also includes the wiring area B5, which is located between the isolation area B4 and the display area A1, and surrounds the isolation area B4. The wiring area B5 includes multiple wirings, and the wirings in the wiring area are electrically connected to the corresponding wirings in the display area.

[0157] refer to Figure 22-25 As shown, routing area B5 may include first routing 129a, second routing 129b, and third routing 129c. The first trace may include, but is not limited to, a data signal line. In this case, the first trace may be electrically connected to the data signal line in the display area. The second trace may include, but is not limited to, a gate line. In this case, the second trace may be electrically connected to the gate line in the display area. The third trace may include, but is not limited to, a reset signal line or an initialization line. In this case, the third trace may be electrically connected to the reset signal line or the initialization line in the display area.

[0158] Alternatively, the first trace may include, but is not limited to, a gate line. In this case, the first trace can be electrically connected to the gate line within the display area. The second trace may include, but is not limited to, a data signal line. In this case, the second trace can be electrically connected to the data signal line within the display area. The third trace may include, but is not limited to, a reset signal line or an initialization line. In this case, the third trace can be electrically connected to the reset signal line or the initialization line within the display area. Of course, other cases are also possible, which will not be elaborated here.

[0159] refer to Figure 24-25 As shown, the display substrate also includes: a buffer layer 102, a gate insulating layer (including a second gate insulator layer 108 and a first gate insulator layer 105) and an interlayer dielectric layer 103 stacked sequentially; the interlayer dielectric layer, the gate insulating layer and the buffer layer are all located in the display area, the wiring area, the isolation area, the first dam area and the transition area; the second dam 1c, the third dams 1b and 1a and the isolation pillar 124 are all disposed on the side of the interlayer dielectric layer 103 away from the substrate 101.

[0160] It should be noted that the structure of the gate insulating layer in the display area is the same as that in the non-display area. For example, if the gate insulating layer in the display area includes a two-layer structure of a first gate insulator layer and a second gate insulator layer, then the gate insulating layer in the non-display area also includes a two-layer structure of a first gate insulator layer and a second gate insulator layer.

[0161] In one or more implementations, refer to Figure 3 and Figure 4 As shown, the display substrate also includes a polarizing layer 54, which is disposed on the side of the touch unit 1 away from the packaging unit 2.

[0162] It should be noted that the display substrate may also include other structures. Only the structures related to the inventive point are introduced here. Other structures can be obtained by referring to relevant technologies, and will not be described in detail here.

[0163] This application also provides a display device, including the display substrate described above.

[0164] The display device can be a flexible display device (also known as a flexible screen) or a rigid display device (i.e., a display device that cannot be bent), and there is no limitation here.

[0165] The display device can be an OLED (Organic Light-Emitting Diode) display device, a Micro LED display device, or a Mini LED display device, as well as any product or component with display function, such as televisions, digital cameras, mobile phones, and tablets, that includes these display devices. This display device can significantly improve the problem of green tint at the screen edges, resulting in better display quality and a superior user experience.

[0166] Optional, see reference Figure 3 and Figure 4 As shown, the display device also includes a packaging substrate 52, and the packaging substrate 52 and the display substrate 50 are fixed together by an adhesive layer 53.

[0167] The encapsulation substrate may include a glass substrate, and the adhesive layer may include OCA (Optically Clear Adhesive).

[0168] It should be noted that, in order to enable the display device to have functions such as taking pictures, the display device can also integrate an optical unit. This optical unit can be disposed on the side of the substrate of the display substrate away from the driving unit (i.e., the back side of the substrate). To better position the optical unit, an isolation layer can also be disposed between the substrate and the optical unit. Of course, the display device can also include other structures, which can be obtained according to relevant technologies, and will not be elaborated here.

[0169] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0170] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A display substrate, characterized in that, include: A display area and a non-display area connected to the display area, the non-display area including an edge area and a first dam area, the first dam area being located between the display area and the edge area; The display substrate further includes: Substrate; An antistatic layer is disposed on the substrate; the antistatic layer is located at least in the edge region; A driving unit and a touch unit are disposed on the substrate; wherein, the driving unit is located in the display area, and the touch unit is located in the display area and the non-display area, and covers the driving unit; The antistatic layer and the touch unit are disposed on the same layer, or the antistatic layer is disposed on the side of the touch unit away from the substrate; The first dam area is arranged around the display area, and the edge area is arranged around the first dam area; The edge region includes a cutting transition region, a crack dam region, and a drive circuit region; the crack dam region is arranged around the first dam region and is disconnected in the drive circuit region; the cutting transition region is arranged around the crack dam region and the drive circuit region. The cracked dam area includes at least one groove, which is disposed around the first dam area and disconnected in the drive circuit area; the antistatic layer at least covers a portion of the groove.

2. The display substrate according to claim 1, characterized in that, The touch unit includes a first touch layer, a first insulating layer, a second touch layer, and a second insulating layer stacked sequentially on the driving unit; the first touch layer and the second touch layer are both located in the display area, and the first insulating layer and the second insulating layer are located in the display area and the non-display area, respectively. In this design, one of the first touch layer and the second touch layer is a metal mesh electrode layer, and the other is a bridging metal layer.

3. The display substrate according to claim 2, characterized in that, When the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the first touch layer are disposed on the same layer; Alternatively, if the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the second touch layer are disposed on the same layer.

4. The display substrate according to claim 3, characterized in that, The second insulating layer covers the first insulating layer, and the boundary of the second insulating layer is farther away from the boundary of the first insulating layer from the first dam area; The second insulating layer located in the non-display area is disposed on the side of the antistatic layer away from the substrate.

5. The display substrate according to claim 4, characterized in that, The orthographic projection of the antistatic layer on the substrate overlaps with the orthographic projection of the second insulating layer on the substrate; Alternatively, the orthographic projection of the antistatic layer on the substrate lies within the orthographic projection of the second insulating layer on the substrate.

6. The display substrate according to claim 2, characterized in that, When the antistatic layer is disposed on the side of the touch unit away from the substrate, the second insulating layer located in the non-display area is disposed on the side of the antistatic layer closer to the substrate.

7. The display substrate according to claim 1, characterized in that, The display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer stacked sequentially; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the first dam area, and the crack dam area; The groove at least penetrates the portion of the interlayer medium layer located in the cracked dam area.

8. The display substrate according to claim 7, characterized in that, The display substrate further includes: a first flat portion and a first protrusion, wherein the first flat portion is located in the cutting transition area and the crack dam area; the first protrusion is located in the crack dam area, is disposed around the first dam area, and is disconnected in the driving circuit area; The first flat portion covers all the grooves, the first protrusion is disposed on the side of the first flat portion away from the substrate, and the antistatic layer covers the first protrusion.

9. The display substrate according to claim 8, characterized in that, The integral formed by the interlayer dielectric layer, the gate insulating layer, and the buffer layer has at least one step near the edge of the cut transition zone; the first flat portion covers all the steps.

10. The display substrate according to claim 8, characterized in that, The edge region also includes a crack detection region, which is located between the first dam region and the cracked dam region; The crack detection area includes multiple crack detection lines, and the antistatic layer covers all the crack detection lines and all the grooves.

11. The display substrate according to claim 10, characterized in that, The antistatic layer is also located in the first dam area; The non-display area also includes a wiring area, which is located between the first dam area and the display area; The display substrate further includes: a power signal line located in the wiring area and the first dam area; the power signal line partially overlaps with the antistatic layer in a direction perpendicular to the substrate.

12. The display substrate according to claim 11, characterized in that, The interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the wiring area and the crack detection area; The first dam area includes at least one first dam, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam includes a second protrusion, a second flat portion, and a third flat portion disposed sequentially; the second flat portion covers the second protrusion, and the third flat portion covers the second flat portion; The second protrusion and the first flat portion are disposed in the same layer, and the second flat portion and the first protrusion are disposed in the same layer.

13. The display substrate according to claim 12, characterized in that, The first dam area also includes a jumper wire and a third protrusion. The third protrusion is disposed on the side of the first dam closest to the cut transition area, near the crack dam area. The jumper wire is disposed on the side of the interlayer dielectric layer away from the substrate. The third protrusion covers the jumper wire. The third protrusion, the second protrusion, and the first flat portion are disposed in the same layer.

14. The display substrate according to claim 13, characterized in that, The power signal line includes at least a first power line, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam is disposed on the side of the first power line away from the substrate. The first power line and the jumper are arranged in the same layer and disconnected from each other, and the third protrusion also covers the edge of the first power line near the cutting transition area; The first power line and the antistatic layer partially overlap in a direction perpendicular to the substrate.

15. The display substrate according to claim 13, characterized in that, The power signal line further includes a second power line and a third power line; the third power line is disposed on the side of the second power line away from the substrate; The second power line is positioned near the edge of the cutting transition zone between the second protrusion and the second flat portion in the first dam closest to the cutting transition zone, and the third power line is positioned near the edge of the cutting transition zone between the second flat portion and the third flat portion in the first dam closest to the cutting transition zone.

16. The display substrate according to claim 15, characterized in that, The display substrate further includes a plurality of light-emitting units arranged in an array; the light-emitting units are located in the display area and are disposed between the driving unit and the touch unit; The light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode; the second electrode is disposed on the side of the light-emitting functional layer away from the driving unit. The driving unit includes an array of transistors, a first flat film, a plurality of transition electrodes, and a second flat film. The first flat film covers the transistors, and the transition electrodes are disposed between the first flat film and the second flat film and are electrically connected to the transistors. The first electrode is disposed on the side of the second flat film away from the substrate and is electrically connected to the transition electrode. In this configuration, the first power line is disposed on the same layer as the source and drain of the transistor; the second power line is disposed on the same layer as the transition electrode; the third power line is disposed on the same layer as the first electrode; the first flat film, the first flat portion, the second protrusion, and the third protrusion are disposed on the same layer; and the second flat film, the second flat portion, and the first protrusion are disposed on the same layer.

17. The display substrate according to claim 1, characterized in that, The edge region includes an opening region and a transition region; the transition region is arranged around the opening region, and the first dam region is arranged around the transition region; The antistatic layer is located at least in the transition zone.

18. The display substrate according to claim 17, characterized in that, The transition zone includes at least one second dam, which is disposed on the side of the antistatic layer near the substrate and at least partially overlaps the antistatic layer in a direction perpendicular to the substrate.

19. The display substrate according to claim 18, characterized in that, The first dam area includes at least one third dam, which is arranged in the same layer as the second dam; The antistatic layer and the third dam do not overlap in a direction perpendicular to the substrate.

20. A display device, characterized in that, Includes the display substrate as described in claim 1.

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