Manufacturing method of groove type MOSFET structure

Abstract

The invention relates to a manufacturing method of a trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure, which comprises the following steps of: forming a p-type body region on an N-type substrate, forming a first opening in a first insulating layer on the p-type body region through single photoetching, and forming an insulating side wall on the side wall of the first opening; and forming a self-alignment structure by using the first insulating layer and the insulating side wall to realize self-alignment injection of the source electrode region, and simultaneously reusing the structure to etch the groove and form the grid electrode. The reserved insulating side wall and the third insulating layer are used for forming a self-alignment structure again to etch the source electrode contact hole, photoetching offset is avoided, accurate alignment can still be guaranteed under the condition of small spacing, multiple mask and photoetching steps are omitted through the self-alignment technology, the manufacturing period is remarkably shortened, the cost is reduced, and the production efficiency is improved. And the high-precision manufacturing of the submicron trench MOSFET is realized.

Description

Technical Field

[0001] This invention relates to the field of power device technology, and in particular to a method for manufacturing a trench MOSFET structure. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used as switching components in power devices, such as power supplies, hand tools, and automotive on-board units (OBCs). Conventional MOSFETs mostly employ a vertical structure, such as trench MOSFETs, to improve power density.

[0003] Higher cell power density results in lower on-resistance, especially for MOSFETs with a breakdown voltage of less than 40V. Generally, trench MOSFETs can reduce the resistance of the epitaxial semiconductor by increasing cell density. However, when the spacing between two cells is less than 0.6 micrometers, the resolution of traditional photolithography equipment is insufficient to meet the requirements for precise alignment, leading to problems such as pattern misalignment, source region and trench misalignment, and contact hole misalignment. These issues severely affect the device's conduction characteristics and may even cause failure. At the same time, the introduction of additional photolithography masks to compensate for insufficient photolithography precision increases manufacturing costs and process complexity. Summary of the Invention

[0004] In view of this, the present invention provides a method for manufacturing a trench MOSFET structure to solve the above problems.

[0005] A method for manufacturing a trench MOSFET structure includes the following steps: Step S1: Provide an N-type substrate, implant P-type impurities into the N-type substrate and push-bond to form a p-type body region on the surface of the N-type substrate, form a first insulating layer on the p-type body region, define the position of the first opening by photolithography, and then etch the first insulating layer to form at least one first opening in the first insulating layer. Step S2: First, a silicon nitride layer is deposited on the first insulating layer. Then, the deposited silicon nitride layer is etched back to remove the silicon nitride layer at the top of the first insulating layer and the bottom of the first opening, while retaining the silicon nitride layer on the sidewall of the first opening, thereby forming an insulating sidewall at the sidewall position of the first opening. Step S3: Using the first insulating layer and the insulating sidewall as self-aligned barrier layers, perform n-type implantation and annealing to form the source region in the p-type body region; Step S4: The source region and the p-type body region below it are etched again using the first insulating layer and the insulating sidewall as self-aligned barrier layers to obtain a vertical trench. A second insulating layer is formed on the inner sidewall and bottom surface of the trench through a thermal oxidation process. Then, polysilicon is deposited and filled in the second insulating layer to at least completely fill the trench and form a gate. Step S5: Form a third insulating layer in the first opening and make the third insulating layer flush with the first insulating layer and the insulating sidewall; Step S6: First, remove the first insulating layer to form a second opening at the first insulating layer to expose the source region and the p-type body region and form a positioning through the two insulating sidewalls. Other areas are still covered by the third insulating layer and the insulating sidewalls. Then, using the third insulating layer and the insulating sidewalls as self-aligning barrier layers, etch the source region and the p-type body region to form a source contact hole. Step S7: First, remove the third insulating layer, then define and etch the gate hole on the gate by photolithography, and finally form an isolation dielectric layer and a metal layer to obtain a trench power device.

[0006] Furthermore, in step S1 above, the first insulating layer is a silicon oxide layer or a stack of a silicon oxide layer and a silicon nitride layer.

[0007] Furthermore, in step S2 above, the thickness of the insulating sidewall is greater than 400 Å.

[0008] Furthermore, in step S3 above, the first insulating layer and the insulating sidewall together form a self-aligning structure. The first insulating layer acts as a positive barrier, and the insulating sidewall acts as a lateral barrier, so that only the bottom of the first opening is exposed as an injection channel, thereby ensuring that the formed source region is between the two insulating sidewalls. The position of the source region is physically located by the two insulating sidewalls, ensuring that the position of the source region is self-aligned.

[0009] Furthermore, in step S4 above, the second insulating layer is preferably a silicon oxide layer.

[0010] Furthermore, in step S4 above, when the polysilicon is filled beyond the trench, the polysilicon is etched back to etch away the excess polysilicon, ensuring that the polysilicon is flush with the trench.

[0011] Furthermore, in step S4 above, the distance between adjacent trenches is less than 0.6 μm.

[0012] Furthermore, in step S5 above, the third insulating layer is an APF layer, which is formed by a CVD process.

[0013] Compared with existing technologies, the trench MOSFET manufacturing method provided by this invention defines the initial position by using a first opening formed by photolithography of the first insulating layer. After forming the insulating sidewall on the sidewall of the first opening, the first insulating layer and the insulating sidewall form a self-aligned structure to achieve self-aligned injection of the source region. Simultaneously, this structure is reused to etch the trench and form the gate. The second opening is the empty space left after removing the first insulating layer. The remaining insulating sidewall and the third insulating layer are used to form a self-aligned structure again to etch the source contact hole. This avoids photolithographic misalignment and ensures accurate alignment even at small pitches. The self-aligned process eliminates multiple masking and photolithography steps, significantly shortens the manufacturing cycle and reduces costs, and achieves high-precision manufacturing of submicron-level trench MOSFETs. Attached Figure Description

[0014] Figure 1 A flowchart illustrating a method for manufacturing a trench MOSFET structure provided by the present invention.

[0015] Figure 2 for Figure 1 An exploded structural diagram illustrating the manufacturing process of a trench MOSFET structure.

[0016] Figure 3 for Figure 1 A schematic diagram of step S3 in the manufacturing method of the trench MOSFET structure.

[0017] Figure 4 for Figure 1 A schematic diagram of step S4 in the manufacturing method of the trench MOSFET structure.

[0018] Figure 5 for Figure 1 A schematic diagram of step S5 in the method for manufacturing a trench MOSFET structure.

[0019] Figure 6 for Figure 1 A schematic diagram of step S6 in the method for manufacturing a trench MOSFET structure.

[0020] Figure 7 for Figure 1 A schematic diagram of the structure after step S6 of the method for manufacturing a trench MOSFET structure is completed. Figure 8 for Figure 1 A schematic diagram of step S7 in the manufacturing method of the trench MOSFET structure. Explanation of reference numerals in the attached figures: N-type substrate 10, p-type body region 20, trench 21, first insulating layer 31, insulating sidewall 32, third insulating layer 33, first opening 40, source region 50, gate 60, second insulating layer 61, polysilicon 62, second opening 70, source contact hole 80, gate hole 90. Detailed Implementation

[0021] The following provides a more detailed description of specific embodiments of the present invention. It should be understood that the description of the embodiments of the present invention herein is not intended to limit the scope of protection of the present invention.

[0022] like Figure 1 As shown, it is a flowchart of the manufacturing method of the trench MOSFET structure provided by the present invention.

[0023] The method for manufacturing the trench MOSFET structure includes the following steps: Step S1: As Figure 2 As shown, an N-type substrate 10 is provided. P-type impurities are implanted into the N-type substrate 10, and a p-type body region 20 is formed on the surface of the N-type substrate 10 through high-temperature push bonding. A first insulating layer 31 is formed on the p-type body region 20. The position of a first opening 40 is defined by photolithography, and then the first insulating layer 31 is etched to form at least one first opening 40 in the first insulating layer 31. The number of first openings 40 is determined by the specifications of the designed semiconductor power device; in this embodiment, three first openings 40 are provided. The N-type substrate 10 is an N-type silicon substrate. The first insulating layer 31 is a silicon oxide layer or a stack of a silicon oxide layer and a silicon nitride layer.

[0024] Step S2: As Figure 3 and Figure 4 As shown, a silicon nitride layer is first deposited on the first insulating layer 31, and then the deposited silicon nitride layer is etched back to remove the silicon nitride layer at the top of the first insulating layer 31 and the bottom of the first opening 40, leaving only the silicon nitride layer on the sidewall of the first opening 40, thereby forming an insulating sidewall 32 at the sidewall position of the first opening 40. The thickness of the insulating sidewall 32 is greater than 400 Å.

[0025] Step S3: As Figure 4As shown, the source region 50 is formed in the p-type body region 20 by n-type injection and annealing using the first insulating layer 31 and the insulating sidewall 32 as self-aligning barrier layers. Specifically, the first insulating layer 31 and the insulating sidewall 32 together form a self-aligning structure. The first insulating layer 31 acts as a positive barrier, and the insulating sidewall 32 acts as a lateral barrier, so that only the bottom of the first opening 40 is exposed as the injection channel, thereby ensuring that the formed source region 50 is located between the two insulating sidewalls 32. The position of the source region 50 is physically positioned by the two insulating sidewalls 32, ensuring that the position of the source region 50 is self-aligned.

[0026] Step S4: As Figure 5 As shown, the source region 50 and the p-type body region 20 below it are etched again using the first insulating layer 31 and the insulating sidewall 32 as self-aligned barrier layers to obtain a vertical trench 21. A second insulating layer 61 is formed on the inner sidewall and bottom surface of the trench 21 by a thermal oxidation process. The second insulating layer 61 is preferably a silicon oxide layer. Next, polysilicon 62 is deposited and filled in the second insulating layer 61 to at least completely fill the trench 21. Then, the deposited polysilicon 62 is etched back to etch away the excess polysilicon 62, ensuring that the polysilicon 62 is flush with the trench 21, thereby forming the gate 60.

[0027] At this point, since the first insulating layer 31 and the insulating sidewall 32 continue to function as a self-aligning barrier layer and positioning reference, trenches are etched downwards. The relative positions of the source region 50 and the trench 21 are determined by the same first opening 40, thus ensuring self-alignment and eliminating the need for photolithography. The distance between adjacent trenches 21 is less than 0.6 μm.

[0028] Step S5: As Figure 6 As shown, a third insulating layer 33 is formed within the first opening 40 and is flush with the first insulating layer 31 and the insulating sidewall 32. In this case, the gate 60 is enclosed by the second insulating layer 61, the third insulating layer 33, and the insulating sidewall 32, preventing subsequent source metal from short-circuiting to the trench 21. The third insulating layer 33 is preferably an APF layer, formed by a CVD process.

[0029] Step S6: As Figure 6As shown, the first insulating layer 31 is first removed, thereby forming a second opening 70 at the first insulating layer 31 to expose the source region 50 and the p-type body region 20, which are positioned by the two insulating sidewalls 32. The other areas are still covered by the third insulating layer 33 and the insulating sidewalls 32. Then, the source region 50 and the p-type body region are etched using the third insulating layer 33 and the insulating sidewalls 32 as self-aligning barrier layers to form source contact holes 80, as shown. Figure 7 As shown.

[0030] At this point, since the area after removing the first insulating layer 31 forms the second opening 70, and the positions of the third insulating layer 33 and the insulating sidewall 32 remain unchanged, the third insulating layer 33 and the insulating sidewall 32 are used together to form a self-aligned structure. The third insulating layer 33 acts as a positive barrier, and the insulating sidewall 32 acts as a lateral barrier, thereby exposing the area between the two trenches 21, i.e., the bottom of the second opening 70, as the etching area, ensuring that the position of the source contact hole 80 is self-aligned. At the same time, no additional photolithography is required, which solves the problem of misalignment caused by existing photolithography being unable to meet the small pitch when the spacing between the two trenches is very small.

[0031] Step S7: As Figure 8 As shown, the third insulating layer 33 is first removed, and the gate hole 90 is etched on the gate 60 using photolithography. Since the first insulating layer 31 has been removed, a photolithographic alignment is required. Finally, an isolation dielectric layer and a metal layer are formed to obtain the trench power device.

[0032] Compared with the prior art, the method for manufacturing a trench MOSFET structure provided by the present invention defines the initial position by using a first opening 40 formed by photolithography of the first insulating layer 31. After forming the insulating sidewall 32 on the sidewall of the first opening 40, the first insulating layer 31 and the insulating sidewall 32 form a self-aligned structure to achieve self-aligned injection of the source region 50. At the same time, the trench 21 is etched and the gate 60 is formed by reusing this structure. The second opening 70 is the empty space left after removing the first insulating layer 31. The source contact hole 80 is etched again by using the remaining insulating sidewall 32 and the third insulating layer 33 to form a self-aligned structure. This avoids photolithographic misalignment and can still ensure accurate alignment at small pitch. The self-aligned process eliminates multiple masking and photolithography steps, significantly shortens the manufacturing cycle and reduces costs, and realizes high-precision manufacturing of submicron trench MOSFETs.

[0033] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions or improvements within the spirit of the present invention are covered within the scope of the claims of the present invention.

Claims

1. A method for manufacturing a trench MOSFET structure, comprising the following steps: Step S1: Provide an N-type substrate, implant P-type impurities into the N-type substrate and push-bond to form a p-type body region on the surface of the N-type substrate, form a first insulating layer on the p-type body region, define the position of the first opening by photolithography, and then etch the first insulating layer to form at least one first opening in the first insulating layer. Step S2: First, a silicon nitride layer is deposited on the first insulating layer. Then, the deposited silicon nitride layer is etched back to remove the silicon nitride layer at the top of the first insulating layer and the bottom of the first opening, while retaining the silicon nitride layer on the sidewall of the first opening, thereby forming an insulating sidewall at the sidewall position of the first opening. Step S3: Using the first insulating layer and the insulating sidewall as self-aligned barrier layers, perform n-type implantation and annealing to form the source region in the p-type body region; Step S4: The source region and the p-type body region below it are etched again using the first insulating layer and the insulating sidewall as self-aligned barrier layers to obtain a vertical trench. A second insulating layer is formed on the inner sidewall and bottom surface of the trench through a thermal oxidation process. Then, polysilicon is deposited and filled in the second insulating layer to at least completely fill the trench and form a gate. Step S5: Form a third insulating layer in the first opening and make the third insulating layer flush with the first insulating layer and the insulating sidewall; Step S6: First, remove the first insulating layer to form a second opening at the first insulating layer to expose the source region and the p-type body region and form a positioning through the two insulating sidewalls. Other areas are still covered by the third insulating layer and the insulating sidewalls. Then, using the third insulating layer and the insulating sidewalls as self-aligning barrier layers, etch the source region and the p-type body region to form a source contact hole. Step S7: First, remove the third insulating layer, then define and etch the gate hole on the gate by photolithography, and finally form an isolation dielectric layer and a metal layer to obtain a trench power device.

2. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S1 above, the first insulating layer is a silicon oxide layer or a stack of a silicon oxide layer and a silicon nitride layer.

3. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S2 above, the thickness of the insulating sidewall is greater than 400 Å.

4. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S3 above, the first insulating layer and the insulating sidewall together form a self-aligning structure. The first insulating layer acts as a positive barrier, and the insulating sidewall acts as a lateral barrier, so that only the bottom of the first opening is exposed as an injection channel, thereby ensuring that the formed source region is between the two insulating sidewalls. The position of the source region is physically located by the two insulating sidewalls, ensuring that the position of the source region is self-aligned.

5. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S4 above, the second insulating layer is preferably a silicon oxide layer.

6. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S4 above, when the polysilicon is filled beyond the trench, the polysilicon is etched back to etch away the excess polysilicon, ensuring that the polysilicon is flush with the trench.

7. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S4 above, the distance between adjacent trenches is less than 0.6 μm.

8. The method for manufacturing the trench MOSFET structure as described in claim 1, characterized in that: In step S5 above, the third insulating layer is an APF layer, which is formed by CVD process.

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