Grounding buried layer SiC JFET resistant to single particle burnout and preparation method

Abstract

The invention discloses a grounding buried layer SiC JFET resistant to single particle burnout and a preparation method, and relates to the technical field of silicon carbide power device.The device comprises a substrate, a drift region, a P + buried layer, a channel layer, a first P + gate region, a second P + gate region, an N + source region, a source electrode, a grid electrode and a drain electrode, the first P + gate region extends in the vertical direction and is in direct contact with the P + buried layer, and the second P + gate region extends in the vertical direction and is in direct contact with the N + source region; a continuous P-type region is formed; the second P + gate region is isolated from the P + buried layer; the grid electrode comprises two parts which are in ohmic contact with the first P + grid region and the second P + grid region respectively, and the part connected with the first P + grid region is used for being grounded. Through the grid electrode-buried layer integrated structure, an in-vivo charge discharge path with the shortest and lowest resistance is realized, and the single-particle burnout resistance is improved; meanwhile, buried layer grounding is achieved through the grid, a complex deep hole contact technology is omitted, and reliability is improved; and by designing parameters of the channel layer, the normally-open or normally-closed characteristic can be flexibly realized.

Description

Technical Field

[0001] This invention belongs to the field of silicon carbide power device technology, specifically relating to a grounded buried layer SiC JFET resistant to single-particle burn-out and its preparation method. Background Technology

[0002] Silicon carbide (SiC) materials have become ideal materials for manufacturing next-generation high-performance power semiconductor devices due to their excellent properties such as wide bandgap, high critical breakdown electric field, and high thermal conductivity. They have broad application prospects in extreme environments such as aerospace, new energy, and rail transportation, as well as in the field of high-efficiency power conversion.

[0003] However, in high-radiation environments such as space, there are a large number of charged particles such as protons and heavy ions. When these high-energy particles enter semiconductor devices, they can trigger single-event effects (SEE), among which single-event burn-out (SEB) is extremely destructive. It is caused by the instantaneous large current and localized thermal runaway generated by particle impact, which can lead to permanent short-circuit failure of the device. Studies have shown that the voltage at which existing SiC power devices experience SEB is often far below their rated breakdown voltage, indicating a severe deficiency in single-event immunity, which limits their application in aerospace-grade equipment.

[0004] Furthermore, most SiC JFETs are currently depletion-mode (normally on) devices. However, in many power applications, enhancement-mode (normally off) devices are more ideal for system startup safety and circuit design compatibility, and can directly replace MOSFETs or IGBTs.

[0005] Therefore, there is an urgent need to develop a SiC power device structure that combines high resistance to single-event burn-out with controllable conduction characteristics (normally on / normally off). Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a grounded buried-layer SiC JFET resistant to single-particle burn-out and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a grounded buried layer SiC JFET resistant to single-event burn-out, comprising: N-type substrate; An N-type epitaxial layer is located on the upper surface of the N-type substrate; The P+ buried layer is located inside the N-type epitaxial layer; An N-type secondary epitaxial layer is located on the upper surface of the N-type epitaxial layer; A first P+ gate region and a second P+ gate region are disposed alternately within the N-type secondary epitaxial layer. The first P+ gate region extends vertically and contacts the P+ buried layer, thereby electrically communicating with the P+ buried layer to form a continuous P-type pillar region. The second P+ gate region is isolated from the P+ buried layer in the vertical direction. The N+ source region is located inside the N-type secondary epitaxial layer between the first P+ gate region and the second P+ gate region; The gate includes a first gate and a second gate, wherein the first gate forms an ohmic contact on the upper surface of the first P+ gate region, and the second gate forms an ohmic contact on the upper surface of the second P+ gate region; The source electrode forms an ohmic contact on the upper surface of the N+ source region; The drain electrode is located on the lower surface of the N-type substrate and forms an ohmic contact. A passivation layer is located on the device surface between the gate and the source.

[0007] In one embodiment of the present invention, the thickness of the N-type epitaxial layer is 1-100 μm, and the doping concentration is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 .

[0008] In one embodiment of the present invention, the doping concentration of the P+ buried layer is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0μm and the junction depth is 0-3μm.

[0009] In one embodiment of the present invention, the doping concentration of the N-type secondary epitaxial layer is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 The thickness is 0.5-3μm.

[0010] In one embodiment of the present invention, the doping concentration of the first P+ gate region is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is not less than the thickness of the N-type secondary epitaxial layer.

[0011] In one embodiment of the present invention, the doping concentration of the second P+ gate region is 1×10⁻⁶. 18 cm-3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is less than the thickness of the N-type secondary epitaxial layer.

[0012] In one embodiment of the present invention, the doping concentration of the N+ source region is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 0.5-2.0μm and the junction depth is 0.1μm-0.5μm.

[0013] In one embodiment of the present invention, the first P+ gate region is configured to receive a fixed reference potential via a first gate connected thereto, so as to fix the potential of the P+ buried layer, wherein the fixed reference potential is the ground potential.

[0014] This invention also provides a method for fabricating a ground-buried SiC JFET resistant to single-event burn-out, applicable to the ground-buried SiC JFET resistant to single-event burn-out described in any of the above embodiments. The fabrication method includes: Step 1: Epitaxially grow an N-type epitaxial layer on the upper surface of an N-type substrate; Step 2: Perform P-type ion implantation on the N-type epitaxial layer to form a P+ buried layer; Step 3: Epitaxially grow an N-type secondary epitaxial layer on the upper surface of the N-type epitaxial layer containing the P+ buried layer; Step 4: Perform two P-type ion implantations and one N-type ion implantation on the N-type secondary epitaxial layer to form a first P+ gate region, a second P+ gate region, and an N+ source region. The junction depth of the first P+ gate region is not less than the thickness of the N-type secondary epitaxial layer to achieve connection with the P+ buried layer. The second P+ gate region is isolated from the P+ buried layer in the vertical direction. Step 5: Deposit a passivation layer on the device surface; Step 6: Etch the passivation layer on a portion of the first P+ gate region, a portion of the second P+ gate region, and a portion of the N+ source region to form an ohmic contact window; deposit metal on the upper surface of the first P+ gate region, the second P+ gate region, and the N+ source region to prepare the source and gate electrodes, and deposit metal on the lower surface of the N-type substrate to prepare the drain electrode.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The grounded buried-layer SiC JFET resistant to single-event burn-out of the present invention forms a continuous P-type pillar region through the direct connection between the first P+ gate region and the P+ buried layer, constructing the shortest and lowest-resistance bulk charge (hole) discharge path from the interior of the drift region to the surface electrode. When a single-event event occurs, the excess holes generated can be instantly collected by the buried layer and directly conducted to the grounded first gate through the low-resistance connected P-type pillar region. The continuous P-type pillar structure completely eliminates the metal-semiconductor contact resistance, long interconnect resistance, and possible parasitic inductance in traditional deep-hole contact structures, making the charge discharge process delay-free and bottleneck-free, thereby most effectively interrupting the electrothermal positive feedback cycle of SEB.

[0016] 2. The threshold characteristics of the grounded buried layer SiC JFET resistant to single-event burn-out of the present invention are jointly determined by the thickness and doping concentration of the N-type secondary epitaxial layer, as well as the doping and junction depth of the second P+ gate region. By precisely designing the parameters of the N-type secondary epitaxial layer, it is possible to control whether the combined depletion layer formed by the first P+ gate region / P+ buried layer and the second P+ gate region can interrupt the conductive channel at zero gate voltage. By adjusting the epitaxial growth conditions in the process, the fabrication of depletion-mode (normally on) or enhancement-mode (normally off) devices can be flexibly realized on the same technology platform, greatly enhancing the application scope and market adaptability of the technology.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a grounded buried layer SiC JFET resistant to single-particle burn-out provided in an embodiment of the present invention; Figure 2 This is a front view of a grounded buried layer SiC JFET resistant to single-particle burn-out provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for fabricating a SiC JFET with a grounding buried layer that is resistant to single-particle burn-out, provided by an embodiment of the present invention. Figure 4 This is a process flow diagram of the fabrication process of a grounded buried layer SiC JFET resistant to single-particle burn-out provided by an embodiment of the present invention.

[0019] Icons: 1-N-type substrate; 2-N-type epitaxial layer; 3-N-type secondary epitaxial layer; 4-N+ ​​source region; 5-First P+ gate region; 6-Second P+ gate region; 7-P+ buried layer; 8-Passivation layer; 9-Gate; 10-Source; 11-Drain. Detailed Implementation

[0020] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a grounded buried layer SiC JFET resistant to single-particle burn-out and its preparation method based on the present invention.

[0021] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0022] Firstly, this invention provides a grounded buried layer SiC JFET resistant to single-event burn-out. The core of this invention lies in proposing a grounded buried layer structure capable of resisting single-event burn-out. By heavily doping to form a low-resistivity region and increasing the contact area with the drift region, the grounded buried layer accelerates the extraction of excess carriers, preventing excessive local accumulation of excess carriers. Although the peak electric field magnitude at the substrate-drift region interface is not reduced, its duration is significantly shortened, resulting in a shorter duration of violent impact ionization at the substrate-drift region interface. This reduces the number of excess carriers generated at this location, effectively suppressing lattice temperature peaks, and thus improving the device's resistance to single-event burn-out. This structure improves the electric field distribution inside the device, effectively mitigating the localized high temperature caused by heavy ion incidence, and exhibits strong resistance to single-event burn-out. Furthermore, this structure allows for the addition of an additional buffer layer in the drift region, further enhancing the device's resistance to single-event burn-out.

[0023] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a grounded buried layer SiCJFET resistant to single-particle burn-out provided in an embodiment of the present invention; Figure 2 This is a front view of a grounded buried layer SiC JFET resistant to single-event burn-out provided in an embodiment of the present invention.

[0024] The grounded buried layer SiC JFET resistant to single-event burn-out in this embodiment includes: an N-type substrate 1, an N-type epitaxial layer 2, an N-type secondary epitaxial layer 3, an N+ source region 4, a first P+ gate region 5, a second P+ gate region 6, a P+ buried layer 7, a passivation layer 8, a gate 9, a source 10, and a drain 11.

[0025] In this structure, the N-type epitaxial layer 2 is located on the upper surface of the N-type substrate 1; the P+ buried layer 7 is located inside the N-type epitaxial layer 2; the N-type secondary epitaxial layer 3 is located on the upper surface of the N-type epitaxial layer 2; the first P+ gate region 5 and the second P+ gate region 6 are spaced apart inside the N-type secondary epitaxial layer 3, wherein the first P+ gate region 5 extends vertically and contacts the P+ buried layer 7, so that the first P+ gate region 5 and the P+ buried layer 7 are electrically connected, forming a continuous P-type pillar region; the second P+ gate region 6 is isolated from the P+ buried layer 7 in the vertical direction. The N+ source region 4 is located inside the N-type secondary epitaxial layer 3 between the first P+ gate region 5 and the second P+ gate region 6; the gate 9 includes a first gate and a second gate, wherein the first gate forms an ohmic contact on the upper surface of the first P+ gate region 5, and the second gate forms an ohmic contact on the upper surface of the second P+ gate region 6; the source 10 forms an ohmic contact on the upper surface of the N+ source region 4; the drain 11 forms an ohmic contact on the lower surface of the N-type substrate 1; and the passivation layer 8 is located on the device surface between the gate 9 and the source 10.

[0026] In this embodiment, the N-type substrate 1 is an N-type SiC substrate, which serves as the drain contact region and mechanical support.

[0027] In this embodiment, the N-type epitaxial layer 2 serves as the drift region, with a thickness of 1-100 μm and a doping concentration of 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 Optionally, the N-type epitaxial layer 2 can be epitaxially grown on the N-type substrate 1 by chemical vapor deposition (CVD), and the doping ions can be N (nitrogen) or P (phosphorus).

[0028] In this embodiment, the doping concentration of the P+ buried layer 7 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm and the junction depth is 0.5-3 μm. The P+ buried layer 7 can be formed on the surface of the N-type epitaxial layer 2 by high-dose aluminum (Al) or boron (B) ion implantation.

[0029] In this embodiment, the N-type secondary epitaxial layer 3 serves as the channel region, forming the vertical conductive channel of the device. The doping concentration of the N-type secondary epitaxial layer 3 is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 The thickness is 0.5-3 μm. Optionally, the N-type secondary epitaxial layer 3 can be grown on the N-type epitaxial layer 2 containing the P+ buried layer 7 by a second CVD epitaxial growth, and the dopant ions can be N (nitrogen) or P (phosphorus).

[0030] In this embodiment, the doping concentration of the first P+ gate region 5 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width of the second P+ gate region 5 is 1.0-6.0 μm, and the junction depth is not less than the thickness of the N-type secondary epitaxial layer 3 to ensure contact between the first P+ gate region 5 and the P+ buried layer 7. The doping concentration of the second P+ gate region 6 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is less than the thickness of the N-type secondary epitaxial layer 3 to ensure that the second P+ gate region 6 is isolated from the P+ buried layer 7. The horizontal distance between the first P+ gate region 5 and the second P+ gate region 6 is the width of the channel.

[0031] Optionally, the first P+ gate region 5 and the second P+ gate region 6 can be formed in the N-type secondary epitaxial layer 3 through two different ion implantation processes.

[0032] For example, the first P+ gate region 5 can be implanted with aluminum (Al) or boron (B) ions using a high-energy ion implantation process. The implantation dose is designed so that the junction depth is not less than the thickness of the N-type secondary epitaxial layer 3, thereby ensuring that it penetrates downward into the N-type secondary epitaxial layer 3 and directly contacts the underlying P+ buried layer 7 to achieve electrical connection and form a continuous low-resistivity P-type pillar region.

[0033] For example, the second P+ gate region 6 can be implanted with aluminum (Al) or boron (B) ions using a conventional energy ion implantation process. The implantation dose is designed so that the junction depth is less than the thickness of the N-type secondary epitaxial layer 3, thereby maintaining isolation from the P+ buried layer 7.

[0034] In this embodiment, the doping concentration of N+ source region 4 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 0.5-2.0 μm and the junction depth is 0.1 μm-0.5 μm. Optionally, the N+ source region 4 can be formed on the surface of the N-type secondary epitaxial layer 3 between the first P+ gate region 5 and the second P+ gate region 6 by N (nitrogen) or P (phosphorus) ion implantation.

[0035] In this embodiment, the passivation layer 8 is made of SiO2 / SiN. x It is applied to the surface of the device to provide protection and passivation.

[0036] In this embodiment, the source 10 is made of Ni metal, the gate 9 is made of Ti / Ni / Al metal, and the drain 11 is made of Ni / Ag metal.

[0037] In this embodiment, the metal layer of gate 9 is patterned into a first gate and a second gate. The first gate forms an ohmic contact with the first P+ gate region 5, and the second gate forms an ohmic contact with the second P+ gate region 6. In circuit applications, the first P+ gate region 5 is configured to receive a fixed reference potential through the first gate connected to it, so as to fix the potential of the P+ buried layer 7. The fixed reference potential is the ground potential.

[0038] In this embodiment of the grounded buried-layer SiC JFET resistant to single-particle burnout, when the device is in a high-voltage blocking state, the P+ buried layer 7 is firmly clamped to ground potential through the first P+ gate region 5 and the first gate. If a high-energy particle is incident on the drift region and generates electron-hole pairs, the holes will rapidly drift towards the lowest potential P+ buried layer 7 under the influence of the electric field and be collected. Since the buried layer and ground are directly connected through a low-resistance semiconductor P-type pillar region and metal, these excess holes can be discharged instantaneously and without obstruction, effectively preventing local charge accumulation, avalanche multiplication, and thermal runaway.

[0039] The device's on / off state is controlled by the voltage applied to the second gate. When a negative voltage (relative to the source) is applied to the second gate, the PN junction formed by the second P+ gate region 6 and the N-type secondary epitaxial layer 3 is reverse-biased, and the depletion layer extends into the channel. Through its interaction with the depletion region of the first P+ gate region 5 / P+ buried layer 7 (at a fixed potential), the N-type channel between the first P+ gate region 5 and the second P+ gate region 6 can be clamped, turning off the device. When the voltage at the second gate is zero or positive, the depletion region contracts, the channel opens, and electrons flow vertically from the source 10 through the channel layer and drift region to the drain 11.

[0040] For the grounded buried layer SiC JFET resistant to single-event burn-out in this embodiment, by designing the thickness and doping concentration of the N-type secondary epitaxial layer 3, the combined depletion layer of the first P+ gate region / P+ buried layer 7 and the second P+ gate region can completely clamp the channel when the second gate voltage is 0V, thereby achieving normally-off (enhancement-mode) characteristics. If normally-on (depletion-mode) characteristics are required, simply increase the thickness of the N-type secondary epitaxial layer 3 in the process, or appropriately increase its doping concentration, so that the channel remains on at zero gate voltage.

[0041] This embodiment of the grounded buried layer SiC JFET with single-event burn-off resistance features a first P+ gate region 5 / P+ buried layer 7. Through heavy doping, a low-resistivity region is formed, increasing the contact area with the drift region. The grounded buried layer accelerates the extraction of excess carriers, preventing excessive local accumulation. By avoiding excess carrier accumulation, the peak electric field at the substrate-drift region interface is alleviated, significantly shortening its duration. The duration of severe impact ionization at the substrate-drift region interface is also shortened, further reducing the excess carriers generated there, effectively suppressing lattice temperature peaks, and thus improving the device's resistance to single-event burn-off. The device channel width and length are jointly determined by the P+ buried layer and the surface P+ gate region doping. The channel parameters are adjustable, allowing for devices with different parameter requirements, and enabling switching from normally on to normally off.

[0042] Secondly, embodiments of the present invention provide a method for fabricating a grounded buried layer SiC JFET resistant to single-event burn-out, applicable to the grounded buried layer SiC JFET resistant to single-event burn-out provided in the first aspect. Please refer to... Figure 3 , Figure 3 This is a flowchart illustrating a method for fabricating a SiC JFET with a grounded buried layer resistant to single-event burn-out, as provided in an embodiment of the present invention. Figure 3 As shown, the fabrication method of the grounded buried layer SiC JFET resistant to single-particle burn-out in this embodiment includes the following steps: Step 1: Epitaxially grow an N-type epitaxial layer on the upper surface of an N-type substrate.

[0043] In this embodiment, the N-type substrate is an N-type SiC substrate, the thickness of the N-type epitaxial layer is 1-100 μm, and the doping concentration is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 Understandably, the thickness and doping concentration of the N-type epitaxial layer are determined by the voltage rating of the device. For typical 1200V silicon carbide devices, the doping concentration and thickness of the N-type epitaxial layer are 8 × 10⁻⁶. 15 cm -3 , 9μm.

[0044] Step 2: Perform P-type ion implantation on the N-type epitaxial layer to form a P+ buried layer.

[0045] Specifically, a mask layer is grown on the upper surface of the N-type epitaxial layer on an N-type substrate using CVD, followed by photoresist coating, exposure, development, etching of the mask layer, photoresist removal, and P-type ion implantation to form a P+ buried layer. Notably, the P+ doped region requires heavy doping to reduce resistivity, with a concentration of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3The width is 1.0-6.0μm and the junction depth is 0.5-3μm.

[0046] Step 3: Epitaxially grow an N-type secondary epitaxial layer on the upper surface of the N-type epitaxial layer containing the P+ buried layer.

[0047] Specifically, a secondary epitaxy is performed on the N-type epitaxial layer to grow a layer with a thickness of 0.5-3 μm and a doping concentration of 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 The N-type secondary epitaxial layer serves as the channel region of the device. It is understood that the doping concentration of the N-type secondary epitaxial layer is determined by the required channel concentration of the device, and the thickness is determined by the required channel width.

[0048] Step 4: Perform two P-type ion implantations and one N-type ion implantation on the N-type secondary epitaxial layer to form a first P+ gate region, a second P+ gate region, and an N+ source region. The junction depth of the first P+ gate region is not less than the thickness of the N-type secondary epitaxial layer to achieve connection with the P+ buried layer. The second P+ gate region is isolated from the P+ buried layer in the vertical direction.

[0049] Specifically, a mask layer is first grown on the upper surface of the N-type secondary epitaxial layer by CVD, then photoresist is applied, exposed, developed, the mask layer is etched, the photoresist is removed, and P-type ion implantation is performed to form the first P+ gate region. The same steps are then performed to form the second P+ gate region by P-type ion implantation. Subsequently, N+ source region is formed by N-type ion implantation.

[0050] In this embodiment, the doping concentration of the first P+ gate region is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width of the second P+ gate region is 1.0-6.0 μm, and the junction depth is not less than the thickness of the N-type secondary epitaxial layer 3 (it must be consistent with the thickness of the N-type secondary epitaxial layer to ensure that the doping of the first P+ gate region and the P+ buried layer can be connected). The doping concentration of the second P+ gate region 6 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is less than the thickness of the N-type secondary epitaxial layer 3. The doping concentration of the N+ source region 4 is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 0.5-2.0μm and the junction depth is 0.1μm-0.5μm.

[0051] Step 5: Deposit a passivation layer on the device surface.

[0052] Specifically, a sacrificial oxide layer is grown on the device surface, then the sacrificial layer is removed, and SiO2 / SiN is deposited. x A passivation layer is formed.

[0053] Step 6: Etch the passivation layer on a portion of the first P+ gate region, a portion of the second P+ gate region, and a portion of the N+ source region to form an ohmic contact window. Deposit metal on the upper surface of the first P+ gate region, the second P+ gate region, and the N+ source region to prepare the source and gate electrodes. Deposit metal on the lower surface of the N-type substrate to prepare the drain electrode.

[0054] Specifically, a source ohmic contact window is etched onto the passivation layer. Ni metal is deposited on the surface of the N+ source region and annealed to form an N-type ohmic contact, thus forming the source. A gate ohmic contact window is etched onto the passivation layer. Ti / Ni / Al metal is deposited on the surfaces of the first and second P+ gate regions and annealed to form a P-type ohmic contact, thus forming the gate. The device is then flipped and subjected to backside metal processing to form the drain.

[0055] The fabrication process of the grounded buried layer SiC JFET resistant to single-particle burn-out in this embodiment is as follows: Figure 4 As shown, Figure 4 This is a process flow diagram of the fabrication process of a grounded buried layer SiC JFET resistant to single-particle burn-out provided by an embodiment of the present invention.

[0056] For details regarding the fabrication method of the ground buried layer SiC JFET resistant to single-event burn-out and its corresponding beneficial effects, please refer to the relevant content on the ground buried layer SiC JFET resistant to single-event burn-out provided in the first aspect, which will not be repeated here.

[0057] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0059] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A grounded buried layer SiC JFET resistant to single-particle burn-out, characterized in that, include: N-type substrate (1); The N-type epitaxial layer (2) is located on the upper surface of the N-type substrate (1); The P+ buried layer (7) is located inside the N-type epitaxial layer (2); The N-type secondary epitaxial layer (3) is located on the upper surface of the N-type epitaxial layer (2); The first P+ gate region (5) and the second P+ gate region (6) are disposed at intervals inside the N-type secondary epitaxial layer (3). The first P+ gate region (5) extends in the vertical direction and contacts the P+ buried layer (7), so that the first P+ gate region (5) and the P+ buried layer (7) are electrically connected to form a continuous P-type pillar region. The second P+ gate region (6) is isolated from the P+ buried layer (7) in the vertical direction. The N+ source region (4) is located inside the N-type secondary epitaxial layer (3) between the first P+ gate region (5) and the second P+ gate region (6); The gate (9) includes a first gate and a second gate, wherein the first gate forms an ohmic contact on the upper surface of the first P+ gate region (5), and the second gate forms an ohmic contact on the upper surface of the second P+ gate region (6). The source electrode (10) forms an ohmic contact on the upper surface of the N+ source region (4); The drain (11) is located on the lower surface of the N-type substrate (1) and forms an ohmic contact; A passivation layer (8) is located on the device surface between the gate (9) and the source (10).

2. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The thickness of the N-type epitaxial layer (2) is 1-100 μm, and the doping concentration is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 .

3. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The doping concentration of the P+ buried layer (7) is 1×10 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0μm and the junction depth is 0-3μm.

4. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The doping concentration of the N-type secondary epitaxial layer (3) is 1×10⁻⁶. 14 cm -3 -1×10 17 cm -3 The thickness is 0.5-3μm.

5. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The doping concentration of the first P+ gate region (5) is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is not less than the thickness of the N-type secondary epitaxial layer (3).

6. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The doping concentration of the second P+ gate region (6) is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The width is 1.0-6.0 μm, and the junction depth is less than the thickness of the N-type secondary epitaxial layer (3).

7. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The doping concentration of the N+ source region (4) is 1×10 18 cm -3 -1×10 20 cm -3 The width is 0.5-2.0μm and the junction depth is 0.1μm-0.5μm.

8. The grounded buried layer SiC JFET resistant to single-particle burn-out according to claim 1, characterized in that, The first P+ gate region (5) is configured to receive a fixed reference potential through a first gate connected thereto, so as to fix the potential of the P+ buried layer (7), wherein the fixed reference potential is the ground potential.

9. A method for fabricating a SiC JFET with a grounded buried layer resistant to single-particle burn-out, characterized in that, The method for preparing the grounded buried layer SiC JFET resistant to single-particle burn-out as described in any one of claims 1-8 includes: Step 1: Epitaxially grow an N-type epitaxial layer on the upper surface of an N-type substrate; Step 2: Perform P-type ion implantation on the N-type epitaxial layer to form a P+ buried layer; Step 3: Epitaxially grow an N-type secondary epitaxial layer on the upper surface of the N-type epitaxial layer containing the P+ buried layer; Step 4: Perform two P-type ion implantations and one N-type ion implantation on the N-type secondary epitaxial layer to form a first P+ gate region, a second P+ gate region, and an N+ source region. The junction depth of the first P+ gate region is not less than the thickness of the N-type secondary epitaxial layer to achieve connection with the P+ buried layer. The second P+ gate region is isolated from the P+ buried layer in the vertical direction. Step 5: Deposit a passivation layer on the device surface; Step 6: Etch the passivation layer on a portion of the first P+ gate region, a portion of the second P+ gate region, and a portion of the N+ source region to form an ohmic contact window. Deposit metal on the upper surface of the first P+ gate region, the second P+ gate region, and the N+ source region to prepare the source and gate electrodes. Deposit metal on the lower surface of the N-type substrate to prepare the drain electrode.

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