Wafer testing method, system and storage medium for surface acoustic wave filter
By parsing configuration files and optimizing algorithms to automate port allocation, the problems of low efficiency, poor accuracy, and resource waste in surface acoustic wave filter wafer testing have been solved, achieving efficient and accurate test resource management.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LANSUS TECH INC
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-19
AI Technical Summary
Existing surface acoustic wave filter wafer testing methods are inefficient and inaccurate, making it difficult to adapt to diverse testing needs. They also have low resource utilization and lack intelligent decision-making capabilities, leading to configuration errors and resource waste.
By parsing configuration files and the vector network analyzer resource list, a communication connection is established. Optimization algorithms are used for port grouping and allocation to achieve automated testing, dynamically adapt to test scenarios, and optimize resource utilization.
It improved testing efficiency and accuracy, reduced human error, enhanced resource utilization and system adaptability, and shortened test preparation time.
Smart Images
Figure CN121923744B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and particularly to a wafer testing method, system, and storage medium for surface acoustic wave (SAW) filters. Background Technology
[0002] With the rapid iteration and large-scale deployment of 5G communication technology, surface acoustic wave (SAW) filters, as core components of the radio frequency front-end, play a crucial role in isolating communication frequency bands and avoiding signal crosstalk and noise interference. They are fundamental to the high-performance signal transmission of modern mobile communication devices, and their market demand has grown dramatically with the popularization of 5G terminals. In the mass production of SAW filter chips, wafer-level testing (Circuit Probing, CP) is a key step in ensuring product quality and improving production yield. It directly determines the performance consistency and reliability of the filter chip, and its testing accuracy and efficiency have a significant impact on cost control and market competitiveness throughout the entire production process.
[0003] Currently, as filter products develop towards miniaturization, high frequency, and high integration, their testing requirements are becoming increasingly complex. Multi-port, multi-site parallel testing has become an inevitable trend to improve testing efficiency and adapt to large-scale production. To achieve multi-port, multi-site testing of surface acoustic wave (SAW) filter wafers, the following three technical solutions are mainly used in existing technologies:
[0004] The first approach is to use a vector network analyzer with a large number of ports. This approach directly meets the needs of multi-port testing by integrating a large number of test ports into a single device, and features high integration and simple test links.
[0005] The second approach is to use multiple vector network analyzers with fewer ports, along with the official multi-port calibration and measurement expansion solution. This expands the ports by connecting multiple devices in parallel, which can improve testing flexibility to some extent.
[0006] The third approach is to use a vector network analyzer with fewer ports per card and implement time-division multiplexing of the ports through a switch matrix, thereby completing multi-port, multi-site testing. This approach has lower equipment costs.
[0007] However, in practical applications, the aforementioned existing technical solutions all rely on test engineers manually configuring equipment parameters and port connections according to test specifications. With the continuous development of 5G communication technology, the product specifications of surface acoustic wave (SAW) filters are becoming increasingly diversified, and the requirements for test frequency bands, number of ports, and test accuracy are constantly increasing, significantly increasing the complexity of testing. The traditional manual configuration method combined with existing technical solutions is gradually revealing many insurmountable problems, severely restricting the efficiency and accuracy of filter wafer testing, as follows:
[0008] First, the configuration efficiency is low. Every time the test specifications change, test engineers need to re-examine the test requirements, calculate the port allocation logic, and manually adjust the device parameters and port connection relationships. The whole process is time-consuming and cannot meet the needs of rapid switching of test specifications in large-scale production, which seriously affects the test throughput.
[0009] Secondly, configuration errors are prone to occur. The port allocation logic for multi-port and multi-site testing is complex. During manual calculation and configuration, problems such as incorrect port allocation and parameter setting deviations are very likely to occur. These errors will directly distort the true performance of the device under test (DUT), affect the accuracy of test results, and may even lead to qualified products being misjudged or unqualified products flowing into the next process, increasing production costs.
[0010] Third, poor adaptability. The configuration logic of the existing solution is deeply tied to the specific test system configuration and equipment specifications. When the test system equipment is replaced, the number of ports is adjusted, or the test requirements change significantly, the configuration solution needs to be redesigned, making it difficult to quickly adapt to changes in various test scenarios.
[0011] Fourth, resource utilization is low. The existing solution cannot dynamically optimize the allocation of test resources based on real-time test workload, test port requirements, and other actual conditions, resulting in some test ports being idle for a long time while others are overloaded, thus wasting test resources.
[0012] Fifth, there is a lack of intelligent decision-making capabilities. Existing technical solutions lack a unified intelligent port allocation algorithm, which cannot combine real-time test system operating status, complex test requirements, and equipment performance parameters to perform optimal port allocation calculations. It is difficult to achieve a balance between test efficiency, test accuracy, and resource utilization, and thus cannot meet the needs of large-scale testing with high precision, high efficiency, and low cost.
[0013] Therefore, there is an urgent need for a new wafer testing method, system, and storage medium for surface acoustic wave (SAW) filters to solve the above-mentioned technical problems. Summary of the Invention
[0014] This invention provides a wafer testing method, system, and storage medium for surface acoustic wave (SAW) filters, aiming to improve the efficiency and automation of SAW filter wafer testing and enhance the overall efficiency of wafer testing.
[0015] In a first aspect, the present invention provides a wafer testing method for surface acoustic wave (SAW) filters, the testing method comprising the following steps:
[0016] S1. Obtain and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list; the configuration file includes a hardware resource configuration file and a test specification, the hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier and network address, and the test specification includes the S-parameter trajectory list;
[0017] S2. Based on the vector network analyzer resource list, establish a communication connection with at least one vector network analyzer via a communication bus, and obtain the number of physical ports corresponding to each of the vector network analyzers with which the communication connection is established, thereby obtaining a port resource list;
[0018] S3. Group the ports according to the S-parameter trajectory list to obtain the first port grouping result;
[0019] S4. Obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB), and perform port grouping again based on the first port grouping result and the number of DUT sites to obtain the second port grouping result;
[0020] S5. Based on the second port grouping result and the port resource list, perform port allocation according to the optimization algorithm and preset constraints to obtain the final allocation scheme;
[0021] S6. Perform automated testing based on the final allocation scheme to obtain test results.
[0022] Preferably, step S1 includes the following sub-steps:
[0023] S11. Determine whether the file format of the configuration file is correct: if yes, proceed to step S12;
[0024] S12. Parse the hardware resource configuration file to obtain the vector network analyzer resource list; parse the test specification to obtain the S-parameter trajectory list.
[0025] Preferably, step S2 includes the following sub-steps:
[0026] S21. Traverse the vector network analyzers in the vector network analyzer resource list and establish a communication connection with each vector network analyzer in turn through the communication bus.
[0027] S22. Determine whether the vector network analyzer is successfully connected: if yes, send a query command to obtain the number of physical ports corresponding to the vector network analyzer and record the device status of the vector network analyzer; if no, mark the vector network analyzer as unavailable.
[0028] S23. Determine whether all the vector network analyzers have been traversed: if yes, generate the port resource list; if no, return to step S21.
[0029] Preferably, step S3 includes the following sub-steps:
[0030] S31. Initialize an empty set of port groups for the device under test;
[0031] S32. Iterate through each S-parameter trajectory in the S-parameter trajectory list and extract the port of the device under test corresponding to the S-parameter trajectory.
[0032] S33. Determine whether the port of the device under test already exists in any group of the port group set of the device under test: if not, create a new group for the port of the device under test and add it to the port group set of the device under test; if yes, merge the port of the device under test into the group corresponding to the port group set of the device under test.
[0033] S34. Determine whether all S-parameter trajectories have been traversed. If not, return to step S32. If yes, output the port grouping set of the device under test as the first port grouping result.
[0034] Preferably, step S4 includes the following sub-steps:
[0035] S41. Initialize an empty global port group list;
[0036] S42. Calculate the port offset of each of the sites of the device under test in sequence;
[0037] S43. Calculate the port grouping result corresponding to the current device under test site based on the port offset and the first port grouping result, and add it to the global port grouping list;
[0038] S44. Determine whether all the sites of the device under test have been traversed: if yes, output the global port grouping list as the second port grouping result; if no, return to step S42.
[0039] Preferably, step S5 includes the following sub-steps:
[0040] S51. Sort the second port grouping results based on the optimization algorithm to obtain the optimized second port grouping results;
[0041] S52. Traverse the optimized second port grouping results and assign the device under test port groups in the optimized second port grouping results to the vector network analyzers in the port resource list that meet the preset constraints, and obtain the allocation results;
[0042] S53. Optimize the allocation result based on the optimization objective of the optimization algorithm to obtain the final allocation scheme.
[0043] Preferably, the preset constraint is that the number of physical ports allocated to the same vector network analyzer does not exceed the total number of its physical ports;
[0044] The optimization objectives of the optimization algorithm include:
[0045] The minimum number of vector network analyzers should be used for testing.
[0046] The average number of physical ports used by the multiple vector network analyzers is then used;
[0047] The ports of the devices under test that do not need to share the same vector network analyzer are grouped and assigned to different vector network analyzers.
[0048] Secondly, the present invention also provides a wafer testing system for surface acoustic wave filters, the wafer testing system comprising:
[0049] The parsing module is used to acquire and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list. The configuration file includes a hardware resource configuration file and a test specification. The hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier, and network address. The test specification includes the S-parameter trajectory list.
[0050] The communication connection module is used to establish a communication connection with at least one vector network analyzer via a communication bus according to the vector network analyzer resource list, and to obtain the number of physical ports corresponding to each of the vector network analyzers for which a communication connection is established, thereby obtaining a port resource list;
[0051] The port grouping module is used to group ports according to the S-parameter trajectory list to obtain the first port grouping result;
[0052] The secondary grouping module is used to obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB), and to perform a second port grouping based on the first port grouping result and the number of DUT sites to obtain the second port grouping result.
[0053] The allocation module is used to allocate ports based on the second port grouping result and the port resource list, using an optimization algorithm and preset constraints, to obtain a final allocation scheme.
[0054] The testing module is used to perform automated testing based on the final allocation scheme and obtain test results.
[0055] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a wafer testing program for a surface acoustic wave filter stored in the memory and executable on the processor, wherein when the processor executes the wafer testing program for the surface acoustic wave filter, it implements the steps in the wafer testing method for the surface acoustic wave filter as described in any of the above embodiments.
[0056] Fourthly, the present invention also provides a computer-readable storage medium storing a wafer testing program for a surface acoustic wave (SAW) filter, wherein when the SAW filter wafer testing program is executed by a processor, the steps in the wafer testing method for a SAW filter as described in any of the above embodiments are implemented.
[0057] Compared to existing technologies, this invention, by parsing configuration files and establishing communication connections with at least one vector network analyzer via a communication bus based on the vector network analyzer resource list, can automatically identify currently available test resources and dynamically generate allocation schemes according to the test requirements. This allows for rapid adaptation to different test scenarios, improving the system's versatility and reusability, ensuring logical correctness of configuration and consistency of execution, and fundamentally avoiding human error. Through optimized algorithms, optimization goals such as minimum number of vector network analyzers, load balancing, and maximizing parallelism are clearly defined. Under the premise of meeting physical port constraints, the algorithmic approach seeks better allocation strategies, thereby improving the overall utilization efficiency of test resources such as instruments and ports. Simultaneously, the optimal port mapping relationship is automatically calculated, eliminating manual calculation steps and significantly shortening the test startup time from preparation to execution. Attached Figure Description
[0058] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:
[0059] Figure 1 This is a flowchart of the wafer testing method for surface acoustic wave filters provided in an embodiment of the present invention;
[0060] Figure 2 This is a schematic diagram of the wafer testing system for surface acoustic wave filters provided in an embodiment of the present invention;
[0061] Figure 3This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation
[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0063] Example 1
[0064] Please refer to Figure 1 This invention provides a wafer testing method for surface acoustic wave (SAW) filters. When performing the wafer testing of SAW filters, this invention employs an automated port allocation control system. The system architecture mainly includes the following components:
[0065] 1. Central Control and Computing Unit: Typically an industrial control computer or high-performance server, on which the automated port allocation control software of this invention runs. It is responsible for executing all calculation, decision-making, and scheduling instructions in the process flow.
[0066] 2. Test Resource Pool: This pool consists of multiple test instruments connected to a central control unit via standard buses (such as GPIB, LAN, USB, PXIe, etc.) and under its unified control. In this invention, the test instruments specifically refer to vector network analyzers (VNAs) used for RF parameter testing. The test resource pool can be structured as follows:
[0067] a. A multiport vector network analyzer.
[0068] b. Multiple vector network analyzers with a small number of ports.
[0069] c. A virtual multiport system formed by expanding a vector network analyzer with a limited number of ports using a multiplexer matrix.
[0070] 3. Wafer Probe Station: Used to carry and position the surface acoustic wave (SAW) filter wafer under test. The probes on its probe card contact the solder balls of the device under test on the wafer, forming an electrical connection path. The probe station also communicates with the central control unit to receive movement and positioning commands.
[0071] 4. Port Connection Network: This includes RF cables, adapters, and possibly a switch matrix, used to flexibly connect the physical test ports of each vector network analyzer in the test resource pool to the corresponding channels on the wafer prober. The specific connection relationships are configured by the central control unit according to the calculated allocation scheme.
[0072] The connection relationship between the components is as follows: the central control and computing unit is connected to the test resource pool (each vector network analyzer), the wafer probe station and the programmable port connection network (such as the switch matrix controller) through the communication bus, thereby forming a closed-loop test system with centralized control and distributed execution.
[0073] The wafer testing method for the surface acoustic wave filter includes the following steps:
[0074] S1. Obtain and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list; the configuration file includes a hardware resource configuration file and a test specification, the hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier and network address, and the test specification includes the S-parameter trajectory list.
[0075] In this embodiment of the invention, step S1 includes the following sub-steps:
[0076] S11. Determine whether the file format of the configuration file is correct: if yes, proceed to step S12;
[0077] S12. Parse the hardware resource configuration file to obtain the vector network analyzer resource list; parse the test specification to obtain the S-parameter trajectory list. For example, each S-parameter trajectory is named in the format S{i}{j}, where i and j are the output and input port numbers of that signal link in the device under test. For example, the trajectory list [S11, S21, S31, S54] indicates the port combination relationship of the device under test to be tested. This step extracts all S{i}{j} trajectory information by parsing the test specification.
[0078] S2. Based on the vector network analyzer resource list, establish a communication connection with at least one vector network analyzer via a communication bus, and obtain the number of physical ports corresponding to each vector network analyzer with which the communication connection is established, thereby obtaining a port resource list.
[0079] In this embodiment of the invention, establishing a communication connection with the vector network analyzer means that the central control and computing unit establishes a connection with the vector network analyzer through a communication bus. Step S2 includes the following sub-steps:
[0080] S21. Traverse the vector network analyzers in the vector network analyzer resource list and establish a communication connection with each vector network analyzer in turn through the communication bus.
[0081] S22. Determine whether the vector network analyzer is successfully connected: if yes, send a query command to obtain the number of physical ports corresponding to the vector network analyzer and record the device status of the vector network analyzer; if no, mark the vector network analyzer as unavailable.
[0082] S23. Determine whether all the vector network analyzers have been traversed: if yes, generate the port resource list; if no, return to step S21.
[0083] S3. Group the ports according to the S-parameter trajectory list to obtain the first port grouping result.
[0084] In this embodiment of the invention, step S3 includes the following sub-steps:
[0085] S31. Initialize an empty set of port groups for the device under test;
[0086] S32. Iterate through each S-parameter trajectory in the S-parameter trajectory list and extract the port of the device under test corresponding to the S-parameter trajectory.
[0087] S33. Determine whether the port of the device under test already exists in any group of the port group set of the device under test: if not, create a new group for the port of the device under test and add it to the port group set of the device under test; if yes, merge the port of the device under test into the group corresponding to the port group set of the device under test.
[0088] S34. Determine whether all S-parameter trajectories have been traversed. If not, return to step S32. If yes, output the port grouping set of the device under test as the first port grouping result.
[0089] In this embodiment of the invention, by traversing the S-parameter trajectory list, the ports of the device under test are automatically divided into several test groups based on the test correlation between ports.
[0090] The grouping logic is as follows: For a trajectory S{i}{j}, it represents a test signal input from port j and output from port i. Therefore, ports i and j must be connected to the test instrument (i.e., a vector network analyzer) at the same time. Based on this, all ports appearing in the same or a group of related trajectories are grouped into the same group.
[0091] For example, for the trajectory list [S21, S31, S54], the algorithm analysis yields:
[0092] S21 is associated with ports 2 and 1.
[0093] S31 is associated with ports 3 and 1 (port 1 has already appeared).
[0094] S54 is associated with ports 5 and 4.
[0095] The grouping results are as follows: ports {1, 2, 3} are grouped into the first group (because they appear together in the test requirements of S21 and S31), and ports {4, 5} are grouped into the second group.
[0096] S4. Obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB). Based on the first port grouping result and the number of DUT sites, perform port grouping again to obtain the second port grouping result.
[0097] In this embodiment of the invention, multi-site parallel testing is often used in wafer testing to improve throughput, meaning that multiple identical devices under test (DUTs) can be tested simultaneously with a single probe card contact. This invention obtains test groups for multiple DUT sites by regularly replicating the single-site DUT grouping pattern from step S3 to all sites. Here, a DUT site refers to the test station / test position of a single DUT on the same entire wafer.
[0098] Step S4 includes the following sub-steps:
[0099] S41. Initialize an empty global port group list;
[0100] S42. Calculate the port offset of each of the sites of the device under test in sequence;
[0101] S43. Calculate the port grouping result corresponding to the current device under test site based on the port offset and the first port grouping result, and add it to the global port grouping list;
[0102] S44. Determine whether all the sites of the device under test have been traversed: if yes, output the global port grouping list as the second port grouping result; if no, return to step S42.
[0103] For example, suppose a single site is grouped as [Group_A, Group_B, ...], with each group containing n ports. If M sites need to be tested, the total number of ports is the number of ports per site multiplied by M. The expanded ports are numbered sequentially according to the original grouping pattern.
[0104] If a single site is grouped as [(1,2,3),(4,5)], and configured for a 2-site test (Site 0 and Site 1), then the expanded groupings are:
[0105] First site: Site0:[(1,2,3),(4,5)];
[0106] Second site Site1: [(6,7,8),(9,10)] (Port number increments from Site0);
[0107] The final global port group list is: [(1,2,3),(4,5),(6,7,8),(9,10)].
[0108] S5. Based on the second port grouping result and the port resource list, port allocation is performed according to the optimization algorithm and preset constraints to obtain the final allocation scheme.
[0109] In this embodiment of the invention, step S5 includes the following sub-steps:
[0110] S51. Sort the second port grouping results based on the optimization algorithm to obtain the optimized second port grouping results;
[0111] S52. Traverse the optimized second port grouping results and assign the device under test port groups in the optimized second port grouping results to the vector network analyzers in the port resource list that meet the preset constraints, and obtain the allocation results;
[0112] S53. Optimize the allocation result based on the optimization objective of the optimization algorithm to obtain the final allocation scheme.
[0113] In this embodiment of the invention, the preset constraint is: the number of physical ports allocated to the same vector network analyzer does not exceed the total number of its physical ports;
[0114] The optimization objectives of the optimization algorithm include:
[0115] (1) Prioritize using the minimum number of the aforementioned vector network analyzers for testing;
[0116] (2) Under the premise of meeting the preset constraints, the number of physical ports used by the multiple vector network analyzers is averaged to avoid individual instruments becoming performance bottlenecks;
[0117] (3) As far as possible, the ports of the device under test that are not related (do not need to share the same vector network analyzer) are grouped and assigned to different vector network analyzers.
[0118] The optimization algorithm used in this invention is a heuristic algorithm (such as First-FitDecreasing). Of course, other optimization algorithms are also feasible and can be set according to the actual situation.
[0119] For example, suppose there are three vector network analyzers: a first vector network analyzer (1:4 port), a second vector network analyzer (2:4 port), and a third vector network analyzer (3:4 port). The optimized grouping result for the second port is [(1,2,3),(4,5),(6,7,8),(9,10)]. A feasible allocation scheme is as follows:
[0120] The first vector network analyzer is assigned (1,2,3) (using port 3);
[0121] The second vector network analyzer is assigned to (4,5) and (9,10) (using 4 ports);
[0122] The third vector network analyzer is assigned to ports (6, 7, 8) (using 3 ports);
[0123] The solution satisfies the constraints and achieves good load balancing.
[0124] S6. Perform automated testing based on the final allocation scheme to obtain test results.
[0125] In this embodiment of the invention, the following steps are performed when executing the actual test process:
[0126] S61. Configure the instruments. Configure each vector network analyzer in sequence, set its operating frequency, power, intermediate frequency bandwidth and other parameters, and create corresponding measurement channels and traces in the instrument according to the assigned port groups of the device under test. For example, configure S21 and S31 measurements for the vector network analyzer assigned to port (1,2,3).
[0127] S62. Control Probe Station and Connection: Control the wafer probe station to move to the test position, making the probes contact the wafer. If the system includes a programmable switch matrix, control the switch states according to the allocation scheme to establish the correct physical connection path.
[0128] S63. Trigger Measurement and Data Collection: Send a synchronization trigger signal to all vector network analyzers to initiate parallel measurements. After the measurements are completed, read the corresponding S-parameter data from each instrument.
[0129] S64. Data Processing and Report Generation: Process, analyze, and judge the collected raw data, generate test reports, and mark qualified and unqualified chips on the wafer.
[0130] Compared to existing technologies, this invention, by parsing configuration files and establishing communication connections with at least one vector network analyzer via a communication bus based on the vector network analyzer resource list, can automatically identify currently available test resources and dynamically generate allocation schemes according to the test requirements. This allows for rapid adaptation to different test scenarios, improving the system's versatility and reusability, ensuring logical correctness of configuration and consistency of execution, and fundamentally avoiding human error. Through optimized algorithms, optimization goals such as minimum number of vector network analyzers, load balancing, and maximizing parallelism are clearly defined. Under the premise of meeting physical port constraints, the algorithmic approach seeks better allocation strategies, thereby improving the overall utilization efficiency of test resources such as instruments and ports. Simultaneously, the optimal port mapping relationship is automatically calculated, eliminating manual calculation steps and significantly shortening the test startup time from preparation to execution.
[0131] Example 2
[0132] This invention also provides a wafer testing system for surface acoustic wave filters, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of a wafer testing system 200 for a surface acoustic wave filter provided in an embodiment of the present invention, which includes:
[0133] 201. A parsing module is used to acquire and parse the configuration file of the surface acoustic wave filter under test to obtain an S-parameter trajectory list and a vector network analyzer resource list. The configuration file includes a hardware resource configuration file and a test specification. The hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier, and network address. The test specification includes the S-parameter trajectory list.
[0134] 202. A communication connection module, used to establish a communication connection with at least one vector network analyzer via a communication bus according to the vector network analyzer resource list, and to obtain the number of physical ports corresponding to each of the vector network analyzers for which a communication connection is established, thereby obtaining a port resource list;
[0135] 203. Port grouping module, used to group ports according to the S-parameter trajectory list to obtain the first port grouping result;
[0136] 204. Secondary grouping module, used to obtain the number of device-under-test sites on the wafer of the surface acoustic wave filter under test, and to perform secondary port grouping based on the first port grouping result and the number of device-under-test sites to obtain the second port grouping result;
[0137] 205. Allocation module, used to allocate ports based on the second port grouping result and the port resource list according to the optimization algorithm and preset constraints, to obtain the final allocation scheme;
[0138] 206. The testing module is used to perform automated testing based on the final allocation scheme and obtain test results.
[0139] The wafer testing system 200 for the surface acoustic wave filter can implement the steps in the wafer testing method for the surface acoustic wave filter as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.
[0140] Example 3
[0141] This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a wafer test program for a surface acoustic wave filter stored in the memory 302 and capable of running on the processor 301.
[0142] The processor 301 calls the wafer testing program for the surface acoustic wave filter stored in the memory 302 and executes the steps in the wafer testing method for the surface acoustic wave filter provided in this embodiment of the invention. Please refer to... Figure 3 Specifically, it includes the following steps:
[0143] The wafer testing method for the surface acoustic wave filter includes the following steps:
[0144] S1. Obtain and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list; the configuration file includes a hardware resource configuration file and a test specification, the hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier and network address, and the test specification includes the S-parameter trajectory list.
[0145] In this embodiment of the invention, step S1 includes the following sub-steps:
[0146] S11. Determine whether the file format of the configuration file is correct: if yes, proceed to step S12;
[0147] S12. Parse the hardware resource configuration file to obtain the resource list of the vector network analyzer;
[0148] The test specification is parsed to obtain the S-parameter trajectory list. For example, each S-parameter trajectory is named in the format S{i}{j}, where i and j are the output and input port numbers of that signal link in the device under test. For example, the trajectory list [S11, S21, S31, S54] indicates the port combination relationship of the device under test to be tested. This step extracts all S{i}{j} trajectory information by parsing the test specification.
[0149] S2. Based on the vector network analyzer resource list, establish a communication connection with at least one vector network analyzer via a communication bus, and obtain the number of physical ports corresponding to each vector network analyzer with which the communication connection is established, thereby obtaining a port resource list.
[0150] In this embodiment of the invention, step S2 includes the following sub-steps:
[0151] S21. Traverse the vector network analyzers in the vector network analyzer resource list and establish a communication connection with each vector network analyzer in turn through the communication bus.
[0152] S22. Determine whether the vector network analyzer is successfully connected: if yes, send a query command to obtain the number of physical ports corresponding to the vector network analyzer and record the device status of the vector network analyzer; if no, mark the vector network analyzer as unavailable.
[0153] S23. Determine whether all the vector network analyzers have been traversed: if yes, generate the port resource list; if no, return to step S21.
[0154] S3. Group the ports according to the S-parameter trajectory list to obtain the first port grouping result.
[0155] In this embodiment of the invention, step S3 includes the following sub-steps:
[0156] S31. Initialize an empty set of port groups for the device under test;
[0157] S32. Iterate through each S-parameter trajectory in the S-parameter trajectory list and extract the port of the device under test corresponding to the S-parameter trajectory.
[0158] S33. Determine whether the port of the device under test already exists in any group of the port group set of the device under test: if not, create a new group for the port of the device under test and add it to the port group set of the device under test; if yes, merge the port of the device under test into the group corresponding to the port group set of the device under test.
[0159] S34. Determine whether all S-parameter trajectories have been traversed. If not, return to step S32. If yes, output the port grouping set of the device under test as the first port grouping result.
[0160] In this embodiment of the invention, by traversing the S-parameter trajectory list, the ports of the device under test are automatically divided into several test groups based on the test correlation between ports.
[0161] The grouping logic is as follows: For a trajectory S{i}{j}, it represents a test signal input from port j and output from port i. Therefore, ports i and j must be connected to the test instrument (i.e., a vector network analyzer) at the same time. Based on this, all ports appearing in the same or a group of related trajectories are grouped into the same group.
[0162] For example, for the trajectory list [S21, S31, S54], the algorithm analysis yields:
[0163] S21 is associated with ports 2 and 1.
[0164] S31 is associated with ports 3 and 1 (port 1 has already appeared).
[0165] S54 is associated with ports 5 and 4.
[0166] The grouping results are as follows: ports {1, 2, 3} are grouped into the first group (because they appear together in the test requirements of S21 and S31), and ports {4, 5} are grouped into the second group.
[0167] S4. Obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB). Based on the first port grouping result and the number of DUT sites, perform port grouping again to obtain the second port grouping result.
[0168] In this embodiment of the invention, multi-site parallel testing is often used in wafer testing to improve throughput, meaning that multiple identical devices under test (DUTs) can be tested simultaneously with a single probe card contact. This invention obtains test groups for multiple DUT sites by regularly replicating the single-site DUT grouping pattern from step S3 to all sites. Here, a DUT site refers to the test station / test position of a single DUT on the same entire wafer.
[0169] Step S4 includes the following sub-steps:
[0170] S41. Initialize an empty global port group list;
[0171] S42. Calculate the port offset of each of the sites of the device under test in sequence;
[0172] S43. Calculate the port grouping result corresponding to the current device under test site based on the port offset and the first port grouping result, and add it to the global port grouping list;
[0173] S44. Determine whether all the sites of the device under test have been traversed: if yes, output the global port grouping list as the second port grouping result; if no, return to step S42.
[0174] For example, suppose a single site is grouped as [Group_A, Group_B, ...], with each group containing n ports. If M sites need to be tested, the total number of ports is the number of ports per site multiplied by M. The expanded ports are numbered sequentially according to the original grouping pattern.
[0175] If a single site is grouped as [(1,2,3),(4,5)], and configured for a 2-site test (Site 0 and Site 1), then the expanded groupings are:
[0176] First site: Site0:[(1,2,3),(4,5)];
[0177] Second site Site1: [(6,7,8),(9,10)] (Port number increments from Site0);
[0178] The final global port group list is: [(1,2,3),(4,5),(6,7,8),(9,10)].
[0179] S5. Based on the second port grouping result and the port resource list, port allocation is performed according to the optimization algorithm and preset constraints to obtain the final allocation scheme.
[0180] In this embodiment of the invention, step S5 includes the following sub-steps:
[0181] S51. Sort the second port grouping results based on the optimization algorithm to obtain the optimized second port grouping results;
[0182] S52. Traverse the optimized second port grouping results and assign the device under test port groups in the optimized second port grouping results to the vector network analyzers in the port resource list that meet the preset constraints, and obtain the allocation results;
[0183] S53. Optimize the allocation result based on the optimization objective of the optimization algorithm to obtain the final allocation scheme.
[0184] In this embodiment of the invention, the preset constraint is: the number of physical ports allocated to the same vector network analyzer does not exceed the total number of its physical ports;
[0185] The optimization objectives of the optimization algorithm include:
[0186] (1) Prioritize using the minimum number of the aforementioned vector network analyzers for testing;
[0187] (2) Under the premise of meeting the preset constraints, the number of physical ports used by the multiple vector network analyzers is averaged to avoid individual instruments becoming performance bottlenecks;
[0188] (3) As far as possible, the ports of the device under test that are not related (do not need to share the same vector network analyzer) are grouped and assigned to different vector network analyzers.
[0189] The optimization algorithm used in this invention is a heuristic algorithm (such as First-FitDecreasing). Of course, other optimization algorithms are also feasible and can be set according to the actual situation.
[0190] For example, suppose there are three vector network analyzers: a first vector network analyzer (1:4 port), a second vector network analyzer (2:4 port), and a third vector network analyzer (3:4 port). The optimized grouping result for the second port is [(1,2,3),(4,5),(6,7,8),(9,10)]. A feasible allocation scheme is as follows:
[0191] The first vector network analyzer is assigned (1,2,3) (using port 3);
[0192] The second vector network analyzer is assigned to (4,5) and (9,10) (using 4 ports);
[0193] The third vector network analyzer is assigned to ports (6, 7, 8) (using 3 ports);
[0194] The solution satisfies the constraints and achieves good load balancing.
[0195] S6. Perform automated testing based on the final allocation scheme to obtain test results.
[0196] In this embodiment of the invention, the following steps are performed when executing the actual test process:
[0197] S61. Configure the instruments. Configure each vector network analyzer in sequence, set its operating frequency, power, intermediate frequency bandwidth and other parameters, and create corresponding measurement channels and traces in the instrument according to the assigned port groups of the device under test. For example, configure S21 and S31 measurements for the vector network analyzer assigned to port (1,2,3).
[0198] S62. Control Probe Station and Connection: Control the wafer probe station to move to the test position, making the probes contact the wafer. If the system includes a programmable switch matrix, control the switch states according to the allocation scheme to establish the correct physical connection path.
[0199] S63. Trigger Measurement and Data Collection: Send a synchronization trigger signal to all vector network analyzers to initiate parallel measurements. After the measurements are completed, read the corresponding S-parameter data from each instrument.
[0200] S64. Data Processing and Report Generation: Process, analyze, and judge the collected raw data, generate test reports, and mark qualified and unqualified chips on the wafer.
[0201] The computer device 300 provided in this embodiment of the invention can implement the steps in the wafer testing method of surface acoustic wave filter as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.
[0202] Example 4
[0203] This invention also provides a computer-readable storage medium storing a wafer testing program for a surface acoustic wave (SAW) filter. When executed by a processor, the SAW filter wafer testing program implements the various processes and steps in the SAW filter wafer testing method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.
[0204] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0205] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0206] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0207] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.
Claims
1. A wafer testing method for a surface acoustic wave (SAW) filter, characterized in that, The testing method includes the following steps: S1. Obtain and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list; the configuration file includes a hardware resource configuration file and a test specification, the hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier and network address, and the test specification includes the S-parameter trajectory list; S2. Based on the vector network analyzer resource list, establish a communication connection with at least one vector network analyzer via a communication bus, and obtain the number of physical ports corresponding to each of the vector network analyzers with which the communication connection is established, thereby obtaining a port resource list; S3. Group the ports according to the S-parameter trajectory list to obtain the first port grouping result; S4. Obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB), and perform port grouping again based on the first port grouping result and the number of DUT sites to obtain the second port grouping result; S5. Based on the second port grouping result and the port resource list, perform port allocation according to the optimization algorithm and preset constraints to obtain the final allocation scheme; S6. Perform automated testing based on the final allocation scheme to obtain the test results; Step S5 includes the following sub-steps: S51. Sort the second port grouping results based on the optimization algorithm to obtain the optimized second port grouping results; S52. Traverse the optimized second port grouping results and assign the device under test port groups in the optimized second port grouping results to the vector network analyzers in the port resource list that meet the preset constraints, and obtain the allocation results; S53. Optimize the allocation result based on the optimization objective of the optimization algorithm to obtain the final allocation scheme; The preset constraint is that the number of physical ports allocated to the same vector network analyzer shall not exceed the total number of its physical ports. The optimization objectives of the optimization algorithm include: The minimum number of vector network analyzers should be used for testing. The number of physical ports used by the multiple vector network analyzers is averaged; The ports of the devices under test that do not need to share the same vector network analyzer are grouped and assigned to different vector network analyzers.
2. The wafer testing method for a surface acoustic wave filter as described in claim 1, characterized in that, Step S1 includes the following sub-steps: S11. Determine if the file format of the configuration file is correct: if yes, proceed to step S12; S12. Parse the hardware resource configuration file to obtain the vector network analyzer resource list; parse the test specification to obtain the S-parameter trajectory list.
3. The wafer testing method for surface acoustic wave filters as described in claim 1, characterized in that, Step S2 includes the following sub-steps: S21. Traverse the vector network analyzers in the vector network analyzer resource list and establish a communication connection with each vector network analyzer in turn through the communication bus. S22. Determine whether the vector network analyzer is successfully connected: if yes, send a query command to obtain the number of physical ports corresponding to the vector network analyzer and record the device status of the vector network analyzer; if no, mark the vector network analyzer as unavailable. S23. Determine whether all the vector network analyzers have been traversed: if yes, generate the port resource list; if no, return to step S21.
4. The wafer testing method for a surface acoustic wave filter as described in claim 1, characterized in that, Step S3 includes the following sub-steps: S31. Initialize an empty set of port groups for the device under test; S32. Iterate through each S-parameter trajectory in the S-parameter trajectory list and extract the port of the device under test corresponding to the S-parameter trajectory. S33. Determine whether the port of the device under test already exists in any group of the port group set of the device under test: if not, create a new group for the port of the device under test and add it to the port group set of the device under test; if yes, merge the port of the device under test into the group corresponding to the port group set of the device under test. S34. Determine whether all S-parameter trajectories have been traversed. If not, return to step S32. If yes, output the port grouping set of the device under test as the first port grouping result.
5. The wafer testing method for a surface acoustic wave filter as described in claim 1, characterized in that, Step S4 includes the following sub-steps: S41. Initialize an empty global port group list; S42. Calculate the port offset of each of the sites of the device under test in sequence; S43. Calculate the port grouping result corresponding to the current device under test site based on the port offset and the first port grouping result, and add it to the global port grouping list; S44. Determine whether all the sites of the device under test have been traversed: if yes, output the global port grouping list as the second port grouping result; if no, return to step S42.
6. A wafer testing system for a surface acoustic wave filter, characterized in that, The wafer testing system includes: The parsing module is used to acquire and parse the configuration file of the surface acoustic filter under test to obtain the S-parameter trajectory list and the vector network analyzer resource list. The configuration file includes a hardware resource configuration file and a test specification. The hardware resource configuration file includes vector network analyzer information, vector network analyzer identifier, and network address. The test specification includes the S-parameter trajectory list. The communication connection module is used to establish a communication connection with at least one vector network analyzer via a communication bus according to the vector network analyzer resource list, and to obtain the number of physical ports corresponding to each of the vector network analyzers for which a communication connection is established, thereby obtaining a port resource list; The port grouping module is used to group ports according to the S-parameter trajectory list to obtain the first port grouping result; The secondary grouping module is used to obtain the number of device-under-test (DUT) sites on the wafer of the surface acoustic wave filter under test (SAWB), and to perform a second port grouping based on the first port grouping result and the number of DUT sites to obtain the second port grouping result. The allocation module is used to allocate ports based on the second port grouping result and the port resource list, using an optimization algorithm and preset constraints, to obtain a final allocation scheme. The testing module is used to perform automated testing based on the final allocation scheme and obtain test results.
7. A computer device, characterized in that, include: The method includes a memory, a processor, and a wafer testing program for a surface acoustic wave filter stored in the memory and executable on the processor. When the processor executes the wafer testing program for the surface acoustic wave filter, it implements the steps of the wafer testing method for a surface acoustic wave filter as described in any one of claims 1-5.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a wafer testing program for a surface acoustic wave (SAW) filter, which, when executed by a processor, implements the steps of the wafer testing method for a SAW filter as described in any one of claims 1-5.