Monitoring node and monitoring system of nuclear fusion control device

Abstract

The invention relates to a monitoring node and a monitoring system of a nuclear fusion control device. The node comprises a transparent transmission module, a synchronous monitoring module, a self-checking module and a local clock, the transparent transmission module is used for latching an inbound timestamp and an outbound timestamp of the time synchronization message by using the hardware timestamp unit to obtain a residence time increment and accumulating the residence time increment to a time synchronization message correction domain; the synchronous monitoring module is used for triggering the monitoring sensor to acquire data when the current time is consistent with the triggering time, and obtaining a data acquisition result according to the transmitted monitoring data and a latched transmission timestamp when the monitoring data is transmitted; the self-checking module is used for responding to a self-checking instruction latch instruction issuing timestamp and outputting a self-checking signal to the feedback transmission unit; performing waveform fitting on the received feedback data to obtain a waveform feature and a waveform feature timestamp; and obtaining a node self-checking result according to the instruction issuing timestamp, the waveform feature timestamp and the waveform feature. By adopting the node, the monitoring reliability of the nuclear fusion control device can be improved.

Description

A monitoring node and monitoring system for a nuclear fusion control device Technical Field

[0001] This application relates to the field of precision measurement and control technology, and in particular to a monitoring node and monitoring system for a nuclear fusion control device. Background Technology

[0002] With the development of nuclear fusion control technology, magnetic confinement fusion devices such as fully superconducting tokamak devices have emerged, and the operation of these devices is gradually moving towards steady-state and high-parameter operation. To ensure the stable operation of fusion control devices, a large number of distributed monitoring nodes need to be deployed to achieve real-time monitoring of various physical indicators. However, in the extreme operating environment of fusion control devices, monitoring nodes using traditional measurement, control, and communication architectures often struggle to achieve reliable monitoring of the device. Summary of the Invention

[0003] Therefore, it is necessary to provide a monitoring node and monitoring system for a nuclear fusion control device to address the aforementioned technical problems.

[0004] Firstly, this application provides a monitoring node for a nuclear fusion control device, including:

[0005] FPGA-based transparent transmission module, synchronous monitoring module, self-test module, and local clock;

[0006] The transparent transmission module is used to latch the current time of the local clock using a hardware timestamp unit deployed at the physical layer boundary when a time synchronization message is detected to be incoming or outgoing, so as to obtain the inbound timestamp and outbound timestamp of the time synchronization message; to obtain the dwell time increment of the time synchronization message based on the inbound timestamp and outbound timestamp, and to accumulate the dwell time increment into the correction field of the outgoing time synchronization message.

[0007] The synchronization monitoring module is used to trigger the monitoring sensors of the nuclear fusion control device to collect data when the current time of the local clock is consistent with the trigger time of the data acquisition task; when monitoring data from the monitoring sensors is detected, the current time of the local clock is latched to obtain the input timestamp of the monitoring data; and the data acquisition result of the data acquisition task is obtained based on the monitoring data and the input timestamp.

[0008] The self-test module is used to respond to a node self-test command by latching the current time of the local clock to obtain a command issuance timestamp and outputting a self-test signal to the feedback transmission unit outside the node; performing waveform fitting processing on the received feedback data to obtain the waveform characteristics of the feedback data and the waveform characteristic timestamp of the feedback data corresponding to the local clock; obtaining the node self-test result based on the command issuance timestamp, the waveform characteristic timestamp, and the waveform characteristics; the feedback data is obtained by sampling the feedback signal from the feedback transmission unit.

[0009] In one embodiment, the transparent transmission module is configured to: latch the current time of the local clock on the first rising clock edge after the arrival of the start-of-frame symbol of the time synchronization message using an input double data rate primitive, to obtain the inbound timestamp of the time synchronization message; and latch the current time of the local clock within the same clock tick after the start-of-frame symbol of the time synchronization message is detected using an output double data rate primitive, to obtain the outbound timestamp of the time synchronization message.

[0010] In one embodiment, the transparent transmission module is further configured to: cache incoming time synchronization messages using a first-in-first-out queue.

[0011] In one embodiment, the synchronization monitoring module includes a hardware timing comparator, which is used to: compare the current time of the local clock with the trigger time of the data acquisition task in each clock cycle; when the current time matches the trigger time, output a trigger level signal to the monitoring sensor of the nuclear fusion control device; the trigger level signal is used to trigger the monitoring sensor to perform data acquisition.

[0012] In one embodiment, the synchronization monitoring module is further configured to: encapsulate the data acquisition results into a data packet and send the data packet to the service network.

[0013] In one embodiment, the self-test module is configured to: use a digital signal processor to perform waveform fitting processing on the received feedback data to obtain a fitted waveform corresponding to the feedback data; and obtain the waveform characteristics of the feedback data based on the waveform amplitude and edge slope of the fitted waveform.

[0014] In one embodiment, the self-test module is configured to: perform waveform fitting processing on the received feedback data using a digital signal processor to obtain a fitted waveform corresponding to the feedback data; and align the moment when the fitted waveform crosses a feature threshold with a local clock to obtain a waveform feature timestamp of the feedback data.

[0015] In one embodiment, the self-test module is configured to: obtain the physical response delay of the monitoring node based on the instruction issuance timestamp and the waveform feature timestamp; obtain a node self-test result indicating a self-test abnormality when the physical response delay is greater than a delay threshold, or when the waveform feature indicates waveform distortion; and send the node self-test result to the service network.

[0016] In one embodiment, the node further includes a magnetic latching relay and a power management chip; the power management chip is used to supply power to the FPGA; the magnetic latching relay is used to turn off the power management chip under the drive of a remote shutdown signal; the magnetic latching relay is also used to turn on the power management chip under the drive of a remote restart signal.

[0017] Secondly, this application also provides a monitoring system for a nuclear fusion control device, comprising:

[0018] The aforementioned monitoring nodes; there are multiple monitoring nodes, and the monitoring nodes are connected in a daisy chain manner.

[0019] The monitoring nodes and monitoring system of the aforementioned nuclear fusion control device provide a highly coupled, integrated hardware architecture for node measurement, control, and communication by offering a transparent transmission module, a synchronization monitoring module, a self-test module, and a local clock based on a Field Programmable Gate Array (FPGA) within the monitoring nodes. Specifically, by utilizing the transparent transmission module to send and receive time synchronization messages, and by using a hardware timestamp unit deployed at the physical layer boundary to latch the current time of the local clock upon detecting incoming and outgoing time synchronization messages, single-clock-cycle-level hard latching of the inbound and outbound timestamps can be achieved without processing through higher-level protocol stacks. This allows for the calculation of a high-precision dwell time increment, stripped of dwell time jitter, based on the inbound and outbound timestamps even in the event of congestion within the node. This enables dynamic correction of the correction domain of the outgoing time synchronization messages, facilitating the maintenance of time synchronization accuracy in multi-level node cascading scenarios. Specifically, by utilizing a synchronous monitoring module to control monitoring sensors for data acquisition and latching the corresponding input timestamps when monitoring data is received, the triggering of monitoring data acquisition and timestamp allocation can be decentralized to the FPGA's underlying logic. This achieves absolute and strict alignment of monitoring data on the timeline without any software intervention, providing high-confidence data support for causal analysis and precise source tracing of transient events such as plasma rupture. Furthermore, by using a self-testing module for monitoring node self-testing, the module latches the command issuance timestamp upon receiving a node self-test command and outputs a self-test signal to the feedback transmission unit outside the node. This self-test signal, after passing through the feedback transmission unit, is transmitted back to the monitoring node as a feedback signal. Sampling and waveform fitting of this feedback signal allows for the accurate extraction of waveform features of the physical signal and waveform feature timestamps characterizing the signal response. Based on the command issuance timestamp, waveform feature timestamp, and waveform features, the signal processing capabilities of the monitoring node can be self-tested at the hardware level from multiple aspects, including waveform health and physical response delay, yielding accurate node self-test results. Meanwhile, by integrating the aforementioned modules into an FPGA chip and using the FPGA's built-in local clock as the global time reference, the monitoring node ensures that all time-sensitive core actions within each module can be completed in a closed loop within the same clock domain of the FPGA's absolute time coordinate system. This avoids the non-deterministic delays caused by cross-module and cross-software stack operations, enabling high-precision time reference sharing and underlying hardware-level collaboration among functional modules. Therefore, the monitoring node and system of the aforementioned nuclear fusion control device can achieve deterministic and highly reliable transparent transmission, synchronous monitoring, and closed-loop self-testing in the extreme operating environment of the nuclear fusion control device. Furthermore, utilizing this node and system can improve the reliability of monitoring the nuclear fusion control device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a schematic diagram of the architecture of the monitoring node of a nuclear fusion control device in one embodiment;

[0022] Figure 2 is a schematic diagram of the operation logic of the remote maintenance module in one embodiment;

[0023] Figure 3 is a schematic diagram of the architecture of the monitoring node of the nuclear fusion control device in another embodiment;

[0024] Figure 4 is a schematic diagram of the operation logic of the transparent transmission module in one embodiment;

[0025] Figure 5 is a schematic diagram of the operation logic of the synchronization monitoring module in one embodiment;

[0026] Figure 6 is a schematic diagram of the operation logic of the self-test module in one embodiment;

[0027] Figure 7 is an internal structural diagram of the monitoring system of a nuclear fusion control device in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0030] In the field of nuclear fusion control devices, with the application of magnetic confinement fusion devices such as fully superconducting tokamaks and the development of fusion control devices towards steady-state and high-parameter operation, monitoring nodes deployed around fusion control devices need to operate in environments with extremely strong stray magnetic fields and high-frequency electromagnetic radiation interference. They also need to withstand the transient massive data surges during fusion experiments and meet stringent nanosecond-level physical timing requirements. Traditional monitoring nodes use general-purpose measurement and control systems and commercial communication architectures that typically treat node clock synchronization, data acquisition, status monitoring, and reset maintenance as independent functional modules, loosely coupled through software or upper-level systems. However, this deployment approach often fails to achieve reliable monitoring of the device under extreme operating conditions.

[0031] On the one hand, in the monitoring of nuclear fusion control devices, in order to adapt to the vast spatial distribution, it is usually necessary to deploy a monitoring system including a large number of distributed monitoring nodes, which are often connected in a daisy-chain topology. In order to maintain the time synchronization accuracy of the precise clock synchronization protocol of the network measurement and control system, namely the IEEE 1588 Precision Timing Protocol (PTP), the related technologies usually use a transparent clock mechanism to correct the residence time. Traditional transparent clock mechanisms are mostly based on commercial Ethernet switching chips or standard field-programmable gate arrays (FPGAs) media access control (MAC) layer IP cores, and are often tagged only after the time synchronization message enters the higher-level logic of the MAC layer. However, this approach is typically based on an ideal line-speed forwarding model (such as ideal line-speed crossbar forwarding). While it can maintain accuracy under normal network load, it is highly susceptible to instantaneous congestion in the underlying crossbars and buffer queues within nodes when faced with the massive concurrent diagnostic data generated by the instantaneous plasma discharge in nuclear fusion experiments. Time synchronization messages are forced to undergo highly uncertain queuing delays within the nodes, and traditional MAC layer dwell time calculation models cannot accurately isolate this dynamic queuing jitter. This results in a rapid decay of time synchronization accuracy after multiple levels of node cascading, and even divergence and loss of lock. This accuracy decay severely limits the scalability of the monitoring network and prevents the entire network from being established on a unified high-precision time reference.

[0032] On the other hand, when using a monitoring system with multiple distributed monitoring nodes for multimodal synchronous monitoring tasks, it is usually necessary to time-stamp the physical quantities (such as magnetic probe signals, microwave reflectometer data, etc.) collected by different nodes to achieve time alignment of the monitoring data. Related technologies typically employ a loosely coupled architecture of "front-end hardware acquisition plus host computer software marking" for data acquisition and time marking. This usually involves using a separate timing receiver card to recover the global time, followed by signal digitization via another data acquisition system. The two are ultimately linked at the industrial control computer level through the operating system's timestamp association. In this architecture, monitoring data is transmitted to the host computer via a Peripheral Component Interconnect Express (PCIe) or Ethernet bus, and software marking is performed by the host computer's operating system's network stack (e.g., timestamp allocation via the operating system's network protocol stack and interrupt scheduling mechanism). Therefore, in the path from the physical sampling point to the marked time, when the computer software finally allocates a system timestamp to the monitoring data, a non-deterministic "soft delay" across the software operating system is introduced. Consequently, the timestamp recorded in the data is not the actual physical moment of the signal occurrence, but rather a logical moment after complex software processing. This kind of nondeterministic jitter can easily cause data collected by different sensors to be out of alignment on the same time axis, making it difficult to meet the needs of nanosecond-level precision diagnosis and analysis of transient events such as plasma rupture.

[0033] Meanwhile, traditional monitoring nodes, after issuing trigger commands, often achieve status readback by reading their internal logic state or by relying on digital I / O interfaces to monitor high and low logic transitions such as Transistor-Transistor Logic (TTL) and Complementary Metal-Oxide-Semiconductor (CMOS) levels. However, traditional self-testing methods based on digital levels can usually only determine whether a signal has been logically issued. They cannot detect the distortion of analog waveforms (such as rising edge degradation and amplitude abnormalities) caused by long-distance transmission, radiation aging, or impedance mismatch in the physical link of a nuclear fusion device monitoring site. They also cannot accurately obtain the transmission delay from command issuance to physical signal feedback, which can easily lead to the system being in a "blind control" state.

[0034] Moreover, the traditional monitoring node's multiple functional modules are independent and loosely coupled, which not only leads to high hardware resource requirements and high power consumption, but also makes it difficult to achieve precise coordination between functional modules, making it difficult to reliably monitor the nuclear fusion control device.

[0035] Based on this, the embodiments of this application provide an integrated node architecture for highly reliable operation and maintenance, which features "closed-loop self-testing, transparent transmission, and synchronous monitoring". It takes the nanosecond-level PTP global time base built into the main control FPGA inside the monitoring node as the core hub, and realizes deep hardware-level coupling of multiple functional modules at the physical layer and data link layer. This enables multiple modules to share underlying hardware resources and timing logic, and can achieve deterministic and highly reliable transparent transmission, synchronous monitoring, and closed-loop self-testing in the extreme operating environment of nuclear fusion control devices, thereby improving the monitoring reliability of nuclear fusion control devices.

[0036] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0037] In one embodiment, as shown in FIG1, a monitoring node for a nuclear fusion control device is provided, which includes an FPGA-based transparent transmission module, a synchronization monitoring module, a self-test module, and a local clock.

[0038] In this embodiment, the monitoring node can be one of the nodes in the monitoring system of the nuclear fusion control device. It can use a Field Programmable Gate Array (FPGA) chip as the main control chip, and a Physical Layer (PHY) chip provides the uplink and downlink interfaces for the node. The nodes in the system can be connected in a daisy-chain topology. The FPGA chip can integrate a local clock based on the Precision Timing Protocol (PTP), which can be used to maintain a nanosecond-level global time counter. This counter can be strictly locked to the main clock in terms of frequency and phase.

[0039] The transparent transmission module is used to latch the current time of the local clock using a hardware timestamp unit deployed at the physical layer boundary when a time synchronization message is detected to be incoming or outgoing. This process yields the inbound and outbound timestamps of the time synchronization message. Based on the inbound and outbound timestamps, the module obtains the dwell time increment of the time synchronization message and adds the dwell time increment to the correction field of the outgoing time synchronization message.

[0040] In this system, the monitoring node acts as a transparent clock to relay time synchronization messages, forwarding them from the upstream node to the downstream node. It also utilizes a transparent transmission module integrated into the FPGA chip to calculate the dwell time increment of the time synchronization message within the node, thereby updating the correction field (CF) of the time synchronization message. For example, the time synchronization message can be a Precision Timing Protocol (PTP) message, which can be used for time synchronization by downstream nodes.

[0041] The transparent transmission module may include a hardware timestamp unit (TSU) deployed at the physical layer boundary. This TSU can be located at the boundary between the physical layer and the data link layer, for example, within the input / output block (IOB) of an FPGA chip. For instance, a monitoring node can use the inbound Ethernet physical layer chip A (hereinafter referred to as PHY A) to parse the time synchronization message from the upstream node into a digital stream and transmit it to the FPGA chip. When the transparent transmission module detects the incoming digital stream (e.g., when it detects the arrival of the Start-of-Frame Delimiter (SFD)), it can use the hardware timestamp unit to instantaneously latch the global timestamp of the current local clock within a single clock tick, obtaining the inbound timestamp t1 of the time synchronization message. Similarly, when the transparent transmission module detects that the digital stream of the time synchronization message is sent to the Ethernet physical layer chip B (hereinafter referred to as PHY B) of the outbound interface of the monitoring node (for example, when the SFD leaves the FPGA chip pin), the hardware timestamp unit can be used to instantly latch the global timestamp of the current local clock within a single clock tick to obtain the outbound timestamp t2 of the time synchronization message.

[0042] In the tail data stream processing stage where the time synchronization message is about to be sent, the hardware pipeline adder of the transparent transmission module can calculate the dwell time increment (ΔT = t2 - t1) of the time synchronization message based on the inbound timestamp t1 and the outbound timestamp t2. This dwell time increment can cover all queuing jitter of the time synchronization message within the FPGA chip. Subsequently, the transparent transmission module can add this dwell time increment ΔT to the correction field within the time synchronization message in real time without disrupting the Ethernet frame structure of the time synchronization message. For example, the transparent transmission module can use a frame modification unit to modify the correction field of the time synchronization message. This frame modification unit can be integrated inside the transparent transmission module or integrated into the FPGA chip and can be called by the transparent transmission module. For example, when a time synchronization message is transmitted, the transparent transmission module can use the frame modification unit to read the original correction value (Old_CF) in the message correction field (CF), and add the dwell time increment ΔT to the correction field to obtain a new correction value (New_CF = Old_CF + ΔT), and synchronously recalculate the message's frame check sequence (FCS). Through the fully hardware pipelined operation of the transparent transmission module, the time synchronization message forwarded by this node to the downstream node can accurately cover the congestion delay introduced by the node itself. Thus, when the downstream node parses the message, it can know and deduct the forwarding time of all upstream nodes, thereby achieving logically "transparent" lossless cascading synchronization.

[0043] The synchronous monitoring module is used to trigger the monitoring sensors of the nuclear fusion control device to collect data when the current time of the local clock is consistent with the trigger time of the data acquisition task; when the monitoring data from the monitoring sensor is detected, the current time of the local clock is latched to obtain the input timestamp of the monitoring data; and the data acquisition result of the data acquisition task is obtained based on the monitoring data and the input timestamp.

[0044] The monitoring nodes can be connected to the monitoring sensors of the nuclear fusion control device, and utilize a synchronous monitoring module integrated into the FPGA chip to collect data from the nuclear fusion control device and its environment through the monitoring sensors, as well as to time-tagged the data transmitted from the monitoring sensors. For example, the monitoring sensors may include, but are not limited to, magnetic field sensors (e.g., magnetic probes), microwave reflectometers, etc.

[0045] The synchronization monitoring module compares the current time of the local clock with the trigger time of the data acquisition task. When the current time matches the trigger time, it outputs a trigger signal to drive the front-end analog-to-digital converter (ADC) of the monitoring node to start operating, converting the physical signals provided by the monitoring sensor into digital signals (i.e., monitoring data), and then transmitting the monitoring data to the FPGA chip in the form of a digital stream. When the monitoring sensor is an active sensor, a trigger signal can also be output to the sensor to control it to sense the corresponding physical quantity. When monitoring data is transmitted to the input / output (I / O) pins of the FPGA chip, the synchronization monitoring module can intercept the data using a data flow control state machine. Within a single system clock cycle when the monitoring data is effectively read into the register, the state machine synchronously latches the current global timestamp of the local clock to obtain the transmission timestamp of the monitoring data. The synchronization monitoring module can also perform high-bit-width register-level concatenation of the monitoring data and the transmission timestamp at the data link layer, and obtain the data acquisition result corresponding to the data acquisition task based on the concatenated "time data composite".

[0046] The self-test module is used to respond to the node self-test command, latch the current time of the local clock to obtain the command issuance timestamp, and output the self-test signal to the feedback transmission unit outside the node; perform waveform fitting processing on the received feedback data to obtain the waveform characteristics of the feedback data and the waveform characteristic timestamp of the feedback data corresponding to the local clock; obtain the node self-test result based on the command issuance timestamp, waveform characteristic timestamp, and waveform characteristics; the feedback data is obtained by sampling the feedback signal from the feedback transmission unit.

[0047] For example, the node panel of the monitoring node may be provided with a trigger output interface and a trigger input interface. A feedback transmission unit may be connected to both the trigger output interface and the trigger input interface of the node, respectively. This unit can be used to transmit the signal received from the trigger output interface of the monitoring node to the trigger input interface of the node. For example, the feedback transmission unit may be a coaxial cable shorting the trigger output interface and the trigger input interface, or it may be a signal transmission channel including the device under test. For example, the monitoring node may also include an analog-to-digital converter (ADC), which can be connected to the trigger input interface of the node and used to sample the feedback signal received from the feedback transmission unit through that interface to obtain corresponding feedback data.

[0048] The monitoring node can perform a self-test using a self-test module integrated into the FPGA chip. In response to a node self-test command, the self-test module outputs a self-test signal to the external feedback transmission unit and simultaneously latches the current time of the local clock to obtain the command issuance timestamp T_tx. For example, the node self-test command can be issued by the node's main control logic or by a host computer. For example, the self-test module can drive the node's underlying I / O units to generate a 5V TTL pulse signal and output it as a self-test signal to the feedback transmission unit via a trigger output interface.

[0049] In the absence of a physical disconnection, the feedback transmission unit, upon receiving a self-test signal, transmits it to the trigger input interface of the monitoring node, allowing the monitoring node to receive the feedback signal from the feedback transmission unit. The monitoring node can then use an onboard analog-to-digital converter to physically quantize the actual voltage waveform of the feedback signal to obtain feedback data in the form of a continuously sampled data stream. For example, a high-speed, high-precision analog-to-digital converter (e.g., a 16-bit, 80MSPS sampling rate ADC) can be used for sampling to convert the physical feedback signal into a high-frequency continuously sampled data stream with an interval of 12.5 nanoseconds.

[0050] The self-test module can use algorithms such as polynomial fitting and linear interpolation to perform waveform fitting on the received feedback data, reconstructing the true physical waveform of the feedback signal using discrete feedback data sampling points. Then, corresponding waveform features and waveform feature timestamps can be extracted from this waveform. For example, the waveform features of the feedback data can include one or more of waveform amplitude and edge slope, and the waveform feature timestamp of the feedback data can be the global timestamp of the local clock corresponding to the moment when the waveform crosses a feature threshold (e.g., 50% threshold level).

[0051] The node self-test result can be obtained based on the command issuance timestamp of the node self-test instruction, and the waveform feature timestamp and waveform features extracted from the feedback data. For example, when the waveform feature timestamp cannot be extracted, or when the time difference between the waveform feature timestamp and the command issuance timestamp is greater than a preset threshold, a node self-test result indicating a physical disconnection can be obtained. For example, when the waveform feature indicates that the waveform amplitude is lower than a preset safety threshold, or when the waveform feature indicates that the signal edge is degraded, a node self-test result indicating waveform distortion can be obtained.

[0052] In the monitoring nodes of the aforementioned nuclear fusion control device, by providing a transparent transmission module, a synchronization monitoring module, a self-test module, and a local clock based on a Field Programmable Gate Array (FPGA), a highly coupled integrated hardware architecture based on the underlying layer can be provided for the node's measurement, control, and communication. Specifically, by utilizing the transparent transmission module to send and receive time synchronization messages, and by using a hardware timestamp unit deployed at the physical layer boundary to latch the current time of the local clock when detecting incoming and outgoing time synchronization messages, single-clock-cycle-level hard latching of the inbound and outbound timestamps can be achieved without processing through higher-level protocol stacks. Therefore, even in the event of congestion within the node, a high-precision dwell time increment, stripped of dwell time jitter, can still be calculated based on the inbound and outbound timestamps. This allows for dynamic correction of the correction domain of the outgoing time synchronization message, which is beneficial for ensuring time synchronization accuracy in multi-level node cascading. Specifically, by utilizing a synchronous monitoring module to control monitoring sensors for data acquisition and latching the corresponding input timestamps when monitoring data is received, the triggering of monitoring data acquisition and timestamp allocation can be decentralized to the FPGA's underlying logic. This achieves absolute and strict alignment of monitoring data on the timeline without any software intervention, providing high-confidence data support for causal analysis and precise source tracing of transient events such as plasma rupture. Furthermore, by using a self-testing module for monitoring node self-testing, the module latches the command issuance timestamp upon receiving a node self-test command and outputs a self-test signal to the feedback transmission unit outside the node. This self-test signal, after passing through the feedback transmission unit, is transmitted back to the monitoring node as a feedback signal. Sampling and waveform fitting of this feedback signal allows for the accurate extraction of waveform features of the physical signal and waveform feature timestamps characterizing the signal response. Based on the command issuance timestamp, waveform feature timestamp, and waveform features, the signal processing capabilities of the monitoring node can be self-tested at the hardware level from multiple aspects, including waveform health and physical response delay, yielding accurate node self-test results. Meanwhile, by integrating the aforementioned modules into an FPGA chip and using the FPGA's built-in local clock as the global time reference, the monitoring node ensures that all time-sensitive core actions within each module can be completed in a closed loop within the same clock domain of the FPGA's absolute time coordinate system. This avoids the non-deterministic delays caused by cross-module and cross-software stack operations, enabling high-precision time reference sharing and underlying hardware-level collaboration among functional modules. Therefore, the monitoring node and system of the aforementioned nuclear fusion control device can achieve deterministic and highly reliable transparent transmission, synchronous monitoring, and closed-loop self-testing in the extreme operating environment of the nuclear fusion control device. Furthermore, utilizing this node and system can improve the reliability of monitoring the nuclear fusion control device.

[0053] In an exemplary embodiment, the transparent transmission module can be used to: latch the current time of the local clock on the first rising edge of the clock after the arrival of the start-of-frame symbol of the time synchronization message, using the input double data rate primitive, to obtain the inbound timestamp of the time synchronization message; and latch the current time of the local clock within the same clock tick after the start-of-frame symbol of the time synchronization message is detected, using the output double data rate primitive, to obtain the outbound timestamp of the time synchronization message.

[0054] For example, the hardware timestamp unit of the transparent transmission module may include an Input Double Data Rate (IDDR) primitive and an Output Double Data Rate (ODDR) primitive. The IDDR primitive can be set at the lowest layer interface between the Ethernet physical layer chip A (PHY A) at the inbound end and the data link layer of the FPGA chip, while the ODDR primitive can be set at the lowest layer interface between the data link layer of the FPGA chip and the Ethernet physical layer chip B (PHY B) at the outbound end.

[0055] At the inbound end, when PHY A parses the time synchronization message into a digital stream and sends it into the FPGA, the transparent transmission module can use the IDDR primitive to instantaneously latch the current timestamp of the local clock on the first rising clock edge upon detecting the arrival of the start-of-frame (SFD) character of the time synchronization message, thus obtaining the inbound timestamp t1 of the time synchronization message. At the outbound end, when the time synchronization message is sent to PHY B, the transparent transmission module can use the ODDR primitive to instantaneously latch the current timestamp of the local clock within a single clock cycle of the start-of-frame (SFD) character leaving the FPGA pin, thus obtaining the outbound timestamp t2 of the time synchronization message.

[0056] In this embodiment, by using the IDDR and ODDR primitives at the interface between the physical layer and the data link layer to perform nanosecond-level bidirectional hard latching of the arrival and departure times of time synchronization messages, the actual dwell time increment of the time synchronization message in the node can be calculated with extremely high precision in a single clock cycle, which is beneficial to ensure high-precision time relay in daisy chain cascaded networks.

[0057] In one exemplary embodiment, the transparent transmission module can also be used to: buffer incoming time synchronization messages using a first-in-first-out queue.

[0058] The transparent transmission module can utilize a first-in-first-out (FIFO) queue to buffer incoming time synchronization messages. For example, when a time synchronization message from the upstream node conflicts with a massive amount of local business data, the transparent transmission module will not discard the time synchronization message. Instead, it will import the message into the FPGA chip's first-in-first-out (FIFO) queue buffer. The time synchronization message can then queue and wait for forwarding until the node's transmission link becomes idle before being sent to the outgoing interface (PHY B), thus preventing message loss caused by data surges.

[0059] In this embodiment, by constructing a queuing mechanism that forces data to pass through a FIFO queue, time synchronization messages can be cached in transient massive data concurrency scenarios such as nuclear fusion experiments. This can avoid message loss caused by data floods and help ensure high-precision time relay in daisy chain cascaded networks.

[0060] In an exemplary embodiment, the synchronization monitoring module includes a hardware timing comparator, which can be used to: compare the current time of the local clock with the trigger time of the data acquisition task in each clock cycle; and trigger the monitoring sensors of the nuclear fusion control device to acquire data when the current time matches the trigger time.

[0061] The synchronous monitoring module may include a hardware timing comparator instantiated within the FPGA. This comparator continuously compares the dynamic current timestamp of the local clock with the trigger time of the data acquisition task every clock cycle (e.g., 125MHz, or 8 nanosecond intervals). When the comparison determines that the current timestamp and the trigger time are strictly equal, the comparator can output a trigger signal to the front-end analog-to-digital converter (ADC) of the monitoring node at a nanosecond level to drive the ADC to start data acquisition, converting the physical signals provided by the monitoring sensor into digital signals (i.e., monitoring data), and transmitting the monitoring data to the FPGA chip in the form of a digital stream. When the monitoring sensor is an active sensor, a trigger signal can also be output to the sensor to control it to sense the corresponding physical quantity.

[0062] In this embodiment, by using a PTP-based local clock as the global time base, a hardware timing comparator is used to compare the current time of the local clock with the trigger time of the data acquisition task. When the two are equal, the comparator outputs a trigger signal at the nanosecond level, which can realize the absolute spatiotemporal synchronization of the actions of all nodes in the monitoring system, thereby enabling synchronous monitoring data acquisition of the nuclear fusion control device.

[0063] In one exemplary embodiment, the synchronous monitoring module can also be used to: encapsulate the data acquisition results into data packets and send the data packets to the business network.

[0064] After obtaining the data acquisition results from the data acquisition task, the synchronous monitoring module can directly push the data acquisition results, which include monitoring data and input timestamps, into the FPGA's built-in User Datagram Protocol / Internet Protocol (UDP / IP) hardware protocol stack for packet encapsulation. The encapsulated data packets are then sent to the service network through the FPGA's underlying Media Access Control (MAC) layer.

[0065] In this embodiment, by having the synchronous monitoring module encapsulate the data acquisition results into data packets and send them to the service network, the entire process from "physical signal capture" to "high-precision synchronous data packet generation" can be completed without the participation of any microprocessor instruction cycle. This avoids timing pollution caused by interrupt nesting and task scheduling, and is conducive to achieving absolute spatiotemporal alignment of cross-modal diagnostic data.

[0066] In an exemplary embodiment, the self-test module can be used to: perform waveform fitting processing on the received feedback data using a digital signal processor to obtain a fitted waveform corresponding to the feedback data; and obtain the waveform characteristics of the feedback data based on the waveform amplitude and edge slope of the fitted waveform.

[0067] The self-test module may include a hard-core operator of a digital signal processor (DSP) integrated into the FPGA. When feedback data is received, the self-test module can invoke the DSP operator to perform waveform fitting processing on the feedback data to obtain the fitted waveform corresponding to the feedback data. For example, the DSP operator can perform polynomial fitting and linear interpolation algorithms on the rising or falling edge data sequence of the waveform captured in the feedback data to achieve waveform fitting of the feedback signal.

[0068] Specifically, based on the fitted waveform obtained using feedback data, its waveform amplitude and edge slope can be extracted, thereby obtaining the waveform characteristics of the feedback data. For example, the waveform characteristics of the feedback data may include the waveform amplitude, rising edge slope, and falling edge slope of the fitted waveform, and may also include edge degradation information obtained based on the rising edge slope and falling edge slope.

[0069] In this embodiment, by utilizing a physical feature extraction architecture that integrates "high-speed analog continuous sampling and DSP waveform interpolation fitting", it is possible to accurately fit and restore the feedback signal waveform. Based on the fitted waveform, various waveform features such as waveform amplitude and edge slope can be extracted, which is beneficial for accurate diagnosis of possible waveform distortion.

[0070] In an exemplary embodiment, the self-test module can be used to: perform waveform fitting processing on the received feedback data using a digital signal processor to obtain a fitted waveform corresponding to the feedback data; and align the moment when the fitted waveform crosses a feature threshold with a local clock to obtain a waveform feature timestamp of the feedback data.

[0071] The self-test module may include a hard-core operator of a digital signal processor (DSP) integrated into the FPGA. When feedback data is received, the self-test module can invoke the DSP operator to perform waveform fitting processing on the feedback data to obtain the fitted waveform corresponding to the feedback data. For example, the DSP operator can perform polynomial fitting and linear interpolation algorithms on the rising or falling edge data sequence of the waveform captured in the feedback data to achieve waveform fitting of the feedback signal.

[0072] Based on the fitted waveform, the absolute time when the waveform crosses a characteristic threshold (such as 50% threshold level) can be accurately calculated, which can be used to characterize the return time of the feedback signal. This absolute time can then be aligned and marked with the global time reference provided by the local clock to obtain the waveform characteristic timestamp of the feedback data.

[0073] In this embodiment, by using the DSP operator integrated in the FPGA to perform waveform fitting processing on the feedback data, it is possible to achieve accurate fitting and restoration of the feedback signal waveform. This can overcome the limitation of the physical sampling rate of the ADC, accurately calculate the absolute time when the sub-nanosecond waveform crosses the feature threshold, and obtain the corresponding waveform feature timestamp by deeply binding with the global time base provided by the underlying PTP-based local clock. This is beneficial for the subsequent accurate calculation of the physical response delay of the monitoring node.

[0074] In an exemplary embodiment, the self-test module can be used to: obtain the physical response delay of the monitoring node based on the instruction issuance timestamp and waveform feature timestamp; obtain the node self-test result indicating self-test abnormality when the physical response delay is greater than the delay threshold, or when the waveform feature indicates waveform distortion; and send the node self-test result to the service network.

[0075] The self-test module, after obtaining the waveform feature timestamp and waveform feature, can combine the instruction issuance timestamp of the node self-test instruction to determine whether there is an abnormality in the monitored node, and when it is determined that there is an abnormality, it obtains the node self-test result indicating the self-test abnormality.

[0076] For example, the self-test module can subtract the instruction issuance timestamp T_tx from the waveform feature timestamp T_rx to obtain the physical response delay (ΔT = T_rx - T_tx), which includes cable transmission delay, isolation optocoupler delay, and driver response delay. The physical response delay is then compared with a preset delay threshold. If the physical response delay is greater than the delay threshold, a node self-test result indicating a self-test anomaly can be obtained.

[0077] For example, the self-test module can also determine whether the waveform features meet the waveform distortion conditions. If the waveform features meet the waveform distortion conditions, a self-test result indicating an abnormal self-test can be obtained. For example, the waveform distortion conditions may include the waveform amplitude of the fitted waveform being lower than a preset safety threshold, or the edge slope of the fitted waveform indicating edge degradation.

[0078] For example, the self-test module can generate a node self-test result indicating a self-test anomaly within 100 microseconds of determining that a node has an abnormal condition, and send it to the service network. For example, the node self-test result indicating a self-test anomaly may include hardware-level alarm flags.

[0079] In this embodiment, by calculating the physical response delay of the monitoring node based on the command issuance timestamp and waveform feature timestamp, the actual physical delay from command issuance to physical signal feedback can be accurately measured. By comparing this physical response delay with a delay threshold, abnormal situations such as physical disconnection of the monitoring node can be effectively detected. Furthermore, by analyzing waveform features, waveform distortions such as "waveform edge softening" or "abnormal amplitude attenuation" caused by cable aging or impedance mismatch can be keenly detected. Combining this online "waveform checkup" with absolute time difference measurement capability can effectively solve the hidden danger of "blind control" in nuclear fusion control systems, realizing a leap from passive troubleshooting to proactive predictive diagnosis in equipment operation and maintenance.

[0080] In an exemplary embodiment, the node may further include a magnetic latching relay and a power management chip; the power management chip is used to power the FPGA; the magnetic latching relay is used to turn off the power management chip under the drive of a remote shutdown signal; the magnetic latching relay is also used to turn on the power management chip under the drive of a remote restart signal.

[0081] The monitoring node may also include a remote maintenance module independent of the main control FPGA logic pins and the conventional service power supply network; this module can be a purely hardware control line. An external controller (such as a remote maintenance server) remotely restarts the FPGA chip and other underlying peripheral chips of the monitoring node through this independent control line.

[0082] For example, the remote maintenance module may include a magnetic latching relay and a power management chip, and its underlying operating logic and signal flow can be as shown in Figure 2. The power management chip can be used to power the FPGA in the monitoring chip and the underlying peripheral chips, and the mechanical contacts of the magnetic latching relay can be directly connected in series with the enable (EN) terminal of the power management chip.

[0083] The external controller can send a remote shutdown signal to the monitoring node, directly driving the magnetic latching relay to flip, thereby shutting down the power management chip and cutting off the power tree of the main control FPGA and core peripheral chips. For example, the remote shutdown signal can be an open collector (OC) drive pulse signal. Since the magnetic latching relay has an embedded permanent magnet, it only requires an external pulse current to drive it during the instant of state switching (within a few milliseconds). Once the state switching is complete, it can lock the state using its internal permanent magnet force without any holding current.

[0084] The external controller can also send a remote restart signal to the monitoring node after a preset time interval (e.g., several seconds) following the issuance of the remote shutdown signal. This causes the magnetic latching relay to flip under the drive of the signal, thereby turning on the power management chip and restoring power supply to the main control FPGA and core peripheral chips. For example, the remote restart signal can be a pulse signal with the opposite direction to the remote shutdown signal.

[0085] In this embodiment, for remote maintenance of monitoring nodes, the traditional maintenance method relying on FPGA logic pin response reset signals is abandoned. Instead, a remote maintenance module independent of the main control FPGA logic and power supply network is constructed using magnetic latching relays and power management chips. This module can be directly driven by external OC control commands, achieving reliable underlying physical power-off and restart without interfering with the transparent transmission of the cascaded network. Based on this remote maintenance module, even if the FPGA experiences single-event upsets (SEUs) due to high-energy neutrons or strong electromagnetic radiation, causing underlying power rail abnormalities or a complete state machine failure, rendering conventional pin reset commands ineffective, a forced physical power-off and cold start for deeply frozen nodes can still be achieved. Furthermore, because the magnetic latching relay has a permanent magnet embedded inside, it only requires an external pulse current to drive it during the moment of state switching. Once the state switching is complete, it can lock the state using the internal permanent magnet force without any holding current. Therefore, even in the strong stray alternating magnetic field around a nuclear fusion tokamak device, the passive locking characteristic of the magnetic latching relay can resist the false triggering of strong stray magnetic fields. This effectively avoids the problem of a surge in coil induced current or even uncontrolled false engagement / disengagement of the iron core that is very likely to occur in ordinary electromagnetic relays in such an environment, leading to unexpected power outages at the node. Thus, by utilizing the remote maintenance module in this embodiment, the monitoring node can achieve a pure hardware-level cold start without manual intervention and unaffected by false triggering of strong magnetic fields. This transforms the shutdown and maintenance that often takes several hours in traditional solutions into a highly reliable online physical self-healing process that takes only seconds, fundamentally ensuring the system's long-term continuous operation capability under harsh conditions.

[0086] In one exemplary embodiment, a monitoring node for a nuclear fusion control device is provided.

[0087] For example, please refer to Figure 3, which is a schematic diagram of the overall architecture of the monitoring node in this embodiment. As shown in Figure 3, the monitoring node may include an FPGA-based local clock, a transparent transmission module, a synchronous monitoring module, a self-test module, and a remote maintenance module. The local clock, transparent transmission module, synchronous monitoring module, and self-test module can be highly coupled within the main control FPGA chip. The transparent transmission module, synchronous monitoring module, and self-test module can deeply share the global time base based on PTP provided by the local clock (i.e., the local clock can provide "same-source time empowerment" for each module), thereby meeting the stringent hardware timing requirements for monitoring nuclear fusion control devices.

[0088] For example, the monitoring node may further include an Ethernet physical layer chip A (PHY A) at the inbound end, an Ethernet physical layer chip B (PHY B) at the outbound end, and physical layer hardware links. The Ethernet physical layer chips PHY A and PHY B can be Gigabit Ethernet physical layer chips. The node can provide uplink and downlink Reduced Gigabit Media Independent Interfaces (RGMII) through PHY A and PHY B respectively, thereby enabling cascading with upstream and downstream nodes to construct a highly reliable physical layer daisy-chain cascaded network. The physical layer hardware links may include driver and output circuits and high-speed analog-to-digital converters.

[0089] For example, the underlying operating logic and data flow of the transparent transmission module can be shown in Figure 4. The transparent transmission module may include an IDDR primitive located at the lowest level interface between the Ethernet physical layer chip A (PHY A) at the inbound end and the data link layer of the FPGA chip, and an ODDR primitive located at the lowest level interface between the data link layer of the FPGA chip and the Ethernet physical layer chip B (PHY B) at the outbound interface. At the inbound end, when PHY A parses the time synchronization message into a digital stream and sends it to the FPGA, the media access control receiving module (MAC receiving module) of the transparent transmission module can call the IDDR primitive to instantaneously latch the current timestamp of the local clock on the first rising edge of the clock when the start of frame symbol (SFD) of the time synchronization message is detected, thus obtaining the inbound timestamp t1 of the time synchronization message. Subsequently, the transparent transmission module can use a deep first-in-first-out (FIFO) queue to buffer the incoming time synchronization message until the node's transmission link is idle before sending the time synchronization message to the outbound interface (PHY B). When a time synchronization message is sent to PHY B, the Media Access Control (MAC) sending module of the transparent transmission module can use the ODDR primitive to instantaneously latch the current timestamp of the local clock within a single clock tick when the start-of-frame (SFD) symbol of the time synchronization message leaves the FPGA pin, thus obtaining the outgoing timestamp t2 of the time synchronization message. During the tail data stream processing stage when the time synchronization message is about to complete transmission, the hardware pipeline adder of the transparent transmission module can calculate the dwell time increment (ΔT = t2 - t1) of the time synchronization message based on the incoming timestamp t1 and the outgoing timestamp t2. This dwell time increment can cover all queuing jitter of the time synchronization message within the FPGA chip. Subsequently, the transparent transmission module can accumulate this dwell time increment ΔT in real time to the correction field (CF) inside the time synchronization message without disrupting the Ethernet frame structure of the time synchronization message, and synchronously recalculate the frame check sequence (FCS).

[0090] For example, the underlying operating logic and data flow of the synchronous monitoring module can be shown in Figure 5. The synchronous monitoring module may include a hardware timing comparator instantiated within the FPGA. This comparator continuously compares the dynamic current timestamp of the local clock with the trigger time of the data acquisition task every clock cycle (e.g., 125MHz, i.e., an 8-nanosecond interval). When the comparison determines that the current timestamp and the trigger time are strictly equal, the comparator can instantly generate a low-level hardware trigger pulse through the drive and output circuits of the physical layer hardware circuit at the nanosecond level. This pulse drives the front-end analog-to-digital converter (ADC) of the monitoring node to start operating, thereby quantizing and converting the physical signal provided by the monitoring sensor into a digital signal (i.e., monitoring data), and transmitting the monitoring data to the FPGA chip in the form of a digital stream. For example, this ADC can be a 24-bit high-precision ADC. When the monitoring sensor is an active sensor, a trigger signal can also be output to the sensor to control the sensor to sense the corresponding physical quantity. When monitoring data is transmitted to the input / output (I / O) pins of the FPGA chip, the synchronous monitoring module can intercept the data using a data flow control state machine. Within a single system clock cycle when the monitoring data is effectively read into the register, the state machine synchronously latches the current global timestamp of the local clock to obtain the transmission timestamp of the monitoring data. Subsequently, at the data link layer, the monitoring data and the transmission timestamp can be concatenated at a high bit width register level. Based on the concatenated "time data complex," the data acquisition result corresponding to the data acquisition task is obtained, and the data acquisition result is encapsulated into a data packet before being sent to the service network.

[0091] For example, the underlying operating logic and data flow of the self-test module can be shown in Figure 6. The self-test module, in response to a node self-test command, drives the node's underlying drive and output circuits to output a self-test signal to the feedback transmission unit outside the node, and simultaneously latches the current time of the local clock to obtain the command issuance timestamp T_tx. This feedback transmission unit can be connected to both the trigger output interface and trigger input interface of the monitoring node, and can transmit the signal received from the self-monitoring node's trigger output interface back to the node's trigger input interface. The self-test module can use a high-speed analog-to-digital converter (e.g., a 16-bit, 80MSPS high-speed dual-channel ADC) to continuously sample the real analog waveform (i.e., the feedback signal) from the feedback transmission unit to obtain the corresponding feedback data. The self-test module can then use the hard-core operators of the digital signal processor (DSP) integrated in the FPGA to perform waveform fitting processing on the feedback data to obtain the fitted waveform corresponding to the feedback data. Subsequently, the waveform features of the feedback data and the waveform feature timestamp T_rx corresponding to the local clock can be extracted from the fitted waveform. Subsequently, the physical response delay (ΔT = T_rx - T_tx) can be obtained by subtracting the instruction issuance timestamp T_tx from the waveform feature timestamp T_rx. The node self-test result is then derived based on the physical response delay and waveform characteristics. For example, if the physical response delay exceeds a preset delay threshold, or if the waveform characteristics meet waveform distortion conditions, an anomaly can be identified in the node. Within 100 microseconds, a node self-test result indicating an anomaly is generated and sent to the service network. For example, this node self-test result indicating an anomaly may include hardware-level alarm flags.

[0092] For example, the underlying operating logic and signal flow of the remote maintenance module can be as shown in Figure 2, which may include a magnetic latching relay and a power management chip. The remote maintenance module can provide a pure hardware control line independent of the main control FPGA chip. The input terminal of the magnetic latching relay can receive independent out-of-band open collector (OC) control commands from an external controller, and the output contact of the magnetic latching relay can be connected in series to the enable terminal of the power management chip of the monitoring node. The magnetic latching relay can shut down the power management chip under the drive of a remote shutdown signal from the external controller, thereby cutting off the power tree of the main control FPGA and core peripheral chips; it can also turn on the power management chip under the drive of a remote restart signal from the external controller, thereby restoring power to the main control FPGA and core peripheral chips, thus restarting the main control FPGA and core peripheral chips.

[0093] The monitoring node of the nuclear fusion control device in this embodiment can achieve at least the following technical effects:

[0094] 1. Absolute Physical-Level High Availability Backup Against Strong Magnetic Fields and Deep Deadlocks: In response to the extreme radiation and strong magnetic field environments of nuclear fusion, the remote maintenance module in the monitoring node of this embodiment, through independent out-of-band OC links and low-level linkage with magnetically latched relays, overcomes the paralysis predicament of traditional software watchdogs when single-event upset (SEU) deadlocks occur in the FPGA. By utilizing the passive locking antimagnetic physical characteristics of the magnetically latched relays, a pure hardware-level cold start after a power outage can be achieved without manual intervention and unaffected by accidental triggering by strong magnetic fields. This mechanism transforms the downtime maintenance that typically takes several hours in traditional solutions into highly reliable online physical self-healing within seconds, fundamentally ensuring the long-term continuous operation capability of the monitoring node under harsh conditions.

[0095] 2. Overcoming "cascading accuracy degradation" under massive data congestion and achieving deterministic synchronization across the entire network: In this embodiment, the transparent transmission module of the monitoring node uses IDDR and ODDR primitives to perform bidirectional hardware labeling on time synchronization messages for both inbound and outbound transmissions, and introduces a deep FIFO queue dwell time compensation mechanism to eliminate the extremely severe network queuing jitter caused by bursts of transient diagnostic data. Even under extreme loads of daisy-chain networks with dozens or even hundreds of levels, the system can still control the dwell time calculation accuracy of PTP message forwarding to the single clock cycle level, thereby eliminating the nanosecond-level error accumulation caused by multi-level cascading of monitoring nodes. This significantly reduces the cost of complex star-shaped fiber optic cabling while providing the link end node with an absolute time reference that is completely consistent with the first node.

[0096] 3. Bridging the software latency gap to achieve "chip-level spatiotemporal rigid alignment" of cross-modal diagnostic data: In this embodiment, the synchronous monitoring module of the monitoring node can decouple the data acquisition triggering and timestamp allocation rights from the host computer operating system and sink them all to the FPGA underlying logic. Specifically, by completing the register-level concatenation of the ADC sampling value and the incoming timestamp based on the PTP global time reference within a single system clock cycle, the microsecond-level nondeterministic soft latency caused by interrupt scheduling in traditional software operating systems can be eliminated. This chip-level rigid binding ensures absolute and strict alignment of heterogeneous physical quantity data such as voltage, current, and magnetic probes on the time axis, providing highly confident data support for causal analysis and precise source tracing of transient events such as plasma rupture.

[0097] 4. Breaking through the blind zone of traditional logic levels, establishing a "spatiotemporal closed-loop" verification mechanism based on waveform characteristics: In this embodiment, the self-test module of the monitoring node, relying on the analog retrieval of high-speed ADC and the polynomial interpolation algorithm of the DSP inside the FPGA, can sink the node self-test from the coarse "digital logic level layer" to the extremely microscopic "analog physical waveform layer". By using the self-test module, the monitoring node can not only accurately capture the signal edge degradation and abnormal amplitude attenuation caused by long cable transmission, but also call the PTP homogeneous time base to calculate the sub-nanosecond level real physical response delay. This online "waveform check-up" and absolute time difference measurement capability can end the hidden danger of "blind control" in nuclear fusion control systems, and realize a major leap from passive troubleshooting to proactive predictive diagnosis in equipment operation and maintenance.

[0098] 5. Breaking away from isolated module assembly and forming a "strongly coupled system synergy effect" with shared underlying time base: In this embodiment, the monitoring node integrates the transparent transmission module, synchronous monitoring module, and self-test module into the main control FPGA chip, and deeply shares the same local clock built into the main control FPGA that provides a nanosecond-level PTP time base. This enables absolute unification of underlying computing power and time coordinate system, allowing the node to simultaneously possess comprehensive capabilities such as micro-waveform diagnosis, macro-network relay, data acquisition, and physical fallback for extreme crashes, all within extremely compact hardware resources and extremely low power consumption. This allows for reliable monitoring of the device in the extreme operating environment surrounding the nuclear fusion control device.

[0099] It should be understood that the structures shown in the accompanying drawings of the embodiments described above are merely block diagrams of some structures related to the present application and do not constitute a limitation on the monitoring nodes applied thereto. Specific monitoring nodes may include more or fewer components than shown in the figures, or combinations of certain components, or different component arrangements. It is understood that the various structural components in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations fall within the scope of protection of this application.

[0100] In one exemplary embodiment, a monitoring system for a nuclear fusion control device is provided, the internal structure of which is shown in Figure 7. This system may include multiple monitoring nodes, which can be connected in a daisy-chain manner. The implementation scheme of the monitoring nodes in the system is similar to that described in the embodiment of the monitoring nodes for the nuclear fusion control device, and will not be repeated here.

[0101] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this application. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A monitoring node for a nuclear fusion control device, characterized in that, The monitoring node includes an FPGA-based transparent transmission module, a synchronization monitoring module, a self-test module, and a local clock. The transparent transmission module is used to latch the current time of the local clock using a hardware timestamp unit deployed at the physical layer boundary when a time synchronization message is detected to be incoming or outgoing, so as to obtain the inbound and outbound timestamps of the time synchronization message. The dwell time increment of the time synchronization message is obtained based on the inbound timestamp and the outbound timestamp, and the dwell time increment is added to the correction field of the outbound time synchronization message. The synchronization monitoring module is used to trigger the monitoring sensors of the nuclear fusion control device to collect data when the current time of the local clock is consistent with the trigger time of the data acquisition task; when monitoring data from the monitoring sensors is detected, the current time of the local clock is latched to obtain the timestamp of the monitoring data. Based on the monitoring data and the input timestamp, the data acquisition results of the data acquisition task are obtained; The self-test module is used to respond to the node self-test command, latch the current time of the local clock to obtain the command issuance timestamp, and output a self-test signal to the feedback transmission unit outside the node; and perform waveform fitting processing on the received feedback data to obtain the waveform characteristics of the feedback data and the waveform characteristic timestamp of the feedback data corresponding to the local clock. The node self-test result is obtained based on the instruction issuance timestamp, the waveform feature timestamp, and the waveform feature; the feedback data is obtained by sampling and processing the feedback signal from the feedback transmission unit.

2. The node according to claim 1, characterized in that, The transparent transmission module is used to: latch the current time of the local clock on the first rising edge of the clock after the arrival of the frame start symbol of the time synchronization message, using the input double data rate primitive, to obtain the inbound timestamp of the time synchronization message. By using the double data rate primitive, the current time of the local clock is latched within the same clock tick when the start-of-frame symbol of the time synchronization message is detected, and the outgoing timestamp of the time synchronization message is obtained.

3. The node according to claim 2, characterized in that, The transparent transmission module is also used to: cache incoming time synchronization messages using a first-in-first-out queue.

4. The node according to claim 1, characterized in that, The synchronization monitoring module includes a hardware timing comparator, which is used to: compare the current time of the local clock with the trigger time of the data acquisition task in each clock cycle; and when the current time matches the trigger time, trigger the monitoring sensors of the nuclear fusion control device to acquire data.

5. The node according to claim 1, characterized in that, The synchronous monitoring module is further configured to: encapsulate the data acquisition results into a data packet and send the data packet to the business network.

6. The node according to claim 1, characterized in that, The self-test module is used to: perform waveform fitting processing on the received feedback data using a digital signal processor to obtain a fitted waveform corresponding to the feedback data; and obtain the waveform characteristics of the feedback data based on the waveform amplitude and edge slope of the fitted waveform.

7. The node according to claim 1, characterized in that, The self-test module is used to: perform waveform fitting processing on the received feedback data using a digital signal processor to obtain the fitted waveform corresponding to the feedback data; and align the moment when the fitted waveform crosses a feature threshold with the local clock to obtain the waveform feature timestamp of the feedback data.

8. The node according to claim 1, characterized in that, The self-test module is used to: obtain the physical response delay of the monitoring node based on the instruction issuance timestamp and the waveform feature timestamp; obtain the node self-test result indicating self-test abnormality when the physical response delay is greater than the delay threshold, or when the waveform feature indicates waveform distortion; and send the node self-test result to the service network.

9. The node according to any one of claims 1 to 8, characterized in that, The node also includes a magnetic latching relay and a power management chip; the power management chip is used to supply power to the FPGA; the magnetic latching relay is used to turn off the power management chip under the drive of a remote shutdown signal. The magnetic latching relay is also used to turn on the power management chip when driven by a remote restart signal.

10. A monitoring system for a nuclear fusion control device, characterized in that, The system includes a monitoring node as described in any one of claims 1 to 9; the number of monitoring nodes is multiple, and the monitoring nodes are connected in a daisy chain manner.

Images