Display panel

Abstract

The invention discloses a display panel. The display panel is provided with a display area, a non-display area and an opening area, and the non-display area is located between the display area and the opening area. The display panel comprises an array substrate, a light emitting device layer, a thin film packaging layer and an isolation dam. The array substrate comprises a substrate body and a driving circuit layer, and the driving circuit layer is located on one side of the substrate body. The light-emitting device layer is located on the side, away from the substrate, of the driving circuit layer and comprises a plurality of light-emitting layers and a common function layer. The plurality of light-emitting layers share the common functional layer. The thin film packaging layer is located on the side, away from the driving circuit layer, of the light-emitting device layer and comprises an organic packaging layer. The isolation dam is located on the substrate and arranged around the opening area in the non-display area, at least part of the organic packaging layer is limited in the area, close to the display area, of the isolation dam, and the isolation dam comprises two opposite side faces. One isolation dam is provided with one or more first isolation grooves, and one first isolation groove sinks inwards from one side face to the other side face to break at least part of the common function layer.

Description

Display panel Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have captured a large market share due to their advantages such as thinness, high brightness, and low power consumption. Currently, OLED display panels typically include one or more camera zones, each with an opening that penetrates the entire panel. To prevent moisture from traveling from the sidewalls of the opening along the organic layer of the light-emitting device to the display area, a partition structure is usually placed around the opening. This partition structure separates the organic layer of the light-emitting device from the cathode layer. However, too many partition structures can lead to an excessively large non-display area, hindering the achievement of narrow bezel designs for OLED display panels. Summary of the Invention

[0003] This application provides a display panel to at least partially solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel having a display area, a non-display area, and an opening area, the non-display area being located between the display area and the opening area. The display panel includes an array substrate, a light-emitting device layer, a thin-film encapsulation layer, and one or more isolation dams. The array substrate includes a substrate and a driving circuit layer, the driving circuit layer being located on one side of the substrate. The light-emitting device layer is located on the side of the driving circuit layer opposite to the substrate, and includes a plurality of light-emitting layers and a common functional layer. The plurality of light-emitting layers share the common functional layer. The thin-film encapsulation layer is located on the side of the light-emitting device layer opposite to the driving circuit layer, and includes an organic encapsulation layer. One or more isolation dams are located on the substrate and are disposed around the opening area in the non-display area, defining at least a portion of the organic encapsulation layer in an area of ​​the isolation dam near the display area, including two opposing sides; wherein one isolation dam is provided with one or more first partition grooves, one of the first partition grooves being recessed from one side towards the other side, and disconnecting at least a portion of the common functional layer.

[0005] In the display panel of this application embodiment, an isolation dam is located on the substrate, surrounding the opening area in the non-display area and confining at least a portion of the organic encapsulation layer within the area near the display area. Therefore, the isolation dam prevents material from the organic encapsulation layer from overflowing into the area near the opening area. Furthermore, the isolation dam is provided with one or more first partition grooves, each recessed from one side towards the other, disconnecting at least a portion of the shared functional layer. Thus, the isolation dam also serves to isolate the shared functional layer, reducing the risk of moisture seeping into the display area along the shared functional layer. Since the isolation dam also serves to isolate the shared functional layer, it can replace existing partition structures to reduce the risk of moisture seeping into the display area and causing black spots on the display panel. Simultaneously, it helps reduce the total number of partition structures and the total space occupied by the partition structures, enabling the display panel to achieve a narrow bezel design. Attached Figure Description

[0006] Figure 1 is a schematic planar structure diagram of the display panel provided in an exemplary embodiment of this application; Figure 2 is a partial cross-sectional view of the display area of ​​the display panel provided in an exemplary embodiment of this application; Figure 3 is a partial cross-sectional view of the non-display area of ​​the display panel provided in an exemplary embodiment of this application; Figure 4 is another partial cross-sectional view of the non-display area of ​​the display panel provided in an exemplary embodiment of this application; Figure 5 is yet another partial cross-sectional view of the non-display area of ​​the display panel provided in an exemplary embodiment of this application; Figure 6 is a partial cross-sectional view of the display area and non-display area of ​​the display panel provided in an exemplary embodiment of this application; Figure 7 is another partial cross-sectional view of the display area and non-display area of ​​the display panel provided in an exemplary embodiment of this application; Figures 8-9 are schematic process diagrams of a method for manufacturing the display panel shown in Figure 3 provided in an exemplary embodiment of this application; Figures 10-11 are schematic process diagrams of a method for manufacturing the display panel shown in Figure 5 provided in an exemplary embodiment of this application.

[0007] Explanation of reference numerals in the attached figures: 100, display panel; AA, display area; NAA, non-display area; HA, aperture area; 1, array substrate; 11, substrate; 111, first flexible layer; 112, second flexible layer; 113, first barrier layer; 114, second barrier layer; 12, driving circuit layer; T, thin film transistor; T1, first thin film transistor; T2, second thin film transistor; 130, metal layer; 131, first metal layer; 132, second metal layer; 133, third metal layer; 134, fourth metal layer; 135, fifth metal layer; 136, sixth metal layer; 137, seventh metal layer; 140, semiconductor layer; 141, first semiconductor layer; 142, second semiconductor layer; 15, inorganic insulating layer; 151, buffer layer; 152, first inorganic insulating layer; 153, second inorganic insulating layer; 154, third inorganic insulating layer; 155, fourth inorganic insulating layer; 156, third... 5. Inorganic insulating layer; 16. Planarization layer; 161. First organic insulating layer; 162. Second organic insulating layer; 163. Third organic insulating layer; 164. Side surface; 2. Pixel definition layer; 3. Light-emitting device layer; 31. Anode layer; 32. Light-emitting layer; 33. Common functional layer; 4. Thin film encapsulation layer; 5. Opening; 61. Color filter layer; 62. Black matrix layer; 7. Isolation dam; 71. Side surface; 72. Top surface; 73. Organic part; 7 31. First organic part; 732. Second organic part; 733. Light-transmitting part; 734. Light-shielding part; 81. First partition groove; 811. Insulating groove wall; 82. Second partition groove; 83. Third partition groove; 84. First groove; 85. Second groove; 9. Partition structure; 91. First part; 92. Second part; S. Mask layer; S1. Photoresist; S2. Hard mask; O. Opening; O1. First opening; O2. Second opening. Detailed Implementation

[0008] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0009] Please refer to Figure 1. This application embodiment provides a display panel 100. The display panel 100 has a display area AA, a non-display area NAA, and an opening area HA. ​​The non-display area NAA is located between the display area AA and the opening area HA.

[0010] Please refer to Figure 2. The display panel 100 includes an array substrate 1, a pixel definition layer 2, a light-emitting device layer 3, and a thin film encapsulation layer 4.

[0011] The display panel 100 also has an opening 5, which is located in the opening area HA and penetrates the array substrate 1, the pixel definition layer 2, the light-emitting device layer 3, and the thin film encapsulation layer 4. In this way, optical functional components such as cameras can be placed in or below the opening 5.

[0012] The array substrate 1 includes a substrate 11 and a driving circuit layer 12, with the driving circuit layer 12 located on one side of the substrate 11.

[0013] The substrate 11 may include one or more flexible layers, making the substrate 11 bendable. In some embodiments, referring to FIG2, the substrate 11 may include a first flexible layer 111, a second flexible layer 112, and a first barrier layer 113. The first barrier layer 113 is located between the first flexible layer 111 and the second flexible layer 112. In some embodiments, the substrate 11 may further include a second barrier layer 114, which is located on the side of the second flexible layer 112 near the driving circuit layer 12. The first flexible layer 111 and the second flexible layer 112 may include flexible materials such as polyimide, and the first barrier layer 113 and the second barrier layer 114 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0014] The driving circuit layer 12 may include multiple pixel driving circuits, and each pixel driving circuit may include one or more thin-film transistors (TFTs) T. The multiple TFTs T may be the same or different. In some embodiments, the multiple TFTs T may include a first TFT T1 and a second TFT T2, where the first TFT T1 may be a low-temperature polysilicon transistor (LTPS) and the second TFT T2 may be a metal-oxide-semiconductor (MODS) transistor. It is understood that the multiple TFTs T may all be LTPS transistors, or all may be MODS transistors.

[0015] From the perspective of film layers, the driving circuit layer 12 includes an inorganic insulating layer 15 and one or more metal layers 130. The inorganic insulating layer 15 is located in the display area AA and the non-display area NAA. The one or more metal layers 130 may be located inside the inorganic insulating layer 15, between the inorganic insulating layer 15 and the substrate 11, and on the side of the inorganic insulating layer 15 facing away from the substrate 11 at least one of these locations. The one or more metal layers 130 may include the gate electrode of the thin-film transistor T and the source / drain electrodes of the thin-film transistor T.

[0016] In some embodiments, referring to FIG2, the multilayer metal layer 130 may include a first metal layer 131 and a second metal layer 132. The first metal layer 131 may include the gate of the thin-film transistor T, and the second metal layer 132 may include the source and drain electrodes of the thin-film transistor T.

[0017] In some embodiments, referring to FIG2, the multilayer metal layer 130 may further include a third metal layer 133, which is located between the first metal layer 131 and the second metal layer 132, and may include the electrode plates of a capacitor.

[0018] In some embodiments, referring to FIG2, the multilayer metal layer 130 may further include a fourth metal layer 134. The fourth metal layer 134 is located on the side of the second metal layer 132 facing away from the substrate 11. The fourth metal layer 134 may include a first connection structure connected to the source / drain electrodes. In some embodiments, referring to FIG2, one or more metal layers 130 may further include a fifth metal layer 135, the fifth metal layer 135 is located on the side of the fourth metal layer 134 facing away from the substrate 11 and may include a second connection structure connected to the first connection structure.

[0019] In some embodiments, referring to FIG2, the multilayer metal layer 130 may further include a sixth metal layer 136. The sixth metal layer 136 is located between the second metal layer 132 and the third metal layer 133, and includes the gate of the thin-film transistor T.

[0020] In some embodiments, referring to FIG2, the multilayer metal layer 130 may further include a seventh metal layer 137. The seventh metal layer 137 is located between the first metal layer 131 and the substrate 11, and includes a light-shielding block that overlaps with the thin-film transistor T.

[0021] In some embodiments, referring to FIG2, when the pixel driving circuit includes a first thin-film transistor T1 and a second thin-film transistor T2, the first metal layer 131 may include the first gate of the first thin-film transistor T1, the second metal layer 132 may include the first source / drain electrode of the first thin-film transistor T1 and the second source / drain electrode of the second thin-film transistor T2, the third metal layer 133 may include the electrode plate of a capacitor and the second gate of the second thin-film transistor T2, the fourth metal layer 134 may include a first connection structure, the fifth metal layer 135 may include a second connection structure, and the sixth metal layer 136 includes the third gate of the second thin-film transistor T2. The electrode plate overlaps with the first gate. The second gate overlaps with the third gate.

[0022] The driving circuit layer 12 may further include one or more semiconductor layers 140, each semiconductor layer 140 including an active layer of a thin-film transistor T. In some embodiments, the multilayer semiconductor layer 140 includes a first semiconductor layer 141 and a second semiconductor layer 142. The first semiconductor layer 141 is located between the first metal layer 131 and the substrate 11, and includes a first active layer of the first thin-film transistor T1, which overlaps with a first gate. The second semiconductor layer 142 is located between the third metal layer 133 and the sixth metal layer 136, and includes a second active layer, which overlaps with a second gate and a third gate.

[0023] The inorganic insulating layer 15 may include one or more stacked inorganic dielectric layers. One inorganic dielectric layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, referring to FIG2, the inorganic insulating layer 15 may include a buffer layer 151, a first inorganic insulating layer 152, a second inorganic insulating layer 153, a third inorganic insulating layer 154, a fourth inorganic insulating layer 155, and a fifth inorganic insulating layer 156. The buffer layer 151 is located between the seventh metal layer 137 and the first semiconductor layer 141. The first inorganic insulating layer 152 is located between the first semiconductor layer 141 and the first metal layer 131. The second inorganic insulating layer 153 is located between the first metal layer 131 and the third metal layer 133. The third inorganic insulating layer 154 is located between the third metal layer 133 and the first metal layer 131. The fourth inorganic insulating layer 155 is located between the second semiconductor layer 142 and the sixth metal layer 136. The fifth inorganic insulating layer 156 is located between the sixth metal layer 136 and the second metal layer 132.

[0024] In some embodiments, the driving circuit layer 12 further includes a planarization layer 16, which is located at least in the display area AA and on the side of the inorganic insulating layer 15 facing away from the substrate 11, to planarize the substrate 11 on which the driving circuit is disposed. In some embodiments, the planarization layer 16 may include one or more organic insulating layers. The thickness of each organic insulating layer may be 1.5 micrometers to 2.5 micrometers. Each organic insulating layer may include at least one of polyimide, polyacrylate, epoxy resin, and silicone.

[0025] In one example, the planarization layer 16 may include a first organic insulating layer 161, a second organic insulating layer 162, and a third organic insulating layer 163. The first organic insulating layer 161 is located on the side of the second metal layer 132 facing away from the substrate 11. The second organic insulating layer 162 covers the fourth metal layer 134 and the first organic insulating layer 161. The third organic insulating layer 163 covers the fifth metal layer 135 and the second organic insulating layer 162.

[0026] The pixel definition layer 2 is located on the side of the driving circuit layer 12 facing away from the substrate 11, and is at least located in the display area AA. In some embodiments, the pixel definition layer 2 is located on the side of the planarization layer 16 facing away from the substrate 11. The pixel definition layer 2 may include a light-transmitting pixel definition layer. In some embodiments, the pixel definition layer 2 may also include a light-shielding pixel definition layer, which is located between the light-transmitting pixel definition layer and the substrate 11. The pixel definition layer 2 is also provided with a pixel opening that extends through the entire pixel definition layer 2 along its thickness direction. The thickness of the light-transmitting pixel definition layer and the light-shielding pixel definition layer may be 0.5 micrometers to 1.5 micrometers. The pixel definition layer 2 also includes a dam and a support portion, with the dam surrounding the pixel opening and the support portion located on the dam.

[0027] The light-emitting device layer 3 is located on the side of the driving circuit layer 12 away from the substrate 11, and includes an anode layer 31, multiple light-emitting layers 32, and a shared functional layer 33, with the multiple light-emitting layers 32 sharing the shared functional layer 33. The anode layer 31 is located between the pixel definition layer 2 and the planarization layer 16, and includes multiple anodes spaced apart. An anode is exposed in a pixel opening. Each light-emitting layer 32 is located on an anode within a pixel opening. The shared functional layer 33 includes multiple shared organic layers and a cathode layer. The cathode layer is located on the side of the light-emitting layers 32 away from the driving circuit layer 12, and is located in the display area AA and the non-display area NAA. The multiple shared organic layers are located between the cathode layer and the light-emitting layers 32, and between the anode and the light-emitting layers 32.

[0028] The thin-film encapsulation layer 4 is located on the side of the light-emitting device layer 3 away from the driving circuit layer 12, and includes an organic encapsulation layer, a first inorganic encapsulation layer, and a second inorganic encapsulation layer. The organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first inorganic encapsulation layer is disposed close to the light-emitting device layer 3.

[0029] In some embodiments, referring to FIG2, the display panel 100 further includes a color filter layer 61 and a black matrix layer 62. The black matrix layer 62 is located on the thin film encapsulation layer 4 away from the light-emitting device layer 3 and has light-transmitting openings. The color filter layer 61 includes color resist units located in the light-transmitting openings.

[0030] In some embodiments, referring to FIG3, the display panel 100 further includes one or more isolation dams 7 located on the substrate 11 and disposed around the opening area HA in the non-display area NAA, defining at least a portion of the organic encapsulation layer in the area of ​​the isolation dam 7 near the display area AA, including two opposing sides 71. One isolation dam 7 is provided with one or more first isolation grooves 81, each recessed from one side 71 toward the other side 71, and disconnecting at least a portion of the shared functional layer 33. Thus, the isolation dam 7 both prevents material from the organic encapsulation layer from overflowing into the area of ​​the isolation dam 7 near the opening area HA and isolates the shared functional layer 33, reducing the risk of moisture penetrating along the shared functional layer 33 into the display area AA. Since the isolation dam 7 is used to separate the shared functional layer 33, the isolation dam 7 can replace the existing partition structure 9 to reduce the risk of water vapor and other substances penetrating into the display area AA and causing black spots to appear when the display panel 100 is displayed. At the same time, it helps to reduce the total number of partition structures 9 and reduce the total layout space occupied by partition structures 9, so that the display panel 100 can achieve a narrow bezel design.

[0031] In some embodiments, referring to Figure 3, the isolation dam 7 may further include a top surface 72, with two side surfaces 71 connected to opposite sides of the top surface 72. The angle between one side surface 71 and the top surface 72 may be greater than 90 degrees.

[0032] In some embodiments, a first partition groove 81 may be provided around the opening area HA, such that the first partition groove 81 can divide the common functional layer 33 into at least two spaced portions.

[0033] In some embodiments, the two first partition grooves 81 of an isolation dam 7 are recessed towards each other from two sides 71. In this way, the isolation dam 7 is provided with two oppositely arranged first partition grooves 81, and the two first partition grooves 81 are recessed towards each other, so as to improve the overall isolation effect of the isolation dam 7 on the shared functional layer 33.

[0034] In some embodiments, an isolation dam 7 may also be provided with a first partition groove 81. The first partition groove 81 may be recessed from the side 71 of the isolation dam 7 near the opening area HA in the direction away from the opening area HA. ​​Alternatively, the first partition groove 81 may be recessed from the side 71 of the isolation dam 7 near the display area AA in the direction away from the display area AA.

[0035] In some embodiments, referring to FIG3, the first partition groove 81 has an insulating groove wall 811 and disconnects the cathode layer in the non-display area NAA. Since the insulating groove wall 811 is insulating, the disconnected cathode layer will not be electrically connected through the insulating groove wall 811, enabling the first partition groove 81 to achieve electrical isolation of the cathode layer. In some embodiments, the first partition groove 81 also disconnects the shared organic layer in the non-display area NAA, reducing the risk of moisture and other contaminants penetrating along the shared organic layer into the display area AA.

[0036] In some embodiments, the insulating groove wall 811 includes a curved surface. Since the first partition groove 81 is typically formed by a dry side-cutting process, the dry side-cutting process typically results in the insulating groove wall 811 including a curved surface.

[0037] In some embodiments, the first partition groove 81 is disposed near the inorganic insulating layer 15.

[0038] In some embodiments, the depth D1 of the first partition groove 81 is 0.05 micrometers to 0.8 micrometers, and the direction of the depth D1 of the first partition groove 81 is from one side 71 to the other side 71. This controls the depth of the first partition groove 81 within a suitable range, ensuring the isolation effect of the first partition groove 81 on the shared functional layer 33, while also ensuring the coverage capability of the first inorganic encapsulation layer and the second inorganic encapsulation layer on the first partition groove 81 and its surrounding area, thereby improving the encapsulation capability of the thin film encapsulation layer 4. Optionally, the depth D1 of the first partition groove 81 is 0.1 micrometers to 0.5 micrometers.

[0039] In some embodiments, the two first partition grooves 81 of an isolation dam 7 may have the same or substantially the same depth, so that the two first partition grooves 81 of an isolation dam 7 can be formed under the same process conditions, simplifying the forming process of an isolation dam 7. In some embodiments, the two first partition grooves 81 of an isolation dam 7 may also have different depths; for example, the depth of the first partition groove 81 near the opening area HA may be different from the depth of the first partition groove 81 near the display area AA.

[0040] It should be noted that the depth of the first partition groove 81 can be the vertical distance between the opening edge of the first partition groove 81 and the bottom of the first partition groove 81. The opening edge of the first partition groove 81 can be the upper edge of the first partition groove 81 away from the substrate 11, such as at point A in Figure 3. The bottom of the first partition groove 81 can be, for example, at point B in Figure 3.

[0041] In some embodiments, the isolation dam 7 includes an organic portion 73 located on the inorganic insulating layer 15, and a first isolation groove 81 located within the organic portion 73. Thus, by removing a portion of the organic portion 73 to form the first isolation groove 81, electrical isolation of the cathode layer can be achieved when the first isolation groove 81 disconnects the cathode layer.

[0042] In some embodiments, the organic portion 73 is located in at least one of the planarization layer 16 and the pixel definition layer 2, so as to increase the height of the isolation dam 7 by utilizing the planarization layer 16 and the pixel definition layer 2, ensuring the ability of the isolation dam 7 to prevent material overflow of the organic encapsulation layer. In one example, the organic portion 73 may include a first organic portion 731 and a second organic portion 732, the second organic portion 732 covering the first organic portion 731, the first organic portion 731 being located in the planarization layer 16, and the second organic portion 732 being located in the pixel definition layer 2, that is, the planarization layer 16 and the pixel definition layer 2 retaining the non-display area portion to form the organic portion 73.

[0043] In some embodiments, please refer to Figures 3 and 4. When the pixel definition layer 2 includes a light-transmitting pixel definition layer, the second organic portion 732 may include a light-transmitting portion 733, which is located in the light-transmitting pixel definition layer.

[0044] In some embodiments, referring to FIG5, when the pixel definition layer 2 includes a light-transmitting pixel definition layer and a light-shielding pixel definition layer, the second organic portion 732 may include a light-transmitting portion 733 and a light-shielding portion 734. The light-transmitting portion 733 is located in the light-transmitting pixel definition layer, and the light-shielding portion 734 may be located in the light-shielding pixel definition layer.

[0045] In some embodiments, the isolation dam 7 further includes a metal portion, which is disposed in at least one of the interior of the organic portion 73, the interior of the inorganic insulating layer 15, and between the organic portion 73 and the inorganic insulating layer 15. This increases the overall height of the isolation dam 7 by utilizing the metal portion, ensuring the isolation dam 7's ability to prevent material leakage from the organic encapsulation layer. In some embodiments, the metal portion may be located in at least one of the second metal layer 132, the fourth metal layer 134, and the fifth metal layer 135.

[0046] In some embodiments, referring to FIG3, the inorganic insulating layer 15 is provided with one or more second partition grooves 82. The second partition groove 82 is located in the non-display area (NAA) and is recessed from the surface of the inorganic insulating layer 15 away from the substrate 11 toward the substrate 11. One second partition groove 82 disconnects at least part of the shared functional layer 33, particularly disconnecting the shared organic layer. The second partition groove 82, in conjunction with the first partition groove 81, provides a better isolation effect on the shared functional layer 33.

[0047] It should be noted that the first partition groove 81 can achieve electrical isolation of the cathode layer, and the second partition groove 82 can achieve physical isolation of the shared organic layer. The combination of the two can improve the overall isolation effect of the shared functional layer 33, and reduce the problem of water vapor penetrating into the display area through the shared functional layer 33, which may lead to encapsulation failure and display abnormality.

[0048] In some embodiments, the second partition groove 82 may be disposed around at least one of the opening area HA and the isolation dam 7, such that the second partition groove 82 can divide the common functional layer 33 into two portions respectively adjacent to the opening area HA and the display area AA. In one example, two second partition grooves 82 are located on opposite sides of the isolation dam 7, one second partition groove 82 is disposed around the opening area HA and the other second partition groove 82 is disposed around the isolation dam 7.

[0049] In some embodiments, at least one second partition groove 82 is adjacent to a first partition groove 81. The adjacent second partition groove 82 and the first partition groove 81 can continuously separate the shared functional layer 33.

[0050] In some embodiments, the second partition groove 82 is a groove that is narrower at the top and wider at the bottom. For example, the shape of the longitudinal section of the second partition groove 82 may include a trapezoid, and the longitudinal section of the second partition groove 82 is perpendicular to the substrate 11.

[0051] In some embodiments, the inorganic insulating layer 15 through which the second partition trench 82 penetrates may include a multilayer inorganic film, wherein the etching rate of the multilayer inorganic film increases under the same etching conditions in the direction close to the substrate 11. For example, the multilayer inorganic film includes an upper inorganic film and a lower inorganic film, the upper inorganic film being located on the side of the lower inorganic film opposite to the substrate 11, the upper inorganic film comprising silicon nitride, and the lower inorganic film comprising silicon oxide.

[0052] In some embodiments, referring to Figures 4 and 5, the display panel 100 is further provided with one or more first grooves 84. The first grooves 84 are located in the non-display area NAA and in the organic portion 73 or the inorganic insulating layer 15. The first grooves 84 are adjacent to the first partition grooves 81 and recessed toward the substrate 11. The common functional layer 33 is continuously located in the first grooves 84.

[0053] In some embodiments, the longitudinal section of the first groove 84 may include an inverted trapezoidal shape, i.e., the second partition groove 82 is a groove that is narrower at the bottom and wider at the top. In some embodiments, the first groove 84 may be arranged around the isolation dam 7.

[0054] In some embodiments, the inorganic insulating layer 15 through which the first groove 84 penetrates may include a multilayer inorganic film, wherein the etching rate of the multilayer inorganic film decreases under the same etching conditions in the direction close to the substrate 11. For example, the multilayer inorganic film includes an upper inorganic film and a lower inorganic film, the upper inorganic film being located on the side of the lower inorganic film opposite to the substrate 11, the upper inorganic film comprising silicon oxide, and the lower inorganic film comprising silicon nitride.

[0055] In some embodiments, adjacent second partition trenches 82 and first partition trenches 81, or adjacent first grooves 84 and first partition trenches 81, can be formed in the same etching process. For example, when the first partition trench 81 is located in the organic portion 73, the etching rate of the organic portion 73 can be greater than the etching rate of the inorganic insulating layer 15 by dry etching. That is, based on the difference in etching rates, a first partition trench 81 extending horizontally (parallel to the substrate 11) and a second partition trench 82 extending longitudinally (perpendicular to the substrate 11) are formed.

[0056] In some embodiments, referring to FIG6, the planarization layer 16 is provided with one or more third partition grooves 83. One third partition groove 83 is adjacent to the boundary between the non-display area NAA and the display area AA. The third partition groove 83 is recessed from the side surface 164 of the planarization layer 16 toward the direction away from the opening area HA and disconnects at least part of the common functional layer 33. In this way, at the boundary between the display area AA and the non-display area NAA, the third partition groove 83 is added by utilizing the side surface 164 of the planarization layer 16 to isolate the common functional layer 33, reduce the risk of moisture and other substances penetrating into the display area at the edge of the display area, and allow the third partition groove 83 to replace the existing partition structure, reduce the overall number of partition structures, reduce the size of the non-display area NAA of the display panel 100, and facilitate the implementation of the bezel of the display panel 100. In some embodiments, the third partition groove 83 may also be provided around the opening area HA.

[0057] In some embodiments, referring to FIG6, at least one second partition groove 82 is adjacent to a third partition groove 83. In this way, the adjacent second partition groove 82 and third partition groove 83 can continuously separate the shared functional layer 33.

[0058] In some embodiments, the third partition groove 83 can be formed in the same etching process as the first partition groove 81 and the second partition groove 82, simplifying the manufacturing process of the display panel 100.

[0059] In some embodiments, the wall of the third partition groove 83 may include a curved surface.

[0060] In some embodiments, referring to FIG7, the display panel 100 is further provided with a second groove 85, which is located in the inorganic insulating layer 15 and adjacent to the third partition groove 83. The second groove 85 is recessed toward the substrate 11, and the common functional layer 33 is continuously located in the second groove 85. In some embodiments, the second groove 85 is located in the inorganic insulating layer 15, and the longitudinal section of the second groove 85 includes a trapezoidal shape. In some embodiments, the second groove 85 may be provided around the isolation dam 7.

[0061] In some embodiments, referring to Figures 3 to 7, the display panel 100 may further include one or more partition structures 9. The one or more partition structures 9 are located on the substrate 11 and in the non-display area NAA, and are disposed around the opening area HA. ​​The one or more partition structures 9 are spaced apart from the isolation dam 7 and disconnect at least a portion of the shared functional layer 33 in the non-display area NAA. The height of the partition structure 9 is lower than the height of the isolation dam 7.

[0062] In some embodiments, at least one partition structure 9 may be located on the side of the isolation dam 7 near the opening area HA and on the inorganic insulating layer 15.

[0063] In some embodiments, the partition structure 9 may include a first portion 91 and a second portion 92, the first portion 91 being located between the second portion 92 and the substrate 11, and the first portion 91 being recessed relative to the second portion 92, such that the partition structure 9 has a structure that is wider at the top and narrower at the bottom. In some embodiments, the first portion 91 may include at least one of a metal layer 130 and an organic layer, and the second portion 92 may include at least one of a metal layer 130 and an organic layer. In some embodiments, the partition structure 9 may further include a third portion, the third portion being located between the first portion 91 and the substrate 11. In one example, the first portion 91, the second portion 92, and the third portion 93 may all include a metal layer 130.

[0064] The following describes the formation process of the first partition groove 81 and the second partition groove 82 shown in Figure 3. The formation process of the first partition groove 81 and the second partition groove 82 includes the following steps: Step S101, as shown in Figure 8, an organic portion 73 of the isolation dam 7 and a mask layer S are formed on the inorganic insulating layer 15 of the non-display area NAA. The mask layer S covers the organic portion 73 and the inorganic insulating layer 15. The mask layer S is provided with an opening O, which exposes part of the inorganic insulating layer 15 and part of the organic portion 73 at the junction of the inorganic insulating layer 15 and the organic portion 73; Step S102, as shown in Figure 9, part of the organic portion 73 and part of the inorganic insulating layer 15 are removed through the opening O to form the first partition groove 81 and the second partition groove 82. The first partition groove 81 is located in the organic portion 73, and the second partition groove 82 is located in the inorganic insulating layer 15; then a common functional layer 33 is formed, which is disconnected at the first partition groove 81 and the second partition groove 82.

[0065] In some embodiments, in step S101, the mask layer S may include photoresist S1, which may have a first opening O1. The first opening O1 can be obtained by exposing and developing the photoresist S1. In other embodiments, the mask layer S may further include a hard mask S2, which is located between the photoresist S1, the organic portion 73, and the inorganic insulating layer 15 and has a second opening O2. The second opening O2 communicates with the first opening O1, and the two together constitute opening O. The hard mask S2 may include, but is not limited to, indium zinc oxide.

[0066] In step S101, for the structure shown in FIG8, the organic portion 73 includes a first organic portion 731 and a second organic portion 732. The second organic portion 732 covers the first organic portion 731. The first organic portion 731 is located in the planarization layer 16, and the second organic portion 732 is located in the light-transmitting pixel definition layer.

[0067] In step S102, the etching rate of organic matter can be greater than that of inorganic matter during the dry etching process, so that part of the organic part 73 is removed to form a first partition groove 81 extending laterally, and part of the inorganic insulating layer 15 is removed to form a second partition groove 82 extending longitudinally.

[0068] For the first partition groove 81 and the second partition groove 82 shown in Figure 5, their formation process is basically the same as steps S101 and S102 described above. The difference is that, as shown in Figures 10 and 11, the second organic part 732 includes a light-transmitting part 733 and a light-shielding part 734. The light-transmitting part 733 and the light-shielding part 734 are partially exposed by the opening O. The light-transmitting part 733 is partially removed by the opening O to form a laterally extending first partition groove 81, and the light-shielding part 734 is partially removed by the opening O to form a longitudinally extending second groove 85.

[0069] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0070] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0071] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0072] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area, a non-display area, and an opening area, the non-display area being located between the display area and the opening area. The display panel includes: an array substrate, comprising a substrate and a driving circuit layer, the driving circuit layer being located on one side of the substrate; a light-emitting device layer, located on the side of the driving circuit layer opposite to the substrate, and including multiple light-emitting layers and a common functional layer, the multiple light-emitting layers sharing the common functional layer; a thin-film encapsulation layer, located on the side of the light-emitting device layer opposite to the driving circuit layer, and including an organic encapsulation layer; one or more isolation dams, located on the substrate and disposed around the opening area in the non-display area, defining at least a portion of the organic encapsulation layer in an area of ​​the isolation dam near the display area, including two opposing sides; wherein one of the isolation dams is provided with one or more first partition grooves, one of the first partition grooves being recessed from one side toward the other side, and disconnecting at least a portion of the common functional layer.

2. The display panel according to claim 1, characterized in that, The shared functional layer includes a cathode layer located in the display area and the non-display area, and the first partition groove has an insulated groove wall and disconnects the cathode layer in the non-display area.

3. The display panel according to claim 1, characterized in that, The depth of the first partition groove is 0.05 micrometers to 0.8 micrometers, and the direction of the depth of the first partition groove is the direction from one side to the other side.

4. The display panel according to claim 1, characterized in that, The two first partition slots of one of the isolation dams are recessed into each other from the two sides.

5. The display panel according to claim 1, characterized in that, The driving circuit layer includes an inorganic insulating layer located in the display area and the non-display area. The isolation dam includes an organic portion located on the inorganic insulating layer, and the first isolation groove is located in the organic portion.

6. The display panel according to claim 5, characterized in that, The driving circuit layer further includes a planarization layer and a pixel definition layer, the planarization layer and the pixel definition layer being located at least in the display area, the planarization layer being located on the side of the inorganic insulating layer facing away from the substrate, and the pixel definition layer being located on the side of the planarization layer facing away from the substrate; the organic portion is located in at least one of the planarization layer and the pixel definition layer.

7. The display panel according to claim 5, characterized in that, The isolation dam also includes a metal portion, and the metal portion is disposed in at least one of the interior of the organic portion, the interior of the inorganic insulating layer, and between the organic portion and the inorganic insulating layer.

8. The display panel according to claim 5, characterized in that, The display panel is further provided with one or more first grooves, the first grooves being located in the non-display area and in the organic portion or the inorganic insulating layer, the first grooves being adjacent to the first partition grooves and recessed toward the substrate, and the shared functional layer being continuously located in the first grooves.

9. The display panel according to claim 5, characterized in that, The inorganic insulating layer is provided with one or more second partition grooves, the second partition grooves being located in the non-display area and recessed from the surface of the inorganic insulating layer away from the substrate toward the substrate, one of the second partition grooves disconnecting at least a portion of the common functional layer.

10. The display panel according to claim 9, characterized in that, At least one of the second partition slots is adjacent to one of the first partition slots.

11. The display panel according to claim 9, characterized in that, The driving circuit layer further includes a planarization layer, which is located at least in the display area and on the side of the inorganic insulating layer away from the substrate. The planarization layer is provided with one or more third partition grooves. One of the third partition grooves is adjacent to the boundary between the non-display area and the display area. Another third partition groove is recessed from the side of the planarization layer toward the direction away from the opening area and disconnects at least part of the common functional layer.

12. The display panel according to claim 11, characterized in that, At least one of the second partition slots is adjacent to one of the third partition slots.

Images