Level shift circuit

Abstract

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

Description

Technical Field

[0001] This invention relates to a level shift circuit that converts the voltage of a signal to the desired level when transmitting signals between circuits supplied with different power supply voltages. Background Technology

[0002] A level shifting circuit is provided, for example, in the interface section where a signal is sent from a circuit inside the LSI operating at a relatively low voltage to a circuit outside the LSI operating at a relatively high voltage. This level shifting circuit is used when converting the voltage of the signal.

[0003] In recent years, as transistors have become increasingly miniaturized, the voltage stress (withstand voltage) that transistors can tolerate has also decreased. Against this backdrop, prior art literature discloses level shifting circuits that perform voltage conversion within a specified withstand voltage range.

[0004] The level shifting circuit in Patent Document 1 is configured to boost both the high-level and low-level voltages. In this way, by reducing the voltage between the low and high levels, the voltage applied between the transistor terminals (e.g., between the gate and source, and between the source and drain) is reduced, thereby alleviating the voltage stress on the transistor.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: US Patent No. 7,151,391 Summary of the Invention

[0008] -The technical problem the invention aims to solve-

[0009] However, in adopting patent document 1 Figure 1 In the case of this structure, the following technical problem arises: the operation of the level shifting circuit cannot keep up with the lower voltage required for low power consumption and / or the higher speed required for high functionality.

[0010] The purpose of this disclosure is to solve the aforementioned technical problems.

[0011] - Technical solutions used to solve technical problems -

[0012] The level shifting circuit of one aspect of this disclosure includes: an input node receiving an input signal converted between a first power supply and a second power supply, wherein the potential of the second power supply is lower than the potential of the first power supply; a first N-type transistor disposed between the input node and the first node, the gate of the first N-type transistor being connected to the first power supply; a first P-type transistor disposed between the first node and an output node, the gate of the first P-type transistor being connected to the first power supply; a second P-type transistor disposed between the output node and the first power supply, the gate of the second P-type transistor being connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; and a second N-type transistor disposed at the inverting input node. Between the second node and the third node, the gate of the second N-type transistor is connected to the first power supply; a third P-type transistor is disposed between the second node and the third node, and its gate is connected to the first power supply; a fourth P-type transistor is disposed between the third node and the first power supply, and its gate is connected to the second node; and a pull-up circuit is disposed between the first node and the second node, the pull-up circuit comprising: a first pull-up circuit, which pulls the second node to the third power supply when the first node transitions from a high level to a low level, the potential of the third power supply being higher than that of the first power supply; and a second pull-up circuit, which pulls the first node to the third power supply when the second node transitions from a high level to a low level.

[0013] In the level shifting circuit of this aspect, the first pull-up circuit operates by pulling the second node up to the third power supply when the first node transitions from a high level to a low level, thus accelerating the voltage drop at the output node. Therefore, the output signal output to the output node is not delayed. Similarly, the second pull-up circuit operates by pulling the first node up to the third power supply when the second node transitions from a high level to a low level, thus accelerating the voltage rise at the output node. Therefore, the output signal output to the output node is also not delayed. Therefore, compared to the case without pull-up circuits, a higher circuit speed can be achieved.

[0014] Furthermore, the level shifting circuit of this aspect consists of two power supplies, a first power supply and a third power supply, and does not use a bias voltage (equivalent to VBIAS in Patent Document 1). In other words, there is no need for a circuit to generate a bias voltage.

[0015] -The effects of the invention-

[0016] In this disclosure, the operating voltage is reduced and / or the circuit operation is accelerated in the level shifting circuit. Attached Figure Description

[0017] Figure 1 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the first embodiment.

[0018] Figure 2 This is a circuit diagram illustrating one example of the structure of a pull-up circuit.

[0019] Figure 3 This is a diagram showing one example of the voltage waveforms at various nodes of a level shifting circuit.

[0020] Figure 4 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the second embodiment.

[0021] Figure 5 This is a circuit diagram illustrating one example of the structure of the level shifting circuit according to the third embodiment.

[0022] Figure 6 This is a circuit diagram showing a modified example of the level shifting circuit according to the first embodiment.

[0023] Figure 7 This is a circuit diagram showing a modified example of a pull-up circuit. Detailed Implementation

[0024] The embodiments will now be described. It should be noted that the specific numerical values ​​shown in the following embodiments are merely examples for easy understanding of the invention and are not intended to limit the scope of the invention. Furthermore, in the following description, sometimes the same symbols or names are used to describe the nodes or terminals of the circuit and the signals passing through those nodes or terminals, and sometimes the same symbols are used to describe the power supply name and the power supply voltage.

[0025] <First Implementation>

[0026] Level shifting circuit 1 is a circuit consisting of a first power supply VDD and a third power supply VDDIO. It boosts the high-level voltage from VDD to VDDIO and boosts the low-level voltage from VSS to VDD. The third power supply VDDIO has a higher voltage than the first power supply VDD. It should be noted that in the following description, low level may sometimes be abbreviated as 'L' and high level as 'H'.

[0027] The level shifting circuit 1 receives the input signal IN, which is converted between the first power supply VDD and ground VSS (equivalent to the second power supply), from the input terminal IN (input node in), and outputs the received signal OUT, which is converted between the third power supply VDDIO and the first power supply VDD, from the output terminal OUT (output node out). In other words, the input signal IN is a signal with an amplitude of VDD, and the output signal OUT is a signal with an amplitude of (VDDIO - VDD).

[0028] Figure 1 An example of a circuit diagram of the level shifting circuit 1 according to the first embodiment is shown.

[0029] The level shifting circuit 1 includes a first circuit 10, a second circuit 20, a pull-up circuit 30, and an inverter 5 that inverts the input signal IN to generate an inverted input signal INB.

[0030] Inverter 5 receives the input signal IN as input and outputs the inverted input signal INB to the inverted input node inb of the second circuit 20. The power supply terminal of inverter 5 is connected to the first power supply VDD, and the ground terminal of inverter 5 is connected to ground VSS. It should be noted that it can also be obtained from... Figure 1 Inverter 5 is omitted. For example, it can also be configured such that an input signal IN and an inverted input signal INB are generated in the pre-stage circuit (not shown) of the level shift circuit 1, and the input signal IN and the inverted input signal INB are input to the level shift circuit 1. The same applies in other figures (other embodiments).

[0031] The first circuit 10 and the second circuit 20 are circuits that boost and convert the input voltage input to the input terminal IN and output the converted voltage from the output terminal OUT. The first circuit 10 and the second circuit 20 are symmetrical to each other.

[0032] The circuits are described below with reference to the attached diagrams.

[0033] - First Circuit -

[0034] The first circuit 10 includes an N-type transistor N1 and P-type transistors P1, P2, and P9. It should be noted that the N-type and P-type transistors in this disclosure are, for example, transistors with a MOS structure.

[0035] The input node in of the first circuit 10 is connected to the input terminal IN and is input with the input signal IN.

[0036] An N-type transistor N1 (equivalent to the first N-type transistor) is positioned between the input node in and the node n11 (equivalent to the first node), with its gate connected to the first power supply VDD. A P-type transistor P9 (equivalent to the first P-type transistor) is positioned between the node n11 and the output node out, with its gate connected to the first power supply VDD. In other words, N-type transistor N1 and P-type transistor P9 are connected in series between the input node in and the output node out.

[0037] It should be noted that in this disclosure, "connection" broadly encompasses the concept of electrical connection, including not only direct connection but also indirect electrical connection via passive components (illustrations omitted).

[0038] P-type transistor P1 (equivalent to the thirteenth P-type transistor) is located between the third power supply VDDIO and the output node out. The gate of P-type transistor P1 is connected to the inverting output node outb (equivalent to the third node).

[0039] P-type transistor P2 (equivalent to the second P-type transistor) is located between the output node out and the first power supply VDD, and the gate of P-type transistor P2 is connected to node n11.

[0040] -Second Circuit-

[0041] The second circuit 20 includes an N-type transistor N2 and P-type transistors P3, P4, and P10. The inverting input node inb, which serves as the input node of the second circuit 20, is connected to the output of the inverter 5 and receives the inverted input signal INB.

[0042] An N-type transistor N2 (equivalent to a second N-type transistor) is positioned between the inverting input node inb and node n12 (equivalent to a second node), with its gate connected to the first power supply VDD. A P-type transistor P10 (equivalent to a third P-type transistor) is positioned between node n12 and the inverting output node outb, with its gate connected to the first power supply VDD. In other words, N-type transistor N2 and P-type transistor P10 are connected in series between the inverting input node inb and the inverting output node outb.

[0043] P-type transistor P3 (equivalent to the fourteenth P-type transistor) is located between the third power supply VDDIO and the inverting output node outb. The gate of P-type transistor P3 is connected to the output node out.

[0044] P-type transistor P4 (equivalent to the fourth P-type transistor) is located between the inverting output node outb and the first power supply VDD. The gate of P-type transistor P4 is connected to node n12.

[0045] As described above, P-type transistor P1 is connected between the third power supply VDDIO and the output node out, and P-type transistor P3 is connected between the third power supply VDDIO and the inverting output node outb. Furthermore, the gate of P-type transistor P1 is connected to the inverting output node outb, and the gate of P-type transistor P3 is connected to the output node out, thus forming a so-called cross-coupled connection. In the following description, the above structure will sometimes be referred to as a "cross-coupled connection" or a "cross-coupled structure".

[0046] - Pull-up circuit -

[0047] The pull-up circuit 30 is a circuit located between node n11 and node n12, and it is a circuit that operates by receiving power from the first power supply VDD and the third power supply VDDIO.

[0048] The pull-up circuit 30 includes circuit 40 and circuit 50, and circuit 40 and circuit 50 are symmetrical to each other.

[0049] Circuit 40 includes P-type transistors P6, P7, P11, and P14.

[0050] P-type transistor P7 (equivalent to the eleventh P-type transistor) is positioned between the third power supply VDDIO and node n16 (equivalent to the seventh node), with its gate connected to node n14 (equivalent to the sixth node). P-type transistor P14 (equivalent to the twelfth P-type transistor) is positioned between node n16 and node n11, with its gate connected to the first power supply VDD. In other words, P-type transistors P7 and P14 are connected in series between the third power supply VDDIO and node n11.

[0051] P-type transistor P6 (equivalent to the sixth P-type transistor) is located between node n13 (equivalent to the fourth node) and the first power supply VDD. The gate of P-type transistor P6 is connected to node n11.

[0052] P-type transistor P11 (equivalent to the fifth P-type transistor) is located between node n11 and node n13, and the gate of P-type transistor P11 is connected to the first power supply VDD.

[0053] Circuit 50 includes P-type transistors P5, P8, P12, and P13.

[0054] P-type transistor P5 (equivalent to the seventh P-type transistor) is positioned between the third power supply VDDIO and node n15 (equivalent to the fifth node), with its gate connected to node n13. P-type transistor P12 (equivalent to the eighth P-type transistor) is positioned between nodes n15 and n12, with its gate connected to the first power supply VDD. In other words, P-type transistors P5 and P12 are connected in series between the third power supply VDDIO and node n12.

[0055] P-type transistor P8 (equivalent to the tenth P-type transistor) is located between node n14 and the first power supply VDD, and the gate of P-type transistor P8 is connected to node n12.

[0056] P-type transistor P13 (equivalent to the ninth P-type transistor) is located between nodes n12 and n14, and the gate of P-type transistor P13 is connected to the first power supply VDD.

[0057] From a functional perspective, the pull-up circuit 30 assists in the boost conversion operation of the first circuit 10 and the second circuit 20. Specifically, the pull-up circuit 30 includes a first pull-up circuit 60 and a second pull-up circuit 70. The first pull-up circuit 60 pulls node n12 up to the third power supply VDDIO when node n11 transitions from a high level to a low level. The second pull-up circuit 70 pulls node n11 up to the third power supply VDDIO when node n12 transitions from a high level to a low level.

[0058] exist Figure 2 In the example, the first pull-up circuit 60 includes the aforementioned P-type transistors P5, P6, P11, and P12. The second pull-up circuit 70 includes the aforementioned P-type transistors P7, P8, P13, and P14.

[0059] [Operation of the level shifting circuit]

[0060] Next, the operation of the level shifting circuit 1 involved in this embodiment will be explained.

[0061] -Work Example (1-1)-

[0062] The operation will be explained when the input 'L' is used as the input signal IN and the output 'L' is used as the output signal OUT, that is, when the input signal voltage is VSS and the output signal voltage is VDD. In the following explanation, the gate-source voltage Vgs of the transistor will be simply referred to as "Vgs".

[0063] In the first circuit 10, since the input signal IN is 'L', the N-type transistor N1 is turned on, node n11 becomes 'L' (voltage VSS), and the P-type transistor P2 is turned on. Therefore, the voltage at the output node out becomes VDD, and 'L' (voltage VDD) is output to the output terminal OUT. Furthermore, as the voltage at the output node out becomes VDD, the P-type transistor P9 is turned off.

[0064] In the second circuit 20, since the voltage at the output node out is VDD, P-type transistors P3 and P10 are turned on. As a result, the voltage at node n12 and the inverting output node outb becomes VDDIO, and P-type transistors P1 and P4 and N-type transistor N2 are turned off.

[0065] In pull-up circuit 30, P-type transistor P6 is turned on, and the voltage at node n13 becomes VDD. Consequently, P-type transistor P11 is turned off, and P-type transistors P5 and P12 are turned on. Therefore, node n12 is pulled up to the third power supply VDDIO.

[0066] On the other hand, since P-type transistor P13 is turned on and P-type transistor P8 is turned off, the voltage at node n14 becomes VDDIO, and P-type transistors P7 and P14 are turned off.

[0067] -Work Example (1-2)-

[0068] The operation will be explained when the input 'H' is used as the input signal IN and the output 'H' is used as the output signal OUT, that is, when the voltage of the input signal is VDD and the voltage of the output signal is VDDIO. Since the first circuit 10 and the second circuit 20 have a symmetrical structure, and the circuit 40 and the circuit 50 have a symmetrical structure, the operation is the opposite of the above-described "Operating Example (1-1)".

[0069] In the second circuit 20, since the inverting input signal INB is 'L', the N-type transistor N2 is turned on, node n12 becomes 'L' (voltage VSS), and the P-type transistor P4 is turned on. Therefore, the voltage at the inverting output node outb becomes VDD, and the P-type transistor P10 is turned off.

[0070] In the first circuit 10, since the voltage at the inverting output node outb is VDD, P-type transistors P1 and P9 are turned on. Therefore, the voltage at node n11 and the output node out becomes VDDIO, and 'H' (VDDIO) is output from the output terminal OUT. Meanwhile, P-type transistors P2 and P3, and N-type transistor N1 are turned off.

[0071] In pull-up circuit 30, P-type transistor P8 is turned on, and the voltage at node n14 becomes VDD. Consequently, P-type transistor P13 is turned off, while P-type transistors P7 and P14 are turned on. Therefore, node n11 is pulled up to the third power supply VDDIO.

[0072] On the other hand, P-type transistor P11 is turned on and P-type transistor P6 is turned off, so the voltage at node n13 becomes VDDIO, and P-type transistors P5 and P12 are turned off.

[0073] -Work Examples (1-3)-

[0074] The operation is explained when the input signal IN changes from 'L' to 'H' and the output signal OUT changes from 'L' to 'H'.

[0075] The conduction / cutoff of each transistor and the voltage at each node change from the state described in "Operating Example (1-1)" to the state described in "Operating Example (1-2)". Hereinafter, the specific operation will be described separately in the case of "with pull-up circuit 30 provided (Example)" and "without pull-up circuit 30 provided (Comparative Example)".

[0076] (Example of operation with pull-up circuit provided [Example])

[0077] When the input signal IN changes from 'L' to 'H', the inverting input signal INB changes from 'H' to 'L'. That is, the voltage of the inverting input signal INB drops from VDD. During this process, the Vgs of the N-type transistor N2 exceeds the threshold, so N-type transistor N2 turns on, and the voltage at node n12 drops from VDDIO. At this time, in the pull-up circuit 30, the Vgs of the P-type transistor P8 exceeds the threshold, so P-type transistor P8 begins to turn on. As a result, the voltage at node n14 begins to drop from VDDIO.

[0078] In pull-up circuit 30, node n14 is connected to the gate of P-type transistor P7, but not to node n15, therefore it is not a cross-coupled structure. Thus, even if P-type transistor P8 starts conducting, there will be no "conduction between the third power supply VDDIO and the first power supply VDD" via P-type transistors P5 and P8. Consequently, the voltage at node n14 drops before the voltage at the inverting output node outb.

[0079] Therefore, P-type transistor P7 turns on before P-type transistor P1, and the voltage at node n11 rises before the voltage at output node out. In other words, pull-up circuit 30 operates by pulling node n11 up to the third power supply VDDIO when node n12 transitions from high to low.

[0080] Subsequently, Vgs of P-type transistor P9 exceeds the threshold, causing P-type transistor P9 to conduct. This connects node n11 and output node out, and the voltage at output node out begins to rise. Therefore, compared to the case without the pull-up circuit 30 described later, the voltage rise at output node out is accelerated, and the turn-off of P-type transistor P3 is advanced. Furthermore, due to the cross-coupling structure, the voltage drop at the inverting output node outb and the earlier conduction of P-type transistor P1 ensure that the signal output (signal conversion from 'L' to 'H') towards output terminal OUT is not delayed.

[0081] (Working example without pull-up circuit [comparative example])

[0082] When the input signal IN changes from 'L' to 'H', the inverting input signal INB changes from 'H' to 'L'. That is, the voltage of the inverting input signal INB drops from VDD. During this process, Vgs of the N-type transistor N2 exceeds its threshold, and N-type transistor N2 turns on, causing the voltage at node n12 to drop from VDDIO. Consequently, Vgs of the P-type transistor P4 exceeds its threshold, and P-type transistor P4 begins to turn on. Thus, the voltage at the inverting output node outb begins to drop from VDDIO. At this time, since P-type transistor P3 is still turning on, a period occurs where the third power supply VDDIO is connected to the first power supply VDD via P-type transistors P3 and P4. Therefore, the voltage drop at the inverting output node outb becomes slow before P-type transistor P3 begins to turn off, which is the reason for the turn-on delay of P-type transistor P1.

[0083] Subsequently, when P-type transistor P1 turns on, the voltage at the output node OUT begins to rise from VDD. At this time, since P-type transistor P2 is still on, a period occurs where the third power supply VDDIO is connected to the first power supply VDD via P-type transistors P1 and P2. Therefore, before P-type transistor P2 turns off, the voltage rise at the output node OUT becomes slow, and the turn-off of P-type transistor P3 is delayed. Additionally, the turn-on delay of P-type transistor P9 slows the voltage rise at node n11, and the turn-off delay of P-type transistor P2. Furthermore, due to the cross-coupling structure, if the turn-off of P-type transistor P3 is delayed, the turn-on delay of P-type transistor P1 will occur; conversely, if the turn-on delay of P-type transistor P1 is delayed, the turn-off delay of P-type transistor P3 will be further delayed. As a result, the output signal OUT (the transition from 'L' to 'H') from the output terminal OUT is delayed.

[0084] -Work Examples (1-4)-

[0085] The operation is explained when the input signal IN changes from 'H' to 'L' and the output signal OUT changes from 'H' to 'L'.

[0086] The conduction / cutoff of each transistor and the voltage at each node change from the state described in "Operating Example (1-2)" to the state described in "Operating Example (1-1)". Hereinafter, the specific operation will be described separately in the case of "with pull-up circuit 30 provided (Example)" and "without pull-up circuit 30 provided (Comparative Example)".

[0087] (Example of operation with pull-up circuit provided [Example])

[0088] When the input signal IN drops from 'H' to 'L', the Vgs of the N-type transistor N1 exceeds the threshold, and N1 turns on, causing the voltage at node n11 to drop from VDDIO. At this time, in pull-up circuit 30, the Vgs of the P-type transistor P6 exceeds the threshold, and P6 turns on. Consequently, the voltage at node n13 begins to drop from VDDIO.

[0089] In pull-up circuit 30, node n13 is connected to the gate of P-type transistor P5, but not to node n16, and therefore is not a cross-coupled structure. Thus, even if P-type transistor P6 starts conducting, there will be no "conduction between the third power supply VDDIO and the first power supply VDD" via P-type transistors P7 and P6. Consequently, the voltage at node n13 drops before the voltage at output node out.

[0090] Therefore, P-type transistor P5 turns on before P-type transistor P3, and the voltage at node n12 rises before the voltage at the inverting output node outb. In other words, the pull-up circuit 30 operates by pulling node n12 up to the third power supply VDDIO when node n11 transitions from a high level to a low level.

[0091] Subsequently, Vgs of P-type transistor P10 exceeds the threshold, causing P-type transistor P10 to conduct. This connects node n12 with the inverting output node outb, and the voltage at outb begins to rise. Therefore, compared to the case without the pull-up circuit 30 described later, the voltage rise at outb is accelerated, and the P-type transistor P1 turns off earlier. Furthermore, due to the cross-coupling structure, the voltage drop at output node out and the earlier conduction of P-type transistor P3 ensure that the signal output (signal conversion from 'H' to 'L') towards the output terminal OUT is not delayed.

[0092] (Working example without pull-up circuit [comparative example])

[0093] When the input signal IN drops from 'H' to 'L', the Vgs of N-type transistor N1 exceeds the threshold, causing N-type transistor N1 to turn on, and the voltage at node n11 drops from VDDIO. This causes the Vgs of P-type transistor P2 to exceed the threshold, and P-type transistor P2 to turn on. Consequently, the voltage at the output node out begins to drop from VDDIO. At this time, since P-type transistor P1 is still on, a period occurs where the third power supply VDDIO is connected to the first power supply VDD via P-type transistors P1 and P2. Therefore, the voltage drop at the output node out becomes slow before P-type transistor P1 begins to turn off, which is the reason for the turn-on delay of P-type transistor P3.

[0094] Subsequently, when P-type transistor P3 turns on, the voltage at the inverting output node outb begins to rise from VDD. At this time, since P-type transistor P4 is still on, a period occurs where the third power supply VDDIO is connected to the first power supply VDD via P-type transistors P3 and P4. Therefore, before P-type transistor P4 turns off, the voltage rise at the inverting output node outb becomes slow, delaying the turn-off of P-type transistor P1. Additionally, the turn-on of P-type transistor P10 is delayed, and the voltage rise at node n12 becomes slow, delaying the turn-off of P-type transistor P4. Furthermore, due to the cross-coupling structure, if the turn-off of P-type transistor P1 is delayed, the turn-on of P-type transistor P3 is delayed; if the turn-on of P-type transistor P3 is delayed, the turn-off of P-type transistor P1 is further delayed. As a result, the output signal OUT (the transition from 'H' to 'L') from the output terminal OUT is delayed.

[0095] [The function and effects of the first embodiment]

[0096] As described above, compared to the case where the pull-up circuit 30 is not provided, by adopting the structure of this embodiment, the output of the signal toward the output terminal OUT is not delayed, and the circuit can be made faster.

[0097] Specifically, in the operating examples (1-3), since the pull-up circuit 30 operates by pulling node n11 to the third power supply VDDIO when node n12 transitions from a high level to a low level, the voltage rise at the output node out is accelerated, and the P-type transistor P3 turns off earlier. Furthermore, due to the voltage drop at the inverting output node outb and the earlier turn-on of the P-type transistor P1, the output signal OUT (the transition from 'L' to 'H') output from the output terminal OUT is not delayed.

[0098] Similarly, in operating examples (1-4), since the pull-up circuit 30 operates by pulling node n12 up to the third power supply VDDIO when node n11 transitions from a high level to a low level, the voltage rise at the inverting output node outb is accelerated, and the P-type transistor P1 turns off earlier. Furthermore, due to the voltage drop at the output node out and the earlier turn-on of the P-type transistor P3, the output signal OUT (the transition from 'H' to 'L') output from the output terminal OUT is not delayed.

[0099] It should be noted that in the level shifting circuit 1 of this embodiment, since an inverter 5 is provided, the propagation time of the signal from the input terminal IN to the output terminal OUT in operating example (1-3) is longer than that in operating example (1-4). Therefore, when the signal propagation time further increases as the operating voltage decreases, the difference between operating example (1-3) and operating example (1-4) increases, but this increase in difference can be suppressed in this embodiment.

[0100] Furthermore, the level shifting circuit 1 in this embodiment is composed of two power supplies, a first power supply VDD and a third power supply VDDIO, and does not use a bias voltage (equivalent to VBIAS in Patent Document 1). In other words, there is no need for a circuit to generate a bias voltage.

[0101] <Second Implementation>

[0102] Figure 4 An example circuit diagram of the level shifting circuit 1 according to the second embodiment is shown. Figure 4 In the middle, to and Figure 1 The corresponding structures are labeled with the same symbols. The following description focuses on the differences from the first embodiment. It should be noted that regarding the... Figure 1 and Figure 4 The use of the same symbols for components (e.g., transistors, inverters) does not imply that their various design parameters / process parameters must be identical. In other words, the scope of this disclosure includes configurations where... Figure 1 and Figure 4 The various parameters of components marked with the same symbol in Figure 1 and Figure 4 They are all different from each other. The relationships between the other attached figures are also the same.

[0103] Compared with the first embodiment, the level shifting circuit 1 in this embodiment is configured to further accelerate the rise of voltage at the output node out and the inverted output node outb.

[0104] In this embodiment, in the first circuit 10, the gate of the P-type transistor P1 is connected to node n14 of the pull-up circuit 30 (refer to...). Figure 2Instead of being connected to the inverting output node outb as in the first embodiment, the gate of the P-type transistor P3 is connected to node n13 of the pull-up circuit 30 (see reference 1). Figure 2 Instead of connecting to the output node out as in the first implementation, it connects to the output node out.

[0105] [Operation of the level shifting circuit]

[0106] Next, the operation of the level shifting circuit 1 according to this embodiment will be described. Here, the description will focus on the differences in operation between this embodiment and the level shifting circuit 1 according to the first embodiment.

[0107] -Work Example (2-1)-

[0108] The operation is explained when the input signal IN changes from 'L' to 'H'.

[0109] In the first embodiment, P-type transistor P7 turns on before P-type transistor P1, and the voltage at node n11 rises before the voltage at output node out. Then, P-type transistor P9 turns on, thereby increasing the voltage at output node out.

[0110] In contrast, in this embodiment, the gates of P-type transistors P7 and P1 are connected to a common node n14, so P-type transistors P7 and P1 turn on at the same time. Therefore, the voltage at node n11 rises at the same time as the voltage at the output node out. Furthermore, since P-type transistors P1 and P3 are not cross-coupled, the voltage at the output node out rises unaffected by the operation of P-type transistor P3. Thus, compared to the first embodiment, the voltage at the output node out rises more quickly.

[0111] -Work Example (2-2)-

[0112] The operation is explained when the input signal IN changes from 'H' to 'L'.

[0113] Similar to the above-described examples (1-4), but compared to example (2-1), the first circuit 10 and the second circuit 20 operate in opposite ways in this example. As a result, the voltage at the inverting output node outb rises regardless of the operation of the P-type transistor P1. Therefore, compared to the first embodiment, the voltage at the inverting output node outb can rise more quickly.

[0114] [The function and effects of the second embodiment]

[0115] As described above, according to this embodiment, compared to the first embodiment, the voltage at the output node out and the voltage at the inverting output node outb can rise more quickly. Therefore, compared to the first embodiment, a higher circuit speed can be achieved.

[0116] <Third Implementation Method>

[0117] Figure 5 An example circuit diagram of the level shifting circuit 1 according to the third embodiment is shown. Figure 5 In the middle, to and Figure 1 Corresponding structural annotations and Figure 1 The same symbols are used. The following description focuses on the differences from other embodiments.

[0118] In this embodiment, the level shifting circuit 1 omits P-type transistors P1 and P3 from the structures of the first and second embodiments. Furthermore, for example, the driving capability of P-type transistor P7, i.e., the size of the transistor, can be set such that the operation of P-type transistor P1 in the first and second embodiments is included in P-type transistor P7. Similarly, the driving capability of P-type transistor P5, i.e., the size of the transistor, can be set such that the operation of P-type transistor P3 is included in P-type transistor P5.

[0119] [Operation of the level shifting circuit]

[0120] In this embodiment, the P-type transistor P5 in the pull-up circuit 30 (refer to...) Figure 2 ) and P-type transistor P7 (refer to Figure 2 When the circuit is turned on, the voltage at node n11, node n12, output node out, and inverting output node outb increases. Therefore, the level shifting circuit 1 in this embodiment operates in the same way as in the second embodiment, achieving the same effect.

[0121] [The function and effects of the third embodiment]

[0122] As described above, according to this embodiment, the same operation as in the second embodiment can achieve the same effect.

[0123] Furthermore, since it is not necessary to arrange P-type transistors P1 and P3, nor their wiring (including the transistor arrangement area and wiring area), the circuit area can be reduced compared to the first and second embodiments. For example, in cases such as those used in control system signals (Enable / Disable signals, etc.) that are slower than clock or data signals, the circuit area can be further reduced without needing to extend the driving capability of P-type transistors P5 and P7.

[0124] It should be noted that the technology in this disclosure is not limited to the structure described in the above embodiments, and can also be applied to embodiments with appropriate modifications, substitutions, additions, omissions, etc. Furthermore, the constituent elements described in the above embodiments can be combined to create new embodiments.

[0125] <Variation Example>

[0126] Figure 6 A modified example of the level shifting circuit 1 according to the first embodiment is shown. Figure 6 In the middle, to and Figure 1 Corresponding structural annotations and Figure 1 The same symbols. In the following description, the differences from the first embodiment will be the focus.

[0127] In addition to the structure of the first embodiment, the level shifting circuit 1 of this embodiment also provides a capacitor C1 between the output node out and the node n11, and a capacitor C2 between the inverting output node outb and the node n12.

[0128] It should be noted that the structure of capacitors C1 and C2 is not particularly limited. For example, capacitor elements can be used as capacitors C1 and C2, or transistor capacitors such as gate capacitors or S / D capacitors (source-drain capacitance) can be used. The same applies to capacitors C3 and C4, which will be discussed later.

[0129] Pull-up circuit 30 can have the same structure as in the first embodiment (see reference). Figure 2 ), or it can be Figure 7 The structure shown. Specifically, it can be... Figure 1 The first circuit 10 and the second circuit 20 shown are... Figure 7 The pull-up circuits 30 shown can be combined to... Figure 6 The first circuit 10 and the second circuit 20 shown are... Figure 2 The pull-up circuit 30 shown is or Figure 7 The pull-up circuit 30 shown is combined.

[0130] - Pull-up circuit -

[0131] Figure 7 Other structural examples of the pull-up circuit 30 are shown. Figure 7 In the middle, to and Figure 2 Corresponding structural annotations and Figure 2 Same symbols.

[0132] Apart from Figure 2 In addition to the structure, Figure 7The pull-up circuit 30 also includes a capacitor C3 between nodes n11 and n13, and a capacitor C4 between nodes n12 and n14. Figure 7 In the example, the first pull-up circuit 60 includes capacitor C3 in addition to the aforementioned P-type transistors P5, P6, P11, and P12. The second pull-up circuit 70 includes capacitor C4 in addition to the aforementioned P-type transistors P7, P8, P13, and P14.

[0133] [Operation of the level shifting circuit]

[0134] Next, the operation of the level shifting circuit 1 involved in this variation will be explained. Here, the operation of the first circuit 10, the second circuit 20, and the pull-up circuit 30 will be summarized and explained.

[0135] - Operation during voltage rise at the output node / inverting output node -

[0136] When the voltage at the output node out rises, the pull-up circuit 30 increases the voltage at node n11, turning on the P-type transistor P9. This connects the output node out with node n11, thus assisting in the voltage rise at the output node out. Consequently, the voltage rise at the output node out can be accelerated.

[0137] Similarly, when the voltage at the inverting output node outb rises, the pull-up circuit 30 raises the voltage at node n12, turning on the P-type transistor P10. This connects the inverting output node outb to node n12, thereby assisting in the voltage rise at the inverting output node outb. This accelerates the voltage rise at the inverting output node outb.

[0138] Here, by adding capacitor C1, the voltage at the output node out will increase as the voltage at node n11 increases before the P-type transistor P9 turns on. Similarly, by adding capacitor C2, the voltage at the inverting output node outb will increase as the voltage at node n12 increases before the P-type transistor P10 turns on.

[0139] Additionally, by adding capacitor C3, the voltage at node n13 will rise before P-type transistor P11 turns on. Similarly, by adding capacitor C4, the voltage at node n14 will rise before P-type transistor P13 turns on.

[0140] - Operation when the voltage drops at the output node / inverting output node -

[0141] When the voltage at the output node out drops, N-type transistor N1 turns on, causing the voltage at node n11 to drop. After P-type transistor P9 turns off, P-type transistor P2 turns on, thus causing the voltage at the output node out to drop to the voltage of the first power supply VDD. Similarly, when the voltage at the inverting output node outb drops, N-type transistor N2 turns on, causing the voltage at node n12 to drop. After P-type transistor P10 turns off, P-type transistor P4 turns on, thus causing the voltage at the inverting output node outb to drop to the voltage of the first power supply VDD.

[0142] Here, if capacitor C1 is added, the voltage at the output node out will decrease as the voltage at node n11 decreases before the P-type transistor P2 turns on. Similarly, if capacitor C2 is added, the voltage at the inverting output node outb will decrease as the voltage at node n12 decreases before the P-type transistor P4 turns on.

[0143] Additionally, by adding capacitor C3, the voltage at node n13 will decrease before P-type transistor P6 turns on. Similarly, by adding capacitor C4, the voltage at node n14 will decrease before P-type transistor P8 turns on.

[0144] [The function and effect of the modified examples]

[0145] As described above, according to this modified example, the voltage rise / fall at the output node out and the inverting output node outb can be accelerated, thereby enabling high-speed operation of the circuit.

[0146] It should be noted that while the above description of "modifications" focuses on modifications to the first embodiment, the same modifications can also be applied in the second or third embodiment to achieve the same effect. Specifically, for example, the above-described modification involved providing capacitors C1 and C2 in addition to the structure of the first embodiment. In the second and third embodiments, capacitors C1 and C2 can also be provided in the same positions as in the first embodiment to achieve the same effect. Furthermore, in the second and third embodiments, alternatives can be used... Figure 2 The pull-up circuit 30 is set up Figure 7 The pull-up circuit 30 can achieve the same effect.

[0147] -Industry Applicability-

[0148] The level shifting circuit disclosed herein is extremely useful because it can accommodate lower operating voltages and / or higher circuit operating speeds.

[0149] - Symbol Explanation -

[0150] 1. Level shifting circuit

[0151] 30 Pull-up circuit

[0152] N1 N-type transistor (first N-type transistor)

[0153] N2 N-type transistor (second N-type transistor)

[0154] P1 P-type transistor (thirteenth P-type transistor)

[0155] P2 P-type transistor (second P-type transistor)

[0156] P3 P-type transistor (fourteenth P-type transistor)

[0157] P4 P-type transistor (fourth P-type transistor)

[0158] P5 P-type transistor (seventh P-type transistor)

[0159] P6 P-type transistor (sixth P-type transistor)

[0160] P7 P-type transistor (eleventh P-type transistor)

[0161] P8 P-type transistor (tenth P-type transistor)

[0162] P9 P-type transistor (first P-type transistor)

[0163] P10 P-type transistor (third P-type transistor)

[0164] P11 P-type transistor (fifth P-type transistor)

[0165] P12 P-type transistor (eighth P-type transistor)

[0166] P13 P-type transistor (ninth P-type transistor)

[0167] P14 P-type transistor (twelfth P-type transistor)

[0168] n11 node (first node)

[0169] n12 node (second node)

[0170] n13 Node (Fourth Node)

[0171] n14 node (sixth node)

[0172] n15 node (the fifth node)

[0173] n16 node (seventh node)

[0174] n17 Node (Third Node)

[0175] in input node

[0176] inb inverting input node

[0177] out output node

[0178] outb is the inverted output node (third node).

[0179] VDD First Power Supply

[0180] VDDIO Third Power Supply

[0181] VSS ground (second power supply)

[0182] C1 capacitor (first capacitor)

[0183] C2 capacitor (second capacitor)

[0184] C3 capacitor (first capacitor)

[0185] C4 capacitor (second capacitor).

Claims

1. A level shifting circuit, characterized in that, The level shifting circuit includes: An input node receives an input signal that is switched between a first power source and a second power source, wherein the potential of the second power source is lower than that of the first power source. A first N-type transistor is disposed between the input node and the first node, and the gate of the first N-type transistor is connected to the first power supply. A first P-type transistor is disposed between the first node and the output node, and the gate of the first P-type transistor is connected to the first power supply. The second P-type transistor is disposed between the output node and the first power supply, and the gate of the second P-type transistor is connected to the first node; An inverting input node receives an inverted input signal obtained by inverting the input signal; The second N-type transistor is disposed between the inverting input node and the second node, and the gate of the second N-type transistor is connected to the first power supply. A third P-type transistor is disposed between the second node and the third node, and the gate of the third P-type transistor is connected to the first power supply. A fourth P-type transistor, wherein the fourth P-type transistor is disposed between the third node and the first power supply, and the gate of the fourth P-type transistor is connected to the second node; and A pull-up circuit is provided between the first node and the second node. The pull-up circuit includes: A first pull-up circuit pulls the second node to a third power supply when the first node transitions from a high level to a low level. The potential of the third power supply is higher than that of the first power supply. The second pull-up circuit pulls the first node to the third power supply when the second node transitions from a high level to a low level.

2. The level shifting circuit according to claim 1, characterized in that, The first pull-up circuit includes: A fifth P-type transistor is disposed between the first node and the fourth node, and the gate of the fifth P-type transistor is connected to the first power supply. A sixth P-type transistor is disposed between the fourth node and the first power supply, and the gate of the sixth P-type transistor is connected to the first node; A seventh P-type transistor, wherein the seventh P-type transistor is disposed between the third power supply and the fifth node, and the gate of the seventh P-type transistor is connected to the fourth node; and An eighth P-type transistor is disposed between the fifth node and the second node, and the gate of the eighth P-type transistor is connected to the first power supply. The second pull-up circuit includes: A ninth P-type transistor is disposed between the second node and the sixth node, and the gate of the ninth P-type transistor is connected to the first power supply. A tenth P-type transistor is disposed between the sixth node and the first power supply, and the gate of the tenth P-type transistor is connected to the second node; An eleventh P-type transistor, wherein the eleventh P-type transistor is disposed between the third power supply and the seventh node, and the gate of the eleventh P-type transistor is connected to the sixth node; and The twelfth P-type transistor is disposed between the seventh node and the first node, and its gate is connected to the first power supply.

3. The level shifting circuit according to claim 2, characterized in that, The level shifting circuit includes: A thirteenth P-type transistor, wherein the thirteenth P-type transistor is disposed between the third power supply and the output node, and the gate of the thirteenth P-type transistor is connected to the sixth node; and The fourteenth P-type transistor is disposed between the third power supply and the third node, and its gate is connected to the fourth node.

4. The level shifting circuit according to claim 2, characterized in that, The first pull-up circuit includes a first capacitor element, which is disposed between the first node and the fourth node. The second pull-up circuit includes a second capacitor element, which is disposed between the second node and the sixth node.

5. The level shifting circuit according to claim 1, characterized in that, The level shifting circuit includes: A thirteenth P-type transistor, wherein the thirteenth P-type transistor is disposed between the third power supply and the output node, and the gate of the thirteenth P-type transistor is connected to the third node; and The fourteenth P-type transistor is disposed between the third power supply and the third node, and its gate is connected to the output node.

6. The level shifting circuit according to claim 1, characterized in that, The level shifting circuit includes: A first capacitor element is disposed between the first node and the output node; and The second capacitor element is disposed between the second node and the third node.

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