Control method of flash memory device and flash memory device
By conducting risk assessments on the hardware information of flash memory devices and dynamically adjusting RAID group members, the data loss problem caused by fixed RAID group configurations was resolved, resulting in higher data reconstruction efficiency and device reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN SHICHUANGYI ELECTRONICS CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-05
AI Technical Summary
Existing redundant arrays of independent disks (RAID groups) have fixed member selection and do not consider health status, which makes the data redundancy array prone to errors and data loss.
By acquiring the hardware information of the flash memory device, the preset storage space is divided into multiple independent disk redundant array reserve members. An unrecoverable error risk assessment is conducted, and the initial disk redundant array group is dynamically adjusted and selected as the initial member to avoid multiple members from experiencing unrecoverable errors at the same time.
It improves data reconstruction success rate, reduces the risk of data loss, and enhances the reliability and efficiency of flash memory devices.
Smart Images
Figure CN121979446A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a control method for a flash memory device and a flash memory device. Background Technology
[0002] NAND flash memory, as a new type of storage medium, offers advantages over hard disk drives (HDDs) such as large capacity, fast read / write speeds, shock and drop resistance, low power consumption, no noise, and low price, leading to its widespread adoption in consumer PCs and enterprise servers. Flash memory devices typically include a storage controller chip that manages multiple NAND flash memory cells. This controller chip handles host data access requests and performs functions such as mapping logical addresses to physical addresses, bad sector management, wear leveling, and error handling through the Flash Translation Layer (FTL). Because NAND flash memory inevitably exhibits errors due to its manufacturing process and physical characteristics, the storage controller chip usually incorporates an Error Correction Code (ECC) mechanism to correct bit errors generated during the read process. However, as the number of write cycles and data storage time of NAND flash increases, the error rate also rises, and relying solely on the ECC mechanism may still face the risk of uncorrectable errors (UECC). To further improve data reliability, some storage controller chips implement a data redundancy mechanism similar to Redundant Array of Independent Disks (RAID) internally.
[0003] However, the number of members in a current redundant array of independent disks (RAID) is fixed, and the health status of the members is not taken into account, which makes the RAID group prone to errors and data loss. Summary of the Invention
[0004] The purpose of this application is to provide a control method and a flash memory device, which improves the probability of a single failure occurring under expected usage conditions by adjusting the composition of independent disk redundant array members, thereby increasing the data reconstruction success rate and avoiding data loss.
[0005] This application discloses a control method for a flash memory device, the control method comprising the following steps: Obtain hardware information for the flash memory device; According to the independent disk redundancy array assembly rules, the preset storage space of the flash memory device is divided into multiple independent disk redundancy array pre-group members; Perform a risk assessment of unrecoverable errors for multiple independent disk redundant arrays; Based on the risk assessment results, an initial independent disk redundant array group was determined from multiple independent disk redundant array prospective members; Perform read and write operations on business data based on the initial independent disk redundant array group; The initial independent disk redundant array group includes at least N consecutive independent disk redundant array reserve members, where N is a natural number greater than or equal to 2.
[0006] Optionally, the step of conducting an unrecoverable error risk assessment on multiple independent disk redundant array pre-construction members includes: Error behavior analysis is performed on each independent disk redundant array preparatory member, and an error behavior index is generated for each independent disk redundant array preparatory member; The risk of unrecoverable errors occurring when multiple independent RAID candidate members become a virtual independent RAID group is calculated based on the error behavior indicators of each independent RAID candidate member.
[0007] Optionally, the step of determining the initial independent redundant disk array group from multiple independent redundant disk array prospective members based on the risk assessment results includes: When the risk of unrecoverable errors in n consecutive independent redundant disk array (RBAC) candidate members is the lowest, the n consecutive RBAC candidate members are selected as the initial RBAC group; where n is a natural number greater than or equal to 2.
[0008] Optionally, the step of calculating the risk of unrecoverable errors occurring when multiple independent disk redundant array (ISA) candidates become a virtual independent disk redundant array (DSA) group based on the error behavior indicators of each independent disk redundant array candidate includes: Arbitrarily select a consecutive 'a' independent disk redundant array pre-group members as a virtual independent disk redundant array group; where a is a natural number greater than or equal to 2; Based on the error behavior indicators of each standby ... The step of determining the initial independent redundant disk array group from multiple independent redundant disk array prospective members based on the risk assessment results includes: Compare the number of independent disk redundancy array reserve members in multiple candidate groups; The candidate group with the largest number of reserve members for the independent disk redundant array is selected as the initial independent disk redundant array group.
[0009] Optionally, after the step of performing read and write operations on business data based on the initial independent disk redundant array group, the method further includes: If an unrecoverable error occurs in one of the standby ... Based on the risk assessment results, the initial independent disk redundant array group was reorganized from multiple independent disk redundant array reserve members.
[0010] Optionally, the rules for constructing the independent disk redundant array include: The preset storage space is divided into multiple independent storage units based on the physical structure in the hardware information of the flash memory device; the independent disk redundancy array pre-group includes an independent storage unit.
[0011] Optionally, the step of dividing the preset storage space of the flash memory device into multiple independent redundant disk array (RBAC) pre-group members according to the independent redundant disk array (RBAC) assembly rules includes: According to the independent disk redundancy array assembly rules, the preset storage space of the flash memory device is divided into multiple logical storage unit groups; wherein, each of the logical storage unit groups includes multiple independent storage units, and each independent storage unit serves as a reserve member of an independent disk redundancy array. The step of arbitrarily selecting a consecutive a independent disk redundant array reserve members as a virtual independent disk redundant array group includes: Within each logical storage unit group, arbitrarily select a consecutive 'a' independent storage units as a virtual independent disk redundant array group, and use a greedy algorithm model to exhaustively enumerate multiple virtual independent disk redundant array groups.
[0012] Optionally, the preset storage space is divided into multiple independent storage units based on the word line parameters in the hardware information of the flash memory device, wherein one word line is considered as an independent storage unit. When the number of logical memory cell groups is b, word lines with the same remainder after taking the remainder from b are considered as the same logical memory cell group, where b is a natural number greater than or equal to 2. Among them, N consecutive word lines within the same logical storage unit group are used as the initial independent disk redundant array group.
[0013] Optionally, the error bit behavior includes the amount of error that can be corrected by the error correction mechanism during the read operation, the trend of the error amount over time or the number of uses, and the frequency at which the error amount approaches the upper limit of the error correction capability.
[0014] This application also discloses a flash memory device for storing program data, which can be executed to implement the control method of the flash memory device described above.
[0015] This application divides a pre-defined storage space into multiple independent redundant disk array (RBAR) reserve members, performs an unrecoverable error risk assessment on these reserve members, and determines an initial RBAR group based on the assessment results. This initial RBAR group is selected from the multiple RBAR reserve members. By using a risk assessment method, this application selects as many healthy RBAR reserve members as possible for the initial RBAR group. In other words, by filtering out RBAR reserve members that may subsequently cause errors or unrecoverable failures, and by adjusting the composition of the RBAR group, the probability of only a single failure occurring under expected usage conditions is increased, thereby improving data reconstruction success and avoiding data loss. Attached Figure Description
[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram illustrating the steps of a control method for a flash memory device according to this application; Figure 2 This is a schematic diagram illustrating the steps of another method for controlling a flash memory device according to this application. Detailed Implementation
[0017] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.
[0018] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Furthermore, terms such as "upper," "lower," "left," "right," "vertical," and "horizontal," indicating orientation or positional relationships, are based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0019] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.
[0020] Figure 1 This is a schematic diagram illustrating the steps of a control method for a flash memory device according to this application. See also... Figure 1 As shown, this application discloses a control method for a flash memory device, the control method comprising the following steps: S100: Obtain hardware information of the flash memory device; S200: Divide the preset storage space of the flash memory device into multiple independent redundant disk array reserve members (RAID reserve members) according to the independent disk redundant array group (RAID group) creation rules. S300: Performs risk assessment of unrecoverable errors for multiple RAID pre-construction members; S400: Determine the initial RAID group from multiple RAID prospective members based on the risk assessment results; S500: Perform read and write operations on service data based on the initial RAID group.
[0021] The initial RAID group includes at least N consecutive RAID reserve members, where N is a natural number greater than or equal to 2.
[0022] This application divides a pre-defined storage space into multiple RAID reserve members, performs an unrecoverable error risk assessment on these reserve members, and determines an initial RAID group based on the assessment results. This initial RAID group is selected from these reserve members. By using a risk assessment method, this application selects as many healthy RAID reserve members as possible for the initial RAID group. In other words, by filtering out RAID reserve members that may subsequently cause errors or unrecoverable failures, and by adjusting the RAID group composition, it increases the probability of only a single failure occurring under expected usage conditions, thereby improving data reconstruction success and avoiding data loss.
[0023] This embodiment uses the RAID5 data redundancy mechanism as an example for explanation, but it does not limit the technical solution of this application to only the RAID5 data redundancy mechanism. RAID5 is a data protection technology that combines data striping and distributed parity. In the RAID5 architecture, data is divided into multiple data blocks and stored in multiple members, while a parity block is generated through XOR (exclusive OR) operation. For a RAID5 stripe containing N members, N-1 members store data blocks, and the remaining member stores the parity block. When any member fails, the lost data content can be reconstructed using the data in the remaining member and the parity block through XOR operation. Therefore, RAID5 can tolerate the failure of a single member without causing data loss. Traditional RAID5 usually assumes that each member is independent and approximately the same in terms of reliability and failure behavior. The N members are the N RAID reserve members in this embodiment.
[0024] In the S100 step, by obtaining information about the flash memory device, taking TLC NAND Flash memory as an example, RAID group member configuration is performed based on word lines.
[0025] In step S200, the RAID configuration rules include: dividing a preset storage space into multiple independent storage units based on one or more parameters in the hardware information of the flash memory device, such as plane, wordline, column, page, block, stream, die, chip enable (CE), or channel. Each independent storage unit can independently perform error analysis and risk assessment.
[0026] For example, in flash storage systems, RAID mechanisms do not use disk devices as members, but rather the physical structure of the NAND flash memory as RAID members, such as channels, chip enable (CE), memory dies, or planes. For instance, a fixed-configuration RAID strategy might be used, defining the members of a RAID group as "number of channels * number of CEs * number of planes operating simultaneously," and then performing XOR parity calculations and storage within that RAID group.
[0027] For example, a Plane can be considered an independent storage unit, i.e., a potential member of a RAID array. Alternatively, independent storage units can be partitioned according to parameters such as Wordline, Column, Page, Block, Stream, Die, CE, or Channel.
[0028] The RAID preparatory members include one or more independent storage units.
[0029] In the S300 process, the N members in RAID5 need to be selected from multiple RAID candidate members through a risk assessment of unrecoverable errors. This group of members can be dynamically adjusted or fixed.
[0030] In practical implementation, due to differences in error behavior and aging behavior among multiple members in a RAID group—partly due to manufacturing process differences and partly due to varying degrees of aging—and the non-linear increase in the error rate of any member over time, different members may reach high-risk states at different times. Furthermore, in actual data redundancy mechanisms, it's difficult to achieve ideal conditions where the probability of any member experiencing an unrecoverable error is independent, or where the write pressure on parity is evenly distributed to maintain reliability. Therefore, a RAID group assembled according to fixed rules may include multiple high-risk members in the same group, causing one or more members in the RAID group to experience more than one (i.e., two or more) unrecoverable errors (UECCs) within a short period, leading to RAID mechanism failure and inability to rebuild data. For example, if a RAID group consists of N planes, and each plane provides a fixed-size data unit (e.g., 16KB), the control chip, when receiving data from the host, will perform an XOR operation on the data from the first N-1 planes, accumulating and generating parity, and then write the final parity to the Nth plane. This RAID strategy has the following characteristics: the members in the RAID group are fixed, the parity position is fixed or rotates according to fixed rules, and the RAID engine does not consider the actual health status of each member.
[0031] In this embodiment, by assessing the risk of unrecoverable errors in a set of initial RAID groups, risk analysis is performed on multiple RAID preparation members, maximizing the probability that only a single unrecoverable error event will occur in the RAID preparation members in the initial RAID group, and reducing the risk of a second unrecoverable error occurring in the same RAID group, i.e., the initial RAID group.
[0032] The risk assessment of unrecoverable errors in this implementation can be considered as a logical module independent of the RAID engine, used to analyze the erroneous behavior of each potential RAID group member. This application does not limit the specific algorithm of this analysis mechanism, but only specifies that its output can be used for the composition decision of the initial RAID group.
[0033] In one specific embodiment, step S300 includes: S310: Analyzes the error behavior of each RAID pre-construction member and generates an error behavior index for each RAID pre-construction member.
[0034] The error bit behavior includes the amount of errors that can be corrected by the error correction mechanism during read operations, the trend of the error amount over time or the number of uses, and the frequency with which the error amount approaches the upper limit of the error correction capability. Through the above analysis, an error behavior indicator can be generated for each RAID pre-construction member to reflect the potential risk of unrecoverable errors in the future.
[0035] In one embodiment, the feature analysis mechanism may include one or more of the following functions: collecting error-related information during the reading process, analyzing the statistical characteristics of error behavior, and estimating risk indicators of unrecoverable errors.
[0036] S320: Calculates the risk of unrecoverable errors occurring when multiple RAID pre-groups become a virtual RAID group based on the error behavior indicators of each RAID pre-group member.
[0037] The steps in S400 include: In S401: When the risk of unrecoverable errors in n consecutive RAID reserve members is the lowest, the n consecutive RAID reserve members are used as the initial RAID group; where n is a natural number greater than or equal to 2.
[0038] The risk of unrecoverable errors (UECC) requires analysis by including multiple RAID pre-construction members within the same virtual RAID group to further estimate the risk of each RAID pre-construction member experiencing an unrecoverable error (UECC). This risk can be expressed as a comparable quantitative result, such as a risk value or ranking result. This application does not limit the calculation method of UECC risk, but only requires that the risk assessment result can reflect the relative failure risk of different RAID pre-construction members.
[0039] In one embodiment, the failure correlation of multiple RAID candidate members may be further considered. In one embodiment, a characteristic analysis mechanism can compare the error behavior characteristics of different members to determine whether they are suitable for inclusion in the same RAID group.
[0040] In this embodiment, the virtual RAID group is formed by selecting different RAID reserve members multiple times. This is because multiple virtual RAID groups may all meet the risk assessment of the aforementioned unrecoverable error. In one embodiment, any one of these virtual RAID groups can be selected as the initial RAID group.
[0041] Steps S310 and S320 of this embodiment can be tested during the testing process to select initial RAID groups for different types of flash memory devices. In subsequent actual use, this configuration is directly imported into the corresponding flash memory device.
[0042] Figure 2 This is a schematic diagram illustrating the steps of another control method for a flash memory device according to this application. See also... Figure 2 As shown, the other steps are the same as in the above embodiment, wherein step S320 includes: S321: Randomly select a consecutive RAID pre-group members as a virtual RAID group; where a is a natural number greater than or equal to 2; S322: Calculate the number of virtual RAID groups in which no more than one RAID candidate group experiences an unrecoverable error simultaneously within multiple virtual RAID groups based on the error behavior index of each RAID candidate group member, and mark them as candidate groups; The steps in S400 include: S411: Compare the number of RAID reserve members in multiple candidate groups; S412: Select the candidate group with the largest number of RAID reserve members as the initial RAID group.
[0043] In this embodiment, multiple virtual RAID groups may all meet the aforementioned risk assessment of unrecoverable errors, meaning there are multiple candidate groups. By comparing the number of RAID reserve members in multiple candidate groups, the candidate group with the most RAID reserve members is selected as the initial RAID group. Relatively speaking, the more members, the wider the fault tolerance coverage and the better the data protection effect, provided that only a single UECC is allowed. Moreover, when the number of members in the initial RAID group is N, the parity overhead is approximately 1 / N. The fewer the members, the more parity needs to be written. Parity writing increases the number of writes, affecting write performance. It also leads to increased Flash consumption and affects Flash lifespan. Therefore, the initial RAID group composition strategy of this invention maximizes the number of members in the initial RAID group as much as possible while meeting the data reliability target, thereby reducing parity overhead.
[0044] Specifically, based on the Wordline parameter in the hardware information of the flash memory device, the preset storage space is divided into multiple independent storage units, where one Wordline is considered an independent storage unit; when the number of logical storage unit groups is b, the Wordline sequence number is modulo b, and Wordlines with the same remainder are considered as the same logical storage unit group, where b is a natural number greater than or equal to 2; and N consecutive Wordlines within the same logical storage unit group are considered as the initial RAID group.
[0045] In one specific embodiment, step S200 includes: S201: Divide the preset storage space of the flash memory device into multiple logical storage unit groups according to the RAID configuration rules; wherein, each of the logical storage unit groups includes multiple independent storage units, and each independent storage unit serves as a RAID pre-group member; The steps in S321 include: S321a: Within each logical storage unit group, arbitrarily select a consecutive independent storage units as a virtual RAID group, and use a greedy algorithm to exhaustively enumerate multiple virtual RAID groups.
[0046] In this embodiment, taking a TLC NAND Flash memory as an example, the TLC NAND Flash is configured to have the following structural characteristics: each block contains multiple Wordlines (WLs), and every 6 WLs form a stream. The corresponding relationship can be expressed as: This means that each stream is considered a logical storage unit group, and there are 6 logical storage unit groups, namely stream 0, stream 1, stream 2, stream 3, stream 4, and stream 5. Stream 0 represents wordlines divisible by 6, such as WL0, WL6, WL12, etc. In stream 0, WL1, WL7, and WL13 are considered consecutive. Stream 1 includes consecutive wordlines such as WL1, WL7, and WL13, whose remainder is 1 when divided by 6. Stream 2 includes consecutive wordlines such as WL2, WL8, and WL14. And so on, with stream 5 including consecutive wordlines such as WL5, WL11, and WL17.
[0047] Taking the aforementioned virtual RAID groups as examples, a mathematical model is used to calculate the composition of the initial RAID group with the largest number of members. Specifically, a virtual RAID group is defined as consisting of... The virtual RAID group consists of several members, each corresponding to a random variable. This random variable can be one of the aforementioned error behavior indicators. The condition for a virtual RAID group to successfully recover data is defined as follows: The number of members in the virtual RAID group experiencing UECC simultaneously cannot exceed one, which is the upper limit that the system can tolerate. The probability of successful data recovery for a virtual RAID group is defined as: .in This represents the probability of successful data protection for the virtual RAID group given its composition. The number of members in the virtual RAID group. For the first The probability of a UECC event is a random variable for each member, which can be derived from the UECC occurrence probability model obtained from the aforementioned NAND characteristic analysis elements.
[0048] Based on the above probability model, this application treats the composition of virtual RAID groups as an optimization problem, and its mathematical model is as follows:
[0049] in, The number of members in the virtual RAID group. This is the set of random variables for each member's UECC event. In multiple [locations / processes], this allows... Among feasible solutions that reach the maximum value or an equivalent maximum value, the number of members in the virtual RAID group is further selected. The largest one.
[0050] In this embodiment, a greedy algorithm model is used to exhaustively enumerate multiple virtual RAID groups. Static analysis does not prioritize speed. Various possible compositions can be calculated using the greedy algorithm and the mathematical model mentioned in this application to obtain the optimal solution.
[0051] Taking a TLC NAND Flash memory as an example, after performing initial characteristic analysis on the NAND Flash (e.g., through experimental P / E cycle testing or sample testing), the following conclusions were drawn: After undergoing the same P / E aging conditions, the probability distributions of UECC occurrences in streams 0 to 5 are roughly consistent. However, the error behavior of multiple consecutive streams with the same stream index (i.e., the same WL index mod 6) shows a high degree of similarity. Further analysis reveals that in a set of 18 consecutive streams, the probability of only one WL experiencing UECC is significantly higher than the probability of two or more WLs experiencing UECC in a set composed of WLs with the same stream index.
[0052] In this implementation example, characteristic analysis shows that for a set consisting of WLs with the same stream index from 18 consecutive streams, the probability of two or more UECCs occurring together is significantly low. Therefore, this set is suitable as an initial RAID group. The following example uses stream index=2, i.e., the initial RAID group's WL2, WL8, WL14, WL20, ..., WL104.
[0053] In another embodiment, the step S500 is followed by: S600: When an unrecoverable error occurs in one of the RAID reserve members in the initial RAID group, the risk assessment of unrecoverable errors in multiple RAID reserve members is repeated; based on the risk assessment results, the initial RAID group is reorganized from multiple RAID reserve members.
[0054] When dynamic performance analysis shows a significant increase in the UECC risk of a member of an initial RAID group, the control chip can reconfigure the initial RAID group composition to avoid including multiple high-risk members in the same initial RAID group. This reconfiguration can be performed in the background and does not affect the host's access interface to the storage device. When a member of an initial RAID group actually experiences UECC, the event itself can be considered a high-weight performance analysis input to update its risk assessment results and dynamically reconfigure the initial RAID group. Through these methods, the probability of successfully recovering data during actual use can be improved, the risk of RAID failure due to multiple unrecoverable errors can be reduced, and the RAID strategy can be dynamically adjusted according to NAND Flash behavior.
[0055] In this embodiment, by analyzing the error bit and UECC behavior of the flash memory device through the static and dynamic characteristics analysis mentioned above, structural units with high failure correlation are identified, and the composition of the RAID group is adjusted accordingly to increase the probability of only a single failure occurring under expected usage conditions, thereby improving the data reconstruction success rate and taking into account both performance and flash memory device utilization efficiency.
[0056] This application also discloses a flash memory device for storing program data, which can be executed to implement the control method of the flash memory device described above.
[0057] This application relates to a reliability improvement technology for data storage systems, particularly to the control chip in non-volatile memory devices such as SSDs, eMMC, and UFS. By analyzing the error behavior and structural characteristics of NAND Flash, the method and mechanism for dynamically determining the composition of RAID groups are described.
[0058] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.
[0059] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.
Claims
1. A control method for a flash memory device, characterized in that, Including the following steps: Obtain hardware information for the flash memory device; According to the independent disk redundancy array assembly rules, the preset storage space of the flash memory device is divided into multiple independent disk redundancy array pre-group members; Perform a risk assessment of unrecoverable errors for multiple independent disk redundant arrays; Based on the risk assessment results, an initial independent disk redundant array group was determined from multiple independent disk redundant array prospective members; Perform read and write operations on business data based on the initial independent disk redundant array group; The initial independent disk redundant array group includes at least N consecutive independent disk redundant array reserve members, where N is a natural number greater than or equal to 2.
2. The control method for a flash memory device according to claim 1, characterized in that, The steps involved in conducting an unrecoverable error risk assessment for multiple independent disk redundant array pre-construction members include: Error behavior analysis is performed on each independent disk redundant array preparatory member, and an error behavior index is generated for each independent disk redundant array preparatory member; The risk of unrecoverable errors occurring when multiple independent RAID candidate members become a virtual independent RAID group is calculated based on the error behavior indicators of each independent RAID candidate member.
3. The control method for a flash memory device according to claim 2, characterized in that, The step of determining the initial independent redundant disk array group from multiple independent redundant disk array prospective members based on the risk assessment results includes: When the risk of unrecoverable errors in n consecutive independent redundant disk array (RBAC) candidate members is the lowest, the n consecutive RBAC candidate members are selected as the initial RBAC group; where n is a natural number greater than or equal to 2.
4. The control method for a flash memory device according to claim 2, characterized in that, The step of calculating the risk of unrecoverable errors occurring when multiple independent disk redundant array (ISA) candidates become a virtual independent disk redundant array group based on the error behavior indicators of each independent disk redundant array candidate includes: Arbitrarily select a consecutive 'a' independent disk redundant array pre-group members as a virtual independent disk redundant array group; where a is a natural number greater than or equal to 2; Based on the error behavior indicators of each standby ... The step of determining the initial independent redundant disk array group from multiple independent redundant disk array prospective members based on the risk assessment results includes: Compare the number of independent disk redundancy array reserve members in multiple candidate groups; The candidate group with the largest number of reserve members for the independent disk redundant array is selected as the initial independent disk redundant array group.
5. The control method for a flash memory device according to claim 1, characterized in that, Following the step of performing read and write operations on business data based on the initial independent redundant disk array group, the method further includes: If an unrecoverable error occurs in one of the standby ... Based on the risk assessment results, the initial independent disk redundant array group was reorganized from multiple independent disk redundant array reserve members.
6. The control method for a flash memory device according to claim 1, characterized in that, The rules for building a redundant independent disk array include: The preset storage space is divided into multiple independent storage units based on the physical structure in the hardware information of the flash memory device; The standby member of the independent disk redundant array includes an independent storage unit.
7. The control method for a flash memory device according to claim 4, characterized in that, The step of dividing the preset storage space of the flash memory device into multiple independent redundant disk array (RBAC) pre-group members according to the independent redundant disk array (RBAC) assembly rules includes: According to the independent disk redundancy array assembly rules, the preset storage space of the flash memory device is divided into multiple logical storage unit groups; wherein, each of the logical storage unit groups includes multiple independent storage units, and each independent storage unit serves as a reserve member of an independent disk redundancy array. The step of arbitrarily selecting a consecutive a independent disk redundant array reserve members as a virtual independent disk redundant array group includes: Within each logical storage unit group, arbitrarily select a consecutive 'a' independent storage units as a virtual independent disk redundant array group, and use a greedy algorithm model to exhaustively enumerate multiple virtual independent disk redundant array groups.
8. The control method for a flash memory device according to claim 7, characterized in that, The preset storage space is divided into multiple independent storage units based on the word line parameters in the hardware information of the flash memory device, where one word line is considered an independent storage unit. When the number of logical memory cell groups is b, word lines with the same remainder after taking the remainder from b are considered as the same logical memory cell group, where b is a natural number greater than or equal to 2. Among them, N consecutive word lines within the same logical storage unit group are used as the initial independent disk redundant array group.
9. The control method for a flash memory device according to claim 4, characterized in that, The error behavior includes the amount of errors that can be corrected by the error correction mechanism during read operations, the trend of the error amount over time or the number of uses, and the frequency at which the error amount approaches the upper limit of the error correction capability.
10. A flash memory device, characterized in that, The flash memory device is used to store program data, which can be executed to implement the control method of the flash memory device according to any one of claims 1 to 9.