Test instruction generation method and device, equipment and storage medium
By generating target instruction test cases, the problem of insufficient test data in chip testing is solved, enabling more efficient and accurate chip verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOPHGO TECH LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-05
AI Technical Summary
Existing chip testing methods suffer from insufficient test data, resulting in inaccurate and incomplete testing, especially in random testing with high repeatability and targeted testing with high time cost and the tendency to miss test points.
By acquiring test requests and instruction parameter modification information, selecting instruction test cases according to the preset instruction test case type library, determining test instruction parameter constraint information according to the test request, adjusting test parameters, and generating target instruction test cases.
It improves the accuracy and flexibility of instruction test cases, and enhances the efficiency and accuracy of chip verification.
Smart Images
Figure CN121979732A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of testing technology, and in particular to a test instruction generation method, apparatus, device, and storage medium. Background Technology
[0002] With the advancement of technology, large language models such as GPT-4 and DeepSeek have been released one after another. The training and inference of large language models have led to an exponential increase in the computing power requirements of devices. Compared with traditional CPUs and GPUs, TPUs (Tensor Processing Units) or NPUs (Neural Network Processing Units) and various AI-specific acceleration chips can provide orders of magnitude advantages in computing power, bandwidth and energy efficiency. Consequently, testing the correctness of chip hardware functions and performance limits is also a very important part. The main purpose of chip function verification is to ensure that the verified chip functions correctly.
[0003] Currently, verification methods include EDA verification, formal verification, emulation verification, and FPGA verification. Chip verification often supports hundreds of custom instructions, dozens of tensor data formats, and multiple mixed-precision modes, thus requiring a large number of test cases for verification testing. These tests can be divided into random testing and targeted testing, depending on the generation method. Random testing has high repeatability but may not fully cover some scenarios, while targeted testing requires significant time investment and is prone to missing test points. Current chip testing suffers from insufficient test data, resulting in inaccurate and incomplete chip testing.
[0004] Therefore, how to generate a large number of test instructions for chip testing is an urgent problem to be solved. Summary of the Invention
[0005] The main objective of this application is to provide a test instruction generation method, apparatus, device, and storage medium, which aims to improve the coverage and accuracy of generated test instructions, thereby improving the efficiency and accuracy of the chip.
[0006] Firstly, this application provides a test instruction generation method, which includes the following steps: Obtain test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; Select instruction test cases from the preset instruction test case type library according to the test request; Based on the test request, determine the test instruction parameter constraint information; Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted to obtain the target instruction test cases.
[0007] Secondly, this application also provides a test instruction generation device, which includes an acquisition module, a selection module, a determination module, and a generation module, wherein: The acquisition module is used to acquire test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; The selection module is used to select instruction test cases from a preset instruction test case type library according to the test request. The preset instruction test case type library is an instruction test case library pre-established based on multiple instruction test case types. The determining module is used to determine the test instruction parameter constraint information based on the test request; The generation module is used to adjust the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases.
[0008] Thirdly, this application also provides a computer device, the computer device including a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the test instruction generation method described above.
[0009] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the test instruction generation method described above.
[0010] This application provides a test instruction generation method, apparatus, device, and storage medium. This application obtains a test request and instruction parameter modification information, which is generated based on parameter updates of the chip under test. It then selects instruction test cases from a preset instruction test case type library according to the test request; determines test instruction parameter constraint information based on the test request; and finally adjusts the test parameters of the instruction test cases according to the test instruction parameter constraint information and instruction parameter modification information, thereby accurately obtaining target instruction test cases. This application determines the test instruction parameter constraint information and instruction parameter modification information through the test request and adjusts the test parameters of the instruction test cases accordingly, accurately obtaining target instruction test cases that meet the requirements. This greatly improves the accuracy of instruction test cases, as well as the flexibility and comprehensiveness of instruction test case configuration, thereby improving the efficiency and accuracy of subsequent chip verification. Attached Figure Description
[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A flowchart illustrating a test instruction generation method provided in an embodiment of this application; Figure 2 A schematic diagram of a scenario for implementing the test instruction generation method provided in this embodiment; Figure 3 A schematic block diagram of a test instruction generation device provided in an embodiment of this application; Figure 4 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.
[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0015] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0016] With the advancement of technology, large language models such as GPT-4 and DeepSeek have been released one after another. The training and inference of large language models have led to an exponential increase in the computing power requirements of devices. Compared with traditional CPUs and GPUs, TPUs (Tensor Processing Units) or NPUs (Neural Network Processing Units) and various AI-specific acceleration chips can provide orders of magnitude advantages in computing power, bandwidth and energy efficiency. Consequently, testing the correctness of chip hardware functions and performance limits is also a very important part. The main purpose of chip function verification is to ensure that the verified chip functions correctly.
[0017] Currently, verification methods include EDA verification, formal verification, emulation verification, and FPGA verification. Chip verification often supports hundreds of custom instructions, dozens of tensor data formats, and multiple mixed-precision modes, thus requiring a large number of test cases for verification testing. These tests can be divided into random testing and targeted testing, depending on the generation method. Random testing has high repeatability but may not fully cover some scenarios, while targeted testing requires significant time investment and is prone to missing test points. Current chip testing suffers from insufficient test data, resulting in inaccurate and incomplete chip testing.
[0018] To address the aforementioned problems, embodiments of this application provide a test instruction generation method, apparatus, device, and storage medium. The test instruction generation method includes acquiring a test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; selecting instruction test cases from a preset instruction test case type library according to the test request; determining test instruction parameter constraint information according to the test request; and adjusting the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain target instruction test cases.
[0019] The test instruction generation method can be applied to computer devices, such as mobile phones, tablets, laptops, desktop computers, personal digital assistants, and wearable devices.
[0020] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0021] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a test instruction generation method provided in an embodiment of this application.
[0022] like Figure 1 As shown, the test instruction generation method includes steps S101 to S104.
[0023] Step S101: Obtain test request and instruction parameter modification information, wherein the instruction parameter modification information is generated based on the parameter update of the chip under test.
[0024] The test request is a test instruction generation request issued by staff to perform functional verification on the chip under test. The chip under test includes, but is not limited to, TPU (Tensor Processing Unit) and NPU (Neural Network Processing Unit). The instruction parameter modification information is generated based on the parameter updates of the chip under test.
[0025] In some embodiments, a test request is generated in response to a worker clicking the chip verification button on a computer device. This timely generation of the test request upon the worker clicking the chip verification button effectively improves the efficiency of chip verification.
[0026] In some embodiments, a test request is generated when the chip is updated. By generating test requests promptly when the chip is updated, the efficiency of chip verification can be effectively improved.
[0027] In some embodiments, parameter update information of the chip under test is acquired and parsed to obtain parameter change category information. Based on the parameter change category information, corresponding instruction parameter modification information is matched from a preset instruction parameter modification information library. The parameter change category information includes at least one of addition, modification, and deletion categories. The preset instruction parameter modification information library is a pre-established library of instruction parameter modification information based on the parameter change category information. Through this preset instruction parameter modification information library, instruction parameter modification information can be accurately matched.
[0028] It should be noted that this parameter update information refers to the chip update information of the chip under test. The "Add" category is for generating new instruction types and extended parameters; the "Modify" category is for updating the original parameters, which includes, but is not limited to, value ranges and instruction dependencies; the "Delete" category includes the deletion of parameter items.
[0029] Step S102: Select instruction test cases from the preset instruction test case type library according to the test request.
[0030] The pre-defined instruction test case type library includes multiple test instruction types, each containing multiple instruction test cases. These instruction types include convolution operation types, matrix multiplication types, arithmetic operation types, vector operation types, and system class types, among others. The convolution operation type includes test cases for fixed-point, floating-point, and deconvolution operations. The matrix multiplication type includes test cases for matrix multiplication, matrix transpose, and block partitioning operations. The vector operation type includes test cases for scalar addition, subtraction, multiplication, division, transcendental functions, and data conversion operations. The system class type includes test cases for system execution instructions.
[0031] In some embodiments, test cases of convolution operation type, matrix multiplication type, arithmetic operation type, vector operation type, and system class type are obtained, and an instruction test case type library is constructed based on the test cases of convolution operation type, matrix multiplication type, arithmetic operation type, vector operation type, and system class type. By constructing an instruction test case type library, the efficiency and accuracy of generating test instructions can be effectively improved.
[0032] In some embodiments, the test instruction type is determined based on the test request; instruction tests are then selected from a preset instruction test case type library based on the test instruction type to obtain instruction test cases. By determining the test instruction type and accurately selecting instruction test cases from the preset instruction test case type library based on the test instruction type, the efficiency and accuracy of test instruction generation are greatly improved.
[0033] In some embodiments, determining the test instruction type based on a test request can be achieved by: parsing the test request to obtain test instruction keywords, acquiring a preset mapping table between test instruction keywords and test instruction types, and querying the test instruction type matching the test instruction keyword from the mapping table. This mapping table is pre-established based on the test instruction keywords and test instruction types, and can be established according to actual circumstances; this embodiment does not specifically limit its implementation. This mapping table allows for accurate determination of the test instruction type, significantly improving the efficiency and accuracy of test instruction generation.
[0034] Step S103: Determine the test instruction parameter constraint information according to the test request.
[0035] The test instruction parameter constraint information includes test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and parameter constraints.
[0036] In some embodiments, the test case generation mode constraints include a random generation mode, a hybrid generation mode, and a targeted generation mode. The random generation mode indicates that all parameters are generated completely randomly, and the instruction test cases generated by this mode are used for testing the correctness of the chip's functionalities. The hybrid generation mode indicates that specified parameters are fixed parameter data and other unspecified parameters are randomly generated; the instruction test cases generated by this mode are used for stress and compatibility testing of the chip. The targeted generation mode indicates that all parameters are generated according to preset constraints; the instruction test cases generated by this mode are used for boundary condition testing of the chip.
[0037] In some embodiments, compatibility constraints limit the precision of input and output data for operation types, and these compatibility constraints are used to test the computational operation precision of the chip. Computational storage constraints constrain the data storage format for reading and writing data during computation, and these computational storage constraints are used to test the matching between the chip's storage format and computational units. Address constraints constrain the addresses of operation parameters. Parameter constraints are used to constrain fixed parameters.
[0038] In some embodiments, the test instruction parameter constraint information further includes test instruction constraint check information, which is used to check the generated test instruction parameters. If an erroneous parameter is detected, a test instruction error detection report is output.
[0039] In some embodiments, the test request is parsed to obtain parameter definition information for instructing the generation of test instructions; a preset mapping table between test instruction parameter constraint information and parameter definition information is obtained, and test instruction parameter constraint information matching the parameter definition information is queried from the mapping table; wherein, the test instruction parameter constraint information includes test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and parameter constraints. The mapping table is pre-established based on the test instruction parameter constraint information and parameter definition information, and can be established according to actual conditions; this embodiment does not specifically limit this. By parsing the test request and querying the mapping table for test instruction parameter constraint information matching the parameter definition information, the efficiency and accuracy of test instruction generation are greatly improved.
[0040] It should be noted that this parameter definition information is used to characterize the chip testing functions, such as convolution function testing, system class compatibility testing, and matrix operation boundary testing, etc.
[0041] Step S104: Adjust the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases.
[0042] The target instruction test case is used for the functional testing of the chip.
[0043] In some embodiments, the test instruction parameter constraint information is modified according to the instruction parameter modification information to obtain the target test instruction parameter constraint information; the test parameters of the instruction test cases are adjusted according to the target test instruction parameter constraint information to obtain the target instruction test cases. By adjusting the test parameters of the instruction test cases using the target test instruction parameter constraint information, the target instruction test cases used for functional testing can be accurately obtained.
[0044] In some embodiments, the method for modifying the test instruction parameter constraint information based on instruction parameter modification information to obtain the target test instruction parameter constraint information can be as follows: Modify the test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and / or parameter constraints in the test instruction parameter constraint information according to the modification item parameters corresponding to at least one of the added category, modified category, and deleted category included in the instruction parameter modification information, thereby obtaining the target test instruction parameter constraint information. Modifying the test instruction parameter constraint information using this instruction parameter modification information allows for timely updates of test instruction case parameters based on chip updates, effectively improving the efficiency and accuracy of chip testing.
[0045] In some embodiments, the method of adjusting the test parameters of instruction test cases according to the target test instruction parameter constraint information to obtain target instruction test cases can be as follows: Adjust the matching parameters in the instruction test cases according to the target test instruction parameter constraint information to obtain target instruction test cases with updated parameters. By adjusting the matching parameters in the instruction test cases, target instruction test cases with updated parameters can be accurately obtained, greatly improving the accuracy and targeted nature of chip testing.
[0046] In some embodiments, based on test instruction parameter constraint information and instruction parameter modification information, the test parameters of the instruction test cases are adjusted multiple times to obtain multiple candidate instruction test cases. These multiple candidate instruction test cases are then concatenated to obtain the target instruction test case. By concatenating the candidate instruction test cases, the generated target instruction test case comprises a test instruction string composed of multiple instruction test cases, which can effectively improve the efficiency of chip testing.
[0047] In some embodiments, the parameter value range of the target instruction test case is obtained, and the parameter value range required for testing the chip under test is also obtained. Based on the parameter value range and the required parameter value range, the test parameter coverage is determined. If the test parameter coverage is less than or equal to a preset test parameter coverage, the uncovered parameter value range is output. The preset test parameter coverage can be set according to actual conditions, and this embodiment does not specifically limit it; for example, the preset test parameter coverage can be set to 80%. Verifying the test parameter coverage can effectively improve the chip's efficiency and accuracy; and outputting the uncovered parameter value range can effectively improve the accuracy of parameter adjustments in the instruction test case.
[0048] For example, such as Figure 2 As shown, Figure 2The test instruction generation platform 10 includes various components and a chip 20. The test instruction generation platform 10 includes an instruction test case type library 11, a test instruction parameter constraint component 12, a parameter update component 13, a test instruction splicing component 14, and a coverage verification component 15. The test instruction generation platform 10 receives a test request 31. The test instruction parameter constraint component 12 determines the test instruction parameter constraint information based on the test request. The instruction test case type library 11 selects instruction test cases based on the test request. The parameter update component 13 receives the chip's parameter update information and parses it to obtain parameter change category information. Based on the parameter change category information, it matches the corresponding instruction parameter modification information from a preset instruction parameter modification information library. The test instruction parameter constraint component 12 modifies the test instruction parameter constraint information according to the instruction parameter modification information to obtain the target test instruction parameter constraint information. Finally, it tests the instruction test cases based on the target test instruction parameter constraint information. Parameter adjustment yields the target instruction test case; the target instruction test case is transmitted to chip 20; chip 20 performs chip testing based on the target instruction test case; the test instruction splicing component 14 can adjust the test parameters of the instruction test case multiple times to obtain multiple candidate instruction test cases, and splice the multiple candidate instruction test cases to obtain the target instruction test case; the coverage verification component 15 obtains the parameter value range of the target instruction test case and the parameter value range required for testing the chip under test; based on the parameter value range and the required parameter value range, the test parameter coverage is determined; if the test parameter coverage is less than or equal to the preset test parameter coverage, the uncovered parameter value range is output.
[0049] The test instruction generation method provided in the above embodiments obtains test requests and instruction parameter modification information, which is generated based on parameter updates of the chip under test; selects instruction test cases from a preset instruction test case type library according to the test request; determines test instruction parameter constraint information according to the test request; and then adjusts the test parameters of the instruction test cases according to the test instruction parameter constraint information and instruction parameter modification information, thereby accurately obtaining target instruction test cases. This application determines test instruction parameter constraint information and instruction parameter modification information through test requests and adjusts the test parameters of instruction test cases accordingly, accurately obtaining target instruction test cases that meet the requirements. This greatly improves the accuracy of instruction test cases, as well as the flexibility and comprehensiveness of instruction test case configuration, thereby improving the efficiency and accuracy of subsequent chip verification.
[0050] Please see Figure 3 , Figure 3 A schematic block diagram of a test instruction generation device provided in an embodiment of this application.
[0051] like Figure 3 As shown, the test instruction generation device 200 includes an acquisition module 210, a selection module 220, a determination module 230, and a generation module 240, wherein: The acquisition module 210 is used to acquire test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; The selection module 220 is used to select instruction test cases from a preset instruction test case type library according to the test request. The preset instruction test case type library is an instruction test case library that is pre-established based on multiple instruction test case types. The determining module 230 is used to determine test instruction parameter constraint information based on the test request; The generation module 240 is used to adjust the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases.
[0052] In some embodiments, the determining module 230 is further configured to: The test request is parsed to obtain parameter definition information that indicates the generation of test instructions; Obtain a mapping table between preset test instruction parameter constraint information and parameter definition information, and query the test instruction parameter constraint information that matches the parameter definition information from the mapping table; The test instruction parameter constraint information includes test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and parameter constraints.
[0053] In some embodiments, the acquisition module 210 is further configured to: Obtain the parameter update information of the chip under test, and parse the parameter update information to obtain parameter change category information; Based on the parameter change category information, the corresponding instruction parameter modification information is matched from the preset instruction parameter modification information database.
[0054] In some embodiments, the selection module 220 is further configured to: Based on the test request, determine the test instruction type; Based on the test instruction type, an instruction test case is obtained by selecting an instruction from the preset instruction test case type library.
[0055] In some embodiments, the generation module 240 is further configured to: The test instruction parameter constraint information is modified according to the instruction parameter modification information to obtain the target test instruction parameter constraint information; The test parameters of the instruction test cases are adjusted according to the target test instruction parameter constraint information to obtain the target instruction test cases.
[0056] In some embodiments, the generation module 240 is further configured to: Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted multiple times to obtain multiple candidate instruction test cases; Multiple candidate instruction test cases are concatenated to obtain the target instruction test case.
[0057] In some embodiments, the test instruction generation device 200 is further configured to: Obtain the parameter value range of the target instruction test case, and obtain the parameter value range required for testing the chip under test; The test parameter coverage rate is determined based on the parameter value range and the required parameter value range for the test. If the test parameter coverage is less than or equal to the preset test parameter coverage, output the range of values for the uncovered parameters.
[0058] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the above-mentioned test instruction generation device can be referred to the corresponding process in the aforementioned test instruction generation method embodiment, and will not be repeated here.
[0059] Please see Figure 4 , Figure 4 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.
[0060] like Figure 4 As shown, the computer device 300 includes a processor 302 and a memory 303 connected via a system bus 301, wherein the memory 303 may include a storage medium and internal memory.
[0061] The storage medium may store a computer program. This computer program includes program instructions that, when executed, cause the processor to perform any method of test instruction generation.
[0062] The processor 302 provides computing and control capabilities to support the operation of the entire computer device.
[0063] Internal memory provides an environment for the execution of computer programs stored in the storage medium. When the computer program is executed by the processor, it enables the processor to execute any test instruction generation method.
[0064] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0065] It should be understood that processor 302 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, the general-purpose processor can be a microprocessor or any conventional processor.
[0066] In one embodiment, the processor 302 is configured to run a computer program stored in a memory to perform the following steps: Obtain test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; Select instruction test cases from the preset instruction test case type library according to the test request; Based on the test request, determine the test instruction parameter constraint information; Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted to obtain the target instruction test cases.
[0067] In one embodiment, when the processor 302 determines the test instruction parameter constraint information according to the test request, it is configured to: The test request is parsed to obtain parameter definition information that indicates the generation of test instructions; Obtain a mapping table between preset test instruction parameter constraint information and parameter definition information, and query the test instruction parameter constraint information that matches the parameter definition information from the mapping table; The test instruction parameter constraint information includes test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and parameter constraints.
[0068] In one embodiment, when the processor 302 acquires instruction parameter modification information, it is used to: Obtain the parameter update information of the chip under test, and parse the parameter update information to obtain parameter change category information; Based on the parameter change category information, the corresponding instruction parameter modification information is matched from the preset instruction parameter modification information database.
[0069] In one embodiment, when the processor 302 selects instruction test cases from a preset instruction test case type library according to the test request, it is configured to: Based on the test request, determine the test instruction type; Based on the test instruction type, an instruction test case is obtained by selecting an instruction from the preset instruction test case type library.
[0070] In one embodiment, when the processor 302 adjusts the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases, it is configured to: The test instruction parameter constraint information is modified according to the instruction parameter modification information to obtain the target test instruction parameter constraint information; The test parameters of the instruction test cases are adjusted according to the target test instruction parameter constraint information to obtain the target instruction test cases.
[0071] In one embodiment, when the processor 302 adjusts the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases, it is configured to: Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted multiple times to obtain multiple candidate instruction test cases; Multiple candidate instruction test cases are concatenated to obtain the target instruction test case.
[0072] In one embodiment, the processor 302 is further configured to implement: Obtain the parameter value range of the target instruction test case, and obtain the parameter value range required for testing the chip under test; The test parameter coverage rate is determined based on the parameter value range and the required parameter value range for the test. If the test parameter coverage is less than or equal to the preset test parameter coverage, output the range of values for the uncovered parameters. It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the above description of the specific working process of the computer device can be referred to the corresponding process in the aforementioned test instruction generation method embodiment, and will not be repeated here.
[0073] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, and the method implemented when the program instructions are executed can refer to various embodiments of the test instruction generation method of this application.
[0074] The computer-readable storage medium can be an internal storage unit of the computer device described in the foregoing embodiments, such as a hard disk or memory of the computer device. The computer-readable storage medium can be non-volatile or volatile. Alternatively, the computer-readable storage medium can be an external storage device of the computer device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.
[0075] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms.
[0076] It should also be understood that the term "and / or" as used in this specification refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0077] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.
Claims
1. A method for generating test instructions, characterized in that, include: Obtain test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; Select instruction test cases from the preset instruction test case type library according to the test request; Based on the test request, determine the test instruction parameter constraint information; Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted to obtain the target instruction test cases.
2. The test instruction generation method as described in claim 1, characterized in that, The step of determining the test instruction parameter constraint information based on the test request includes: The test request is parsed to obtain parameter definition information that indicates the generation of test instructions; Obtain a mapping table between preset test instruction parameter constraint information and parameter definition information, and query the test instruction parameter constraint information that matches the parameter definition information from the mapping table; The test instruction parameter constraint information includes test case generation mode constraints, compatibility constraints, computation and storage constraints, address constraints, and parameter constraints.
3. The test instruction generation method as described in claim 1, characterized in that, Retrieve command parameter modification information, including: Obtain the parameter update information of the chip under test, and parse the parameter update information to obtain parameter change category information; Based on the parameter change category information, the corresponding instruction parameter modification information is matched from the preset instruction parameter modification information database.
4. The test instruction generation method as described in claim 1, characterized in that, The step of selecting instruction test cases from a preset instruction test case type library according to the test request includes: Based on the test request, determine the test instruction type; Based on the test instruction type, an instruction test case is obtained by selecting an instruction from the preset instruction test case type library.
5. The test instruction generation method as described in claim 1, characterized in that, The step of adjusting the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases includes: The test instruction parameter constraint information is modified according to the instruction parameter modification information to obtain the target test instruction parameter constraint information; The test parameters of the instruction test cases are adjusted according to the target test instruction parameter constraint information to obtain the target instruction test cases.
6. The test instruction generation method as described in claim 5, characterized in that, The step of adjusting the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases includes: Based on the test instruction parameter constraint information and the instruction parameter modification information, the test parameters of the instruction test cases are adjusted multiple times to obtain multiple candidate instruction test cases; Multiple candidate instruction test cases are concatenated to obtain the target instruction test case.
7. The test instruction generation method according to any one of claims 1-6, characterized in that, The method further includes: Obtain the parameter value range of the target instruction test case, and obtain the parameter value range required for testing the chip under test; The test parameter coverage rate is determined based on the parameter value range and the required parameter value range for the test. If the test parameter coverage is less than or equal to the preset test parameter coverage, output the range of values for the uncovered parameters.
8. A test instruction generation device, characterized in that, The test instruction generation device includes an acquisition module, a selection module, a determination module, and a generation module, wherein: The acquisition module is used to acquire test requests and instruction parameter modification information, wherein the instruction parameter modification information is generated based on parameter updates of the chip under test; The selection module is used to select instruction test cases from a preset instruction test case type library according to the test request. The preset instruction test case type library is an instruction test case library pre-established based on multiple instruction test case types. The determining module is used to determine the test instruction parameter constraint information based on the test request; The generation module is used to adjust the test parameters of the instruction test cases according to the test instruction parameter constraint information and the instruction parameter modification information to obtain the target instruction test cases.
9. A computer device, characterized in that, The computer device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the test instruction generation method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the test instruction generation method as described in any one of claims 1 to 7.