Asynchronous multi-modal electrochemical detection method and multi-channel potentiostat system

Abstract

The application relates to the field of electrochemical detection, and discloses an asynchronous multi-modal electrochemical detection method and a multi-channel constant potential instrument system. The system comprises an upper computer and a lower computer. The lower computer comprises a multi-task scheduling kernel and a plurality of detection channels. The detection method comprises the following steps: S1, the upper computer receives independent configuration instructions for N detection channels and sends the instructions to the lower computer, wherein the independent configuration instructions corresponding to the detection channels are independent of each other; S2, the lower computer analyzes the independent configuration instructions based on the multi-task scheduling kernel and configures the working modes of the detection channels respectively; S3, in response to a start instruction, the lower computer reads current data of the plurality of detection channels in parallel; during the reading process, the lower computer executes real-time range adjustment based on the multi-task scheduling kernel, adjusts the gain parameters of the corresponding channels, and reacquires; and S4, the lower computer returns the current data to the upper computer for processing. The application makes the configuration and execution of the detection channels independent of each other, and realizes continuous detection of the multi-channel parallel.

Description

Technical Field

[0001] This application relates to the field of electrochemical detection, and in particular to an asynchronous multimodal electrochemical detection method and a multichannel potentiostat system. Background Technology

[0002] With the widespread application of electrochemical sensing technology in environmental monitoring, biomedicine, and other fields, the demand for multi-channel, high-precision, real-time parallel electrochemical detection systems is increasing. An ideal modern multi-channel potentiostat system not only needs to support independent detection method configurations for multiple channels, but also must have extremely high real-time response capabilities during data acquisition.

[0003] However, upon examining existing multi-channel electrochemical detection schemes, the following technical shortcomings are commonly found: First, in terms of multi-channel independent configuration and real-time scheduling, there is a disconnect between the application-layer RTOS scheduling and the detection-layer state machine logic. Although real-time operating systems (RTOS) have been introduced into this field—for example, utility model patent CN201107295Y discloses a portable dual-channel electrochemical analysis device that uses the ThreadX real-time operating system to manage peripherals such as USB, SD card, LAN network, and LCD display—the RTOS in this solution only operates at the peripheral driver and communication scheduling level. Its dual-channel detection logic (such as CV, DPV, and other method steps) essentially still relies on fixed hardware circuit mappings and predefined scripts. When faced with N channels needing to execute different electrochemical methods completely independently and in real-time, existing technologies lack a coordinated architecture of channel configuration instructions, RTOS dynamic task instantiation, and hardware execution. Task blocking or timing jitter still exists, failing to achieve true decoupling of multi-channel concurrent execution.

[0004] Secondly, there is a bottleneck in the underlying bus for data concurrency throughput. To increase the number of channels, existing technologies mostly rely on external hosts for multi-channel configuration and reading. For example, a known modular multi-channel potentiostat system uses a Raspberry Pi with an I2C multiplexer to read up to 64 channels in a time-division multiplexing manner. This purely software-interventional, bus-polling-based architecture is highly susceptible to data loss or timing jitter due to I2C bus bandwidth contention during concurrent acquisition, and cannot meet the high throughput requirements of independent parallel reading at the hardware level.

[0005] Third, in multi-channel concurrent scenarios, dynamic range adjustment and continuous data acquisition present a difficult-to-balance timing and signal integrity conflict. Some solutions attempt to support multi-channel range switching. For example, patent publication number CN119198874A discloses a portable electro-hydraulic workstation that uses the main processor's GPIO to control an analog switch module to switch resistors of different values ​​in the operational amplifier circuit to achieve measurements with different sensitivities. However, a closer analysis of its range control logic reveals that its range switching is a static pre-configuration (i.e., performed before or during acquisition). In traditional microcontroller control architectures, dynamic range adjustment (switching analog switches and operational amplifier setup) requires a certain hardware stabilization time. If range switching is forcibly performed within the continuous clock cycle of multi-channel high-concurrency ADC reading, it will not only introduce severe switching transient noise (crosstalk to other parallel channels) but also cause ADC sampling timing conflicts and data errors. Therefore, existing technologies can only compromise between pausing concurrent acquisition to switch ranges and maintaining concurrent acquisition with a fixed range. In a continuous data stream with multiple channels reading concurrently, it is difficult to achieve seamless and interference-free adjustment of the real-time dynamic range.

[0006] Fourth, some distributed solutions sacrifice system compactness and global coordination capabilities. For example, Taiwan Patent Publication No. TW202212820A uses an architecture with multiple independent electrode connectors and a remote controller, with each connector having its own processor for local calculations. While this approach alleviates the pressure on central control, it results in high system costs, bloated size, and isolated data islands for each connector, losing the possibility of real-time global coordination at the central node (such as dynamic range synchronization adjustment across channels).

[0007] In summary, existing technologies fail to provide an architecture that deeply integrates hardware-level parallel reading with real-time dynamic range adjustment during acquisition. There is an inherent conflict between the hardware settling time required for dynamic range adjustment and the hardware timing of multi-channel continuous acquisition. If range switching is performed within a concurrent acquisition cycle, it introduces switching transient noise and interferes with other channels; if acquisition is paused for adjustment, the continuity of the data stream is disrupted. Therefore, a novel electrochemical detection scheme is urgently needed to overcome these architectural barriers. Summary of the Invention

[0008] To overcome the above-mentioned technical problems, this application provides an asynchronous multimodal electrochemical detection method and a multichannel potentiostat system.

[0009] Firstly, the asynchronous multimodal electrochemical detection method provided in this application adopts the following technical solution: An asynchronous multimodal electrochemical detection method is applied to a multichannel potentiostat system. The multichannel potentiostat system includes a host computer and a slave computer that communicate with each other. The slave computer includes a main control module and an analog channel array. The main control module includes a multi-task scheduling kernel, and the analog channel array includes multiple detection channels. The asynchronous multimodal electrochemical detection method includes the following steps: S1, the host computer receives independent configuration instructions for N detection channels and sends the independent configuration instructions to the slave computer. The independent configuration instructions for each detection channel are independent of each other and are used to set the asynchronous multimodal electrochemical detection method and corresponding parameters for the corresponding channel. N is an integer greater than 1. S2. The lower-level machine parses the independent configuration instruction based on the multi-task scheduling kernel and independently configures the working mode of the multiple detection channels; S3. After configuration, in response to the start instruction, the lower-level machine reads the current data of the multiple detection channels in parallel through the hardware-level data transmission channel; during the reading process, the lower-level machine performs real-time range adjustment based on the multi-task scheduling kernel: it determines whether the current data exceeds the preset safety range. If it exceeds the upper limit, it reduces the gain parameter of the corresponding channel; if it is below the lower limit, it increases the gain parameter of the corresponding channel, and re-acquires based on the adjusted gain parameter; S4. The lower-level machine sends the current data back to the upper-level machine for display and processing.

[0010] By adopting the above technical solution, this application constructs a linked architecture of independent configuration instructions, multi-task scheduling kernel parsing, hardware-level parallel reading, and real-time range adjustment, decoupling the detection logic during multi-channel concurrent execution. The hardware-level data transmission channel eliminates the bus bandwidth bottleneck and timing jitter caused by traditional software polling, ensuring the integrity of the data stream under high concurrency in multi-channel conditions. At the same time, the continuous reading and real-time range adjustment mechanism based on the multi-task scheduling kernel breaks the timing conflict between traditional static range switching and concurrent acquisition, enabling the system to achieve real-time dynamic range adjustment of the target channel without interrupting the data stream of other channels or causing crosstalk between channels, thereby achieving wide-range, high-concurrency continuous electrochemical detection.

[0011] Preferably, before executing step S1, the method further includes a system wake-up step: the multi-channel potentiostat system further includes a hardware monitoring module and a modular adapter, and the lower-level machine further includes a sensor interface module; in low-power standby mode, the hardware monitoring module monitors the electrical characteristic changes of the sensor interface module; when the conductive terminal of the modular adapter is connected to the sensor interface module, the electrical characteristic change is triggered, and the hardware monitoring module triggers a hardware interrupt of the main control module to wake up the lower-level machine; wherein, the modular adapter includes a substrate, a connector disposed at one end of the substrate for adapting to a micro sensor, a conductive terminal disposed at the other end of the substrate for being clamped by an external clamping terminal, and a micro cell formed on the substrate and located at the connector for containing electrolyte.

[0012] By adopting the above technical solutions, the detection system achieves plug-and-play functionality and low-power standby. Replacing software polling with hardware-level electrical characteristic monitoring reduces power consumption in standby mode. The accompanying modular adapters not only facilitate rapid electrical connection of the micro-sensors, but their integrated micro-cells also provide a standardized, current-limiting microenvironment for adding trace amounts of electrolyte, improving the ease of operation and sample utilization in on-site testing.

[0013] Preferably, the main control module runs a real-time operating system and creates and schedules multiple tasks with different priorities through the multi-task scheduling kernel. The multiple tasks include at least an acquisition task, a processing task, and a communication task. The acquisition task is configured with the highest priority and is used to perform data reading and real-time range adjustment in step S3. The processing task is used to parse the independent configuration instruction and configure the working mode. The communication task is used to perform data backhaul in step S4.

[0014] By adopting the above technical solution, a real-time scheduling strategy centered on ensuring the timing accuracy of the underlying hardware was established. Data acquisition tasks involving reading and range adjustment were set as the highest priority, effectively preventing the underlying electrochemical hardware operations from being blocked by time-consuming tasks such as communication or processing / analysis. This also mitigated the potential system scheduling delays and data loss risks that might occur when multiple channels independently execute different methods.

[0015] Preferably, after the acquisition task completes a parallel reading of the current data of the multiple detection channels, if it is determined that the current data of a certain channel exceeds the safe range, a corresponding range adjustment command is generated; the execution of the corresponding range adjustment command and the update configuration of the corresponding channel gain parameter are both completed within the interval time when the hardware-level data transmission channel performs the next parallel reading operation.

[0016] By adopting the above technical solution, the execution of the range adjustment command and parameter configuration are limited to the time interval between two adjacent parallel reading operations. This ensures from the underlying timing dimension that the range adjustment process will not occupy or block the normal, periodic concurrent data acquisition stream, thus achieving "uninterrupted" adjustment. This solves the timing conflict problem in the existing technology where dynamic range adjustment and high-concurrency continuous data acquisition are difficult to balance, and provides a deterministic timing implementation scheme for the system to achieve dynamic range switching in high-throughput scenarios.

[0017] Preferably, the hardware-level data transmission channel includes a first direct memory access channel and a second direct memory access channel integrated into the main control module; the first direct memory access channel is used to read data from the analog channel array, and the second direct memory access channel is used to send data to the host computer.

[0018] By adopting the above technical solution, a high-speed data transfer channel that does not require frequent intervention from the microcontroller's CPU core was constructed. The first and second direct memory access channels separate the transmission and reception of underlying data, effectively freeing up the microcontroller's computing resources, allowing it to focus on executing multi-task scheduling and real-time range algorithms, thereby supporting large-scale, high-throughput data acquisition across more channels.

[0019] Preferably, the asynchronous multimodal electrochemical detection method includes a first type of method that requires high-speed potential scanning and a second type of method that does not require high-speed potential scanning; during the execution of step S3, the lower-level machine configures the upper limit of the number of channels that synchronously execute the second type of method to N, and configures the upper limit of the number of channels that synchronously execute the first type of method to a maximum of M, where M is less than N.

[0020] By adopting the above technical solution, a dynamic load balancing mechanism that balances hardware resources and detection requirements was established. Based on the scanning speed characteristics of the electrochemical method, the system's upper limit was allocated, and the bus bandwidth and computational load were reasonably constrained. This reduced the risk of system overload and crashes due to excessive distribution of high-speed, high-frequency detection tasks, ensuring operational stability under extreme concurrent conditions.

[0021] Preferably, during the execution of step S3, for channels that synchronously execute the first type of method, the lower-level machine controls the corresponding detection channel to output an excitation waveform at a first frequency and to collect the current data at a second frequency; for channels that synchronously execute the second type of method, the lower-level machine controls the corresponding detection channel to output an excitation waveform at a third frequency and to collect the current data at a fourth frequency; wherein, the first frequency is greater than the third frequency, and the second frequency is greater than the fourth frequency.

[0022] By adopting the above technical solution, time-series resource optimization for different electrochemical signal characteristics was achieved. Matching excitation and sampling frequencies were allocated to high-speed and non-high-speed methods, ensuring the integrity of high-speed scanning signals and the ability to capture transient features while suppressing redundant data generated by low-speed methods, further optimizing the overall communication bandwidth and storage efficiency of the system.

[0023] Secondly, the multi-channel potentiostat system provided in this application adopts the following technical solution: A multi-channel potentiostat system includes: a host computer; a slave computer including a main control module and an analog channel array connected to the main control module, the main control module being configured to perform the method as described in any of the first aspects above; and a sensor interface module connected to the analog channel array for accessing micro sensors.

[0024] By adopting the above technical solution, the aforementioned hardware and software collaborative detection method is materialized into a highly integrated hardware device. Compared with independent distributed processing nodes, this architecture maintains a compact system physical size and controllable manufacturing costs while retaining the main control module's ability to perform global synchronization and concurrent control of all channels, overcoming the data silos and collaborative lag defects of traditional distributed nodes.

[0025] Preferably, the main control module includes a microcontroller, and the analog channel array includes at least two analog front-end chips. The microcontroller is connected to the at least two analog front-end chips through a shared data bus and an independent chip select channel.

[0026] By adopting the above technical solution, the pin occupancy rate of the microcontroller is effectively controlled while ensuring independent operation of multiple channels at the hardware level. Independent chip select channels ensure high-speed addressing and deterministic response of each analog front-end chip, while the shared data bus simplifies the hardware wiring topology of the motherboard, providing a cost-effective hardware foundation for the smooth expansion of the potentiostat to dozens or even hundreds of channels.

[0027] Preferably, the system further includes a modular adapter, comprising: a substrate; a connector disposed at one end of the substrate for adapting to and electrically contacting a microsensor; a conductive terminal disposed at the other end of the substrate, the conductive terminal being electrically connected to the connector via the interior of the substrate, the conductive terminal being configured to provide an electrical contact surface for clamping by an external clamping terminal to connect to the sensor interface module via the external clamping terminal; and a microcell formed on the substrate and located at the connector for containing an electrolyte to allow the electrolyte to contact the microsensor.

[0028] By adopting the above technical solution, an integrated consumable solution is provided that balances compatibility with traditional test fixtures and testing of microscopic samples. The conductive terminals provide a reliable electrical contact surface for large-sized test terminals such as traditional alligator clips in the laboratory, and the connectors are securely adapted to miniature sensors, improving the versatility of the potentiostat in various application scenarios such as high-throughput screening in the laboratory and portable rapid testing in the field outdoors.

[0029] In summary, this application includes at least one of the following beneficial technical effects: 1. Overcoming the timing conflict between multi-channel concurrency and dynamic range: A linked architecture of independent instruction configuration, multi-task scheduling kernel, and hardware-level parallel reading was constructed, achieving decoupling of multi-channel tasks. The hardware-level dual DMA path eliminates the bus reading bottleneck, enabling the system to perform real-time range adjustment by the multi-task kernel without interrupting the continuous data stream or causing transient crosstalk, thus balancing high concurrency throughput and wide range detection accuracy; 2. High integration and global collaborative control: It abandons the costly and data-fragmented distributed processing architecture. Through a hardware array design with a shared data bus and independent chip select channels, a highly compact single main control module can perform global parallel collaboration on N channels, reducing the size of the device and the hardware cost of multi-channel expansion. 3. Excellent anti-interference capability and system stability: At the physical level, deep isolation between digital and analog power rails is adopted to suppress the interference of high-frequency digital noise on weak electrochemical signals; at the logical level, through reasonable division of multi-task priorities and upper limit constraints on the number of concurrent tasks in high- and low-speed methods, the underlying timing accuracy and operational stability of the system under large-scale high-concurrency conditions are guaranteed. 4. Enhanced test versatility and ease of operation: The modular adapter design integrates connectors, conductive terminals, and miniature cells, making it compatible with traditional large-size fixtures and new miniature sensors. Combined with the plug-and-play wake-up mechanism of the hardware interface, it achieves low standby power consumption and plug-and-play functionality, optimizing the sample processing flow for on-site testing. Attached Figure Description

[0030] Figure 1 This is a block diagram of the overall architecture of the multichannel potentiostat system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the hardware architecture of the lower-level machine provided in the embodiments of this application; Figure 3 This is a circuit diagram of the lower-level machine regarding the main control module provided in an embodiment of this application; Figure 4 This is a circuit diagram of the power management module of the lower-level machine provided in an embodiment of this application; Figure 5 This is a circuit diagram of the communication interface module of the lower-level machine provided in an embodiment of this application; Figure 6 This is a schematic diagram of the modular adapter provided in the embodiments of this application; Figure 7 This is a flowchart of the asynchronous multimodal electrochemical detection method provided in the embodiments of this application; Figure 8 This is an operation flowchart of the lower-level machine software provided in the embodiments of this application; Figure 9 This is a functional architecture diagram of the host computer software system provided in the embodiments of this application; Figure 10 This is an operation flowchart of the host computer software provided in the embodiments of this application.

[0031] Explanation of reference numerals in the attached figures: 10. Host computer; 20. Sub-computer; 21. Main control module; 22. Analog channel array; 23. Sensor interface module; 24. Communication interface module; 25. Power management module; 26. Battery; 27. Power detection circuit; 30. Modular adapter; 31. Base plate; 32. Connector; 33. Conductive terminal; 34. Miniature cell; 40. Hardware monitoring module; 50. Miniature sensor. Detailed Implementation

[0032] The following is in conjunction with the appendix Figure 1-10 This application will be described in further detail.

[0033] It should be noted that in the description of this application, the following abbreviations have the following meanings: MCU (Microcontroller Unit), AFE (Analog Front End), SPI (Serial Peripheral Interface), UART / USART (Universal Asynchronous / Synchronous Receiver Transmitter), DMA (Direct Memory Access), RTOS (Real-Time Operating System), ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), PGA (Programmable Gain Amplifier), CV (Cyclic Voltammetry), CA (Chronoamperometry), SWV (Square Wave Voltammetry), OCP (Open Circuit Potential), LSV (Linear Sweep). Voltammetry (linear scanning voltammetry), BLE (Bluetooth Low Energy), LDO (Low Dropout Regulator), POCT (Point-of-Care Testing), and SPE (Screen-Printed Electrode).

[0034] In existing technologies, multi-channel electrochemical detection generally suffers from the following problems: On the one hand, some solutions rely on adding mechanical switching devices or electronic multiplexers outside the single-channel workstation to achieve channel expansion, which essentially adopts a pseudo-multi-channel mode of time-division multiplexing, resulting in low detection efficiency and the risk of signal switching crosstalk; on the other hand, existing multi-channel devices mostly adopt a control mode in which all channels run the same detection method synchronously, which cannot meet the actual needs of different detection indicators requiring independent configuration of different electrochemical methods and parameters; in addition, in terms of data concurrency throughput, the traditional software polling reading architecture faces bus bandwidth competition and timing jitter problems under high concurrency of multiple channels, and there are also timing conflicts that are difficult to balance between dynamic range adjustment and continuous data acquisition.

[0035] To address the aforementioned issues, this application provides an asynchronous multimodal electrochemical detection method and a multichannel potentiostat system. By constructing a linkage architecture of "independent configuration instructions - multi-task scheduling kernel parsing - hardware-level parallel reading - real-time range adjustment", independent asynchronous detection and real-time dynamic range adjustment of multiple channels are achieved without interrupting the data flow.

[0036] Reference Figure 1 , Figure 1 This paper illustrates the overall architecture block diagram of a multi-channel potentiostat system provided in an embodiment of this application. This application discloses a multi-channel potentiostat system, including a host computer 10, a slave computer 20, and a sensor interface module 23.

[0037] The host computer 10 is an intelligent terminal device that runs host computer software, which can be a personal computer, tablet computer, or smartphone. The host computer 10 establishes a communication connection with the slave computer 20 through a wired communication interface (such as USB to serial port) or a wireless communication interface (such as Bluetooth), and is used to send independent configuration commands and control commands to the slave computer 20, and to receive and process the detection data returned by the slave computer 20.

[0038] The lower-level machine 20 includes a main control module 21 and an analog channel array 22 connected to the main control module 21. The main control module 21, as the core of the system's control and data processing, is configured to execute the asynchronous multimodal electrochemical detection method of this application. The analog channel array 22, as the system's detection unit, is used to realize the excitation and acquisition of electrochemical signals from multiple channels.

[0039] Sensor interface module 23 connects to analog channel array 22 for accessing miniature sensor 50. Sensor interface module 23 provides a standardized physical connection interface, enabling the system to quickly and reliably connect multiple independent three-electrode systems (including working electrode WE, reference electrode RE, and counter electrode CE) or two-electrode systems.

[0040] The following sections provide a detailed description of each module of the multichannel potentiostat system and the asynchronous multimodal electrochemical detection method.

[0041] Reference Figure 2 , Figure 2 A schematic diagram of the hardware architecture of the lower-level machine 20 provided in an embodiment of this application is shown. The lower-level machine 20 adopts a modular design and includes a main control module 21, an analog channel array 22, a communication interface module 24, a power management module 25, and a sensor interface module 23.

[0042] Reference Figure 2 and Figure 3In one embodiment, the main control module 21 includes a microcontroller. This microcontroller employs a high-performance processor based on the ARM Cortex-M core; preferably, in a specific embodiment, it uses an STM32F1 series microcontroller. The microcontroller is configured with multiple independent high-speed SPI interfaces for data and command interaction with the analog channel array 22; it is also configured with at least two USART interfaces for data communication with the host computer 10 software in wired and wireless Bluetooth modes, respectively. The microcontroller integrates a DMA controller for hardware-level data transfer, forming the hardware-level data transmission channel of this application. The microcontroller also runs an RTOS kernel, serving as the multi-task scheduling kernel of this application, for creating and scheduling multiple tasks with different priorities.

[0043] like Figure 3 As shown, the main control module 21's circuit is centered around the microcontroller chip U2, with peripheral configurations including a dual-channel clock source circuit, a reset circuit, and debugging and expansion interfaces. Specifically, the high-speed clock input pins PD0-OSC_IN and PD1-OSC_OUT of the microcontroller chip U2 are connected to the first crystal oscillator X1 and its matching capacitors C12 and C13 to provide the system's main clock; the low-speed clock input pins PC14-OSC32_IN and PC15-OSC32_OUT are connected to the second crystal oscillator X2 and its matching capacitors C2 and C11 to provide the 32.768kHz low-speed clock reference required by the real-time clock (RTC). The NRST pin of the microcontroller chip U2 is connected to the power supply via a pull-up resistor R1 and coupled to ground via a capacitor C1, and is also connected to the reset button RESET1 for performing a manual hardware reset operation on the microcontroller when needed. The BOOT0 pin of the microcontroller chip U2 is connected to ground via a pull-down resistor R14 to configure the system boot mode to boot from the internal Flash. In addition, the circuit board features multiple screw terminals SCREW1 to SCREW4 and a pin header interface. Screw terminals SCREW1 and SCREW2 are connected to the general-purpose I / O pins of the microcontroller chip U2 via resistor R27 for expanding external signal access. The pin header interface includes a reserved SWD debug line interface for easy program burning and online debugging during development. Multiple power supply pins VDD_1 to VDD_4 and the analog power supply pin VDDA of the microcontroller chip U2 are each equipped with decoupling capacitors nearby. The analog reference ground VSSA is connected to the digital ground via resistor R6 to achieve single-point grounding isolation between the analog and digital power domains, reducing interference from digital switching noise on the analog reference voltage. The microcontroller chip U2 also includes a button SW2 and related pull-up resistors R2 and R3 for user-manual triggering functions (such as manual wake-up or mode switching).

[0044] It is understandable that the "hardware-level data transfer channel" here refers to a transfer channel that does not rely on the microcontroller core's byte-by-byte intervention and is autonomously completed by the microcontroller's internal dedicated DMA hardware logic, as opposed to the traditional software polling read mode. In the software polling mode, the microcontroller core needs to execute read and write instructions byte by byte during each data transfer, and is entirely dedicated to data transfer operations; while in the DMA mode, the DMA controller autonomously completes the transfer of the entire block of data after receiving the start command, and the microcontroller core can execute other tasks in parallel during this period (such as range determination algorithms, task scheduling, etc.), thereby eliminating the bus bandwidth bottleneck and timing jitter caused by traditional software polling.

[0045] Reference Figure 2 In one embodiment, the analog channel array 22 includes at least two analog front-end chips. Preferably, in a specific embodiment, the analog channel array 22 uses two four-channel highly integrated analog front-end chips (model MAX30134) to form an eight-channel detection capability. Each analog front-end chip integrates four completely independent detection channels, each channel including a 12-bit DAC for precise potential control, a 16-bit ADC for high-resolution weak current measurement, and a programmable gain amplifier (PGA).

[0046] Reference Figure 2 The microcontroller connects to at least two analog front-end chips via a shared data bus and independent chip select channels. Specifically, the clock lines (SCLK) and data lines (MOSI / MISO) of the two analog front-end chips share the same SPI data bus, while each analog front-end chip has its own independent chip select line (CS). The microcontroller selects which analog front-end chip to communicate with by controlling different chip select lines.

[0047] Understandably, the shared data bus combined with independent chip select connections controls the pin occupancy rate of the microcontroller while ensuring that each analog front-end chip can be independently addressed and accessed at high speed. When it is necessary to expand the number of channels, it is only necessary to increase the number of analog front-end chips and assign an independent chip select line to each new chip. For example, adding three analog front-end chips can form a twelve-channel detection system, and adding four chips can form a sixteen-channel detection system. The number of detection channels of the system can be linearly expanded, while the hardware wiring topology of the data bus remains unchanged, providing a cost-effective hardware foundation for the smooth expansion of potentiostats to a large number of channels.

[0048] Reference Figure 2 and Figure 4In one embodiment, the lower-level machine 20 further includes a power management module 25, which includes a multi-channel regulator to provide mutually isolated independent power rails for the analog circuits of the analog channel array 22 and the digital circuits of the main control module 21.

[0049] Specifically, the power management module 25 employs multi-stage low-noise, high power supply rejection ratio (PSRR) low-dropout linear regulators (LDOs). The first LDO provides a clean and stable analog power rail for the analog front-end chip array, while the second LDO provides a digital power rail for the microcontroller and communication modules. The analog and digital power rails are physically isolated on the circuit board using independent power traces and ground planes.

[0050] like Figure 4 As shown, the power management module 25 includes a USB power supply interface circuit, a charging management circuit, and an LDO voltage regulator circuit. The USB power supply interface circuit uses the Type-C connector USB1 as its input. The VBUS pin of connector USB1 is connected to the system power path via a toggle switch SW3, which controls the overall power supply of the system. The CC1 and CC2 pins of connector USB1 are grounded via pull-down resistors R33 and R54, respectively, to configure the USB Type-C power supply role, enabling the system to establish a power connection with the USB host as a powered device. The DP1 / DN1 and DP2 / DN2 differential signal pairs of connector USB1 are connected to the USB data pins of the microcontroller, serving both data communication and power supply functions. The USB power supply interface circuit also includes an ESD protection component EH, connected in parallel between the USB data line and ground, to clamp electrostatic discharge spikes and protect subsequent circuits. The charging management circuit is centered around the charging management chip U24. The input VIN of the charging management chip U24 is connected to the VBUS power supply switched by switch SW3 via a filter capacitor C18, and the output VOUT is connected to the lithium battery 26. The GND pin is grounded. The charging indicator pin of the charging management chip U24 is connected to the charging indicator LED6 via a current-limiting resistor R40 to indicate the current charging status. Filter capacitors C27 and C25 are located near the output of the charging management chip U24 to smooth the charging output ripple and stabilize the charging voltage of battery 26. LDO voltage regulator circuit ( Figure 4 (Not fully shown, its input is connected to the output of battery 26) converts the voltage of battery 26 into various stable power rails required by the system, including analog power rails for powering the analog front-end chip array and digital power rails for powering the microcontroller and communication modules.

[0051] Understandably, digital circuits (especially microcontrollers and SPI buses) generate high-frequency switching noise during high-speed signal transitions. If this noise is coupled to the current sensing path of the analog front-end chip through a shared power rail or shared ground plane, it will affect the measurement accuracy of weak current signals. By providing mutually isolated independent power rails through multiple voltage regulators, crosstalk from the digital domain switching noise to the analog domain is physically blocked, improving the signal-to-noise ratio for detecting weak current signals at the microampere or even nanoampere level.

[0052] It should be noted that, in a preferred embodiment, the PCB design of the circuit board physically isolates and shields all high-frequency digital signal traces (such as SPI clock lines and data lines) from sensitive analog signal traces (such as the current detection path of the analog front-end chip). All power supply traces that supply power to the analog section are designed with thicker thickness, and decoupling capacitors are placed near key power supply pins to further optimize power quality.

[0053] Reference Figure 2 and Figure 5 In one embodiment, the communication interface module 24 supports both wired and wireless communication methods. (See also...) Figure 3 The communication interface module 24 includes a wired communication interface (such as a USB-to-serial circuit) connected to the first USART interface of the microcontroller and a wireless communication module (such as a BLE Bluetooth chip) connected to the second USART interface of the microcontroller. The wired communication interface is directly connected to the host computer 10 via a USB cable, suitable for stable data transmission in a laboratory environment; the wireless communication module is wirelessly connected to the host computer 10 via Bluetooth protocol, realizing physical separation between the testing equipment and the data processing terminal, suitable for portable on-site testing scenarios.

[0054] like Figure 5As shown, the communication interface module 24 includes a Bluetooth wireless communication unit, a USB-to-serial wired communication unit, and an ESD protection unit. The Bluetooth wireless communication unit is based on a low-power Bluetooth chip U4. The VCC pin of the Bluetooth chip U4 is connected to the 3.3V power rail via a ferrite bead L4 and a decoupling capacitor. The ferrite bead L4 filters out high-frequency noise on the power line, ensuring the cleanliness of the power supply for the Bluetooth RF circuit. The LINK pin of the Bluetooth chip U4 is connected to a status indicator LED2 and its current-limiting resistor R7, used to indicate the Bluetooth connection status (e.g., flashing indicates broadcasting, solid indicates connection). The RXD and TXD pins of the Bluetooth chip U4 are connected to the TXD and RXD pins of the microcontroller's second USART via series resistors R10 and R9, respectively, enabling serial data exchange between the Bluetooth chip and the microcontroller. The RST pin of the Bluetooth chip U4 is left floating (marked as × in the figure) and uses internal reset. The Bluetooth chip U4 connects to an external antenna via an antenna interface H6 (H6 is a 6-pin header, with some pins connected to the antenna feed line and some pins connected to the ground plane) for transmitting and receiving Bluetooth wireless signals. The USB-to-serial wired communication unit uses the USB-to-serial bridge chip U23 as its core. The UD+ and UD- pins of the bridge chip U23 are connected to the D+ and D- data lines of the USB connector, respectively. The RXD and TXD pins of the bridge chip U23 are connected to the TXD and RXD pins of the microcontroller's first USART, enabling bridging and conversion between the USB and UART protocols. The VCC and V3 pins of the bridge chip U23 are connected to a 3.3V power supply, and the GND pin is grounded. Externally, it is equipped with filter capacitors C36 and C37 and a termination resistor R61. The ESD protection unit includes Zener diodes D3 and D2, connected in parallel between the signal lines of the Bluetooth and USB communication units and the 3.3V power supply, respectively. The anode of each Zener diode is connected to the 3.3V power supply via pull-up resistors R25 or R26, and the cathode is connected to the corresponding signal line. This clamps potential ESD spikes or overvoltage surges on the signal lines, protecting the input ports of the microcontroller and communication chip from damage.

[0055] In one embodiment, the sensor interface module 23 uses a highly reliable connector with anti-misplugging design. Preferably, in a specific embodiment, four 6-channel aviation sockets are used as the sensor interface. By connecting corresponding aviation plugs to these aviation sockets and finally to 24 alligator clips, eight independent three-electrode systems can be quickly and reliably connected. Specifically, each aviation socket provides six pins, corresponding to two independent three-electrode systems (each group has three pins connected to WE, RE, and CE respectively). The four aviation sockets provide physical connection ports for eight three-electrode systems, corresponding one-to-one with the eight detection channels (two four-channel analog front-end chips) of the analog channel array 22. Each aviation socket is connected to six alligator clips via adapter cables, and the four aviation sockets connect to a total of 24 alligator clips. This design ensures orderly management of connection lines during multi-channel parallel experiments and simplifies the user's operation of replacing or connecting different microsensors 50.

[0056] It should be noted that the working mode of the sensor interface module 23 can be flexibly configured according to the application scenario. The two-electrode working mode or the three-electrode working mode can be selected through the software settings of the host computer 10.

[0057] In one embodiment, the lower-level computer 20 also integrates a thermistor (not shown in the figure) for directly measuring the ambient temperature around the device, providing a reference for determining whether the experimental environment conditions meet the requirements. Simultaneously, the main control module 21 monitors the minute current changes generated by the sensor interface module 23 when the micro-sensor 50 is connected, automatically identifying the insertion event of the micro-sensor 50 and triggering corresponding workflow switching or low-power management modes based on the connection status, further improving the device's intelligence and operational efficiency. Furthermore, the analog front-end chip also integrates a temperature sensor, providing its own temperature data. Both the ambient temperature and the chip's internal temperature data can be transmitted back to the upper-level computer 10 for user monitoring of ambient temperature and threshold alarms.

[0058] Reference Figure 2 In one embodiment, the lower-level computer 20 further includes a battery 26 and a power detection circuit 27. The power detection circuit 27 samples the voltage of the battery 26 in real time and converts the sampled data into standardized power status information (such as good power or low power), which is synchronously transmitted back to the upper-level computer 10 for low power reminder and power supply status monitoring.

[0059] It should be noted that, in a preferred embodiment, the circuit board size of the entire lower-level machine 20 hardware is approximately 12cm × 12cm, which meets the size requirements of portable devices and can be accommodated in a handheld casing.

[0060] Reference Figure 6 , Figure 6 A schematic diagram of the modular adapter 30 provided in an embodiment of this application is shown.

[0061] To enhance the system's adaptability to various miniaturized and integrated micro-sensors 50, this application also provides a modular adapter 30. The modular adapter 30 includes a substrate 31, a connector 32, conductive terminals 33, and a microcell 34.

[0062] The substrate 31 serves as the main structure of the modular adapter 30, and its material can be FR-4 copper-clad laminate, flexible circuit board material, or ceramic substrate 31. Conductive lines that electrically connect the connector 32 and the conductive terminal 33 are arranged inside the substrate 31.

[0063] A connector 32 is disposed at one end of the substrate 31 and is used to adapt to and electrically contact the microsensor 50. The electrode carrier of the microsensor 50 includes, but is not limited to, screen-printed electrodes (SPE), microfluidic chip electrodes, etc.; the surface of the electrode carrier can be modified with appropriate sensitive materials according to detection requirements to form a microsensor 50 targeting a specific analyte. The type and size of the connector 32 are determined according to the packaging form of the adapted microsensor 50, for example, it can be a slot-type connector 32 or a pin header connector 32 to achieve a secure insertion and reliable electrical contact of the microsensor 50.

[0064] A conductive terminal 33 is disposed at the other end of the substrate 31. The conductive terminal 33 and the connector 32 are electrically connected through conductive lines inside the substrate 31. The conductive terminal 33 is configured to provide an electrical contact surface for external clamping terminals to be held, so as to connect to the sensor interface module 23 via the external clamping terminals. The external clamping terminals are alligator clips or other large-size test clamps commonly used in laboratories.

[0065] Specifically, in one embodiment, the conductive terminal 33 includes three independent terminals corresponding to the three-electrode system, respectively corresponding to the signal paths of the working electrode WE, the reference electrode RE, and the counter electrode CE. Sufficient spacing is maintained between the terminals to ensure that short circuits do not occur between adjacent terminals when the alligator clip is in use. The surface of the conductive terminal 33 may be gold-plated to reduce contact resistance and improve corrosion resistance.

[0066] A microcell 34 is formed on the substrate 31 and located near the connector 32 to contain electrolyte so that the electrolyte can make electrical contact with the microsensor 50. The microcell 34 can be an open cavity structure enclosing the surface of the substrate 31, and its volume is designed according to actual detection needs, typically ranging from tens to hundreds of microliters, to meet the needs of adding micro-samples.

[0067] Understandably, the modular adapter 30 is designed to quickly adapt to various non-standard interface miniaturized sensors 50 without altering the standard alligator clip interface of the potentiostat host, achieving multi-purpose functionality. In use, the miniature sensor 50 is inserted into the connector 32 of the adapter board, the alligator clip of the potentiostat host is connected to the conductive terminal 33 of the adapter board, and finally, the electrolyte to be tested is added to the miniature cell 34 for detection. The conductive terminal 33 provides a reliable electrical contact surface for traditional large-size test terminals such as alligator clips in the laboratory, while the miniature cell 34 provides a standardized current-limiting microenvironment for adding trace amounts of electrolyte. The combination of these two features improves the ease of operation and sample utilization in on-site testing.

[0068] Reference Figure 7 , Figure 7 A flowchart of the asynchronous multimodal electrochemical detection method provided in an embodiment of this application is shown. This application discloses an asynchronous multimodal electrochemical detection method applied to the aforementioned multichannel potentiostat system. The steps of this method are described in detail below.

[0069] Step S0: System wake-up (optional) Before performing step S1, the asynchronous multimodal electrochemical detection method may also include a system wake-up step.

[0070] The multi-channel potentiostat system also includes a hardware monitoring module 40 and a modular adapter 30. The lower-level machine 20 also includes a microcontroller and a sensor interface module 23, which is a physical connection port (such as an aviation socket) for external micro-sensors 50 or the modular adapter 30 to connect to. The hardware monitoring module 40 is a hardware circuit unit within the lower-level machine 20 used to monitor changes in the electrical characteristics of the sensor interface module 23.

[0071] In low-power standby mode, the microcontroller enters a low-power sleep state, and most of the system's functional modules are in a shutdown or low-power state. Only the hardware monitoring module 40 remains operational, continuously monitoring the electrical characteristics of the sensor interface module 23.

[0072] When the conductive terminal 33 of the modular adapter 30 is connected to the sensor interface module 23 via alligator clips, the electrical connection between the conductive terminal 33 and the sensor interface module 23 causes a change in the electrical characteristics of the sensor interface module 23. This change in electrical characteristics can be a change in the interface pin level (e.g., from high level to low level), a change in pin current, or a change in pin impedance.

[0073] Specifically, in one embodiment, the hardware monitoring module 40 is implemented by setting a pull-up resistor on a specific pin of the sensor interface module 23 and connecting it to the external interrupt input pin of the microcontroller. When no microsensor 50 is connected, the pin is kept high through the pull-up resistor; when the conductive terminal 33 of the modular adapter 30 is connected, the conductive line on the conductive terminal 33 pulls the pin low, generating a falling edge signal, triggering a hardware interrupt of the microcontroller, thereby waking up the microcontroller, causing the lower-level machine 20 to exit the low-power mode and enter the normal detection process.

[0074] Understandably, this system's wake-up mechanism utilizes hardware-level electrical characteristic monitoring instead of the traditional software-based periodic polling method. In standby mode, the system consumes almost no power, reducing the power consumption of portable devices in standby mode and extending the single-charge working time powered by battery 26. Simultaneously, the insertion of the micro-sensor 50 automatically triggers system wake-up, achieving a plug-and-play user experience without requiring manual button operation to start the device.

[0075] It should be noted that the system wake-up step is optional. In another embodiment, the lower-level machine 20 can also always remain in normal working state, and the user can manually send a wake-up command through the upper-level machine 10 to start the detection process.

[0076] Step S1: Receiving and sending independent configuration instructions. The host computer 10 receives independent configuration instructions for N detection channels and sends the independent configuration instructions to the slave computer 20. The independent configuration instructions for each channel are independent of each other and are used to set the asynchronous multimodal electrochemical detection method and corresponding parameters for the corresponding channel, where N is an integer greater than 1.

[0077] Step S2: The lower-level machine 20 parses the independent configuration instructions based on the multi-task scheduling kernel and independently configures the working mode of multiple detection channels in the multiple analog channel array 22; Step S3: After configuration is completed, in response to the start command, the lower-level machine 20 reads the current data of multiple detection channels in parallel through the hardware-level data transmission channel. During the reading process, the lower-level machine 20 performs real-time range adjustment based on the multi-task scheduling kernel: it determines whether the current data exceeds the preset safety range. If it exceeds the upper limit, it reduces the gain parameter of the corresponding channel. If it is below the lower limit, it increases the gain parameter of the corresponding channel and re-acquires based on the adjusted gain parameter. Step S4: The lower-level computer 20 transmits the current data back to the upper-level computer 10 for display and processing.

[0078] Specifically, in step S1, the host computer 10 software provides a graphical parameter configuration interface. The user first configures the total number N of channels involved in the experiment in the interface. In a specific embodiment, the maximum value of N is 8, corresponding to the eight physical detection channels of the slave computer 20. The software dynamically generates N channel configuration units based on the total number N specified by the user. The user then independently selects the required asynchronous multimodal electrochemical detection method for each channel. Selectable methods include, but are not limited to, cyclic voltammetry (CV), chronoamperometry (CA), square wave voltammetry (SWV), open-circuit potential method (OCP), and linear sweep voltammetry (LSV). Depending on the method selected for each channel, the software automatically generates a corresponding parameter configuration table for the user to fill in or modify.

[0079] For example, when a user selects cyclic voltammetry (CV) for a channel, the parameter configuration table automatically generated by the software includes parameters such as initial potential, maximum potential, minimum potential, scan rate, and number of scan cycles; when a user selects time-amperometry (CA) for a channel, the parameter configuration table includes parameters such as applied potential and acquisition time; when a user selects square wave voltammetry (SWV) for a channel, the parameter configuration table includes parameters such as initial potential, termination potential, step potential, pulse amplitude, and pulse frequency.

[0080] In one specific embodiment, the independent configuration instructions are organized into two types of data packets according to a preset data transmission protocol: channel configuration packets and parameter configuration packets. The channel configuration packets are used to transmit the number of channels and the detection method for each channel, configured by the user. An example of its format is "channels=4,ch1_CV,ch2_CA,ch3_SWV,ch4_OCP", indicating that four channels are used in this experiment: channel 1 performs cyclic voltammetry, channel 2 performs chronoamperometry, channel 3 performs square wave voltammetry, and channel 4 performs open-circuit potential voltammetry. The parameter configuration packets are used to transmit the specific electrochemical parameters of each channel. An example of its format is "ch1,Init_E=0.04,High_E=0.04,Sweep=2", indicating that the initial potential of channel 1 is 0.04V, the highest potential is 0.04V, and the number of scan cycles is 2.

[0081] The host computer 10 sends the above data packets to the slave computer 20 through a wired or wireless communication interface.

[0082] It is understandable that the independent configuration commands for each channel mean that each channel can be configured with completely different asynchronous multimodal electrochemical detection methods and parameters than the other channels, and there are no strong coupling constraints between channels in terms of methods or parameters. For example, channel 1 can perform cyclic voltammetry (CV) for electrode characterization, while channel 2 can perform chronoamperometry (CA) for quantitative detection of glucose concentration, channel 3 can perform square wave voltammetry (SWV) for trace heavy metal ion detection, and channel 4 can perform open-circuit potential (OCP) to monitor changes in the open-circuit potential of the electrode. This "asynchronous multimodal" configuration capability allows a single device to complete multiple different types of detection tasks in the same experiment.

[0083] In step S2, the lower-level machine 20 parses the independent configuration instructions and configures the working mode based on the multi-task scheduling kernel, and independently configures the working mode of multiple detection channels in the multiple analog channel array 22.

[0084] Specifically, the microcontroller of the lower-level machine 20 runs an RTOS (FreeRTOS in one specific embodiment), which creates and schedules multiple tasks with different priorities through a multi-task scheduling kernel. These multiple tasks include at least acquisition tasks, processing tasks, communication tasks, and system monitoring tasks.

[0085] Among them, the acquisition task is configured with the highest priority and is used to perform data reading and real-time range adjustment in step S3; the processing task is configured with the second highest priority and is used to parse independent configuration instructions and configure the working mode; the communication task is configured with the lowest priority and is used to manage data exchange with the host computer 10 and perform data return in step S4; the system monitoring task is configured with the lowest priority and is used to periodically check the running status of each task and the system resource usage, and is responsible for system health management, power consumption control and mode switching.

[0086] Understandably, setting the acquisition task as the highest priority is crucial because electrochemical data acquisition has stringent real-time requirements. This is especially true when performing high-speed potential scanning methods such as cyclic voltammetry, where the ADC sampling timing must be precisely synchronized with the excitation waveform output by the DAC. Any deviation in sampling timing will lead to distortion of the current-potential curve. If the acquisition task has a lower priority than communication or processing tasks, it will be blocked while the latter are performing time-consuming operations (such as serial transmission of large data packets or complex instruction parsing), causing ADC sampling delays, timing jitter, and data loss. Therefore, setting the acquisition task as the highest priority ensures that it can preempt other tasks and execute immediately at any time, guaranteeing the timing accuracy of the underlying electrochemical hardware operations.

[0087] Efficient synchronization and data transfer between tasks are achieved through RTOS mechanisms such as message queues, semaphores, and event flags. For example, after the communication task receives a data packet from the host computer 10, it puts it into a message queue, and the processing task retrieves the data packet from the message queue for parsing; after the acquisition task completes a round of data acquisition, it puts the data into another message queue, and the communication task retrieves the data from it and sends it to the host computer 10.

[0088] In step S2, the communication task first receives the channel configuration packet and parameter configuration packet from the host computer 10 and forwards them to the processing task through a message queue. After the processing task is activated, it parses the data packet to extract the detection method and corresponding parameters for each channel. Subsequently, based on the parsing results, the processing task generates the corresponding configuration data and precisely writes it into the internal control register of the corresponding analog front-end chip via the SPI bus, completing the setting of all operating parameters such as the potential waveform, scanning parameters, and working mode for each channel.

[0089] For example, when the processing task determines that channel 1 needs to perform cyclic voltammetry, it converts the parameters required for cyclic voltammetry, such as the initial potential, upper scan limit potential, lower scan limit potential, and potential step value, into digital configuration values ​​of the analog front-end chip's DAC register, and writes them to the corresponding register of channel 1 of the first analog front-end chip via SPI; when it determines that channel 5 needs to perform timing amperometry, it writes the applied potential value and acquisition time parameters to the corresponding register of channel 1 of the second analog front-end chip (channel 1 of the second chip physically corresponds to channel 5 of the system).

[0090] It should be noted that asynchronous multimodal electrochemical detection methods can be divided into two categories based on their potential scan speed requirements: the first category requires high-speed potential scanning, and the second category does not. The first category includes cyclic voltammetry (CV), linear sweep voltammetry (LSV), and square wave voltammetry (SWV). These methods require the DAC to output a continuously changing potential excitation waveform at a high frequency, while the ADC needs to synchronously acquire the response current at a matching high frequency, placing high demands on the system's data throughput and timing accuracy. The second category includes time-of-flight amperometry (CA) and open-circuit potential method (OCP). These methods only require the DAC to output a constant potential or no potential output at all, while the ADC acquires the response current or potential at a relatively low frequency, placing lower demands on the system's data throughput and timing accuracy.

[0091] Based on the above classification, during the execution of step S3, the lower-level machine 20 configures the upper limit of the number of channels that can synchronously execute the second type of method to N (that is, all channels can synchronously execute the second type of method), and configures the upper limit of the number of channels that can synchronously execute the first type of method to a maximum of M, where M is less than N.

[0092] In one specific embodiment, N=8 and M=2. That is, the eight-channel potentiostat system supports fully synchronous operation of all eight channels for the second type of methods such as CA and OCP, while for the first type of methods such as CV and SWV, due to the limitations of the internal DAC waveform generator architecture of the analog front-end chip and the bandwidth constraints of the SPI bus, it can only support a maximum of two channels operating synchronously.

[0093] Understandably, setting an upper limit M on the number of channels simultaneously executing the first type of method is a dynamic load balancing mechanism that balances hardware resources and detection requirements. The first type of method requires high-frequency writing of DAC update values ​​to the analog front-end chip and reading of ADC conversion results via the SPI bus. If too many channels are allowed to execute this high-speed method simultaneously, the SPI bus bandwidth will become a bottleneck, leading to untimely DAC updates, misaligned ADC sampling timing, and ultimately, distortion of the potential scan waveform and errors in current data. By limiting the number of synchronous channels for the first type of method to M=2, sufficient bandwidth on the SPI bus is ensured to provide high-speed and accurate data services for these two channels, guaranteeing signal integrity and the accuracy of the detection results. The second type of method, due to its low data interaction frequency and small data volume per transmission, will not cause bus overload even if eight channels run simultaneously.

[0094] In one embodiment, when the detection scheme configured by the user in step S1 exceeds the system's concurrency limit (e.g., attempting to configure cyclic voltammetry for more than three channels simultaneously), the host computer software 10 provides prompts or restrictions in the parameter configuration interface to guide the user to adjust the configuration scheme.

[0095] In step S3, parallel data reading and real-time range adjustment are specifically as follows: In response to the start command, the lower-level machine 20 reads the current data of multiple detection channels in parallel through the hardware-level data transmission channel; during the reading process, the lower-level machine 20 performs real-time range adjustment based on the multi-task scheduling kernel.

[0096] Specifically, after the hardware configuration is completed in step S2, the system waits for the host computer 10 to send a start command. There are two types of start commands: "Start All" and "Start Specified Channel". The "Start All" command causes all configured channels to simultaneously enter the acquisition state; the "Start Specified Channel" command only causes one or more specified channels to enter the acquisition state, while the remaining channels remain in standby mode. This dual-mode start control provides users with the flexibility for batch operations and fine-grained scheduling.

[0097] Once the start command is received, the system enters the core data acquisition loop. The acquisition task (highest priority) is periodically triggered to read raw data from each channel of the analog front-end chip through the hardware-level data transmission channel.

[0098] The hardware-level data transmission channels include a first DMA path and a second DMA path integrated into the microcontroller. The first DMA path is used to read data from the analog channel array 22: the microcontroller configures the first DMA path to associate with the SPI receive buffer. When the SPI bus receives data from the analog front-end chip, the first DMA path automatically moves the received data from the SPI receive buffer to a preset memory array; the entire process requires no byte-by-byte intervention from the microcontroller core. The second DMA path is used to send data to the host computer 10: the microcontroller configures the second DMA path to associate with the UART transmit buffer. When data needs to be sent back to the host computer 10, the second DMA path automatically moves the packaged data frame in memory to the UART transmit buffer and starts transmission; similarly, no microcontroller core intervention is required.

[0099] Understandably, the first and second DMA paths separate the underlying data transmission and reception operations, and the two DMA paths can work in parallel. While the first DMA path is receiving a new round of data from SPI, the second DMA path can simultaneously send the results of the previous round of acquisition via UART, achieving efficient pipelined data flow. This design frees up the microcontroller's core computing resources, allowing it to focus on executing multi-task scheduling and intelligent range judgment algorithms, thereby supporting large-scale, high-throughput data acquisition across more channels.

[0100] During the data acquisition cycle, for channels synchronously executing the first type of method (such as CV, SWV), the lower-level machine 20 controls the corresponding detection channel to output an excitation waveform at a first frequency and acquire current data at a second frequency; for channels synchronously executing the second type of method (such as CA, OCP), the lower-level machine 20 controls the corresponding detection channel to output an excitation waveform at a third frequency and acquire current data at a fourth frequency. The first frequency is greater than the third frequency, and the second frequency is greater than the fourth frequency.

[0101] In one specific embodiment, for the channel performing the cyclic voltammetry method, the DAC output frequency (first frequency) is 100 to 1000 potential updates per second, and the ADC sampling frequency (second frequency) is synchronized with the DAC update frequency or an integer multiple thereof; for the channel performing the timing ampere method, the DAC only needs to output a constant potential once at the beginning of the experiment (the third frequency is close to zero or a very low frequency), and the ADC sampling frequency (fourth frequency) is 1 to 100 times per second.

[0102] It is understandable that allocating matching excitation and sampling frequencies to different types of electrochemical methods is a time-series resource optimization configuration tailored to the characteristics of different electrochemical signals. High-speed scanning methods (such as CV) require high-frequency DAC updates and ADC sampling to faithfully reproduce continuously changing potential-current curves; insufficient sampling frequency will result in the loss of key transient features such as peak current. Meanwhile, steady-state methods (such as CA) have slowly changing current signals; excessively high sampling frequencies not only generate a large amount of redundant data, increasing storage and communication burdens, but may also introduce more high-frequency noise. By configuring differentiated frequencies, the signal integrity of high-speed methods is ensured while suppressing redundant data generation in low-speed methods, thus optimizing the overall communication bandwidth and storage efficiency of the system.

[0103] The real-time range adjustment in step S3 is specifically as follows: During the reading process, the lower-level machine 20 performs real-time range adjustment based on the multi-task scheduling kernel. The specific process of this real-time range adjustment is as follows: After each round of data acquisition is completed, the current data of each channel is evaluated in real time to determine whether the current data of each channel exceeds the preset safety range under the current range setting of that channel.

[0104] The preset safety range is determined by the upper and lower thresholds of the ADC range. In one specific embodiment, the upper threshold is set to 80% of the ADC full-range reading under the current range, and the lower threshold is set to 20% of the ADC full-range reading under the current range.

[0105] If the current data of a certain channel exceeds the upper limit threshold, it indicates that the actual current signal amplitude of the channel is close to or exceeds the upper limit of the ADC range, and there is a risk of signal saturation (truncation). At this time, the acquisition task generates a range adjustment command, reduces the gain parameter of the PGA inside the analog front-end chip of the channel through the SPI bus (i.e., switches to a larger range), so as to expand the measurable current range, and then re-acquires data for the channel based on the adjusted gain parameter.

[0106] If the current data of a certain channel is lower than the lower threshold, it indicates that the actual current signal amplitude of the channel is much smaller than the range of the ADC, the effective resolution of the signal is low, and it may be submerged in quantization noise. At this time, the acquisition task generates a range adjustment command, increases the gain parameter of the PGA inside the analog front-end chip of the channel through the SPI bus (i.e., switches to a smaller range) to improve the signal resolution, and then re-acquires data for the channel based on the adjusted gain parameter.

[0107] If the current data of a certain channel is between the upper and lower thresholds (i.e., within the safe range), it indicates that the current range is well matched and no adjustment is needed. The data of this channel is directly marked as valid data and enters the data reporting process.

[0108] The gain parameter specifically refers to the gain setting value of the PGA inside the analog front-end chip. In one specific embodiment, the PGA of the analog front-end chip supports multiple gain levels (such as 1x, 2x, 4x, 8x, 16x, 32x, etc.), with each gain level corresponding to a current measurement range. A higher gain results in a smaller minimum detectable current (higher resolution), but also a smaller maximum detectable current (narrower range); a lower gain results in a larger maximum detectable current (wider range), but a corresponding decrease in resolution. Real-time range adjustment dynamically switches the PGA gain level to ensure the signal is always within the optimal measurement window of the ADC, balancing high resolution for weak signals with anti-saturation capability for strong signals.

[0109] Understandably, the real-time range adjustment process is executed within the acquisition task (highest priority), and the range adjustment command is directly written to the PGA configuration register of the analog front-end chip via the SPI bus. The adjustment operation only affects the target channel and does not affect the normal acquisition of other channels. This is because the PGA of each channel of the analog front-end chip is configured independently; modifying the PGA gain of one channel will not change the gain settings of other channels, thus achieving real-time dynamic range adjustment of the target channel without interrupting the data flow of other channels.

[0110] It should be noted that after PGA gain switching, the internal amplifier of the analog front-end chip requires a certain settling time (typically on the order of microseconds to tens of microseconds) for the output signal to stabilize. After issuing the gain adjustment command, the acquisition task will wait for a preset stabilization time window before performing a re-acquisition operation to ensure that the re-acquisitioned data is valid data after the gain adjustment has stabilized, and to avoid the transient noise introduced by the settling transition from affecting the measurement results.

[0111] In one specific embodiment, regarding the timing control in the aforementioned real-time range adjustment step, this application adopts a "gap time staggered configuration" mechanism based on the hardware-level data transmission channel (i.e., the first DMA path). That is, after the acquisition task completes a parallel reading of current data from multiple detection channels, if it determines that the current data of a certain channel exceeds the safe range, a corresponding range adjustment instruction is generated. The execution of the corresponding range adjustment instruction and the update configuration of the corresponding channel gain parameters are both completed within the gap time of the next parallel reading operation on the hardware-level data transmission channel, thus eliminating the timing conflict between the hardware stabilization time required for range adjustment and the continuous concurrent acquisition of multiple channels. Specifically, the system strictly divides a continuous acquisition cycle into two non-overlapping stages on the time axis: the first stage is the "DMA data transfer stage," during which the first DMA path exclusively uses the bus to autonomously transfer the current data from the analog channel array 22 to memory, at which time the microcontroller core does not interfere with the data flow; the second stage is the "gap processing stage," which is the bus idle window that exists after the first DMA path completes a parallel reading operation and before the hardware timing triggers the next parallel reading operation.

[0112] When the acquisition task determines that the current data of a certain channel exceeds the safe range and generates a range adjustment command, the execution of this command (written to the PGA configuration register of the analog front-end chip via the SPI bus) and the hardware establishment process of the corresponding channel gain parameters are both strictly limited to the aforementioned "gap processing stage". This timing design ensures from the underlying logic that the range adjustment process will not occupy or block the periodic concurrent data acquisition stream, achieving "uninterrupted" adjustment.

[0113] To ensure the reliability of this gap adjustment mechanism in engineering, this application sets up a triple collaborative protection logic at both the software and hardware levels: First, there is a significant order-of-magnitude advantage in computing power time windows. In this embodiment, the time taken for the first DMA path to complete a multi-channel parallel read is typically in the microsecond range (e.g., 10 μs), while the hardware trigger cycle between two adjacent reads is typically in the millisecond range (e.g., 1 ms). Therefore, the "gap processing phase" between two reads can last for hundreds of microseconds. After the RTOS hands over CPU execution to the acquisition task, the microcontroller's CPU core writes the PGA configuration register to the peripheral via the SPI bus and executes a software delay to wait for the setup time of the simulated front-end hardware to finish. The maximum time taken for these operations is typically within tens of microseconds. The gap time is orders of magnitude larger than the time taken for the CPU to perform adjustments, eliminating the possibility of timeouts from a hardware physical perspective.

[0114] Second, CPU execution rights are isolated. Since the acquisition task that performs range adjustment is configured with the highest priority by the RTOS, when the first DMA path transfer is completed and an interrupt is triggered to enter the "gap processing stage", the acquisition task can immediately preempt the CPU usage rights of other low-priority tasks (such as communication tasks and processing tasks), ensuring that the range adjustment instruction obtains a contention-free execution environment.

[0115] Third, non-blocking fault-tolerant degradation under extreme conditions. In rare abnormal situations (such as SPI communication delays caused by bus transient interference), if the gain parameter update configuration cannot be completed during the current "gap processing phase," the system will not extend the gap time or block the start of the next round of DMA. Instead, the system will abandon this adjustment, allowing the first DMA path to continue executing the next parallel read with the original gain parameters, while marking the channel as "pending adjustment" and deferring the range adjustment command to the next gap time. Thus, potential "timing conflicts" are transformed into acceptable "response delays" under extreme conditions, thereby preserving the timing integrity and data flow continuity of multi-channel continuous concurrent data acquisition.

[0116] It should be noted that this application embeds the range adjustment logic into the highest priority acquisition task through the RTOS, leveraging the hardware characteristic that each channel's PGA can be independently configured. When the data in a certain channel exceeds the limit, the acquisition task immediately modifies only the PGA gain register of that channel via SPI. Since the PGA gain switching and settling time (in microseconds) is much shorter than the multi-channel cyclic acquisition cycle (in milliseconds), and this operation is point-to-point, it does not affect the hardware status of other channels. Therefore, this adjustment can be "wrapped" within one execution cycle of the acquisition task, or completed using the CPU idle time slice during DMA data transfer, thereby achieving "unobtrusive" maintenance of the continuity of external data streams.

[0117] In addition, in a preferred embodiment, the real-time range adjustment algorithm is also equipped with anti-jitter logic: the range switching operation is only performed when the signal amplitude is detected to touch the upper or lower threshold multiple times (e.g., three times in a row) to prevent the PGA gain from frequently switching back and forth (i.e., range jitter) when the signal fluctuates near the threshold, thereby improving the stability of the range adjustment.

[0118] It should be noted that when performing range adjustment on the target channel, since the PGA of each channel of the analog front-end chip is an independently configured hardware unit, an SPI write operation to the PGA gain register of one channel will not modify the register contents of other channels. Meanwhile, the setup time for PGA gain switching is typically on the order of microseconds to tens of microseconds, while the DMA data reading cycle from each channel is typically on the order of milliseconds. Therefore, the range adjustment operation of a single channel (including SPI write + setup wait + re-acquisition) can be completed within the time interval between two DMA reads of other channels, without causing delays in the acquisition cycle of other channels or data overwriting. This single-channel perturbation, globally imperceptible range adjustment characteristic is an advantage of the linkage architecture in this application compared to the traditional scheme of pausing all acquisitions for range switching.

[0119] In step S4, the lower-level computer 20 transmits the current data back to the upper-level computer 10 for display and processing.

[0120] Specifically, after the acquisition task completes data reading and range determination, it packages the effective current data of each channel, the ambient temperature collected by the thermistor, the internal temperature of the analog front-end chip, and the power status information into data frames and places them into the communication task's sending queue. The communication task retrieves the data frames from the sending queue and sends them to the host computer 10 via the second DMA path and the UART interface for display, processing, and anomaly alerts.

[0121] In one embodiment, when the system is in an idle state with no active detection tasks, all detection channels are turned off, and the analog front-end of each channel does not output excitation signals or perform ADC acquisition. At this time, the lower-level computer 20 can enter a low-power mode to save power according to the instructions of the system monitoring task.

[0122] It should be noted that the data return process and the data acquisition process are parallelized at the hardware level through the DMA path. While the second DMA path is sending the data frame of the current round via UART, the first DMA path is already reading the acquisition data of the next round via SPI. The two operations are executed in overlapping time, maximizing the system's data throughput efficiency.

[0123] In one embodiment, the data acquisition cycle continues until the communication task receives a stop command from the host computer 10. The stop command includes two types: a "stop all" command and a "stop specified channel" command. Upon receiving a "stop all" command, all channels stop acquiring data, and the system can return to standby mode or wait for new configuration commands. Upon receiving a "stop specified channel" command, only the corresponding channel stops acquiring data, while the remaining channels continue to operate normally without being affected.

[0124] In a preferred embodiment, the system supports dynamic reconfiguration. During or after detection, the user can issue new configuration commands through the host computer 10. Each task receives the new configuration through a message queue and seamlessly switches to the new detection method and parameters in the next acquisition cycle without restarting the system.

[0125] Reference Figure 8 , Figure 8 The flowchart of the operation of the lower-level machine 20 software provided in the embodiment of this application is shown. The flowchart fully shows the working logic of the entire process from hardware power-on to detection end from the perspective of the lower-level machine 20 firmware, which corresponds to the method steps S0 to S4 above.

[0126] like Figure 8 As shown, the operation flow of the lower-level machine 20 software includes the following stages: Initialization and Standby Phase. After the hardware is powered on, the microcontroller first performs peripheral initialization, including configuring the operating parameters of hardware peripherals such as the SPI interface, USART interface, DMA controller, GPIO pins, and ADC; then it starts the FreeRTOS kernel (i.e., the multi-task scheduling kernel of this application), creating acquisition tasks, processing tasks, communication tasks, and system monitoring tasks. After initialization is complete, the system enters low-power standby mode.

[0127] Wake-up and mode switching phase. In low-power standby mode, the system continuously waits for a wake-up event. For example... Figure 8 As shown, it is determined whether a command has been received from the host computer 10 or whether the insertion of the micro sensor 50 has been detected (corresponding to the system wake-up step S0 of this application): if not, the system continues to maintain the low power mode; if yes, the system exits the low power mode and enters the normal test mode.

[0128] Command Reception and Configuration Phase. After entering normal test mode, the lower-level machine 20 receives data packets related to channel configuration from the upper-level machine 10 software (corresponding to the step of upper-level machine 10 issuing independent configuration commands in step S1 of this application). The processing task then parses the data packets and sends the parsed detection methods and parameter data of each channel to the corresponding registers of the analog front-end chip (i.e., AFE) via the SPI bus to complete the hardware configuration of each channel (corresponding to the step of lower-level machine 20 parsing independent configuration commands and configuring the working mode in step S2 of this application). After configuration, the system waits for the upper-level machine 10 to send a start command.

[0129] Data acquisition and range adjustment cycle stage. For example... Figure 8As shown, the system determines whether it has received a start command from the host computer 10: if not, the system continues to wait; if yes, the system enters the core data acquisition loop. In the acquisition loop, the acquisition task waits for the analog front-end chip to complete the ADC conversion and then reads the data (i.e., waits for the AFE to read and retrieve the data), and reads the raw data of each channel in parallel from the data register of the analog front-end chip through the first DMA path (corresponding to step S3 of this application, which involves reading the current data of multiple detection channels in parallel through a hardware-level data transmission channel). After reading, the acquisition task parses the raw data, dividing it into three categories: test data (i.e., current data from electrochemical detection), temperature data, and power data. Temperature data is directly reported to the host computer 10 for ambient temperature monitoring; power data, after conversion, is reported to the host computer 10 in the form of sufficient or insufficient status commands for low power alarms.

[0130] For the test data (i.e., current data), after reporting to the host computer 10, the acquisition task executes a real-time range adjustment program (corresponding to the step in step S3 of this application where real-time range adjustment is performed based on a multi-task scheduling kernel). Figure 8 As shown, the system determines whether the test data is within the safe range: if yes, the data is valid and the system proceeds to the end judgment stage; if no, the system performs a range switching operation—increasing the range (i.e., decreasing the PGA gain parameter) when the data is greater than the upper limit of the safe range, and decreasing the range (i.e., increasing the PGA gain parameter) when the data is less than the lower limit of the safe range, and then re-acquiring the channel data based on the adjusted gain parameter.

[0131] It should be noted that, Figure 8 The flowchart indicates that the range increases when it exceeds the safety range and decreases when it is below the safety range. The physical meaning of this is the same as in the embodiment of this application, where the gain parameter of the corresponding channel is decreased when it exceeds the upper limit and increased when it is below the lower limit: increasing the range is equivalent to decreasing the PGA gain (expanding the measurable current range), and decreasing the range is equivalent to increasing the PGA gain (improving the resolution of weak currents).

[0132] End of judgment phase. After each data acquisition cycle, the system checks whether it has received an end command from the host computer 10: if not, the system returns to the beginning of the data acquisition cycle and continues the next round of data reading and range adjustment (corresponding to the continuous loop execution of step S3); if yes, the system exits the data acquisition cycle, the process ends, and the system can return to standby state or wait for new configuration commands.

[0133] Reference Figure 9 and Figure 10 The functional architecture diagram and operation flowchart of the host computer 10 software system provided in the embodiments of this application are shown respectively.

[0134] like Figure 9As shown, the host computer 10 software system adopts a layered architecture design, including five functional modules: device management layer, parameter configuration layer, data visualization layer, intelligent analysis layer, and data storage module. The modules collaborate loosely through clearly defined internal interfaces, ensuring the system's scalability and maintainability.

[0135] The device management layer is responsible for connecting devices, monitoring their status, and scheduling data acquisition. Specifically, the management layer supports discovering, connecting to, and managing one or more slave devices 20 via wired (USB to serial port) or wireless (Bluetooth) communication interfaces. After successful connection, the management layer monitors the working status and network link quality of each connected device in real time, centrally displaying the real-time working status (idle, running, error), core device temperature, and battery level 26 of each channel. When the temperature exceeds the user-defined threshold or the battery level falls below the preset value, the software interface provides visual alarms (such as color changes of interface elements or pop-up prompts) and audible alarms (such as buzzer prompts) to ensure experimental safety and continuity.

[0136] The parameter configuration layer provides users with a graphical, wizard-driven interface for defining experimental tasks, corresponding to the operations on the host computer 10 side in step S1 of the asynchronous multimodal electrochemical detection method. The interface interaction flow of the parameter configuration layer is as follows: The user first specifies the total number of channels N participating in the detection in the interface; the software dynamically generates N channel configuration units based on N. The user then independently selects an asynchronous multimodal electrochemical detection method (such as CV, CA, SWV, OCP, etc.) for each channel. The software automatically generates a corresponding parameter configuration table based on the selected method, listing all parameter items required for the method and their default values, which the user can modify one by one. In addition, the parameter configuration layer also provides "Start / Stop All" and "Start / Stop Specify Channel" buttons for generating and issuing corresponding control commands.

[0137] Understandably, the interface layout and functional elements of the parameter configuration layer can dynamically adapt to the number of channels activated by the user and the selected method. For example, when the user only enables 3 channels, the interface only displays 3 channel configuration units and 3 corresponding parameter tables, without displaying redundant configuration areas for inactive channels, thus simplifying the user configuration process for complex multi-channel experiments. In a preferred embodiment, the parameter configuration layer supports saving all configurations as experimental template files. Users can directly call the saved templates in subsequent experiments without reconfiguration, improving the preparation efficiency for repetitive experiments.

[0138] The data visualization layer features dynamic layout and multi-channel real-time rendering capabilities, corresponding to the display function on the host computer 10 side in step S4 of the asynchronous multimodal electrochemical detection method. Specifically, the data visualization layer automatically generates a corresponding number of curve display windows based on the number of activated channels, with each window independently displaying the real-time data stream of one channel. Each window clearly displays the channel number and the name of the currently executed detection method above it, and uses curves of different colors for intuitive differentiation.

[0139] In one specific embodiment, for a channel performing cyclic voltammetry (CV), the horizontal axis of the window displays potential (V) and the vertical axis displays current (μA), plotting a current-potential cycle curve in real time; for a channel performing chronoamperometry (CA), the horizontal axis of the window displays time (s) and the vertical axis displays current (μA), plotting a current-time response curve in real time; for a channel performing open-circuit potential (OCP), the horizontal axis of the window displays time (s) and the vertical axis displays potential (V), plotting a potential-time curve in real time. Users can independently zoom and pan any window to observe data details; operations between windows do not affect each other.

[0140] The intelligent analysis layer integrates a professional signal processing and data analysis algorithm library, providing general data preprocessing functions as well as specific analysis tools for different electrochemical methods.

[0141] General data preprocessing functions include algorithms such as data smoothing (e.g., Savitzky-Golay filtering) and denoising (e.g., wavelet denoising), applicable to all types of electrochemical curve data.

[0142] The specific analysis tools automatically match the corresponding analysis algorithm based on the electrochemical method being performed in the current channel. For example, for cyclic voltammetry (CV) curves, the intelligent analysis layer incorporates a baseline correction algorithm and an automatic redox peak identification algorithm, which can automatically calibrate the peak potential position, peak current height, and peak area. For square wave voltammetry (SWV) curves, the intelligent analysis layer incorporates a differential current extraction algorithm and a peak height / peak area calculation algorithm. The processing results can be displayed in real time overlaid on the original curve (e.g., peak positions are marked with markers or auxiliary lines) or presented in a separate results window.

[0143] Understandably, the intelligent analysis layer transfers a large number of computationally intensive data post-processing tasks from the lower-level machine 20 to the more powerful upper-level machine 10, reducing the real-time computing burden on the main control module 21 of the lower-level machine 20. The main control module 21 is only responsible for the underlying data acquisition, range adjustment, and data reporting, while complex signal processing algorithms (such as peak identification and baseline fitting) are completed by the processor of the upper-level machine 10, thus achieving a reasonable distribution of computing load between the upper-level machine 10 and the lower-level machine 20.

[0144] The data storage module is responsible for the full lifecycle management of experimental data. Specifically, the data storage module supports real-time high-speed recording of data during the experiment, writing the raw acquisition data from each channel to local storage files in timestamp order; it supports complete playback and traceability of historical data after the experiment, allowing users to retrieve complete data from any historical experiment, redraw curves in the data visualization layer, and perform secondary analysis; it also supports users to export raw data, processing results, and charts in various common formats (such as CSV and Excel) for easy archiving, report generation, and in-depth analysis.

[0145] Reference Figure 10 , Figure 10 This document illustrates the operation flowchart of the host computer 10 software provided in an embodiment of this application. The flowchart, from the perspective of the user on the host computer 10, fully demonstrates the interactive logic from software startup to the end of the detection process.

[0146] like Figure 10 As shown, the operation flow of the host computer software 10 includes the following stages: Device connection phase. After the host computer 10 software starts, it first completes the connection between the host computer 10 and the hardware circuit board of the slave computer 20 according to the different communication methods (wired USB or wireless Bluetooth). This step is executed by the device management layer of the host computer 10 software system. Specifically, the device management layer automatically searches for available communication ports, identifies and establishes a communication link with the slave computer 20.

[0147] Channel and Method Configuration Phase. After the connection is established, the user configures the number of channels through the parameter configuration layer, specifying the total number N channels participating in the detection in this experiment. The software automatically generates channels that can be configured for method based on the number of activated channels, that is, dynamically generates N channel configuration units. The user independently selects an asynchronous multimodal electrochemical detection method for each channel (corresponding to the generation process of the independent configuration command in step S1). Subsequently, the software automatically generates the corresponding electrochemical parameter configuration table based on the number of activated channels and the method, allowing the user to fill in or modify the specific electrochemical parameters of each channel.

[0148] Command issuance and interface preparation phase. After configuration, the host computer 10 packages the data according to the data transmission protocol and sends it to the slave computer 20 (corresponding to the issuance process of the independent configuration command in step S1). At the same time, it automatically generates a corresponding number of curve display windows according to the number of activated channels (executed by the data visualization layer). After the interface is ready, it waits for the user to click the start button.

[0149] Data acquisition and real-time display stage. For example... Figure 10As shown, the system determines whether the user clicks the batch start test button or the start button for a single channel: if not, the system continues to wait; if so, the host computer 10 sends the corresponding start command to the slave computer 20, and then enters the real-time data reception and display loop. In this loop, the host computer 10 receives data from the slave computer 20 in real time (corresponding to the process of the slave computer 20 transmitting current data in step S4) and displays it in the corresponding window; the curve window interface of the data visualization layer draws and updates the detection curves of each channel in real time.

[0150] It stops at the data analysis stage. For example... Figure 10 As shown, the system determines whether the user clicks the "End Batch" or "End Single Channel" button: if not, the system continues to receive and display real-time data; if so, the host computer 10 sends an end signal to the slave computer 20 and stops receiving data. After completion, the user can selectively perform data analysis operations. Figure 10 As shown, the system determines whether the user clicks the data correction button: if not, the data analysis step is skipped; if so, the intelligent analysis layer performs data processing (such as baseline correction, peak identification, etc.) for different electrochemical methods and the data processing method selected by the user.

[0151] Data storage stage. For example... Figure 10 As shown, the system determines whether the user clicks the data storage button: if not, the process proceeds directly to the end stage; if so, the data storage module stores the data according to the user-specified data storage mode (such as exporting in CSV format or archiving in a database). After storage is complete, the user can choose to end the test or start a new round of data testing.

[0152] Understandable Figure 10 The operation process of the host computer 10 shown is as follows: Figure 8 The operation flow of the lower-level machine 20 shown is coordinated in timing: the channel and method configuration stage of the upper-level machine 10 ( Figure 10 The corresponding instruction receiving and configuration stage of the lower-level machine 20 () Figure 8 ); Data acquisition and real-time display stage after the host computer clicks the start button ( Figure 10 The corresponding data acquisition and range adjustment cycle stage after the lower-level machine 20 receives the start command ( Figure 8 ); The host computer clicks the end button ( Figure 10 After receiving the end command, the corresponding lower-level machine 20 exits the acquisition loop. Figure 8 The two communicate through the communication interface module 24 to achieve full-process command and data interaction, together forming a complete electrochemical detection system workflow.

[0153] The following example, using a specific multi-indicator parallel detection scenario, illustrates the collaborative workflow of the host computer 10, the slave computer 20, and the modular adapter 30.

[0154] In this embodiment, the user needs to test four different samples simultaneously: Sample 1 is characterized by cyclic voltammetry (CV), Sample 2 is quantified by chronoamperometry (CA), Sample 3 is detected by square wave voltammetry (SWV) for trace heavy metal ions, and Sample 4 is monitored by open circuit potential (OCP) to detect the open circuit potential of the electrode.

[0155] First, the user inserts four miniature sensors 50 into the connectors 32 of four modular adapters 30, adds the corresponding electrolyte to be tested to the miniature cells 34 of each adapter board, and then clamps the alligator clips of the potentiostat host onto the conductive terminals 33 of the four adapter boards. When the conductive terminal 33 of the first adapter board is connected to the sensor interface module 23 through the alligator clip, the hardware monitoring module 40 detects a change in electrical characteristics, triggering a hardware interrupt in the main control module 21 (microcontroller), and the system wakes up from low-power standby mode.

[0156] After the system wakes up, the user configures the total number of channels to 4 in the parameter configuration interface of the host computer 10 software, and selects the CV method for channel 1, the CA method for channel 2, the SWV method for channel 3, and the OCP method for channel 4, and then fills in the corresponding electrochemical parameters for each channel. After the configuration is completed, the host computer 10 sends the channel configuration package and parameter configuration package to the slave computer 20.

[0157] After receiving the data packet, the lower-level computer 20 forwards it to the processing task via a message queue. The processing task parses the instructions and writes the configuration parameters of each channel into the control registers corresponding to channels 1 to 4 of the first analog front-end chip via the SPI bus. Simultaneously, the upper-level computer 10's data visualization layer generates four curve display windows.

[0158] The user clicks the "Start All" button on the host computer 10 interface, and the host computer 10 issues a "Start All" control command. After receiving the command, the slave computer 20 simultaneously enters the acquisition cycle for all four channels. The acquisition task is executed periodically with the highest priority: for channels 1 (CV) and 3 (SWV), the DAC output excitation waveform is controlled via SPI at a higher frequency, and the ADC current data is read through the first DMA path; for channels 2 (CA) and 4 (OCP), the same operation is performed at a lower frequency.

[0159] During data acquisition, assuming the glucose concentration in channel 2 is high, resulting in a large response current exceeding 80% of the ADC's full-scale reading (upper limit threshold) under the current PGA gain setting, the acquisition task detects this and reduces the PGA gain of channel 2 from the current 8x to 4x (switching to a larger range) via the SPI bus. After the PGA stabilizes, data from channel 2 is reacquired, and the new data is marked as valid once it falls within the safe range. During this process, data acquisition from channels 1, 3, and 4 remains unaffected; the PGA gain of each channel is configured independently, and the range adjustment operation only applies to channel 2.

[0160] The valid data from each channel is packaged into data frames and transmitted back to the host computer 10 via the UART interface through the second DMA path. The data visualization layer of the host computer 10 parses the data frames in real time and plots the data of each channel in the corresponding curve window: the window for channel 1 displays the CV curve, the window for channel 2 displays the CA curve, the window for channel 3 displays the SWV curve, and the window for channel 4 displays the OCP curve.

[0161] During the testing process, if the user wishes to perform real-time data analysis on the SWV curve of channel 3, they can click the "Data Correction" button in the channel 3 window. The intelligent analysis layer of the host computer 10 will automatically call the differential current extraction and peak recognition algorithm dedicated to SWV to process the real-time curve of channel 3 and overlay and annotate the results such as peak potential and peak current on the curve.

[0162] Once the preset time for OCP monitoring in channel 4 has elapsed, the user can click the "Stop Channel 4" button to stop data acquisition for channel 4 only, while the other channels continue to run. After all tests are completed, the user can click the "Stop All" button to terminate the acquisition cycle. The user can then export all experimental data to their local computer in CSV format via the data storage module.

[0163] It should be noted that the above-described 4-channel parallel detection scenario is merely an illustrative example. In a preferred embodiment, the system can support up to 8 channels running the second type of method simultaneously (e.g., 8-channel CA for high-throughput glucose concentration screening in parallel), or up to 2 channels running the first type of method simultaneously in conjunction with the remaining channels running the second type of method (e.g., a hybrid detection mode of 2-channel CV plus 6-channel CA). Users can flexibly combine these methods according to their actual detection needs.

[0164] Furthermore, the multi-channel potentiostat system of this application is not limited to the above-mentioned eight-channel implementation. By increasing the number of analog front-end chips on the SPI bus and assigning an independent chip select line to each new chip, the number of detection channels of the system can be linearly expanded to twelve, sixteen, or more channels. The expanded system only requires adding SPI read / write operations for the new chips in the acquisition task at the embedded software level, and only requires adding corresponding channel configuration units and curve display windows at the host computer software level. The basic design concept and data flow logic of the system architecture remain unchanged.

[0165] It should be noted that the specific values ​​of the parameters in the above embodiments (such as 16-bit ADC, 12-bit DAC, PGA gain levels, upper threshold of 80%, lower threshold of 20%, N=8, M=2, etc.) are preferred exemplary values ​​used to help understand the technical solution of this application. In other embodiments, the above parameters can be adjusted according to factors such as the actual selected analog front-end chip model, microcontroller performance, and application scenario requirements, as long as they meet the functional relationships and logical constraints defined in this application. The above specific values ​​should not be construed as limitations on the scope of protection of this application.

[0166] This application also discloses the product form of a lower-level machine 20 of a multi-channel potentiostat system.

[0167] In one embodiment, the lower-level machine 20 includes a housing, a circuit board disposed within the housing, and the aforementioned circuit modules integrated on the circuit board. The housing may be made of injection-molded engineering plastic or aluminum alloy, and has dustproof and splashproof functions, protecting the internal circuitry from the influence of liquids and dust in the detection environment. The circuit board integrates all hardware modules such as a microcontroller, an analog front-end chip array, a Bluetooth communication module, a power management circuit, and a sensor interface module 23. In a preferred embodiment, the size of the entire circuit board is approximately 12cm × 12cm, and the overall size of the housing can be controlled within the range of portable handheld devices, meeting the portability requirements for on-site real-time detection.

[0168] The housing features an exposed connector (such as an aviation socket) for the sensor interface module 23, a USB port, a power switch, and status indicator lights. The aviation socket is used to connect alligator clip adapter cables or modular adapters 30; the USB port is used for wired data communication and device charging; and the status indicator lights indicate the device's operating status (such as standby, running, charging, low battery, etc.).

[0169] Understandably, by highly integrating the aforementioned multi-channel detection hardware, embedded software, and communication modules into a single portable casing, a complete detection system is formed, encompassing signal sensing, real-time processing, wireless transmission, and intelligent analysis. Compared to traditional benchtop electrochemical workstations, this product form, while retaining multi-channel parallel detection capabilities and high-precision measurement performance, achieves miniaturization and portability, extending laboratory-level electrochemical analysis capabilities to non-laboratory scenarios such as field environmental monitoring, point-of-care testing, and industrial production line quality inspection.

[0170] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. An asynchronous multimodal electrochemical detection method, characterized in that, The method is applied to a multi-channel potentiostat system, which includes a host computer (10) and a slave computer (20) that communicate with each other. The slave computer (20) includes a main control module (21) and an analog channel array (22). The main control module (21) includes a multi-task scheduling kernel, and the analog channel array (22) includes multiple detection channels. The asynchronous multimodal electrochemical detection method includes the following steps: S1. The host computer (10) receives independent configuration instructions for N detection channels and sends the independent configuration instructions to the slave computer (20). The independent configuration instructions corresponding to each detection channel are independent of each other and are used to set the electrochemical detection method and corresponding parameters of the corresponding channel. N is an integer greater than 1. S2. The lower-level machine (20) parses the independent configuration instruction based on the multi-task scheduling kernel and independently configures the working mode of the multiple detection channels; S3. After configuration, in response to the start command, the lower-level machine (20) reads the current data of the multiple detection channels in parallel through the hardware-level data transmission channel. During the reading process, the lower-level machine (20) performs real-time range adjustment based on the multi-task scheduling kernel: it determines whether the current data exceeds the preset safety range. If it exceeds the upper limit, the gain parameter of the corresponding channel is reduced. If it is lower than the lower limit, the gain parameter of the corresponding channel is increased, and the data is re-acquired based on the adjusted gain parameter. S4. The lower-level machine (20) transmits the current data back to the upper-level machine (10) for display and processing.

2. The asynchronous multimodal electrochemical detection method according to claim 1, characterized in that, Before performing step S1, the asynchronous multimodal electrochemical detection method further includes a system wake-up step: The multi-channel potentiostat system also includes a hardware monitoring module (40) and a modular adapter (30), and the lower-level machine (20) also includes a sensor interface module (23). In low-power standby mode, the hardware monitoring module (40) monitors changes in the electrical characteristics of the sensor interface module (23); When the conductive terminal (33) of the modular adapter (30) is connected to the sensor interface module (23), the electrical characteristic change is triggered, and the hardware monitoring module (40) triggers the hardware interrupt of the main control module (21) to wake up the lower-level machine (20); wherein, the modular adapter (30) includes a substrate (31), a connector (32) disposed at one end of the substrate (31) for adapting to the micro sensor (50), the conductive terminal (33) disposed at the other end of the substrate (31) for external clamping terminal clamping, and a micro cell (34) formed on the substrate (31) and located at the connector (32) for containing electrolyte.

3. The asynchronous multimodal electrochemical detection method according to claim 1, characterized in that, The main control module (21) runs a real-time operating system and creates and schedules multiple tasks with different priorities through the multi-task scheduling kernel. The multiple tasks include at least a data acquisition task, a processing task, and a communication task. The data acquisition task is configured with the highest priority and is used to perform data reading and real-time range adjustment in step S3. The processing task is used to parse the independent configuration instruction and configure the working mode. The communication task is used to perform data transmission in step S4.

4. The asynchronous multimodal electrochemical detection method according to claim 3, characterized in that, The real-time range adjustment step in step S3 includes: after the acquisition task completes a parallel reading of the current data of the multiple detection channels, if it is determined that the current data of a certain channel exceeds the safe range, a corresponding range adjustment command is generated; the execution of the corresponding range adjustment command and the update configuration of the corresponding channel gain parameter are both completed within the interval time when the hardware-level data transmission channel performs the next parallel reading operation.

5. The asynchronous multimodal electrochemical detection method according to claim 1, characterized in that, The hardware-level data transmission channel includes a first direct memory access channel and a second direct memory access channel integrated in the main control module (21); the first direct memory access channel is used to read data from the analog channel array (22), and the second direct memory access channel is used to send data to the host computer (10).

6. The asynchronous multimodal electrochemical detection method according to any one of claims 1-5, characterized in that, The asynchronous multimodal electrochemical detection method includes at least a first type of method that requires high-speed potential scanning and a second type of method that does not require high-speed potential scanning; during the execution of step S3, the lower-level machine (20) configures the upper limit of the number of channels that synchronously execute the second type of method to N, and configures the upper limit of the number of channels that synchronously execute the first type of method to a maximum of M, where M is less than N.

7. The asynchronous multimodal electrochemical detection method according to claim 6, characterized in that, During the execution of step S3, for the channel that synchronously executes the first type of method, the lower computer (20) controls the corresponding detection channel to output the excitation waveform at the first frequency and to collect the current data at the second frequency; For a channel that synchronously executes the second type of method, the lower-level machine (20) controls the corresponding detection channel to output an excitation waveform at a third frequency and to collect the current data at a fourth frequency; wherein, the first frequency is greater than the third frequency, and the second frequency is greater than the fourth frequency.

8. A multi-channel potentiostat system, characterized in that, include: Host computer (10); The lower-level machine (20) includes a main control module (21) and an analog channel array (22) connected to the main control module (21), wherein the main control module (21) is configured to perform the asynchronous multimodal electrochemical detection method as described in any one of claims 1-7; The sensor interface module (23) is connected to the analog channel array (22) and is used to access the micro sensor (50).

9. The multi-channel potentiostat system according to claim 8, characterized in that, The main control module (21) includes a microcontroller, and the analog channel array (22) includes at least two analog front-end chips. The microcontroller is connected to the at least two analog front-end chips through a shared data bus and an independent chip select channel.

10. The multi-channel potentiostat system according to claim 8, characterized in that, It also includes a modular adapter (30), which comprises: substrate(31); A connector (32) is disposed at one end of the substrate (31) for adapting to and electrically contacting the micro sensor (50). A conductive terminal (33) is disposed at the other end of the substrate (31). The conductive terminal (33) is electrically connected to the connector (32) through the interior of the substrate (31). The conductive terminal (33) is configured to provide an electrical contact surface that can be clamped by an external clamping terminal to connect to the sensor interface module (23) through the external clamping terminal. A microcell (34), formed on the substrate (31) and located at the connector (32), is used to contain electrolyte so that the electrolyte comes into contact with the microsensor (50).

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