A data processing method and related apparatus
By writing data into ECC memory for error detection and correction, the time overhead caused by instruction copying in existing technologies is solved, achieving efficient data protection and system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-22
- Publication Date
- 2026-06-12
Smart Images
Figure CN122195742A_ABST
Abstract
Description
[0001] This application is a divisional application. The original application has the application number 202110694352.1 and the original application date is June 22, 2021. The entire contents of the original application are incorporated herein by reference. Technical Field
[0002] This application relates to the field of computer technology, and in particular to a data processing method and related apparatus. Background Technology
[0003] Memory, an essential component of computer systems, typically exists in the form of memory modules across different system architectures. During system operation, memory can experience either hard failure or soft failure. Hard failure refers to unrecoverable data errors caused by hardware problems. Soft failure refers to data errors caused by data jumps that can be recovered from by power-on / power-off or a restart. To maintain normal system operation, it is usually necessary to detect and repair data errors caused by soft failures.
[0004] In related technologies, error detection methods based on instruction copying are primarily used to detect data errors introduced by soft failures. This method involves the compiler copying each original instruction to obtain a duplicate instruction, allocating different memory locations for the original and duplicate instructions. During instruction execution, if inconsistencies are detected between the original and duplicate instructions, a soft failure is considered to have occurred, and data repair is initiated.
[0005] However, because the original instructions need to be copied in the related technologies, the size of the final compiled program is increased, which in turn increases the runtime overhead of the program. Summary of the Invention
[0006] This application provides a data processing method that, by changing the target data, such as the instruction data of the program itself or the data generated during program execution, which is to be written to a specific memory area, to a memory with error checking and correction (ECC) function, the target data is protected by the memory with ECC function, thereby avoiding the execution of large-scale programs and effectively reducing the time overhead of program execution.
[0007] This application provides a data processing method applicable to threads running in a virtualization privileged layer. The method includes: the thread acquiring a first instruction. The first instruction may include the logical address of a first target region, and the first instruction instructs the writing of first data to the first target region in first memory. The first target region is a storage area on the first memory, which does not have error checking and correction (ECC) functions. The logical address of the first target region may be pre-configured on the thread. Therefore, during the execution of the first instruction by the terminal, the thread can intercept the first instruction based on the logical address of the first target region.
[0008] Then, the thread determines a second target region in the second memory according to the first instruction. The second target region is a storage area on the second memory, which has ECC functionality. Specifically, the thread can determine the second target region by searching for a memory region marked as a reserved memory region in the second memory; alternatively, after receiving the first instruction, the thread can allocate a memory region in the second memory as the second target region corresponding to the first target region. Alternatively, the thread can determine the second target region corresponding to the first target region based on a pre-established second mapping relationship. This second mapping relationship is pre-established and used to indicate the correspondence between the first and second target regions.
[0009] Finally, the thread writes the first data to the second target region. For example, the thread can modify the physical address mapped to the logical address of the first target region to the physical address of the second target region. In this way, when the terminal executes the first instruction, it will determine the physical address of the second target region mapped to it based on the logical address of the first target region in the first instruction, and thus write the first data in the first instruction to the second target region.
[0010] In this solution, a specific memory region on memory without ECC functionality is specified, and the target data to be stored in that specific memory region is instead stored in memory with ECC functionality. The memory with ECC functionality performs error detection and correction on the target data, avoiding the execution of large-scale programs and effectively reducing the time overhead during program execution.
[0011] In one possible implementation, if the thread searches for a memory region marked as a reserved memory region in the second memory to determine the second target region, or allocates a memory region in the second memory as the second target region corresponding to the first target region, the thread can also establish a mapping relationship between the first target region and the second target region to facilitate subsequent data reading or writing.
[0012] Specifically, the method further includes: a thread establishing a first mapping relationship between the second target region and the first target region, the first mapping relationship being used to indicate data reading or writing. The first mapping relationship established by the thread between the second target region and the first target region can actually be a mapping relationship between the logical address of the first target region and the physical address of the second target region.
[0013] By establishing a first mapping relationship between the second target area and the first target area, it is possible to ensure that data can be written to the second target area or read from the second target area when an instruction to write data to the first target area or read data from the first target area is subsequently received.
[0014] In one possible implementation, the method further includes: the terminal acquiring a second instruction, the second instruction being used to instruct the reading of data in the first target area, i.e., the second instruction carrying the logical address of the first target area. Then, the terminal reads the first data in the second target area according to the aforementioned relationship and the second instruction. That is, the terminal can determine, based on the aforementioned first mapping relationship, that the physical address corresponding to the logical address of the first target area in the second instruction is the physical address of the second target area, and therefore the terminal reads the first data from the second target area.
[0015] In one possible implementation, the method further includes: the terminal obtaining a third instruction, the third instruction being used to instruct the writing of second data to the first target region, i.e., the third instruction also carries the logical address of the first target region. Then, the terminal can write the second data indicated in the third instruction to the second target region according to the aforementioned first mapping relationship and the third instruction. That is, the terminal can determine, based on the aforementioned first mapping relationship, that the physical address corresponding to the logical address of the first target region in the third instruction is the physical address of the second target region, and therefore the terminal writes the second data to the second target region.
[0016] In one possible implementation, before writing the first data to the second target area, the method further includes: if there is no free storage space in the second target area, the thread moves the third data out of the second target area.
[0017] By moving the third data out of the second target area, it can be ensured that the second target area has enough space to store the first data.
[0018] In one possible implementation, the thread moving the third data out of the second target area includes: the thread writing the third data from the second target area into the first target area and a backup area, wherein the backup area has a first mapping relationship with the first target area and the backup area is located in memory without ECC function; and the thread deleting the third data in the second target area.
[0019] The first target region and the backup region can reside in the same memory location, or they can reside in different memory locations. Furthermore, neither the first target region nor the backup region has ECC functionality. After the terminal is configured with a first target region that requires error detection, the thread can allocate a backup region corresponding to the first target region in memory that lacks ECC functionality to back up the data stored in the first target region.
[0020] In this solution, when there is no free storage space in the second target area, the data in the second target area is moved to the first target area and the backup area. The first target area and the backup area then perform error detection on the data, ensuring that error detection can be performed on the data in memory and guaranteeing the reliability of system operation. Furthermore, using the first target area and the backup area for error detection also avoids executing larger programs, thereby reducing the memory usage of the program during runtime.
[0021] In one possible implementation, the third data is determined according to the Least Recently Used (LRU) algorithm.
[0022] In one possible implementation, the method further includes: a thread acquiring a fourth instruction, the fourth instruction being used to instruct the reading of the third data; the thread reading data in the first target area and data in the backup area based on the fourth instruction; if the data in the first target area and the data in the backup area are the same, then the thread returning the data in the first target area.
[0023] A second aspect of this application provides a data processing method, comprising: obtaining a fifth instruction, the fifth instruction being used to instruct the writing of target data into a first region; determining a second region according to the fifth instruction; and writing the target data into the first region and the second region.
[0024] In this solution, data is written to both the first and second regions simultaneously to detect data errors. This avoids the execution of larger programs, thereby reducing the memory usage of the program during runtime.
[0025] In one possible implementation, the method further includes: obtaining a sixth instruction, the sixth instruction being used to instruct the reading of data in the first region; reading data in the first region and data in the second region according to the sixth instruction; if the data in the first region is the same as the data in the second region, then returning the data in the first region; if the data in the first region is the same as the data in the second region, then determining that a data error has occurred.
[0026] A third aspect of this application provides a data processing apparatus, including an acquisition unit and a processing unit; the acquisition unit is configured to acquire a first instruction, the first instruction being configured to instruct the writing of first data to a first target region, the first target region being a storage region on a first memory, the first memory not having error checking and correction (ECC) functions; the processing unit is configured to determine a second target region in a second memory according to the first instruction, the second target region being a storage region on a second memory, the second memory having ECC functions; the processing unit is further configured to write the first data to the second target region.
[0027] In one possible implementation, the processing unit is further configured to establish a first mapping relationship between the second target region and the first target region, the first mapping relationship being used to indicate the reading or writing of data.
[0028] In one possible implementation, the acquisition unit is further configured to acquire a second instruction, the second instruction being used to instruct the reading of data in the first target area; the processing unit is further configured to read the first data in the second target area according to the first mapping relationship and the second instruction.
[0029] In one possible implementation, the acquisition unit is further configured to acquire a third instruction, the third instruction being used to instruct the writing of second data to the first target region; the processing unit is further configured to write the second data to the second target region according to the first mapping relationship and the third instruction.
[0030] In one possible implementation, the processing unit is further configured to determine the second target region in the second memory according to the first instruction and a preset second mapping relationship; the second mapping relationship is used to indicate that the first target region corresponds to the second target region.
[0031] In one possible implementation, the processing unit is further configured to remove the third data from the second target area if there is no free storage space in the second target area.
[0032] In one possible implementation, the processing unit is further configured to write the third data in the second target area into the first target area and the backup area, wherein the backup area has a first mapping relationship with the first target area and the backup area is located in memory without ECC function; the processing unit is further configured to delete the third data in the second target area.
[0033] In one possible implementation, the third data is determined according to the Least Recently Used (LRU) algorithm.
[0034] In one possible implementation, the acquisition unit is further configured to acquire a fourth instruction, the fourth instruction being used to instruct the reading of the third data; the processing unit is further configured to read data in the first target area and data in the backup area based on the fourth instruction; the processing unit is further configured to return the data in the first target area if the data in the first target area and the data in the backup area are the same.
[0035] In one possible implementation, the apparatus is applied to a thread running in a virtualization privileged layer, the thread being used to retrieve the first instruction based on the address of the first target region.
[0036] A fourth aspect of this application provides a data processing apparatus, comprising: an acquisition unit and a processing unit; the acquisition unit is configured to acquire a fifth instruction, the fifth instruction being configured to instruct the writing of target data into a first region; the processing unit is configured to determine a second region according to the fifth instruction; the processing unit is further configured to write the target data into the first region and the second region.
[0037] In one possible implementation, the acquisition unit is further configured to acquire a sixth instruction, the sixth instruction being used to instruct the reading of data in the first region; the processing unit is further configured to: read data in the first region and data in the second region according to the sixth instruction; if the data in the first region is the same as the data in the second region, then return the data in the first region; if the data in the first region is the same as the data in the second region, then determine that a data error has occurred.
[0038] The fifth aspect of this application provides a terminal, the terminal comprising: a memory and a processor; the memory storing code, the processor being configured to execute the code, wherein when the code is executed, the terminal performs a method as implemented in either the first or second aspect.
[0039] The sixth aspect of this application provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform a method as implemented in either the first or second aspect.
[0040] The seventh aspect of this application provides a computer program product that, when run on a computer, causes the computer to perform a method as described in either the first or second aspect.
[0041] An eighth aspect of this application provides a chip including one or more processors. Part or all of the processors are configured to read and execute a computer program stored in memory to perform the methods in any possible implementation of any of the preceding aspects.
[0042] Optionally, the chip includes a memory, which is connected to the processor via a circuit or wire. Optionally, the chip also includes a communication interface, to which the processor is connected. The communication interface is used to receive data and / or information that needs to be processed. The processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. The communication interface can be an input / output interface. The method provided in this application can be implemented by a single chip or by multiple chips working together. Attached Figure Description
[0043] Figure 1 A schematic diagram of the system software layer related to the exception level provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a terminal 101 provided in an embodiment of this application; Figure 3 A flowchart illustrating a data processing method 300 provided in an embodiment of this application; Figure 4 A schematic diagram illustrating how an HBED thread stores first data based on a first instruction, provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the HBED thread storing data in the buffer pool according to an embodiment of this application. Figure 6 This is a schematic diagram illustrating the storage of data from an application / operating system to a buffer pool, as provided in an embodiment of this application. Figure 7 This is a schematic diagram illustrating the process of moving data out of a second target region, as provided in an embodiment of this application. Figure 8 A flowchart illustrating a data processing method 800 provided in an embodiment of this application; Figure 9A schematic diagram illustrating how an HBED thread stores target data based on a fifth instruction, as provided in an embodiment of this application; Figure 10 This is a schematic diagram of the HBED thread reading data provided in an embodiment of this application; Figure 11 This is a schematic diagram of the structure of a data processing device 1100 provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of a computer-readable storage medium 1200 provided in an embodiment of this application. Detailed Implementation
[0044] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will recognize, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0045] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved.
[0046] For ease of understanding, the technical terms involved in the embodiments of this application will be introduced below.
[0047] Soft Failure: Soft failure is a hardware transient fault phenomenon induced by factors such as high-energy particle irradiation, voltage disturbances, and geomagnetic interference in the external environment. When high-energy subatomic particles pass through silicon in the storage units (flip-flops, register units, or random access memory units) of very large-scale integrated circuits, free charges are generated. These charges accumulate in circuit nodes within a very short time interval (about 15 ps). When the charge accumulation exceeds a certain level, the stored data changes, causing the system to malfunction. Since the damage to the circuit is not permanent, this phenomenon is called soft failure or soft error. Soft failure may be caused by cosmic rays, Boron fission, Alpha rays, system noise, or electromagnetic interference, etc.
[0048] Soft failure does not damage the internal structure of the circuit, but it can affect the normal operation of the program by changing the processor state or the value of the storage unit, etc., thus seriously affecting the system reliability. With the development of integrated circuit manufacturing technology, while the performance of modern microprocessors has been greatly improved, the threat of soft failure is becoming more and more serious. For example, sudden electronic interference near the memory and other factors may cause the occurrence of memory soft failure.
[0049] Exception Level (EL): The concept of exception level was first introduced in the processor architecture ARMv8, and each exception level represents a different privilege level. Please refer to Figure 1 , Figure 1 for the schematic diagram at the system software level related to the exception level provided in the embodiments of this application. As Figure 1 shown, the processor has different exception levels during operation. Among them, the user level is represented by EL0; the privileged level is represented by EL1; the Hypervisor level is represented by EL2, which is used for the mode to implement virtualization technology; the Monitor mode is represented by EL3. And the privileges of EL0, EL1, EL2, and EL3 are different, and the order of privilege sizes is: EL0 < EL1 < EL2 < EL3. Generally speaking, EL0 represents the user space layer and is used to run application programs; EL1 represents the operating system layer and is used to run the operating system; EL2 represents the virtualization privilege layer and is used to run virtual machines; EL3 represents the security monitoring layer and is used to implement the switching between the secure state and the non-secure state.
[0050] Virtualization Technology: Virtualize the resources of a physical computer into multiple logical computers. Different operating systems and application programs can run in each logical computer without affecting each other, so as to make full use of hardware resources.
[0051] A hypervisor is software used to create and execute virtual machines, running at the virtualization privilege tier. A hypervisor is software that runs directly on the physical hardware; its function is to manage the physical hardware so that different virtual machines can share physical resources (such as processors, memory, and peripherals). Because the hypervisor directly interfaces with physical resources, it needs to run at the virtualization privilege tier. A hypervisor running at the virtualization privilege tier can manage all software programs running in both user space and the operating system layer.
[0052] Error checking and correction (ECC): A technology that enables error checking and correction. ECC can correct single-bit or multi-bit errors in memory and is computationally fast. This allows for the tolerance and correction of errors in memory, enabling the system to continue operating normally without interruption due to errors.
[0053] ECC (Error Correction Control) evolved from parity checking. In digital circuits, the smallest unit of data is called a bit, also known as a data bit. A bit is the smallest unit in memory, and bits use "1" and "0" to represent high and low level signals. In digital circuits, eight consecutive bits make up a byte. In memory without parity checking, each byte has only eight bits. If an error occurs in one of its bits, the corresponding data stored in it will change, causing errors in the application. Memory with parity checking adds an extra bit to each byte (8 bits) for error detection. For example, if a byte stores a value (1, 0, 1, 0, 1, 0, 1, 1), and these bits are added together (1+0+1+0+1+0+1+1=5), 5 is an odd number. If odd parity is used (i.e., the sum of the 9 corresponding bits in the byte (8 bits) plus the error-checking bit is odd), then the error-checking bit should be 0 (5+0=5 is odd). If even parity is used (i.e., the sum of the 9 corresponding bits in the byte (8 bits) plus the error-checking bit is even), then the error-checking bit should be 1 (5+1=6 is even). When the processor returns to read the stored data, it will add the data stored in the first 8 bits again and check if the result matches the parity bit. When the processor finds a difference, it will attempt to correct these errors.
[0054] Parity checking checks the correctness of 8 data bits by adding a parity bit to the original data bits. However, as the number of data bits increases, the number of parity bits also increases exponentially; eight data bits require one parity bit, and sixteen data bits require two parity bits. ECC also adds a parity bit to the original data bits. Unlike parity checking, ECC requires 5 additional bits for error checking and correction if the data bits are 8 bits. For every doubling of the data bits, ECC only adds one parity bit. That is, when the data bits are 16 bits, the ECC bits are 6; with 32 bits, they are 7; with 64 bits, they are 8, and so on—each doubling of the data bits only adds one ECC bit. ECC has more parity bits, resulting in stronger fault tolerance.
[0055] ECC memory: This refers to memory that utilizes ECC technology. ECC memory has ECC functionality and is commonly used in servers and graphics workstations to improve the reliability of computer operation.
[0056] Logical address: In computer architecture, this refers to the address of a memory location as seen from the application's perspective. Logical addresses often differ from physical addresses. Address translators or mapping functions can convert logical addresses to physical addresses. In computers with address translation capabilities, the address given by instructions accessing memory is often called the logical address, also known as the relative address. Generally, based on the logical address, calculations or transformations using addressing modes are needed to obtain the actual effective address in memory, i.e., the physical address.
[0057] Physical address: refers to the address signal that appears in physical memory, and is the final address resulting from address translation. The physical address is actually the actual address in memory.
[0058] In related technologies, error detection based on instruction copying is primarily used to detect data errors introduced by soft failures. This method involves the compiler copying each original instruction during the program compilation phase, creating duplicate instructions, and allocating different memory locations for the original and duplicate instructions. During compilation, the compiler needs to copy the original instructions and rearrange their positions to allow for parallel execution of both. If, during instruction execution, the processor detects inconsistencies between the original and duplicate instructions, it considers a soft failure to have occurred and initiates data repair.
[0059] Clearly, because these technologies require copying the original instructions, the size of the final compiled program is increased, leading to increased runtime overhead. Furthermore, since these technologies involve copying and rearranging instructions during the compilation phase, they impose intrusive modifications on the program and cannot protect the already compiled code.
[0060] In view of this, embodiments of this application provide a data processing method that, by changing the target data, such as the instruction data of the program itself or the data generated during program execution, which is to be written to a memory with error checking and correction (ECC) function, the target data is protected by the memory with ECC function, avoiding the execution of large-scale programs and reducing the time overhead of program execution.
[0061] The terminal involved in the embodiments of this application may include memory with ECC function and memory without ECC function. Exemplarily, the terminal may be a personal computer (PC), laptop computer, server, mobile phone, tablet computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. The terminal may be a device running Android, iOS, Windows, or other systems. For ease of understanding, the data processing method provided in the embodiments of this application will be described below using a smartphone as an example.
[0062] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a terminal 101 provided in an embodiment of this application. Figure 2As shown, terminal 101 includes a processor 103, which is coupled to a system bus 105. The processor 103 can be one or more processors, each of which can include one or more processor cores. A video adapter 107 drives a display 109, which is coupled to the system bus 105. The system bus 105 is coupled to an input / output (I / O) bus via a bus bridge 111. An I / O interface 115 is coupled to the I / O bus. The I / O interface 115 communicates with various I / O devices, such as input devices 117 (e.g., touchscreens), external storage 121 (e.g., hard disks, floppy disks, optical disks, or USB flash drives), multimedia interfaces, etc. A transceiver 123 (capable of sending and / or receiving radio communication signals), a camera 155 (capable of capturing still and moving digital video images), and an external USB port 125. Optionally, the interface connected to the I / O interface 115 can be a USB interface.
[0063] The processor 103 can be any conventional processor, including a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, or a combination thereof. Optionally, the processor can be a special-purpose device such as an ASIC.
[0064] Terminal 101 can communicate with software deployment server 149 via network interface 129. Exemplarily, network interface 129 is a hardware network interface, such as a network interface card (NIC). Network 127 can be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (VPN). Optionally, network 127 can also be a wireless network, such as a WiFi network or a cellular network.
[0065] Hard disk drive interface 131 is coupled to system bus 105. Hardware driver interface is connected to hard disk drive 133. Memory 135 is coupled to system bus 105. Data running in memory 135 may include operating system (OS) 137, application program 143, and scheduling table of terminal 101. Memory 135 includes memory with ECC capability (i.e., ECC memory 1351) and memory without ECC capability (i.e., non-ECC memory 1352). Hypervisor and threads running in the virtualization privileged layer can be deployed on memory with ECC capability, while operating system (OS) 137 and application program 143 can be deployed on memory without ECC capability.
[0066] An operating system consists of the Shell 139 and the kernel 141. The Shell 139 is an interface between the user and the operating system kernel. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input for the operating system, and processing various operating system outputs.
[0067] Kernel 141 consists of the parts of the operating system used to manage memory, files, peripherals, and system resources. Kernel 141 interacts directly with the hardware. The operating system kernel typically runs processes and provides inter-process communication, CPU time-slice management, interrupts, memory management, I / O management, and so on.
[0068] For example, when terminal 101 is a smartphone, application 143 includes instant messaging related programs. In one embodiment, when application 143 needs to be executed, terminal 101 can download application 143 from software deployment server 149.
[0069] Please refer to Figure 3 , Figure 3 This is a flowchart illustrating a data processing method 300 provided in an embodiment of this application. Figure 3 As shown, the data processing method 300 includes the following steps 301-303.
[0070] Step 301: Obtain a first instruction, which is used to instruct the writing of first data to a first target area, the first target area being a storage area on a first memory, and the first memory not having ECC functionality.
[0071] In this embodiment, the data processing method 300 can be applied to a thread running in the virtualization privileged layer, which can be, for example, called a Hypervisor-based error detection (HBED) thread. The Hypervisor and HBED threads running in the virtualization privileged layer can be deployed on memory with ECC functionality to ensure the reliability of the Hypervisor and HBED threads during operation. The operating system and applications in the terminal both run in virtual machines managed by the Hypervisor.
[0072] During the execution of an application, the processor in the terminal executes a first instruction. This first instruction may include the logical address of a first target region, and is used to instruct the writing of first data to the first target region in first memory.
[0073] Generally, during application execution on a terminal, the operating system first loads the application's instruction code from the hard drive into memory, and then the terminal's processor executes the application's instruction code in memory. For example, the first instruction can be an instruction from the operating system, and this first instruction instructs the writing of the application's instruction code to a first target area; that is, the first data indicated in the first instruction is the application's instruction code. Alternatively, the first instruction can be an instruction from the application itself, and this first instruction instructs the writing of data generated by the application to the first target area; that is, the first data indicated in the first instruction is data generated by the application during its runtime.
[0074] Before executing the first instruction, the HBED thread in the terminal can pre-configure the logical address of the first target region. The first target region is a storage area on first memory without ECC functionality, and it is configured as a protected object, meaning the data in the first target region requires soft failure detection. Therefore, during the execution of the first instruction, the HBED thread can intercept the first instruction based on the logical address of the first target region. For example, a user can configure a memory region as the first target region in a user configuration file, such as a device tree blob (DTB), so that the HBED thread can obtain the logical address of the first target region. Specifically, the user can configure a memory region as the first target region by specifying the start address and size of the memory region; or, the user can configure a memory region as the first target region by specifying the start and end addresses of the memory region.
[0075] Step 302: Determine a second target region in the second memory according to the first instruction. The second target region is a storage region on the second memory, and the second memory has ECC functionality.
[0076] Since the first data to be written to the first target area requires soft error detection, the HBED thread in the terminal can determine the second target area in the second memory based on the first target area indicated in the first instruction, so as to write the first data to the second target area. The second target area is a storage area on the second memory with ECC functionality. Therefore, when writing the first data to the second target area, error detection and correction of the first data can be achieved by the second memory with ECC functionality.
[0077] In one possible implementation, the terminal can reserve a memory region in the second memory (i.e., the aforementioned second target region) to store data to be written to the first target region. For example, the terminal marks the reserved second target region in the second memory. Thus, after receiving a first instruction to write data to the first target region, the HBED thread can determine the second target region corresponding to the first target region in the second memory. For example, the HBED thread searches for a memory region marked as a reserved memory region in the second memory and uses this memory region as the second target region.
[0078] In another possible implementation, the HBED thread may allocate a memory region in the second memory as the second target region corresponding to the first target region after receiving the first instruction, so as to store the data to be written to the first target region.
[0079] In another possible implementation, the HBED thread can determine the second target region corresponding to the first target region based on a pre-defined second mapping relationship. This second mapping relationship is established in advance to indicate the correspondence between the first and second target regions.
[0080] Step 303: Write the first data into the second target area.
[0081] In one possible implementation, after the HBED thread in the terminal determines the second target region corresponding to the first target region, the HBED thread can modify the physical address mapped to the logical address of the first target region to the physical address of the second target region. Thus, after the address mapping is modified, the logical address of the first target region is mapped to the physical address of the second target region. Therefore, when the terminal executes the first instruction, it determines the physical address of the second target region mapped to it based on the logical address of the first target region in the first instruction, and then writes the first data from the first instruction into the second target region.
[0082] For example, see Figure 4 , Figure 4 This is a schematic diagram illustrating how an HBED thread stores first data based on a first instruction, as provided in an embodiment of this application. Figure 4As shown, during the execution of the application, the processor in the terminal executes a first instruction in the application. This first instruction carries a logical address and first data, instructing the data to be stored in the region corresponding to that logical address. The logical address in the first instruction points to a first target region in first memory. The HBED thread has a pre-configured logical address for the entire first target region, allowing it to intercept the first instruction corresponding to the application based on the logical address of the first target region. Furthermore, the HBED thread modifies the physical address corresponding to the logical address carried in the first instruction to the physical address of a second target region in second memory. Thus, when the terminal executes the first instruction, it can map the logical address in the first instruction to the physical address of the second target region in second memory, thereby storing the first data in the second target region of second memory.
[0083] In this embodiment, by specifying a specific memory region on memory without ECC functionality, and changing the target data to be stored in that specific memory region to be stored in memory with ECC functionality, the memory with ECC functionality can perform error detection and correction on the target data, thus avoiding the execution of large-scale programs and effectively reducing the time overhead of program execution.
[0084] In one possible embodiment, if the thread searches for a memory region marked as a reserved memory region in the second memory to determine the second target region, or allocates a memory region in the second memory as the second target region corresponding to the first target region, the thread can also establish a mapping relationship between the first target region and the second target region to facilitate subsequent data reading or writing.
[0085] Specifically, after the HBED thread determines the second target region in the second memory according to the first instruction, the HBED thread can also establish a first mapping relationship between the second target region and the first target region. The first mapping relationship is used to indicate whether data is read or written. By establishing the first mapping relationship between the second target region and the first target region, it is guaranteed that when an instruction to write data to the first target region or read data from the first target region is subsequently received, it can be ensured that data can be written to the second target region or read from the second target region.
[0086] Specifically, the first mapping relationship established by the HBED thread between the second target region and the first target region can actually be a mapping relationship between the logical address of the first target region and the physical address of the second target region. Thus, after the HBED thread establishes the first mapping relationship between the logical address of the first target region and the physical address of the second target region, when the terminal subsequently executes instructions carrying the logical address of the first target region, it can determine the physical address of the second target region corresponding to the logical address of the first target region based on the established first mapping relationship, thereby performing data writing or reading in the second target region.
[0087] In one possible example, after the HBED thread establishes a first mapping relationship between the second target region and the first target region, the terminal obtains a second instruction. This second instruction instructs the reading of data from the first target region; that is, the second instruction carries the logical address of the first target region. Then, based on the aforementioned relationship and the second instruction, the terminal reads the first data from the second target region. In other words, the terminal can determine, based on the first mapping relationship, that the physical address corresponding to the logical address of the first target region in the second instruction is the physical address of the second target region, and therefore the terminal reads the first data from the second target region.
[0088] In another possible example, after the HBED thread establishes a first mapping relationship between the second target region and the first target region, the terminal obtains a third instruction. This third instruction instructs the writing of second data to the first target region; that is, the third instruction also carries the logical address of the first target region. Then, the terminal can write the second data indicated in the third instruction to the second target region according to the aforementioned first mapping relationship and the third instruction. In other words, the terminal can determine, based on the aforementioned first mapping relationship, that the physical address corresponding to the logical address of the first target region in the third instruction is the physical address of the second target region, and therefore the terminal writes the second data to the second target region.
[0089] In the example above, by establishing a first mapping relationship between the second target region and the first target region, the terminal can read and write data from the second target region based on the first mapping relationship when executing instructions to read or write data in the first target region. Based on the established first mapping relationship between the second and first target regions, the step of the HBED thread running at the virtualization privilege layer intercepting instructions related to the first target region and modifying the physical address mapped to the logical address in the instruction can be eliminated, thereby further reducing the runtime overhead of the program.
[0090] Since the capacity of memory with ECC functionality is limited, the capacity allocated to the second target area is also limited. Therefore, even if the second target area is already full of data, it is necessary to ensure that new data can still be written to it.
[0091] In one possible embodiment, before writing the first data to the second target area, the method further includes: if there is no free storage space in the second target area, the HBED thread moves the third data out of the second target area. By moving the third data out of the second target area, it can be ensured that the second target area has sufficient space to store the first data.
[0092] In one possible implementation, the third data is determined according to the Least Recently Used (LRU) algorithm. The LRU algorithm is a page replacement algorithm used to select the least recently used page for replacement. Specifically, the LRU algorithm assigns an access field to each page in memory to record the time t elapsed since the page was last accessed. When a page needs to be replaced, the LRU algorithm selects the page with the largest time value t among the existing pages as the page to be replaced. In this way, based on the LRU algorithm, the terminal can determine the least recently used third data in the second target area and remove the third data from the second target area.
[0093] The amount of third data to be moved out of the second target area can be determined based on the amount of first data indicated by the first instruction. To ensure that there is sufficient free space in the second target area to store the first data after the third data is moved out, the amount of third data can be greater than or equal to the amount of first data. For example, when the amount of first data indicated by the first instruction is 10 megabytes (MByte), the HBED thread can determine the least recently used 10 megabytes of data in the second target area as the third data and move this 10 megabytes of third data out of the second target area.
[0094] Furthermore, if there is still some free storage space remaining in the second target area, but the remaining free space is not enough to store the first data, then the sum of the amount of the third data to be moved out of the second target area and the amount of the remaining free space in the second target area must be greater than or equal to the amount of the first data.
[0095] In this embodiment, since the second target region is located on a second memory with ECC functionality, after the HBED thread moves the third data out of the second target region, the moved-out third data will no longer be located on the second memory with ECC functionality. That is, after the third data is moved out, since error detection on the third data is no longer performed by memory with ECC functionality, other methods are needed to perform error detection on the third data.
[0096] For example, the HBED thread moves the third data out of the second target area, including: the HBED thread writes the third data from the second target area into the first target area and a backup area, wherein the backup area has a first mapping relationship with the first target area and is located in memory without ECC functionality. After the third data is written into the first target area and the backup area, the HBED thread deletes the third data in the second target area.
[0097] The first target region and the backup region can reside in the same memory location, or they can reside in different memory locations. Furthermore, neither the first target region nor the backup region has ECC functionality. After the terminal is configured with a first target region that requires error detection, the HBED thread can allocate a backup region corresponding to the first target region in memory that lacks ECC functionality to back up the data stored in the first target region.
[0098] In other words, after the HBED thread moves the third data out of the memory with ECC functionality, the HBED thread stores the third data in two different memory areas so that error detection can be performed on the third data when it is read later.
[0099] Furthermore, before storing the third data in the second target area, the HBED thread receives instructions to store the third data in the first target area, and these instructions also carry the logical address in the first target area used to store the third data. Therefore, after moving the third data out of the second target area, the HBED thread can store the third data in the address originally specified in the first target area, so that the third data can be correctly read from the first target area subsequently. For the backup area, when allocating the backup area, the HBED thread can establish a first mapping relationship between addresses in the backup area and addresses in the target area. Thus, after determining the storage address of the third data in the first target area, the HBED thread can store the third data in the address corresponding to the backup area.
[0100] In this solution, when there is no free storage space in the second target area, the data in the second target area is moved to the first target area and the backup area. The first target area and the backup area then perform error detection on the data, ensuring that error detection can be performed on the data in memory and guaranteeing the reliability of system operation. Furthermore, using the first target area and the backup area for error detection also avoids executing larger programs, thereby reducing the memory usage of the program during runtime.
[0101] In one possible embodiment, after the HBED thread stores the third data in the first target area and the backup area, the method further includes: the HBED thread can obtain a fourth instruction, which instructs the reading of the third data. That is, the fourth instruction may carry the storage address of the third data in the first target area (this storage address is a logical address). Since the HBED thread establishes a first mapping relationship between the first target area and the backup area, the HBED thread can read data in the first target area based on the storage address indicated by the fourth instruction, and read data in the backup area based on the address in the backup area corresponding to that storage address.
[0102] After the HBED thread reads data from the first target area and the backup area, it compares the two sets of data. If the data in the first target area and the data in the backup area are the same, the HBED thread returns the data from the first target area to the application that requested the third set of data. If the data in the first target area and the data in the backup area are different, the HBED thread can determine that a soft failure error has occurred, and it can return a message indicating the data error to facilitate subsequent data repair.
[0103] To facilitate understanding, the data processing method provided in this embodiment will be described in detail below with examples.
[0104] Specifically, the HBED thread first reserves a region in memory with ECC functionality as the second target region mentioned above, used to map the protected memory region (i.e., the first target region mentioned above). This reserved memory region by the HBED thread can be called a buffer pool.
[0105] Please refer to Figure 5 , Figure 5This diagram illustrates the HBED thread storing data in the buffer pool according to an embodiment of this application. When an application located at EL0 or an operating system located at EL1 first writes data to the first target area, it enters the virtualization privilege layer. This means that the data write command from the application or operating system is intercepted by the HBED thread, which then takes over the data writing. Based on the data write command, the HBED thread searches for a free memory region in the buffer pool, which can be, for example, called the second target area. The HBED thread establishes a mapping from the first target area to the second target area and writes the data to the second target area.
[0106] Please refer to Figure 6 , Figure 6 This is a schematic diagram illustrating the storage of data in the buffer pool by an application / operating system provided in an embodiment of this application. Figure 6 As shown, after the HBED thread establishes the first mapping relationship between the first target region and the second target region, when the application / operating system needs to write data to or read data from the first target region, it no longer needs to enter the virtualization privilege layer, but directly writes the data to the corresponding second target region or reads the data from the second target region.
[0107] Please refer to Figure 7 , Figure 7 This is a schematic diagram illustrating how data is moved out of a second target region, as provided in an embodiment of this application. Figure 7 As shown, during the continuous writing of data to the buffer pool by the HBED thread, if the HBED thread finds that there is no longer any free memory area in the buffer pool, the HBED thread will move some data out of the buffer pool. Specifically, the HBED thread will simultaneously write some data from the buffer pool to both the first target area and the backup area, and delete some data from the buffer pool.
[0108] The above embodiments illustrate how to achieve data error detection by storing data in memory with ECC functionality. The following will describe how to achieve data error detection by storing data in multiple regions.
[0109] See section 8. Figure 8 This is a flowchart illustrating a data processing method 800 provided in an embodiment of this application. Figure 8 As shown, the data processing method 800 includes the following steps 801-803.
[0110] Step 801: Obtain the fifth instruction, which is used to instruct the writing of target data into the first region.
[0111] In this embodiment, the data processing method 300 can be applied to threads running in the virtualization privileged layer, such as the HBED thread mentioned above. During the execution of an application, the processor in the terminal executes a fifth instruction. This fifth instruction may include the logical address of a first region, and the first instruction is used to instruct the writing of target data to the first region in memory.
[0112] Before executing the fifth instruction, the HBED thread in the terminal can be pre-configured with the logical address of a first region. This first region is a memory storage area without ECC functionality, and it is configured as a protected area, meaning the data in this region requires soft failure detection. Therefore, during the execution of the fifth instruction, the HBED thread can intercept the fifth instruction based on the logical address of the first region.
[0113] Step 802: Determine the second region according to the fifth instruction.
[0114] Since the target data to be written to the first region needs to undergo soft failure detection, the HBED thread in the terminal can determine a second region in memory outside the first region based on the first region indicated in the fifth instruction, so that the target data can be written to the second region simultaneously. The second region and the first region are two non-overlapping memory regions.
[0115] In one possible implementation, the HBED thread, after receiving the fifth instruction, may allocate another memory region as a second region corresponding to the first region to store the data to be written to the first region. The size of the second region can be the same as the size of the first region.
[0116] Step 803: Write the target data into the first region and the second region.
[0117] After determining the second region, the HBED thread can write the target data indicated in the fifth instruction into the first and second regions based on the fifth instruction, thus realizing the storage of target data in the first and second regions.
[0118] In this way, since the target data is stored in both the first and second regions, when it is necessary to read the target data, the corresponding data can be read from the first and second regions and compared to achieve error detection of the target data.
[0119] For example, see Figure 9 , Figure 9 This is a schematic diagram illustrating how an HBED thread stores target data based on a fifth instruction, as provided in an embodiment of this application. Figure 9As shown, during the execution of the application, the processor in the terminal executes the fifth instruction in the application. This fifth instruction carries a logical address and target data, instructing the target data to be stored in the first region corresponding to that logical address. The logical address of the first region is pre-configured in the HBED thread, so the HBED thread can intercept the fifth instruction corresponding to the application based on the logical address of the first region. Finally, the HBED thread stores the target data indicated in the fifth instruction in both the first and second regions.
[0120] In this solution, data is written to both the first and second regions simultaneously to detect data errors. This avoids the execution of larger programs, thereby reducing the memory usage of the program during runtime.
[0121] Please refer to Figure 10 , Figure 10 This is a schematic diagram illustrating the process of HBED thread reading data provided in an embodiment of this application. Figure 10 As shown, in one possible embodiment, the data processing method 800 further includes: an HBED thread acquiring a sixth instruction, the sixth instruction being used to instruct the reading of data in the first region. The HBED thread reads data in the first region and data in the second region according to the sixth instruction. If the data in the first region is the same as the data in the second region, the HBED thread returns the data in the first region to the application that issued the sixth instruction; if the data in the first region is different from the data in the second region, it is determined that a data error has occurred, and the HBED thread can return an error message to facilitate subsequent data repair.
[0122] To facilitate verification of the beneficial effects of the data processing method described in the above embodiments, this embodiment conducted corresponding tests based on the above data processing method.
[0123] Specifically, in the test, the Protected Environment Keystone (PEK) was used as the hypervisor running at the virtualization privileged layer, and the HBED thread was built within PEK. PEK and HBED were deployed on memory with ECC functionality to ensure their reliability. Furthermore, a virtual machine was launched by PEK, and the application ran within it. A DTB file served as the configuration file for PEK, configuring a protected memory region within the DTB. To test the runtime overhead of the HBED thread, the application in the virtual machine continuously read and wrote to the protected memory region 50,000 times each. Table 1 shows a comparison of the read / write time overhead between existing solutions and the error detection solution based on HBED and ECC-enabled memory provided in this embodiment (i.e., the data processing method 300 described above).
[0124] Table 1
[0125] As can be seen from Table 1, the runtime overhead of the method provided in this embodiment when performing 50,000 read and write operations is 64.86% and 61.78% of that of the existing solutions, respectively. Obviously, the runtime overhead is significantly lower than that of the existing solutions.
[0126] Furthermore, regarding memory usage, existing solutions copy each instruction, resulting in the target program size doubling compared to the original program. In contrast, the method provided in this embodiment does not modify the original program, and the program size remains unchanged.
[0127] exist Figures 1 to 10 Based on the corresponding embodiments, in order to better implement the above-described solutions of the embodiments of this application, related equipment for implementing the above-described solutions is also provided below.
[0128] For details, please refer to [link / reference]. Figure 11 , Figure 11 This is a schematic diagram of a data processing device 1100 provided in an embodiment of this application. The data processing device 1100 includes an acquisition unit 1101 and a processing unit 1102. The acquisition unit 1101 is used to acquire a first instruction, which instructs the writing of first data to a first target area, the first target area being a storage area on a first memory, which does not have error checking and correction (ECC) functions. The processing unit 1102 is used to determine a second target area in a second memory according to the first instruction, the second target area being a storage area on a second memory, which has ECC functions. The processing unit 1102 is also used to write the first data to the second target area.
[0129] In one possible implementation, the processing unit 1102 is further configured to establish a first mapping relationship between the second target region and the first target region, the first mapping relationship being used to indicate the reading or writing of data.
[0130] In one possible implementation, the acquisition unit 1101 is further configured to acquire a second instruction, the second instruction being configured to instruct the reading of data in the first target area; the processing unit 1102 is further configured to read the first data in the second target area according to the first mapping relationship and the second instruction.
[0131] In one possible implementation, the acquisition unit 1101 is further configured to acquire a third instruction, the third instruction being configured to instruct the writing of second data to the first target region; the processing unit 1102 is further configured to write the second data to the second target region according to the first mapping relationship and the third instruction.
[0132] In one possible implementation, the processing unit 1102 is further configured to determine the second target region in the second memory according to the first instruction and a preset second mapping relationship; the second mapping relationship is used to indicate that the first target region corresponds to the second target region.
[0133] In one possible implementation, the processing unit 1102 is further configured to remove the third data in the second target area from the second target area if there is no free storage space in the second target area.
[0134] In one possible implementation, the processing unit 1102 is further configured to write the third data in the second target area into the first target area and the backup area, wherein the backup area has a first mapping relationship with the first target area and the backup area is located in memory without ECC function; the processing unit 1102 is further configured to delete the third data in the second target area.
[0135] In one possible implementation, the third data is determined according to the LRU algorithm.
[0136] In one possible implementation, the acquisition unit 1101 is further configured to acquire a fourth instruction, the fourth instruction being used to instruct the reading of the third data; the processing unit 1102 is further configured to read data in the first target area and data in the backup area based on the fourth instruction; the processing unit 1102 is further configured to return the data in the first target area if the data in the first target area and the data in the backup area are the same.
[0137] In one possible implementation, the apparatus is applied to a thread running in a virtualization privileged layer, the thread being used to retrieve the first instruction based on the address of the first target region.
[0138] In another possible embodiment, the acquisition unit 1101 is configured to acquire a fifth instruction, the fifth instruction being configured to instruct the writing of target data into a first region; the processing unit 1102 is configured to determine a second region according to the fifth instruction; the processing unit 1102 is further configured to write the target data into the first region and the second region.
[0139] In one possible implementation, the acquisition unit 1101 is further configured to acquire a sixth instruction, the sixth instruction being used to instruct the reading of data in the first region; the processing unit 1102 is further configured to: read data in the first region and data in the second region according to the sixth instruction; if the data in the first region is the same as the data in the second region, then return the data in the first region; if the data in the first region is the same as the data in the second region, then determine that a data error has occurred.
[0140] The data processing method provided in this application embodiment can be specifically executed by a chip in a terminal. This chip includes a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, pins, or circuitry. The processing unit can execute computer execution instructions stored in a storage unit, causing the chip in the server to perform the aforementioned operations. Figures 1 to 10 The data processing method described in the illustrated embodiment. Optionally, the storage unit is an in-chip storage unit, such as a register or cache. Alternatively, the storage unit can be an external storage unit located within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).
[0141] Reference Figure 12 This application also provides a computer-readable storage medium, in some embodiments of which the above-described... Figure 3 The disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.
[0142] Figure 12 A conceptual partial view of an example computer-readable storage medium arranged according to at least some of the embodiments shown herein is illustrated schematically. The example computer-readable storage medium includes a computer program for executing computer processes on a computing device.
[0143] In one embodiment, the computer-readable storage medium 1200 is provided using a signal bearer medium 1201. The signal bearer medium 1201 may include one or more program instructions 1202, which, when executed by one or more processors, can provide the above-mentioned... Figure 2 The described function or part of the function. Therefore, for example, refer to... Figure 3 In the embodiment shown, one or more features of steps 301-303 can be provided by one or more instructions associated with the signal carrying medium 1201. Furthermore, Figure 12 The program instruction 1202 in the document also describes example instructions.
[0144] In some examples, signal carrying medium 1201 may include computer-readable medium 1203, such as, but not limited to, hard disk drive, compact disc (CD), digital video disc (DVD), digital magnetic tape, memory, ROM or RAM, etc.
[0145] In some embodiments, the signal-bearing medium 1201 may comprise a computer-recordable medium 1204, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, the signal-bearing medium 1201 may comprise a communication medium 1205, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Therefore, for example, the signal-bearing medium 1201 may be transmitted by a wireless communication medium 1205 (e.g., a wireless communication medium conforming to the IEEE 802.12 standard or other transmission protocols).
[0146] One or more program instructions 1202 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 1202 conveyed to the computing device via a computer-readable medium 1203, a computer-recordable medium 1204, and / or a communication medium 1205.
[0147] It should be understood that the arrangements described herein are for illustrative purposes only. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements may be omitted depending on the desired outcome. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location with other components.
[0148] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0149] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.
[0150] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0151] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0152] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
Claims
1. A system comprising: First memory; Second memory, the second memory has ECC functionality; A virtual machine manager is configured on the first memory and the second memory, the virtual machine manager including a soft failure detection framework thread; Applications configured on the virtual machine manager; The first memory is configured to store the first data of the application, and the data is stored in the second memory.
2. The system according to claim 1, characterized in that: The first memory includes a first target region, and the second memory includes a second target region; The first target area is configured to store the first data; The second target area is configured to store the first data.
3. The system according to claim 1, characterized in that: The second target region and the first target region include a first mapping relationship, which is used to indicate the reading or writing of the first data.
4. A terminal, characterized in that, Includes the system as described in any one of claims 1-3.