Method, device and equipment for protecting sensitive data of embedded system and medium

Abstract

The application discloses an embedded system sensitive data security protection method, device, equipment and medium. The method comprises the following steps: in response to a data write request, obtaining original sensitive data from an embedded system processor through a confidentiality protection module, encrypting the original sensitive data based on a post-quantum cryptography algorithm to obtain encrypted sensitive data, and sending the encrypted sensitive data to an integrity monitoring module and an external memory; generating a first integrity check tag of the encrypted sensitive data based on an expandable output function algorithm through the integrity monitoring module; in response to a data read request, obtaining the encrypted sensitive data from the external memory through the integrity monitoring module, generating a second integrity check tag of the encrypted sensitive data based on the expandable output function algorithm, comparing the first integrity check tag with the second integrity check tag to determine a check result of the encrypted sensitive data; and if the check fails, sending an interrupt signal to the embedded system processor and triggering a security alarm. The scheme can realize high security protection and low performance loss of sensitive data.

Description

Technical Field

[0001] This invention relates to the field of embedded system security technology, and in particular to a method, apparatus, device and medium for protecting sensitive data in embedded systems. Background Technology

[0002] Embedded systems, with their advantages of compact structure, low power consumption, stable and reliable performance, and low cost, are widely used in many fields such as the Internet of Things, medical devices, industrial control, finance, defense, aerospace, and automotive electronics. With the development of autonomous driving, new energy vehicles, and AI (Artificial Intelligence) technologies, the application scale of embedded systems continues to expand. However, their characteristics, such as limited resources, complex deployment environments, and stringent security requirements, expose sensitive data to serious security threats such as eavesdropping, tampering, and destruction. Therefore, the security protection of sensitive data is a critical issue that urgently needs to be addressed.

[0003] Among existing embedded system sensitive data security protection schemes, hardware-software co-protection schemes are one of the important technical paths. For example, Erhu Feng et al. proposed a hardware-software co-design scheme in their paper "Scalable Memory Protection in the PENGLAI Enclave," implementing a RISC-V prototype system based on the PENGLAI architecture. This scheme supports dynamic, fine-grained, large-scale secure storage and fast initialization technology, and can encrypt and protect the page tables and Merkle trees. Wenjia Zhao et al. proposed a memory protection mechanism called MPTEE in their paper "MPTEE: Bringing Flexible and Efficient Memory Protection to Intel SGX." This mechanism provides flexible and efficient execution of memory page permissions in Intel's Software Defense Extensions technology.

[0004] However, the aforementioned embedded system sensitive data security protection schemes feature complex protection mechanisms and cumbersome deployment processes. They are particularly cost-effective in low-end embedded systems with limited hardware resources, making it difficult to meet the demands of low-cost, lightweight applications. Furthermore, existing post-quantum cryptography (PQC) hardware solutions are typically large and power-intensive because the encryption and hashing modules are often designed separately, resulting in wasted gate counts. Summary of the Invention

[0005] This invention provides a method, apparatus, device, and medium for protecting sensitive data in embedded systems. Through the synergistic effect of a confidentiality protection module and an integrity monitoring module, it can achieve high security protection, low performance loss, and flexible adaptation to different security requirements for sensitive data in embedded systems, while also having good reusability and portability.

[0006] According to one aspect of the present invention, a method for protecting sensitive data in an embedded system is provided, the method comprising: In response to a data write request from an embedded system, the original sensitive data is obtained from the embedded system processor through a confidentiality protection module, and the original sensitive data is encrypted based on a post-quantum cryptography algorithm to obtain encrypted sensitive data. The encrypted sensitive data is then sent to an integrity monitoring module and an external memory. The integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on the Extendable Output Function (XOF) algorithm, and stores the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; In response to the data read request of the embedded system, the encrypted sensitive data is obtained from the external memory through the integrity monitoring module, a second integrity verification tag for the encrypted sensitive data is generated based on the extensible output function algorithm, and the verification result of the encrypted sensitive data is determined according to the comparison result between the second integrity verification tag and the first integrity verification tag. If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered.

[0007] According to another aspect of the present invention, an embedded system sensitive data security protection device is provided, the device comprising: The confidentiality protection module is used to respond to the data write request of the embedded system, obtain the original sensitive data from the embedded system processor, encrypt the original sensitive data based on the post-quantum cryptography algorithm to obtain encrypted sensitive data, and send the encrypted sensitive data to the integrity monitoring module and the external memory. The integrity monitoring module is used to generate a first integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and to store the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; The integrity monitoring module is further configured to respond to the data read request of the embedded system, obtain the encrypted sensitive data from the external memory, generate a second integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and determine the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag; If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the embedded system sensitive data security protection method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the embedded system sensitive data security protection method according to any embodiment of the present invention.

[0010] The technical solution of this invention, in response to a data write request from an embedded system, obtains the original sensitive data from the embedded system processor through a confidentiality protection module, encrypts the original sensitive data based on a post-quantum cryptography algorithm to obtain encrypted sensitive data, and sends the encrypted sensitive data to an integrity monitoring module and an external memory. The integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on a scalable output function algorithm and stores the first integrity verification tag. The digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data. In response to a data read request from the embedded system, the integrity monitoring module obtains the encrypted sensitive data from the external memory, generates a second integrity verification tag for the encrypted sensitive data based on a scalable output function algorithm, and determines the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag. If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered. This technical solution, through the synergistic effect of the confidentiality protection module and the integrity monitoring module, can achieve high security and low-loss protection of sensitive data throughout the entire lifecycle of the embedded system, and can support multiple security levels of data protection based on the data sensitivity level, thereby flexibly adapting to different security requirements.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a method for protecting sensitive data in an embedded system according to an embodiment of the present invention; Figure 2 This is a flowchart of another method for protecting sensitive data in an embedded system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the overall process of a method for protecting sensitive data in an embedded system according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an embedded system sensitive data security protection device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device that implements an embedded system sensitive data security protection method according to an embodiment of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1 This is a flowchart of a method for protecting sensitive data in an embedded system according to Embodiment 1 of the present invention. This embodiment is applicable to situations requiring high security protection and low performance loss for sensitive data in embedded systems. The method can be executed by an embedded system sensitive data security protection device, which can be implemented in hardware and / or software. This device can be configured in an electronic device with data processing capabilities. Figure 1 As shown, the method includes: S110, in response to the data write request of the embedded system, obtains the original sensitive data from the embedded system processor through the confidentiality protection module, encrypts the original sensitive data based on the post-quantum cryptography algorithm to obtain encrypted sensitive data, and sends the encrypted sensitive data to the integrity monitoring module and external memory.

[0017] The technical solution provided in this invention is applicable to various types of embedded systems, such as RISC-V embedded systems. This system uses the open-source E906 soft core and can operate at frequencies exceeding 100MHz. It should be noted that the confidentiality protection module and integrity monitoring module designed in this invention are both deployed on-chip in the embedded system, employing an independent module architecture and interacting with the RISC-V E906 soft core via a bus. This eliminates the need to modify existing modules in the embedded system, thereby improving module reusability and portability while ensuring module security. Furthermore, the parallel operation of the two modules with the embedded system eliminates additional performance overhead and ensures the system's operational efficiency.

[0018] The data write request can refer to an operation request to write sensitive data from within the embedded system to external memory. The confidentiality protection module is used to implement encrypted protection of sensitive data. Optionally, the post-quantum cryptography algorithm uses the CRYSTALS-KYBER algorithm. It should be noted that although this embodiment uses the CRYSTALS-KYBER algorithm as an example, the invention is not limited to this. In practical applications, this confidentiality protection module can be built based on other post-quantum key encapsulation mechanisms based on lattice cryptography, aiming to resist attacks from quantum computers. CRYSTALS-KYBER, as an optimized algorithm selected in the third round of standardization by NIST, is based on the Module Learning Error Problem (MLWE) and is chosen as the specific implementation method in this embodiment to demonstrate the efficiency of this scheme. The original sensitive data can refer to the sensitive data output by the embedded system processor, i.e., the sensitive data within the embedded system. The encrypted sensitive data can refer to the sensitive data obtained after encrypting the original sensitive data.

[0019] In this embodiment, when a data write request from the embedded system is detected, the original sensitive data output by the embedded system processor is first obtained through the confidentiality protection module. The original sensitive data is then encrypted using a post-quantum cryptography algorithm to obtain encrypted sensitive data, which is then sent to the integrity monitoring module and external memory. The data write operation is finally completed by storing the encrypted sensitive data at the target address in the external memory. For example, when using the CRYSTALS-KYBER algorithm, the Kyber-512 parameter set can be used. The parameter configuration can be set as follows: polynomial degree n=256, vector dimension k=2, modulus q=3329, and error vector sampling range. , Compression ratio , Decryption error probability .

[0020] In this embodiment, optionally, the confidentiality protection module includes an NTT module and a Keccak module; the NTT module integrates multiplication, modulo, and compression / decompression operations. The modulo operation is implemented based on a preset lookup table and a multi-level compression structure. The preset lookup table is used to describe the operation result after the input data within a preset range is moduloed by a preset modulus.

[0021] NTT (Number Theoretic Transform) is a discrete transformation method based on modular arithmetic of integers within a finite field. It leverages the properties of circular convolution for fast computation, avoiding floating-point errors, and is simple to implement in hardware. The butterfly arithmetic unit in the NTT module integrates multiplication, modulo operation, and compression / decompression operations. The multiplication unit uses a compressor + adder architecture, with register insertion to implement a two-stage pipeline, keeping the clock delay within two cycles. The modulo operation is implemented based on a preset lookup table and a multi-stage compression structure (e.g., four stages). The preset lookup table describes the result of modulo operation on a preset modulus from input data within a preset range. For example, the preset range can be set to... to The preset modulus can be set to 3329, and the calculation result can include the quotient and remainder, that is, the preset lookup table stores... to The data within the range is modulo 3329 to obtain the quotient and remainder. Specifically, in the modulo operation, a pre-computed lookup table combined with a 4-level compression structure can be used to compress the 24-item cumulative input into 7 items, quickly completing the modulo operation of the input data with respect to the modulus 3329, avoiding the high latency caused by direct calculation. In addition, a pipelined parallel architecture is adopted for NTT, INTT (inverse number-theoretic transform), and coefficient multiplication, thereby improving the calculation speed and running frequency.

[0022] In general, the encryption process involves receiving raw sensitive data, performing NTT transformation, coefficient multiplication, and compression to generate ciphertext (i.e., encrypted sensitive data), and then outputting it to the integrity monitoring module and external memory. The entire process takes 230 clock cycles (2.3 seconds delay at 100MHz). ).

[0023] S120, the integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and stores the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data.

[0024] The integrity monitoring module can calculate integrity verification tags for sensitive data based on a hash algorithm with variable output length (i.e., the XOF algorithm). The first integrity verification tag can refer to the integrity verification tag generated on encrypted sensitive data during the data writing phase based on the extensible output function algorithm, and can serve as one of the bases for data integrity verification. Sensitivity levels can be used to reflect the degree of data sensitivity, thereby characterizing the data's security level. For example, sensitivity levels can include extremely sensitive, core sensitive, important sensitive, and generally sensitive.

[0025] In this embodiment, optionally, the scalable output function algorithm adopts the SHAKE-256 algorithm. The CRYSTALS-KYBER algorithm and the SHAKE-256 algorithm reuse the Keccak-f

[1600] operation structure of the Keccak module. As an implementation of the present invention, this embodiment selects the SHAKE-256 algorithm. The SHAKE-256 algorithm is one of the SHA-3 cryptographic hash functions. The present invention utilizes its variable output length characteristic to flexibly adapt to the needs of different data security levels. This algorithm can support digest outputs of various lengths (such as 64 / 128 / 192 / 256 bits). It should be noted that, taking advantage of the fact that the Keccak algorithm in CRYSTALS-KYBER and the SHAKE-256 algorithm are from the same source (both originate from the SHA-3 algorithm), the underlying Keccak-f

[1600] structure of the Keccak module can be reused, that is, the CRYSTALS-KYBER algorithm and the SHAKE-256 algorithm share a set of Keccak-f

[1600] underlying operation structures. The Keccak module can be used as a random number generator in the CRYSTALS-KYBER algorithm to generate random vector matrices, noise vectors, and error vectors, significantly saving hardware resource overhead. Thanks to pipeline optimization of the NTT module and reuse design of the underlying computational structure, this invention significantly improves computational efficiency while ensuring security. Experimental verification shows that, under the same parameter set, the encryption latency of this invention is reduced by approximately 32% and the decryption latency by approximately 70% compared to existing technologies, effectively overcoming the performance degradation of existing post-quantum encryption schemes in embedded systems.

[0026] In this embodiment, an extensible output function algorithm is used as the core of the integrity monitoring module. Its variable-length output characteristic is used to design a multi-security level mechanism. Specifically, different length digest outputs are used for different sensitivity levels of encrypted sensitive data, flexibly adapting to the security requirements of data with different sensitivity levels. For example, when the confidentiality protection module obtains the original sensitive data from the embedded system processor, it can also obtain a sensitive tag (reflecting the data's sensitivity level) manually added to the original sensitive data. This sensitive tag is carried throughout the subsequent encryption and storage process, allowing for rapid determination of the sensitivity level of the encrypted sensitive data. Specifically, the integrity monitoring module can receive the encrypted sensitive data (e.g., 6144 bits) output by the confidentiality protection module, group it into 1088-bit blocks and pad it (e.g., padding format 32'h8000_0000||n||32'h0000_1f00), calculate the corresponding sensitivity level tag using the SHAKE-256 algorithm, and store the first integrity verification tag in the integrity monitoring module.

[0027] In this embodiment, optionally, generating a first integrity verification tag for encrypted sensitive data based on the extensible output function algorithm includes: determining the sensitivity level of the encrypted sensitive data according to the scenario source of the encrypted sensitive data; determining the digest length of the encrypted sensitive data according to the sensitivity level of the encrypted sensitive data; and generating a first integrity verification tag for the encrypted sensitive data using the extensible output function algorithm based on the digest length of the encrypted sensitive data.

[0028] For example, a mapping table can be pre-set and stored in the integrity monitoring module. This table can be used to describe the mapping relationship between the scenario source, sensitivity level, and digest length of sensitive data. For example, the scenario source can include national defense secrets, financial transactions, user privacy, etc. The mapping relationship between sensitivity level and digest length can be determined based on the mapping relationship between the output length of the SHAKE-256 algorithm and collision resistance in the NISTSP 800-185 standard. For example, for extremely sensitive data such as national defense secrets and core keys, to meet the requirements of resisting high-intensity attacks in a quantum computing environment, the digest length is determined to be 256 bits. According to the characteristics of the SHAKE-256 algorithm, a 256-bit digest provides approximately 128 bits of collision resistance, which is sufficient to resist quantum computer-assisted birthday attacks. For core sensitive data such as financial transaction vouchers, to achieve a balance between security and storage resources, the digest length is determined to be 192 bits. This length provides approximately 96 bits of collision resistance, meeting the high security and integrity standards for bank-grade data. For critical and sensitive data such as industrial control commands, a digest length of 128 bits is determined. This length provides 64 bits of collision resistance, effectively defending against tampering attacks using conventional computing power while reducing storage overhead. For general sensitive data such as log information and ordinary status updates, a digest length of 64 bits is determined. In this case, the avalanche effect of the hash function is mainly used to replace the traditional cyclic redundancy check (CRC) to detect random transmission errors or low-cost tampering attempts, achieving extremely low latency and minimal storage footprint.

[0029] Specifically, when generating the first integrity verification label for encrypted sensitive data based on the SHAKE-256 algorithm, the process first involves searching a pre-stored correspondence table based on the data's source context. The successfully matched sensitivity level is taken as the sensitivity level of the encrypted sensitive data, and the successfully matched digest length is taken as the digest length of the encrypted sensitive data. Thus, the required digest length for encrypted sensitive data can be quickly and automatically determined simply by searching the correspondence table based on the data's source context. Then, the SHAKE-256 algorithm is used to generate a label with the corresponding digest length for the encrypted sensitive data, which serves as the first integrity verification label.

[0030] In this embodiment, optionally, the digest length of the encrypted sensitive data is determined according to the sensitivity level of the encrypted sensitive data, including: if the sensitivity level of the encrypted sensitive data is extremely sensitive, then the digest length of the encrypted sensitive data is determined to be 256 bits; if the sensitivity level of the encrypted sensitive data is core sensitive, then the digest length of the encrypted sensitive data is determined to be 192 bits; if the sensitivity level of the encrypted sensitive data is important sensitive, then the digest length of the encrypted sensitive data is determined to be 128 bits; if the sensitivity level of the encrypted sensitive data is generally sensitive, then the digest length of the encrypted sensitive data is determined to be 64 bits.

[0031] Specifically, this invention employs a hierarchical security design based on the Sponge Construction security theory: extremely sensitive data corresponds to a 256-bit digest, providing 128-bit resistance to collision attacks and 256-bit resistance to surface-level attacks, meeting the security baseline requirements of post-quantum cryptography for highly sensitive data; core sensitive data corresponds to a 192-bit digest, providing 96-bit resistance to collision attacks, primarily targeting core financial credentials, balancing security and resource consumption; important sensitive data corresponds to a 128-bit digest, providing 64-bit resistance to collision attacks, sufficient to defend against conventional collision attacks under current computing power; general sensitive data corresponds to a 64-bit digest, although with lower collision resistance (32 bits), its main purpose is to serve as a keyed strong checksum, replacing insecure Cyclic Redundancy Check (CRC), for integrity verification in extremely low-latency scenarios. Furthermore, through pipelined optimization, the 24 round functions of SHAKE-256 are instantiated using combinational logic, with registers inserted after rounds 6, 12, 18, and 24, achieving a 4-stage pipeline. This allows the integrity monitoring module to execute in parallel with the embedded system, eliminating performance overhead.

[0032] For example, the integrity monitoring module includes a tag storage module. After generating a first integrity verification tag for encrypted sensitive data, it can be stored in the tag storage module. Optionally, storing the first integrity verification tag includes using a secondary mapping mechanism. Using a secondary mapping mechanism to store the integrity verification tags generated by the integrity monitoring module can reduce storage resource waste.

[0033] Regarding the "secondary mapping mechanism" of the tag storage module, this embodiment specifically includes the following steps: First-level mapping (physical address index mapping): The integrity monitoring module receives the physical address (PA) of the encrypted sensitive data sent by the confidentiality protection module. First, the physical address is bit-field split. Assuming the embedded system data block size is 32 bytes (256 bits), the lower 5 bits of the physical address (Bit[4:0]) are ignored as the block offset. Next, the middle N bits of the physical address (e.g., Bit[4+N:5]) are selected as the index value of the first-level mapping, used to directly address the static random access memory (SRAM) inside the tag storage module. This index value determines the storage row address of the first integrity verification tag of the current sensitive data in the SRAM.

[0034] Secondary Mapping (High-Level Tag Anchoring and Collision Prevention): To resolve the "hash collision" problem where different physical addresses may map to the same SRAM row address, this invention employs high-level tag anchoring as a secondary mapping. The remaining high-order bits of the physical address (e.g., Bits [31:5+N]) are used as the address tag. When writing the first integrity check tag to the SRAM, not only is the tag value itself stored, but the tag value is also stored in the same address row.

[0035] Collision Check: When performing data read verification, the system again uses the middle N bits of the read address to find the corresponding row in SRAM, retrieves the stored Tag value, and compares it with the high-order Tag bits of the current read address. If the tag matches: This means that the integrity verification tag stored at this location does indeed belong to the currently read data block, allowing subsequent hash comparisons.

[0036] If the tag does not match, it indicates an address conflict, meaning that the data at this location has been overwritten by data at another address, or the current address is not protected. In this case, the verification fails or a miss is triggered.

[0037] Through the above-mentioned secondary mapping mechanism of "index addressing + tag anchoring", the present invention can efficiently manage sensitive data tags in a large range of off-chip storage space within limited on-chip storage resources (SRAM), effectively solving the problem of multi-address mapping conflicts.

[0038] S130, in response to the data read request of the embedded system, obtains encrypted sensitive data from the external memory through the integrity monitoring module, generates a second integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and determines the verification result of the encrypted sensitive data based on the comparison result of the second integrity verification tag and the first integrity verification tag.

[0039] The data read request can refer to an operation request to read sensitive data stored in external memory into the embedded system. The second integrity verification tag can be an integrity verification tag generated on encrypted sensitive data based on the extensible output function algorithm during the data read phase, and can also serve as one of the bases for data integrity verification. The verification result includes verification success or verification failure.

[0040] In this embodiment, when a data read request from the embedded system is detected, the encrypted sensitive data stored at the target address of the external memory is first read through the integrity monitoring module. Then, a second integrity verification tag for the encrypted sensitive data is generated based on the extensible output function algorithm, specifically referring to the generation process of the first integrity verification tag. The newly generated second integrity verification tag is then compared with the previously stored first integrity verification tag, and the verification result of the encrypted sensitive data is determined based on their consistency. If the second integrity verification tag matches the first integrity verification tag, it indicates that the original sensitive data was not corrupted during transmission (i.e., the original sensitive data has integrity), and the verification result can be determined as successful. If the second integrity verification tag does not match the first integrity verification tag, it indicates that the original sensitive data was corrupted during transmission (i.e., the original sensitive data does not have integrity), and the verification result can be determined as failed.

[0041] Furthermore, in this embodiment, a control scheduling module (such as a state machine) can also be set to coordinate the timing logic of the integrity monitoring module and the confidentiality protection module, so as to realize the parallel execution of encryption / decryption and tag calculation / verification during data reading and writing, avoid timing conflicts, and help improve the security protection efficiency of sensitive data in embedded systems.

[0042] S140 If the verification fails, an interrupt signal is sent to the embedded system processor and a security alarm is triggered.

[0043] In this embodiment, when the verification result of encrypted sensitive data is determined to be a verification failure, in order to maintain the data security of the embedded system, an interrupt signal needs to be immediately sent to the embedded system processor to terminate the data reading process. Simultaneously, a security alarm is triggered to remind relevant management personnel to handle the situation promptly, thereby achieving security protection for sensitive data in the embedded system. It should be noted that this embodiment does not specifically limit the content and form of the security alarm, and can be flexibly set according to actual needs. For example, the security alarm content may include the corrupted data and its source, sensitivity level, integrity verification label, and external storage address (i.e., target address). Furthermore, the security alarm form may include text alerts (such as SMS), voice alerts (such as telephone calls), interactive interface pop-up alerts, and audible and visual alarms, and one or more of these methods can be selected based on the data sensitivity level.

[0044] The technical solution of this invention, in response to a data write request from an embedded system, obtains original sensitive data from the embedded system processor through a confidentiality protection module, encrypts the original sensitive data based on a post-quantum cryptography algorithm to obtain encrypted sensitive data, and sends the encrypted sensitive data to an integrity monitoring module and an external memory; the integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and stores the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; in response to a data read request from the embedded system, the integrity monitoring module obtains the encrypted sensitive data from the external memory, generates a second integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and determines the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag; if the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered. This technical solution, through the synergistic effect of the confidentiality protection module and the integrity monitoring module, can achieve high security and low loss protection of sensitive data in embedded systems throughout their entire lifecycle. It can also support multiple security levels of data protection based on data sensitivity levels, thereby flexibly adapting to different security needs. At the same time, it has good reusability and portability, overcoming the shortcomings of existing data security protection solutions such as excessive resource consumption, large performance loss, and limited applicability.

[0045] In this embodiment, optionally, the confidentiality protection module further includes a data block caching module, which is used to convert the original sensitive data into 256-bit data blocks and cache the data that has been successfully verified.

[0046] The data block caching module can package raw sensitive data (such as 32-bit data) into 256-bit data blocks to facilitate calculations by the confidentiality protection and integrity monitoring modules. Furthermore, the data block caching module provides data caching functionality, caching frequently accessed data that has successfully verified (including sensitive data and integrity verification tags), thereby reducing the frequency of repeated verifications, decreasing the number of verifications, and further reducing performance overhead. The state transition logic of the data block caching module can adapt to data read / write timing requirements.

[0047] Example 2 Figure 2This is a flowchart of a method for protecting sensitive data in an embedded system according to Embodiment 2 of the present invention. This embodiment is an optimization based on the above embodiment. Specifically, the optimization is as follows: the method further includes: in response to a data read request from the embedded system, obtaining encrypted sensitive data from an external memory through a confidentiality protection module; if the verification is successful, decrypting the encrypted sensitive data using a post-quantum cryptography algorithm through the confidentiality protection module to obtain the original sensitive data, and sending the original sensitive data to the embedded system processor.

[0048] like Figure 2 As shown, the method in this embodiment specifically includes the following steps: S210, in response to the data write request of the embedded system, obtains the original sensitive data from the embedded system processor through the confidentiality protection module, encrypts the original sensitive data based on the post-quantum cryptography algorithm to obtain encrypted sensitive data, and sends the encrypted sensitive data to the integrity monitoring module and external memory.

[0049] S220, the integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and stores the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data.

[0050] S230, in response to a data read request from the embedded system, retrieves encrypted sensitive data from the external memory through the integrity monitoring module and the confidentiality protection module, respectively.

[0051] In this embodiment, when a data read request from the embedded system is detected, encrypted sensitive data is retrieved from the external memory through the integrity monitoring module and the confidentiality protection module, respectively.

[0052] S240, the integrity monitoring module generates a second integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and determines the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag.

[0053] S250: If the verification is successful, the confidentiality protection module decrypts the encrypted sensitive data based on the post-quantum cryptography algorithm to obtain the original sensitive data, and then sends the original sensitive data to the embedded system processor.

[0054] Specifically, the decryption process involves reading encrypted sensitive data from external storage, decompressing it, performing an inverse INTT transform, and performing error correction to recover the original sensitive data before outputting it to the embedded system processor. This process takes 146 clock cycles (1.46 clock cycles at 100MHz). ).

[0055] If the verification fails, S260 sends an interrupt signal to the embedded system processor and triggers a security alarm.

[0056] like Figure 3 As shown, the overall process of this invention is as follows: (1) Data writing path: original sensitive data of the embedded system → encryption by the confidentiality protection module → generation of ciphertext → output in two paths (one to external memory, the other to the integrity monitoring module) → the integrity monitoring module calculates the integrity verification tag → the tag storage module stores the tag; (2) Data reading path: external storage of ciphertext → input in two paths (one to the confidentiality protection module for decryption, the other to the integrity monitoring module for verification) → plaintext output by the confidentiality protection module → tag comparison by the integrity monitoring module → if the verification is successful, the plaintext is input into the embedded system; if the verification fails, an interrupt signal is issued and a security alarm is triggered. Among them, the data block cache module (Data BlockCache) is deployed on the on-chip area of ​​the embedded system and is located outside the confidentiality protection module; the off-chip memory is the external memory; the bus matrix unit is the core component in the bus architecture.

[0057] The following test platform is built based on the RISC-V open-source E906 soft core. The hardware uses a Kintex 7 XC7K325 FPGA development board, and the software tools include Xilinx_VIVADO_2023.1 (simulation, synthesis, placement and routing) and a VIVADO_ILA logic analyzer. Utilizing module-level testing, system-level testing, and FPGA verification, the functional correctness and feasibility of the invention are verified by changing the security level, algorithm parameters, and test data types, while highlighting the performance advantages of the invention. Each test instance is an independent and complete experimental record, as detailed below: Test Example 1: High-Security Protection Experiment for Extremely Sensitive Data (256-bit Digest) 1. Experimental objective: To verify the effectiveness of this invention in protecting the integrity and confidentiality of extremely sensitive data (such as national defense secrets), with a focus on testing the performance of the highest security level corresponding to the 256-bit digest.

[0058] 2. Experimental plan: (1) Test data preparation: 6144 bits of extremely sensitive simulated data (generated from the NIST standard test dataset, data identifier: {200{8'hA3}} extended) were selected as the original sensitive data. (2) Security parameter configuration: 1) Integrity monitoring module: the security level was set to "extremely sensitive", the digest length was 256 bits, and the tag storage adopted a secondary mapping mechanism; 2) Confidentiality protection module: the CRYSTALS-KYBER algorithm Kyber-512 parameter set (n=256, k=2, q=3329) was adopted, and the NTT module enabled a 4-level pipeline.

[0059] 3. Experimental steps: (1) Data writing stage: The original data is input into the confidentiality protection module, and after NTT transformation, coefficient multiplication and compression operation, ciphertext is generated, which takes 230 clock cycles; at the same time, the ciphertext is input into the integrity monitoring module, grouped into 1088 bits and filled (filling format: 32'h8000_0000||560'd0||32'h0000_1f00), and after 7 rounds of SHAKE-256 algorithm operation, a 256-bit integrity check tag is generated and stored in the tag storage module. (2) Data reading stage: The ciphertext is decrypted by the confidentiality protection module (146 clock cycles) to restore the original data; the integrity monitoring module recalculates the integrity check tag of the ciphertext and compares it with the stored integrity check tag. (3) Attack test: Collision attack and replay attack simulation are performed on the ciphertext in the transmission process, and the system response is observed.

[0060] 4. Test results: (1) Integrity: The integrity verification tag comparison results are consistent, the anti-collision attack level reaches 128 bits, the original phenomenon attack level reaches 256 bits, and the reverse collision probability is (2) Confidentiality: The decrypted data is completely consistent with the original data, and no data leakage occurred during the quantum attack resistance test; (3) Performance: The operating frequency is 100MHz, and the encryption delay is Decryption delay (4) Attack protection: Successfully resist collision attacks and replay attacks, triggering an attack alarm mechanism.

[0061] Test Example 2: Lightweight Protection Test for Generally Sensitive Data (64-bit Digest) 1. Experimental objective: To verify the lightweight protection effect of this invention on general sensitive data (such as ordinary user privacy information), and to test the resource consumption and performance under low security levels.

[0062] 2. Test plan: (1) Test data preparation: Select 6144 bits of general sensitive simulation data (user basic information splicing data, including name, contact information, etc.). (2) Security parameter configuration: 1) Integrity monitoring module: Security level is set to "generally sensitive", digest length is 64 bits, and tag storage adopts a secondary mapping mechanism; 2) Confidentiality protection module: Keep the Kyber-512 parameter set unchanged, and turn off some unnecessary optimizations (such as data block cache module).

[0063] 3. Experimental steps: (1) Data writing stage: The original data is encrypted by the confidentiality protection module to generate ciphertext; the integrity monitoring module calculates 64-bit tags for each group of ciphertext and stores them. Due to the shortened digest length, the tag calculation only requires 5 rounds of SHAKE-256 operation. (2) Data reading stage: After the ciphertext is decrypted, the integrity monitoring module quickly verifies the integrity verification tag to verify the data integrity. (3) Resource overhead test: The hardware resource consumption (LUT, FF, DSP) is statistically analyzed using the VIVADO_ILA logic analyzer. Among them, LUT is a lookup table, FF is a flip-flop, and DSP is a digital signal processor.

[0064] 4. Test Results: (1) Integrity: The integrity verification tags match, and the anti-collision attack level is 32 bits, meeting the lightweight security requirements; (2) Confidentiality: The decrypted data is undistorted and can effectively resist conventional theft attacks; (3) Resource Consumption: The LUT occupies 88k, the FF occupies 29.8k, and the DSP occupies 0, saving 15% of tag storage resources compared to the 256-bit digest scheme; (4) Performance: Encryption delay Decryption delay The tag calculation time is reduced by 20% compared to the highest security level.

[0065] Test Example 3: Quantum Protection Enhancement Experiment for Core Sensitive Data 1. Experimental objective: To verify the performance improvement effect and quantum resistance capability of the NTT module optimization in the protection of core sensitive data (such as financial transaction data).

[0066] 2. Test plan: (1) Test data preparation: Select 6144 bits of core sensitive simulation data (including encrypted fields such as transaction amount and account information). (2) Security parameter configuration: 1) Integrity monitoring module: Security level is set to "core sensitive", digest length is 192 bits; 2) Confidentiality protection module: Kyber-512 parameter set, NTT module optimization is enabled (butterfly operation unit integrates multiplication / modulo / compression and decompression, pre-compute lookup table optimizes modulo operation).

[0067] 3. Experimental steps: (1) Data writing stage: The original data is accelerated and encrypted by the optimized NTT module to generate ciphertext; the integrity monitoring module calculates and stores the 192-bit tag. (2) Data reading stage: The ciphertext is decrypted by the optimized NTT module, and the integrity verification tag is verified. (3) Comparative test: Compared with the scheme without NTT optimization, the difference in encryption and decryption delay is statistically analyzed.

[0068] 4. Test results: (1) Integrity: The integrity verification tag is consistent, the collision attack resistance level is 96 bits, and the original phenomenon attack resistance level is 192 bits; (2) Confidentiality: In the simulation test of quantum algorithm (Shor algorithm, Grover algorithm), the data was not cracked; (3) Performance optimization: After enabling NTT optimization, the encryption latency is reduced by 32% and the decryption latency is reduced by 70% compared with the unoptimized scheme. Compared with test example 1, the 192-bit digest scheme achieves a balance between security and resource overhead; (4) Compatibility: No need to modify the original E906 soft core module, directly adapt to the embedded system bus.

[0069] Test Case 4: Cross-Platform Porting Compatibility Experiment (Adapting to Different RISC-V Embedded Systems) 1. Experimental objective: To verify the portability of the present invention and test the compatibility of the security module (including the confidentiality protection module and the integrity monitoring module) in different RISC-V embedded systems.

[0070] 2. Test Plan: (1) Test Platform Adjustment: The security module was ported to two different RISC-V embedded systems (Platform A: E906 soft core + industrial control motherboard; Platform B: E907 soft core + IoT terminal motherboard). (2) Test Data Preparation: 6144 bits of cross-scenario sensitive data (industrial control instructions + IoT device status data). (3) Security Parameter Configuration: 1) Integrity Monitoring Module: The security level was set to "Important Sensitive", and the digest length was 128 bits; 2) Confidentiality Protection Module: The Kyber-512 parameter set was maintained and adapted to the bus interface protocols of different platforms.

[0071] 3. Test steps: (1) Module deployment: Connect the security module to the two platforms through the bus interface without modifying the original hardware and software modules of the platforms. (2) Data protection: Complete the data encryption, tag storage, decryption and verification operations according to the test example one. (3) Compatibility test: Test the module's running stability and data transmission compatibility under different platforms.

[0072] 4. Test results: (1) Portability: The security module was successfully deployed on both platforms in less than 2 hours, and no additional adaptation code was required; (2) Integrity and confidentiality: The data protection effect on both platforms was consistent with that of Test Instance 1, the tag verification was accurate, and there was no data leakage; (3) Stability: During the continuous 72-hour test, no module failure or performance degradation occurred, and the operating frequency was stable at around 100MHz; (4) Compatibility: It perfectly adapts to the bus protocols of different platforms, and there is no packet loss or abnormal delay in data transmission.

[0073] This invention achieves significant technical results in the field of sensitive data security protection in RISC-V embedded systems through algorithm selection optimization, architecture reuse design, and independent module deployment. All performance indicators, verified by FPGA (based on a Kintex 7 XC7K325 development board, 100MHz clock frequency), outperform existing technologies, as detailed below: 1. Safety meets quantum era protection standards (1) Outstanding confidentiality against quantum attacks: The invention employs the CRYSTALS-KYBER algorithm (Kyber-512 parameter set) and constructs a security mechanism based on the Module Learning Error Problem (MLWE), theoretically resisting attacks from Shor's algorithm and Grover's algorithm on quantum computers. Compared to traditional encryption schemes such as AES-256 and RSA-2048, this invention maintains stable confidentiality protection in the era of quantum computing, solving the problem of security failure of classical encryption algorithms under quantum threats.

[0074] (2) Leading integrity protection level: Based on the SHAKE-256 algorithm, it provides four security levels of 64 / 128 / 192 / 256 bits, which can achieve the highest 128-bit anti-collision attack and 256-bit anti-phenomenal attack, and the reverse collision probability reaches Compared with existing mainstream hardware security models, it has significant security advantages: 1) It outperforms the AES-GCM model (reverse collision probability). ); 2) Far exceeds the AEGIS model (reverse collision probability) ) and TEC-Tree model (reverse collision probability) ); 3) The lowest security level (64-bit digest) can also provide 32-bit collision resistance, reaching the highest security level of the lightweight hash algorithm L-Hash.

[0075] 2. Performance loss is significantly reduced, and operating efficiency is improved. (1) No performance loss in integrity verification: By designing a 4-stage pipeline for the SHAKE-256 module, the 24 round functions are instantiated using combinational logic and inserted into registers, enabling the integrity verification and embedded system to run in parallel. Test results show that this module does not introduce additional delay to the system and completely eliminates the performance degradation problem caused by traditional integrity verification modules.

[0076] (2) Encryption and decryption latency is significantly reduced: After optimizing the butterfly operation unit, designing the multiplication / modulo unit pipeline, and optimizing the pre-computed lookup table of the NTT module of the CRYSTALS-KYBER algorithm, the encryption and decryption efficiency is greatly improved: 1) Encryption latency is only Compared to existing hardware implementations of the Kyber algorithm (Ni Z et al.'s scheme), the encryption delay is significantly reduced. 1) Reduced by 32%; 2) Decryption delay only Compared to existing solutions (decryption delay) 1) Reduced by 70%; 2) The operating frequency is stable at over 100MHz to meet the real-time requirements of embedded systems.

[0077] 3. Optimized resource utilization and reduced deployment costs: (1) High hardware resource reuse rate: By utilizing the homology between the Keccak algorithm in CRYSTALS-KYBER and SHAKE-256 (both originating from the SHA-3 algorithm), the underlying Keccak-f

[1600] structure is reused, significantly reducing hardware resource redundancy. Compared with the scheme that requires separate deployment of encryption and hashing modules, this invention reduces the consumption of hardware logic resources while ensuring functional integrity.

[0078] (2) Reasonable and controllable storage overhead: The tag storage module adopts a secondary mapping mechanism, which greatly reduces the waste of tag storage resources. The overall storage resource overhead of the system is 37.1KB, which is higher than some low-security solutions (such as CETD's 13.81KB and XOM's 12.62KB), but it has obvious advantages in storage efficiency among similar solutions that provide quantum-level security protection, and does not exceed the carrying capacity of conventional storage resources in embedded systems.

[0079] 4. High reusability and portability, adaptable to a wide range of scenarios. Employing an independent architecture, this module interacts with the RISC-V E906 soft core via a bus, eliminating the need to modify existing embedded system modules. Testing and verification demonstrate that this module can be directly adapted to RISC-V embedded systems in various scenarios, including IoT, industrial control, automotive electronics, and financial equipment. Its flexible deployment and broad adaptability reduce the development costs of cross-platform applications.

[0080] 5. Flexible security level adaptation enhances usability. It supports flexible selection of four integrity digest output levels (64 / 128 / 192 / 256 bits) based on sensitivity level (extremely sensitive, core sensitive, important sensitive, general sensitive), which not only meets the high security requirements of defense, finance and other fields, but also adapts to lightweight security scenarios such as smart homes and ordinary IoT devices. It can balance security and resource consumption, and its practicality is significantly better than traditional solutions with fixed security levels.

[0081] The technical solution of this invention, through the synergistic effect of the confidentiality protection module and the integrity monitoring module, can achieve high security and low loss protection of sensitive data in embedded systems throughout their entire lifecycle. It can also support multiple security levels of data protection based on data sensitivity levels, thereby flexibly adapting to different security needs. At the same time, it has good reusability and portability, thus overcoming the defects of existing data security protection schemes such as excessive resource consumption, large performance loss, and limited applicability.

[0082] Example 3 Figure 4 This is a schematic diagram of a sensitive data security protection device for an embedded system provided in Embodiment 3 of the present invention. This device can execute the sensitive data security protection method for embedded systems provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. For example... Figure 4 As shown, the device includes: The confidentiality protection module is used to respond to the data write request of the embedded system, obtain the original sensitive data from the embedded system processor, encrypt the original sensitive data based on the post-quantum cryptography algorithm to obtain encrypted sensitive data, and send the encrypted sensitive data to the integrity monitoring module and the external memory. The integrity monitoring module is used to generate a first integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and to store the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; The integrity monitoring module is further configured to respond to the data read request of the embedded system, obtain the encrypted sensitive data from the external memory, generate a second integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and determine the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag; If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered.

[0083] Optionally, the confidentiality protection module includes an NTT module and a Keccak module; the NTT module integrates multiplication, modulo, and compression / decompression operations, the modulo operation is implemented based on a preset lookup table and a multi-level compression structure, the preset lookup table is used to describe the operation result of input data within a preset range after performing a modulo operation on a preset modulus.

[0084] Optionally, the confidentiality protection module further includes a data block caching module, which is used to convert the original sensitive data into 256-bit data blocks and cache the data that has been successfully verified.

[0085] Optionally, the post-quantum cryptography algorithm adopts the CRYSTALS-KYBER algorithm, the scalable output function algorithm adopts the SHAKE-256 algorithm, and the CRYSTALS-KYBER algorithm and the SHAKE-256 algorithm reuse the Keccak-f

[1600] operation structure of the Keccak module.

[0086] Optionally, the integrity monitoring module is further configured to: The sensitivity level of the encrypted sensitive data is determined based on the scenario source of the encrypted sensitive data; The digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; The first integrity verification tag of the encrypted sensitive data is generated using an extensible output function algorithm based on the digest length of the encrypted sensitive data.

[0087] Optionally, the integrity monitoring module is further configured to: If the sensitivity level of the encrypted sensitive data is extremely sensitive, then the digest length of the encrypted sensitive data is determined to be 256 bits; If the sensitivity level of the encrypted sensitive data is core sensitive, then the digest length of the encrypted sensitive data is determined to be 192 bits; If the sensitivity level of the encrypted sensitive data is "important sensitive", then the digest length of the encrypted sensitive data is determined to be 128 bits. If the sensitivity level of the encrypted sensitive data is general sensitivity, then the digest length of the encrypted sensitive data is determined to be 64 bits.

[0088] Optionally, the integrity monitoring module is further configured to: The first integrity verification tag is stored using a secondary mapping mechanism.

[0089] Optionally, the confidentiality protection module is further configured to: In response to a data read request from the embedded system, the encrypted sensitive data is retrieved from the external memory via the confidentiality protection module; If the verification is successful, the confidentiality protection module decrypts the encrypted sensitive data based on the post-quantum cryptography algorithm to obtain the original sensitive data, and then sends the original sensitive data to the embedded system processor.

[0090] The embedded system sensitive data security protection device provided in the embodiments of the present invention can execute the embedded system sensitive data security protection method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0091] Example 4 Figure 5A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0092] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0093] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as methods for protecting sensitive data in embedded systems.

[0095] In some embodiments, the embedded system sensitive data security protection method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the embedded system sensitive data security protection method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the embedded system sensitive data security protection method by any other suitable means (e.g., by means of firmware).

[0096] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0098] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0100] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0101] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0102] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for protecting sensitive data in an embedded system, characterized in that, The method includes: In response to a data write request from an embedded system, the original sensitive data is obtained from the embedded system processor through a confidentiality protection module, and the original sensitive data is encrypted based on a post-quantum cryptography algorithm to obtain encrypted sensitive data. The encrypted sensitive data is then sent to an integrity monitoring module and an external memory. The integrity monitoring module generates a first integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and stores the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; In response to the data read request of the embedded system, the encrypted sensitive data is obtained from the external memory through the integrity monitoring module, a second integrity verification tag for the encrypted sensitive data is generated based on the extensible output function algorithm, and the verification result of the encrypted sensitive data is determined according to the comparison result between the second integrity verification tag and the first integrity verification tag. If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered.

2. The method according to claim 1, characterized in that, The confidentiality protection module includes an NTT module and a Keccak module; the NTT module integrates multiplication, modulo, and compression / decompression operations. The modulo operation is implemented based on a preset lookup table and a multi-level compression structure. The preset lookup table is used to describe the operation result of input data within a preset range after performing a modulo operation on a preset modulus.

3. The method according to claim 2, characterized in that, The confidentiality protection module also includes a data block caching module, which is used to convert the original sensitive data into 256-bit data blocks and cache the data that has been successfully verified.

4. The method according to claim 2, characterized in that, The post-quantum cryptography algorithm uses the CRYSTALS-KYBER algorithm, and the scalable output function algorithm uses the SHAKE-256 algorithm. The CRYSTALS-KYBER algorithm and the SHAKE-256 algorithm reuse the Keccak-f[1600] operation structure of the Keccak module.

5. The method according to claim 1, characterized in that, The first integrity verification tag for the encrypted sensitive data is generated based on the extensible output function algorithm, including: The sensitivity level of the encrypted sensitive data is determined based on the scenario source of the encrypted sensitive data; The digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; The first integrity verification tag of the encrypted sensitive data is generated using an extensible output function algorithm based on the digest length of the encrypted sensitive data.

6. The method according to claim 5, characterized in that, Determining the digest length of the encrypted sensitive data based on its sensitivity level includes: If the sensitivity level of the encrypted sensitive data is extremely sensitive, then the digest length of the encrypted sensitive data is determined to be 256 bits; If the sensitivity level of the encrypted sensitive data is core sensitive, then the digest length of the encrypted sensitive data is determined to be 192 bits; If the sensitivity level of the encrypted sensitive data is "important sensitive", then the digest length of the encrypted sensitive data is determined to be 128 bits. If the sensitivity level of the encrypted sensitive data is general sensitivity, then the digest length of the encrypted sensitive data is determined to be 64 bits.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: In response to a data read request from the embedded system, the encrypted sensitive data is retrieved from the external memory via the confidentiality protection module; If the verification is successful, the confidentiality protection module decrypts the encrypted sensitive data based on the post-quantum cryptography algorithm to obtain the original sensitive data, and then sends the original sensitive data to the embedded system processor.

8. A sensitive data security protection device for embedded systems, characterized in that, The device includes: The confidentiality protection module is used to respond to the data write request of the embedded system, obtain the original sensitive data from the embedded system processor, encrypt the original sensitive data based on the post-quantum cryptography algorithm to obtain encrypted sensitive data, and send the encrypted sensitive data to the integrity monitoring module and the external memory. The integrity monitoring module is used to generate a first integrity verification tag for the encrypted sensitive data based on an extensible output function algorithm, and to store the first integrity verification tag; wherein, the digest length of the encrypted sensitive data is determined based on the sensitivity level of the encrypted sensitive data; The integrity monitoring module is further configured to respond to the data read request of the embedded system, obtain the encrypted sensitive data from the external memory, generate a second integrity verification tag for the encrypted sensitive data based on the extensible output function algorithm, and determine the verification result of the encrypted sensitive data based on the comparison result between the second integrity verification tag and the first integrity verification tag; If the verification fails, an interrupt signal is sent to the embedded system processor, and a security alarm is triggered.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the embedded system sensitive data security protection method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the embedded system sensitive data security protection method according to any one of claims 1-7.

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