Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes a plurality of sub-pixels, a plurality of data lines electrically connected to the plurality of sub-pixels, a plurality of data pads electrically connected to the plurality of data lines, a plurality of test pads including a first test pad and a second test pad, the first test pad and the second test pad being spaced apart from the plurality of data pads, a first group of demultiplexing switching elements connecting a first group of data lines among the plurality of data lines to the plurality of data pads, a second group of demultiplexing switching elements connecting a second group of data lines among the plurality of data lines to the plurality of data pads, and a first test switching element between a first electrode of any one of first demultiplexing switching elements included in the first group of demultiplexing switching elements and the first test pad.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0184597, filed on December 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to display devices and electronic devices including the display devices. Background Technology

[0003] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smartphones, digital cameras, laptops, navigators, and smart TVs.

[0004] Display devices include light-receiving display devices such as liquid crystal display devices, field emission display devices, and light-emitting display devices, as well as organic light-emitting display devices including organic light-emitting elements, inorganic light-emitting display devices including inorganic light-emitting elements such as inorganic semiconductors, and micron-emitting display devices including micron-emitting elements. Summary of the Invention

[0005] Embodiments of this disclosure may relate to a display device capable of testing the data voltage output from a demultiplexing switching element.

[0006] However, this disclosure is not limited thereto, and the above and additional aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description or may be learned by practicing one or more of the embodiments presented in this disclosure.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a plurality of sub-pixels; a plurality of data lines electrically connected to the plurality of sub-pixels; a plurality of data pads electrically connected to the plurality of data lines; a plurality of test pads, including a first test pad and a second test pad, the first test pad and the second test pad being spaced apart from the plurality of data pads; a first set of demultiplexing switching elements connecting a first set of data lines among the plurality of data lines to the plurality of data pads; a second set of demultiplexing switching elements connecting a second set of data lines among the plurality of data lines to the plurality of data pads; and a first test switching element located between a first electrode of any of the first demultiplexing switching elements included in the first set of demultiplexing switching elements and a first test pad.

[0008] In an embodiment, other first demultiplexing switching elements may be electrically disconnected from the first test switching element, except for any one of the first demultiplexing switching elements included in the first group of demultiplexing switching elements.

[0009] In an embodiment, the display device may further include: a second test switch element located between the first electrode of any of the second demultiplexing switch elements included in the second set of demultiplexing switch elements and the second test pad.

[0010] In an embodiment, other second demultiplexing switching elements may be electrically disconnected from the second test switching element, except for any one of the second demultiplexing switching elements included in the second set of demultiplexing switching elements.

[0011] In an embodiment, the display device may further include: a resistor connected to the gate electrode of the first test switch element and the gate electrode of the second test switch element.

[0012] In an embodiment, the display device may further include an electrostatic discharge circuit electrically connected to a plurality of data pads, a plurality of test pads, and a resistor.

[0013] In one embodiment, the first set of demultiplexing switching elements may include multiple transistors connected in parallel with each other.

[0014] In one embodiment, the second set of demultiplexing switching elements may include multiple transistors connected in parallel with each other.

[0015] In one embodiment, the first test switch element may include a plurality of transistors connected in series with each other.

[0016] In one embodiment, the second test switch element may include a plurality of transistors connected in series with each other.

[0017] In an embodiment, the plurality of sub-pixels may include: a first group of sub-pixels connected to a first group of demultiplexing switch elements via a first group of data lines; and a second group of sub-pixels connected to a second group of demultiplexing switch elements via a second group of data lines. Any one of the plurality of first sub-pixels included in the first group of sub-pixels can implement a first color and can be connected to any one of the first demultiplexing switch elements, and any one of the plurality of second sub-pixels included in the second group of sub-pixels can implement a first color and can be connected to any one of the second demultiplexing switch elements.

[0018] In an embodiment, any one of the plurality of first sub-pixels can be connected to the first electrode of any one of the first demultiplexing switching elements, and any one of the plurality of second sub-pixels can be connected to the first electrode of any one of the second demultiplexing switching elements.

[0019] According to one or more embodiments of this disclosure, an electronic device includes: a display module configured to display an image; a power supply module configured to supply power to the display module; and a processor configured to transmit data signals and control signals to the display module. The display module includes: a plurality of sub-pixels; a plurality of data lines electrically connected to the plurality of sub-pixels; a plurality of data pads electrically connected to the plurality of data lines; a plurality of test pads, including a first test pad and a second test pad, the first and second test pads being spaced apart from the plurality of data pads; a first set of demultiplexing switching elements connecting a first set of data lines among the plurality of data lines to the plurality of data pads; a second set of demultiplexing switching elements connecting a second set of data lines among the plurality of data lines to the plurality of data pads; and a first test switching element located between a first electrode of any of the first demultiplexing switching elements included in the first set of demultiplexing switching elements and a first test pad.

[0020] In an embodiment, the electronic device may further include a resistive active layer, and the first test switch element may include the first test active layer and a first test gate electrode located on a gate insulating film covering the first test active layer. The resistive active layer may be electrically connected to the first test gate electrode of the first test switch element, and the first test active layer may include: a first electrode connected to a first electrode of any of the first demultiplexing switch elements; a second electrode connected to a first test pad; and a channel located between the first electrode and the second electrode of the first test active layer.

[0021] In an embodiment, the first test active layer and the resistive active layer may be located on the same layer as each other.

[0022] In an embodiment, the electronic device may further include: a second test switch element located between a first electrode of any of the second demultiplexing switch elements included in the second set of demultiplexing switch elements and a second test pad; the second test switch element may include a second test active layer and a second test gate electrode located on a gate insulating film covering the second test active layer. A resistive active layer may be electrically connected to the second test gate electrode of the second test switch element, and the second test active layer may include: a first electrode connected to the first electrode of any of the second demultiplexing switch elements; a second electrode connected to the second test pad; and a channel located between the first electrode and the second electrode of the second test active layer.

[0023] In an embodiment, the first electrode of the first test switch element can be connected to the first electrode of any of the first demultiplexing switch elements via a second test connection line, the second electrode of the first test switch element can be connected to the first test pad via a first test connection line, the first electrode of the second test switch element can be connected to the first electrode of any of the second demultiplexing switch elements via a fourth test connection line, and the second electrode of the second test switch element can be connected to the second test pad via a third test connection line. The second test connection line and the fourth test connection line can be located on the same layer as each other.

[0024] In this embodiment, the first test connection line and the third test connection line may be located on different layers.

[0025] In an embodiment, the electronic device may further include: a first power line configured to be applied a first power supply voltage, and the first power line may be spaced apart from the first test switch element in a plan view.

[0026] In an embodiment, the first power line may be separated from the active resistive layer in a plan view.

[0027] In an embodiment, the first power line may overlap with the first set of demultiplexing switching elements and the second set of demultiplexing switching elements in a plan view.

[0028] In an embodiment, the electronic device may further include: a first resistive connection electrode connected to the resistive active layer through a plurality of first sets of resistive contact holes; and a second resistive connection electrode connected to the resistive active layer through a plurality of second sets of resistive contact holes;

[0029] In an embodiment, the number of the plurality of first group resistor contact holes connecting the first resistor connection electrode to the resistor active layer can be the same as the number of the plurality of second group resistor contact holes connecting the second resistor connection electrode to the resistor active layer.

[0030] In this embodiment, the resistance of the active resistive layer can be above 1000Ω and below 10000Ω.

[0031] In an embodiment, the plurality of data pads may include a first data pad and a second data pad, and at least one of the plurality of demultiplexing connection lines connecting the first data pad to the first set of demultiplexing switching elements may be located on a different layer from at least one of the plurality of demultiplexing connection lines connecting the second data pad to the first set of demultiplexing switching elements.

[0032] According to some embodiments of this disclosure, in a display device, a first test switch element and a second test switch element can be turned on to supply data voltages applied to each of a first sub-pixel and a second sub-pixel that implement a first color. An operator can turn on the test switch elements to check whether appropriate data voltages are output to the multiple sub-pixels from the first and second demultiplexing switch elements. Additionally, in cases where measuring the output data voltage is not desired due to reasons such as product shipping, the test switch elements can be turned off. Accordingly, interference with data lines disposed in the display area (e.g., current leakage or the occurrence of parasitic capacitance) can be reduced.

[0033] According to some embodiments of this disclosure, the display device may include an electrostatic discharge (ESD) circuit for output units connected to multiple pads via adjacent lines. Additionally, the display device may include a resistor connected to a test gate pad. Unlike a resistor, the ESD circuit can perform the function of discharging static electricity to the outside of the display device using grounding or the like. A resistor can protect the display device from ESD while smoothly turning on / off test switching elements.

[0034] According to some embodiments of this disclosure, the display device may include a plurality of test switching elements, a plurality of test pads, and a test gate pad to test the data voltage output from the demultiplexing switching elements. In this case, it can be verified whether the first demultiplexing switching element for implementing the first color and the second demultiplexing switching element for implementing the first color uniformly output the data voltage from the first data pad.

[0035] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and other aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and will be apparent in part from the description or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0036] The above and other aspects and features of this disclosure will become clearer from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0037] Figure 1 This is a perspective view illustrating a display device according to an embodiment of the present disclosure;

[0038] Figure 2 This is a plan view illustrating a display device according to an embodiment of the present disclosure;

[0039] Figure 3 This is a circuit diagram illustrating a display device according to an embodiment of the present disclosure;

[0040] Figure 4 It is a diagram. Figure 2 A magnified view of part J;

[0041] Figure 5A It is a diagram. Figure 2 A magnified view of part K;

[0042] Figure 5B It is a diagram. Figure 5A A magnified view of part L;

[0043] Figure 5C It is a diagram. Figure 5A A magnified view of part M;

[0044] Figure 5D It is a diagram. Figure 5A A magnified view of part N;

[0045] Figure 6 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line I-I';

[0046] Figure 7 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line II-II';

[0047] Figure 8 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line III-III';

[0048] Figure 9 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line IV-IV';

[0049] Figure 10 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line II-II';

[0050] Figure 11 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line III-III';

[0051] Figure 12 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line IV-IV';

[0052] Figure 13 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line V-V';

[0053] Figure 14 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line VI-VI';

[0054] Figure 15 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line VII-VII';

[0055] Figure 16 This is a block diagram of an electronic device according to embodiments of the present disclosure; and

[0056] Figure 17 The figure shows a schematic diagram of an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0057] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be embodied in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals refer to the same elements throughout the drawings and written description, and therefore, redundant descriptions will not be repeated.

[0058] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0059] Furthermore, as will be understood by those skilled in the art, given the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of one another or in combination with one another in any suitable way, unless otherwise stated or implied.

[0060] In the accompanying drawings, for clarity, the relative sizes, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” are used herein to describe the relationship of one element or feature relative to another element(s) as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both the above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0061] Furthermore, it should be anticipated that the shapes shown in the figures may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Accordingly, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, but should be interpreted in light of possible shape variations, such as those due to manufacturing processes. Therefore, the shapes shown in the figures may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0062] In the various figures, the X, Y, and Z axes are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X, Y, and Z axes can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0063] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion without departing from the spirit and scope of this disclosure.

[0064] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or coupled to that other element or layer, or one or more intermediary elements or layers may exist. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be directly electrically connected to that other layer, region, or element, or it may be indirectly electrically connected to that other layer, region, or element using one or more intermediary layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between those two elements or layers, or one or more intermediary elements or layers may exist.

[0065] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and “having,” and variations thereof, indicate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the listed associated items. For example, the expression “A and / or B” means A, B, or A and B. Expressions such as “at least one of”, when placed after a list of elements, modify the entire list of elements rather than individual elements in that list. For example, the expressions “at least one of a, b, and c” and “at least one selected from the group consisting of a, b, and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0066] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to take into account the inherent biases of measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0067] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense.

[0068] Figure 1 This is a perspective view illustrating a display device according to an embodiment of the present disclosure. Figure 2 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0069] refer to Figure 1 and Figure 2 The display device 10 is a device for displaying moving or still images. The display device 10 can be used as a display screen for various suitable products such as televisions, laptops, monitors, billboards, and devices for the Internet of Things (IoT), as well as for various suitable portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic diaries, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs).

[0070] Display device 10 may be an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or a micron (or nano) light-emitting display device using micron (or nano) light-emitting diodes (micron LEDs or nano LEDs). In the following description, for ease of explanation, display device 10 may be described in more detail in the context of an organic light-emitting display device, but this disclosure is not limited thereto.

[0071] The display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

[0072] The display panel 100 can be formed as a rectangular plane having a long side extending in a first direction (e.g., the X-axis direction) and a short side extending in a second direction (e.g., the Y-axis direction) intersecting the first direction. The corners where the long side extending in the first direction (e.g., the X-axis direction) and the short side extending in the second direction (e.g., the Y-axis direction) intersect each other can be formed at right angles or rounded to have a suitable curvature (e.g., a predetermined curvature). However, the planar shape of the display panel 100 is not limited to a rectangular shape and can be formed in other polygonal, circular, or elliptical shapes. The display panel 100 can be formed as flat or substantially flat, but this disclosure is not limited thereto. For example, the display panel 100 may include curved portions with constant or variable curvature formed at the left and right ends or sides. Additionally, the display panel 100 can be flexibly formed to be bent, twisted, folded, rolled, or rolled.

[0073] The display panel 100 may include a display area DA for displaying images and a non-display area NDA disposed near the display area DA (e.g., adjacent to the display area DA). As another example, the display area DA and the non-display area NDA may be defined within a substrate of the display panel 100.

[0074] The display area DA can occupy most of the area of ​​the display panel 100. The display area DA can be set in the center of the display panel 100. Pixels can be set in the display area DA to display images.

[0075] The non-display area NDA can be set to be adjacent to the display area DA. The non-display area NDA can be the outer periphery of the display area DA. The non-display area NDA can be set to surround the display area DA (e.g., around the periphery of the display area DA). The non-display area NDA can be an edge region of the display panel 100.

[0076] The pads (PADs) can be located in the non-display area (NDA) so that they are electrically connected to the circuit board 300. The pads (PADs) can also be located at one edge of the display panel 100. For example, the pads (PADs) can be located at the lower edge of the display panel 100.

[0077] Circuit board 300 can be disposed on a pad PAD located at one edge of display panel 100. Circuit board 300 can be attached to pad PAD using a low-resistance and high-reliability material such as anisotropic conductive film or self-assembling anisotropic conductive adhesive (SAP). Therefore, circuit board 300 can be electrically connected to the signal lines of display panel 100. Display panel 100 can receive data voltage, power supply voltage, and scan timing signals through circuit board 300. Circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as chip-on-film.

[0078] The display driver circuit 200 can generate data voltage, power supply voltage, and scan timing signals. The display driver circuit 200 can supply the data voltage, power supply voltage, and scan timing signals to the display panel 100 via the circuit board 300.

[0079] Each of the display driving circuits 200 can be formed of an integrated circuit (IC) and attached to the circuit board 300. As another example, the display driving circuits 200 can be attached to the display panel 100 in a chip-on-glass (COG) mode, a chip-on-plastic (COP) mode, or an ultrasonic bonding mode.

[0080] Figure 3 This is a circuit diagram illustrating a display device according to an embodiment of the present disclosure.

[0081] refer to Figure 3 The display device according to embodiments of the present disclosure includes pads, a first set of demultiplexing switching elements GDEMT1, a second set of demultiplexing switching elements GDEMT2, a first test switching element TET1, a second test switching element TET2, a resistor RP, a first set of sub-pixels GSP1, and a second set of sub-pixels GSP2. Hereinafter, the switching elements may be described in more detail as switching thin-film transistors (TFTs), but the present disclosure is not limited thereto.

[0082] The first group of sub-pixels GSP1 and the second group of sub-pixels GSP2 can be set in the display area, and other elements besides the first group of sub-pixels GSP1 and the second group of sub-pixels GSP2 can be set in the non-display area.

[0083] The first group of subpixels GSP1 may include multiple first subpixels SP11, SP12, and SP13. The multiple first subpixels SP11, SP12, and SP13 may include a first subpixel SP11 for implementing a first color, a second subpixel SP12 for implementing a second color, and a third subpixel SP13 for implementing a third color.

[0084] The second group of subpixels GSP2 may include multiple second subpixels SP21, SP22, and SP23. These multiple second subpixels SP21, SP22, and SP23 may include a second subpixel SP21 for implementing the first color, a second subpixel SP22 for implementing the second color, and a third subpixel SP23 for implementing the third color.

[0085] In a display device according to an embodiment of the present disclosure, a first group of sub-pixels GSP1 and a second group of sub-pixels GSP2 may be repeatedly arranged along a first direction (e.g., a row direction). As shown, the first group of sub-pixels GSP1 and the second group of sub-pixels GSP2 may be arranged sequentially along the first direction, and may be repeatedly arranged along the first direction starting from the second group of sub-pixels GSP2.

[0086] In the first group of sub-pixels GSP1, each of the first sub-pixel SP11 for implementing the first color, the second sub-pixel SP12 for implementing the second color, and the first sub-pixel SP13 for implementing the third color can be repeatedly set in the second direction (e.g., the column direction).

[0087] In the second group of sub-pixels GSP2, each of the second sub-pixel SP21 for implementing the first color, the second sub-pixel SP22 for implementing the second color, and the third sub-pixel SP23 for implementing the third color can be repeatedly set in the second direction (e.g., the column direction).

[0088] Each of the first, second, and third colors can be any suitable color selected from the group consisting of red, green, and blue, so as not to repeat each other. For example, the first color can be red, the second color can be green, and the third color can be blue, but this disclosure is not limited thereto.

[0089] The pads may include multiple data pads DP1, DP2, and DP3, multiple test pads TP1 and TP2, a test gate pad TGP, multiple clock pads CLP1 and CLP2, and multiple gate pads GP. The multiple test pads TP1 and TP2 may be separated from the multiple data pads DP1, DP2, and DP3.

[0090] Multiple data pads DP1, DP2, and DP3 can supply data voltage to the first group of sub-pixels GSP1 and the second group of sub-pixels GSP2. The multiple data pads DP1, DP2, and DP3 can include a first data pad DP1, a second data pad DP2, and a third data pad DP3.

[0091] The data voltage supplied from the first data pad DP1, the second data pad DP2, and the third data pad DP3 can be applied to a plurality of first sub-pixels SP11, SP12, and SP13 disposed in the first group of sub-pixels GSP1, and a plurality of second sub-pixels SP21, SP22, and SP23 disposed in the second group of sub-pixels GSP2, respectively.

[0092] For example, a data voltage supplied from the first data pad DP1 can be applied to a first sub-pixel SP11 and a second sub-pixel SP21 for implementing a first color. A data voltage supplied from the second data pad DP2 can be applied to a first sub-pixel SP12 and a second sub-pixel SP22 for implementing a second color. A data voltage supplied from the third data pad DP3 can be applied to a first sub-pixel SP13 and a second sub-pixel SP23 for implementing a third color. However, this disclosure is not limited to the examples described above.

[0093] The first set of demultiplexing switching elements GDEMT1 may include multiple first demultiplexing switching elements, and the second set of demultiplexing switching elements GDEMT2 may include multiple second demultiplexing switching elements.

[0094] The gate electrode of the first set of demultiplexing switching elements GDEMT1 can be connected to the first clock pad CLP1. The first electrodes of the plurality of first demultiplexing switching elements included in the first set of demultiplexing switching elements GDEMT1 can be respectively connected to the first sub-pixel SP11 for implementing the first color, the first sub-pixel SP12 for implementing the second color, and the first sub-pixel SP13 for implementing the third color. The second electrodes of the plurality of first demultiplexing switching elements included in the first set of demultiplexing switching elements GDEMT1 can be respectively connected to the first data pad DP1, the second data pad DP2, and the third data pad DP3. The first set of demultiplexing switching elements GDEMT1 can be turned on by a signal applied through the first clock pad CLP1, so that the data voltages transmitted from the first data pad DP1, the second data pad DP2, and the third data pad DP3 are respectively applied to the first sub-pixel SP11 for implementing the first color, the first sub-pixel SP12 for implementing the second color, and the first sub-pixel SP13 for implementing the third color.

[0095] The gate electrode of the second set of demultiplexing switching elements GDEMT2 can be connected to the second clock pad CLP2. The first electrodes of the plurality of second demultiplexing switching elements included in the second set of demultiplexing switching elements GDEMT2 can be respectively connected to the second sub-pixel SP21 for implementing the first color, the second sub-pixel SP22 for implementing the second color, and the second sub-pixel SP23 for implementing the third color. The second electrodes of the plurality of second demultiplexing switching elements included in the second set of demultiplexing switching elements GDEMT2 can be respectively connected to the first data pad DP1, the second data pad DP2, and the third data pad DP3. The second set of demultiplexing switching elements GDEMT2 can be turned on by a signal applied through the second clock pad CLP2, so that the data voltages transmitted from the first data pad DP1, the second data pad DP2, and the third data pad DP3 are respectively applied to the second sub-pixel SP21 for implementing the first color, the second sub-pixel SP22 for implementing the second color, and the second sub-pixel SP23 for implementing the third color.

[0096] A first data pad DP1 can be connected to a first sub-pixel SP11 and a second sub-pixel SP21 for implementing a first color. A first demultiplexing switch element DEMT1 for implementing the first color can be disposed between the first sub-pixel SP11 and the first data pad DP1. A second demultiplexing switch element for implementing the first color can be disposed between the second sub-pixel SP21 and the first data pad DP1.

[0097] The second data pad DP2 can be connected to the first sub-pixel SP12 and the second sub-pixel SP22 used to implement the second color. A first demultiplexing switch element used to implement the second color can be disposed between the first sub-pixel SP12 and the second data pad DP2. A second demultiplexing switch element used to implement the second color can be disposed between the second sub-pixel SP22 and the second data pad DP2.

[0098] The third data pad DP3 can be connected to the first sub-pixel SP13 and the second sub-pixel SP23 used to implement the third color. A first demultiplexing switch element used to implement the third color can be disposed between the first sub-pixel SP13 and the third data pad DP3. A second demultiplexing switch element used to implement the third color can be disposed between the second sub-pixel SP23 and the third data pad DP3.

[0099] Each of the first demultiplexing switching element and the second demultiplexing switching element that implements one of the first, second, and third colors may include a plurality of sub-demultiplexing switching elements DEMT11, DEMT12, DEMT13, and DEMT14 connected in parallel with each other. For example, refer to Figure 3 An enlarged view of the first demultiplexing switch element DEMT1 in the image shows that the first demultiplexing switch element DEMT1, used to implement the first color, may include a first sub-demultiplexing switch element DEMT11, a second sub-demultiplexing switch element DEMT12, a third sub-demultiplexing switch element DEMT13, and a fourth sub-demultiplexing switch element DEMT14. The first electrodes of the sub-demultiplexing switch elements can be connected to the same nodes as each other, and the second electrodes of the sub-demultiplexing switch elements can be connected to the same nodes as each other. Because the first demultiplexing switch element DEMT1 includes multiple sub-demultiplexing switch elements DEMT11, DEMT12, DEMT13, and DEMT14 connected in parallel, it can handle relatively large currents and reduce the power consumption of the display device.

[0100] As described above, the first electrode of the first demultiplexing switch element DEMT1 for implementing the first color can be connected to the first sub-pixel SP11 for implementing the first color. Additionally, the first electrode of the first demultiplexing switch element DEMT1 for implementing the first color can also be connected to the first test pad TP1. The first electrode of the first demultiplexing switch element DEMT1 for implementing the first color can be connected not only to the first sub-pixel SP11 for implementing the first color, but also to the first test pad TP1. The first test switch element TET1 can be disposed between the first electrode of the first demultiplexing switch element DEMT1 for implementing the first color and the first test pad TP1. The gate electrode of the first test switch element TET1 can be connected to the test gate pad TGP. The first electrode of the first test switch element TET1 can be connected to the first electrode of the first demultiplexing switch element DEMT1 for implementing the first color. The second electrode of the first test switch element TET1 can be connected to the first test pad TP1.

[0101] As described above, the first connection electrode of the second demultiplexing switch element used to implement the first color can be connected to the second sub-pixel SP21 used to implement the first color. Additionally, the first connection electrode of the second demultiplexing switch element used to implement the first color can also be connected to the second test pad TP2. The first connection electrode of the second demultiplexing switch element used to implement the first color can be connected not only to the second sub-pixel SP21 used to implement the first color, but also to the second test pad TP2. The second test switch element TET2 can be disposed between the first connection electrode of the second demultiplexing switch element used to implement the first color and the second test pad TP2. The gate electrode of the second test switch element TET2 can be connected to the test gate pad TGP. The first electrode of the second test switch element TET2 can be connected to the first connection electrode of the second demultiplexing switch element used to implement the first color. The second electrode of the second test switch element TET2 can be connected to the second test pad TP2.

[0102] The gate electrode of the first test switch element TET1 and the gate electrode of the second test switch element TET2 can be connected to the test gate pad TGP. The first test switch element TET1 and the second test switch element TET2 can be turned on by a signal applied through the test gate pad TGP. The first test switch element TET1 and the second test switch element TET2, which can be turned on, supply data voltage applied to each of the first sub-pixel SP11 and the second sub-pixel SP21 that implement the first color. The operator can turn on the test switch elements TET1 and TET2 to check whether appropriate data voltages are output to the multiple sub-pixels from the first demultiplexing switch element and the second demultiplexing switch element. Additionally, in cases where it is not desirable to measure the output data voltage due to reasons such as product shipping, the test switch elements can be turned off. Accordingly, interference with data lines located in the display area (e.g., current leakage or parasitic capacitance) can be reduced.

[0103] Each of the first test switch element TET1 and the second test switch element TET2 may include a plurality of sub-test switch elements connected in series.

[0104] For example, refer to Figure 3In an enlarged view, the first test switch element TET1 may include a first sub-test switch element (e.g., the 11th test switch element) TET11 and a second sub-test switch element (e.g., the 12th test switch element) TET12. The first electrode of the first sub-test switch element TET11 may be connected to the second electrode of the second sub-test switch element TET12. The second electrode of the first sub-test switch element TET11 may be connected to the first test pad TP1. The first electrode of the second sub-test switch element TET12 may be connected to the first electrode of the first demultiplexing switch element DEMT1. Because the first test switch element TET1 includes the series-connected sub-test switch elements TET11 and TET12, high-voltage processing can be performed more smoothly, and overheating of individual switch elements can be prevented or substantially prevented. Therefore, the reliability of the display device can be improved.

[0105] The second test switch element TET2 may include a third sub-test switch element (e.g., the 21st test switch element) TET21 and a fourth sub-test switch element (e.g., the 22nd test switch element) TET22. The first electrode of the third sub-test switch element TET21 may be connected to the second electrode of the fourth sub-test switch element TET22. The second electrode of the third sub-test switch element TET21 may be connected to the second test pad TP2. The first electrode of the fourth sub-test switch element TET22 may be connected to the first electrode of the second demultiplexing switch element.

[0106] The display device according to an embodiment may further include a resistor RP disposed between the test gate pad TGP and the first test switch element TET1 (or the second test switch element TET2). The resistor RP can be used to protect the test switch elements TET1 and TET2, including the first test switch element TET1 and the second test switch element TET2, and the sub-pixels SP11, SP12, SP13, SP21, SP22, and SP23 disposed in the display area from electrostatic discharge (ESD) that may occur from the test gate pad TGP. In an embodiment, the resistance of the resistor RP may be greater than 1000Ω and less than 10000Ω. The resistance of the resistor RP may be substantially equal to the resistance of the resistive active layer constituting the resistor RP (as discussed later). When the resistance of the resistor RP is less than 1000Ω, the display device may not be adequately protected from ESD. When the resistance of the resistor RP is greater than 10000Ω, the first test switch element TET1 or the second test switch element TET2 may not be properly turned on or off, thereby potentially resulting in inadequate testing or interference. More specifically, the resistance of resistor RP can be 2000Ω or more and 8000Ω or less. More specifically, the resistance of resistor RP can be 3000Ω or more and 6000Ω or less. Within these ranges, the display device can be appropriately protected from electrostatic discharge while the first test switch element TET1, etc., is smoothly turned on / off. In embodiments, resistor RP can be omitted as needed or desired.

[0107] The display device according to embodiments of this disclosure may further include an electrostatic discharge circuit (EDC) connected via adjacent lines to output units of multiple pads TGP, TP1, TP2, DP1, DP2, and DP3. Unlike the resistor RP, the EDC can perform the function of discharging static electricity to the outside of the display device by utilizing grounding or the like. For example, an EDC capable of discharging static electricity to external parts of the display device may be provided. The EDC may be connected to multiple pads, and the resistor RP may be connected to the test gate pad TGP.

[0108] The display device according to an embodiment of the present disclosure includes a plurality of test switching elements TET1 and TET2, a plurality of test pads TP1 and TP2, and a test gate pad TGP, for testing the data voltage output from the demultiplexing switching elements. In this case, it can be verified whether the first demultiplexing switching element DEMT1 for implementing the first color and the second demultiplexing switching element for implementing the first color output the data voltage from the first data pad DP1 uniformly or substantially uniformly.

[0109] To verify the uniformity of the output data voltage, the display device according to embodiments of this disclosure connects a first test pad TP1 to any one (e.g., a single) of the first demultiplexing switching elements. The first test switching element TET1 may be disposed between the first demultiplexing switching element and the first test pad TP1. A first set of demultiplexing switching elements GDEMT1 may include a plurality of first demultiplexing switching elements. The plurality of first demultiplexing switching elements may include any one of the first demultiplexing switching elements connected to the first test pad TP1 (e.g., DEMT1) and other first demultiplexing switching elements besides that one (e.g., DEMT1).

[0110] The figure shows an enlarged view of the first set of demultiplexing switch elements GDEMT1. The first demultiplexing switch element DEMT1 can be any of the aforementioned "first demultiplexing switch elements", and other first demultiplexing switch elements besides "any of the first demultiplexing switch elements" can be electrically decoupled from the first test switch element TET1 and the first test pad TP1.

[0111] Similarly, to verify the uniformity of the output data voltage, the display device according to embodiments of this disclosure connects the second test pad TP2 to any one (e.g., a single) of the second demultiplexing switching elements. The second test switching element TET2 may be disposed between the second demultiplexing switching element and the second test pad TP2. The second set of demultiplexing switching elements GDEMT2 may include a plurality of second demultiplexing switching elements. The plurality of second demultiplexing switching elements may include any one of the second demultiplexing switching elements connected to the second test pad TP2, and other second demultiplexing switching elements besides that one. The other second demultiplexing switching elements besides that one of the second demultiplexing switching elements in the second set of demultiplexing switching elements GDEMT2 may be electrically disconnected from the second test switching element TET2 and the second test pad TP2.

[0112] In an embodiment, the color (e.g., the first color) implemented by a sub-pixel connected to the first test pad TP1 (e.g., the first sub-pixel SP11 for implementing the first color) can be the same as the color (e.g., the first color) implemented by a sub-pixel connected to the second test pad TP2 (e.g., the second sub-pixel SP21 for implementing the first color). Additionally, the first test switch element TET1 and the second test switch element TET2 can be connected to the same data pad (e.g., the first data pad DP1).

[0113] In a display device according to an embodiment of the present disclosure, multiple test pads TP1 and TP2 are respectively connected to the first electrodes of multiple demultiplexing switching elements (e.g., a first demultiplexing switching element DEMT1 for implementing a first color and a second demultiplexing switching element for implementing a first color) connected to the same data pad (e.g., a first data pad DP1). Therefore, it is possible to check whether the data voltage supplied from the data pads is properly applied to the sub-pixel after the demultiplexing switching element.

[0114] Figure 4 It is a diagram. Figure 2 A magnified view of part J. Figure 5A It is a diagram. Figure 2 A magnified view of part K. Figure 5B It is a diagram. Figure 5A A magnified view of part L. Figure 5C It is a diagram. Figure 5A A magnified view of part M. Figure 5D It is a diagram. Figure 5A A magnified view of part N.

[0115] refer to Figure 2 and Figure 4 The test gate pad TGP can be connected to the resistor connection line RPCL. The first test pad TP1 can be connected to the first test connection line TECL1, and the second test pad TP2 can be connected to the third test connection line TECL3. The first data pad DP1 can be connected to the 13th demultiplexing connection line DEML13, the second data pad DP2 can be connected to the 23rd demultiplexing connection line DEML23, and the third data pad DP3 can be connected to the 33rd demultiplexing connection line DEML33.

[0116] The resistor connection line RPCL, the first test connection line TECL1, the second test connection line TECL2, the 13th demultiplexing connection line DEML13, the 23rd demultiplexing connection line DEML23, and the 33rd demultiplexing connection line DEML33 can all be connected to the lines connected to the electrostatic discharge circuit EDC via multiple contact holes. The lines connected to the electrostatic discharge circuit EDC are connected to multiple interconnected cross lines via contact holes, and the multiple cross lines are then reconnected to the resistor connection line RPCL, the first test connection line TECL1, the second test connection line TECL2, the 13th demultiplexing connection line DEML13, the 23rd demultiplexing connection line DEML23, and the 33rd demultiplexing connection line DEML33 via contact holes.

[0117] refer to Figure 2 , Figure 4 as well as Figures 5A to 5DThe 13th demultiplexing connection line DEML13 can be connected to the 12th demultiplexing connection line DEML12 through the first demultiplexing connection contact hole DEMCT1. The first demultiplexing connection contact hole DEMCT1 can be formed as a plurality of first demultiplexing connection contact holes. In the following text, the mention of multiple contact holes may be omitted.

[0118] Demultiplexing cable DEML12 (number 12) can be connected to demultiplexing cable DEML111 (number 11) via demultiplexing connection contact hole DEMCT11. Demultiplexing cable DEML12 (number 12) can be connected to demultiplexing cable DEML211 (number 21) via demultiplexing connection contact hole DEMCT21.

[0119] The 111th demultiplexing connection line DEML111 can be connected to the second connection electrode DEMSD211 of the first demultiplexing switching element used to achieve the first color through the 11th demultiplexing contact hole DECT11.

[0120] The second connection electrode DEMSD211 of the first demultiplexing switching element for implementing the first color can be connected to the 11th demultiplexing active layer DEMACT11 via a contact hole. The 11th demultiplexing active layer DEMACT11, together with the 11th demultiplexing gate electrode DEMG11, constitutes the first demultiplexing switching element for implementing the first color. The 11th demultiplexing gate electrode DEMG11 can be connected to the first clock line CL1. The 11th demultiplexing active layer DEMACT11 can be connected to the first connection electrode DEMSD111 of the first demultiplexing switching element for implementing the first color via a contact hole. The first connection electrode DEMSD111 of the first demultiplexing switching element for implementing the first color is connected to the 11th data line DL11, and the 11th data line DL11 can apply a data voltage from the first data pad DP1 to the first sub-pixel SP11 for implementing the first color.

[0121] The 211th demultiplexing connection line DEML211 can be connected to the second connection electrode DEMSD221 of the second demultiplexing switching element used to achieve the first color through the 21st demultiplexing contact hole DECT21.

[0122] The second connection electrode DEMSD221 of the second demultiplexing switching element for implementing the first color can be connected to the 21st demultiplexing active layer DEMACT21 via a contact hole. The 21st demultiplexing active layer DEMACT21, together with the 21st demultiplexing gate electrode DEMG21, constitutes the second demultiplexing switching element for implementing the first color. The 21st demultiplexing gate electrode DEMG21 can be connected to the second clock line CL2. The 21st demultiplexing active layer DEMACT21 can be connected to the first connection electrode DEMSD121 of the second demultiplexing switching element for implementing the first color via a contact hole. The first connection electrode DEMSD121 of the second demultiplexing switching element for implementing the first color is connected to the 21st data line DL21, and the 21st data line DL21 can apply a data voltage from the first data pad DP1 to the second sub-pixel SP21 for implementing the first color.

[0123] The 23rd demultiplexing connection line DEML23 can be connected to the 22nd demultiplexing connection line DEML22 through the second demultiplexing connection contact hole DEMCT2.

[0124] Demultiplexing cable DEML22 (22nd demultiplexing connection) can be connected to demultiplexing cable DEML121 (121st demultiplexing connection) via demultiplexing connection contact hole DEMCT12 (12th demultiplexing connection). Demultiplexing cable DEML22 (22nd demultiplexing connection) can be connected to demultiplexing cable DEML221 (221st demultiplexing connection) via demultiplexing connection contact hole DEMCT22 (22nd demultiplexing connection).

[0125] The 121st demultiplexing connection line DEML121 can be connected to the second connection electrode DEMSD212 of the first demultiplexing switching element used to achieve the second color through the 12th demultiplexing contact hole DECT12.

[0126] The second connection electrode DEMSD212 of the first demultiplexing switching element for implementing the second color can be connected to the 12th demultiplexing active layer DEMACT12 via a contact hole. The 12th demultiplexing active layer DEMACT12, together with the 12th demultiplexing gate electrode DEMG12, constitutes the first demultiplexing switching element for implementing the second color. The 12th demultiplexing gate electrode DEMG12 can be connected to the first clock line CL1. The 12th demultiplexing active layer DEMACT12 can be connected to the first connection electrode DEMSD112 of the first demultiplexing switching element for implementing the second color via a contact hole. The first connection electrode DEMSD112 of the first demultiplexing switching element for implementing the second color is connected to the 12th data line DL12, and the 12th data line DL12 can apply a data voltage from the second data pad DP2 to the first sub-pixel SP12 for implementing the second color.

[0127] The 221st demultiplexing connection line DEML221 can be connected to the second connection electrode DEMSD222 of the second demultiplexing switching element used to achieve the second color through the 22nd demultiplexing contact hole DECT22.

[0128] The second connection electrode DEMSD222 of the second demultiplexing switching element used to implement the second color can be connected to the 22nd demultiplexing active layer DEMACT22 via a contact hole. The 22nd demultiplexing active layer DEMACT22, together with the 22nd demultiplexing gate electrode DEMG22, constitutes the second demultiplexing switching element used to implement the second color. The 22nd demultiplexing gate electrode DEMG22 can be connected to the second clock line CL2. The 22nd demultiplexing active layer DEMACT22 can be connected to the first connection electrode DEMSD122 of the second demultiplexing switching element used to implement the second color via a contact hole. The first connection electrode DEMSD122 of the second demultiplexing switching element used to implement the second color can be connected to the 22nd data line DL22, and the 22nd data line DL22 can apply a data voltage from the second data pad DP2 to the second sub-pixel SP22 used to implement the second color.

[0129] The 33rd demultiplexing connection line DEML33 can be connected to the 32nd demultiplexing connection line DEML32 through the third demultiplexing connection contact hole DEMCT3.

[0130] Demultiplexing cable DEML32 (number 32) can be connected to demultiplexing cable DEML131 (number 13) via demultiplexing connection contact hole DEMCT13. Demultiplexing cable DEML32 (number 32) can be connected to demultiplexing cable DEML231 (number 23) via demultiplexing connection contact hole DEMCT23.

[0131] The 131st demultiplexing connection line DEML131 can be connected to the second connection electrode DEMSD213 of the first demultiplexing switching element used to achieve the third color through the 13th demultiplexing contact hole DECT13.

[0132] The second connection electrode DEMSD213 of the first demultiplexing switching element for implementing the third color can be connected to the 13th demultiplexing active layer DEMACT13 via a contact hole. The 13th demultiplexing active layer DEMACT13, together with the 13th demultiplexing gate electrode DEMG13, constitutes the first demultiplexing switching element for implementing the third color. The 13th demultiplexing gate electrode DEMG13 can be connected to the first clock line CL1. The 13th demultiplexing active layer DEMACT13 can be connected to the first connection electrode DEMSD113 of the first demultiplexing switching element for implementing the third color via a contact hole. The first connection electrode DEMSD113 of the first demultiplexing switching element for implementing the third color is connected to the 13th data line DL13, and the 13th data line DL13 can apply a data voltage from the third data pad DP3 to the first sub-pixel SP13 for implementing the third color.

[0133] The 231st demultiplexing connection line DEML231 can be connected to the second connection electrode DEMSD223 of the second demultiplexing switching element used to realize the third color through the 23rd demultiplexing contact hole DECT23.

[0134] The second connection electrode DEMSD223 of the second demultiplexing switching element used to implement the third color can be connected to the 23rd demultiplexing active layer DEMACT23 via a contact hole. The 23rd demultiplexing active layer DEMACT23, together with the 23rd demultiplexing gate electrode DEMG23, constitutes the second demultiplexing switching element used to implement the third color. The 23rd demultiplexing gate electrode DEMG23 can be connected to the second clock line CL2. The 23rd demultiplexing active layer DEMACT23 can be connected to the first connection electrode DEMSD123 of the second demultiplexing switching element used to implement the third color via a contact hole. The first connection electrode DEMSD123 of the second demultiplexing switching element used to implement the third color is connected to the 23rd data line DL23, and the 23rd data line DL23 can apply a data voltage from the third data pad DP3 to the second sub-pixel SP23 used to implement the third color.

[0135] As shown, the first power line PSL1 may overlap with the first set of demultiplexing switching elements, the second set of demultiplexing switching elements, and multiple demultiplexing connection lines.

[0136] The first power line PSL1 may be spaced apart from the first test switch element TET1, the second test switch element TET2, and the resistor RP. The resistor RP may include a resistive active layer RPACT.

[0137] The first test switch element TET1 can be connected to the first test connection electrode TECE1 and the second test connection electrode TECE2. The second test switch element TET2 can be connected to the third test connection electrode TECE3 and the fourth test connection electrode TECE4.

[0138] The first test connection electrode TECE1 can be connected to the first test connection line TECL1. The second test connection electrode TECE2 can be connected to the second test connection line TECL2. The third test connection electrode TECE3 can be connected to the third test connection line TECL3. The fourth test connection electrode TECE4 can be connected to the fourth test connection line TECL4.

[0139] The first test connection line TECL1 and the third test connection line TECL3 can be connected to the first test pad TP1 and the second test pad TP2, respectively.

[0140] The second test connection line TECL2 and the fourth test connection line TECL4 can be connected to the first demultiplexing switch element and the second demultiplexing switch element, respectively. For example, the second test connection line TECL2 can be connected to the first connection electrode DEMSD121 of the second demultiplexing switch element used to achieve the first color. The fourth test connection line TECL4 can be connected to the first connection electrode DEMSD111 of the first demultiplexing switch element used to achieve the first color.

[0141] The gate electrode of the first test switch element TET1 and the gate electrode of the second test switch element TET2 can be connected to each other. The test gate electrode TEG can be connected to the second resistor connection electrode RPCE2 through a contact hole.

[0142] The second resistor connection electrode RPCE2 can be connected to the active resistor layer RPACT via a contact hole. The active resistor layer RPACT can be connected to the first resistor connection electrode RPCE1 via a contact hole. The first resistor connection electrode RPCE1 can be connected to the resistor connection line RPCL, and the resistor connection line RPCL can be connected to the test gate pad TGP.

[0143] Figure 6 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line I-I'.

[0144] refer to Figure 5A and Figure 6 The illustrated cross-sectional view may represent a cross-sectional view of a sub-pixel SP according to an embodiment of the present disclosure. Each of the sub-pixels SP (e.g., SP11, SP12, SP13, SP21, SP22, and SP23) may include at least one display transistor DT, a capacitor C1, and at least one light-emitting element.

[0145] The substrate SUB can be made of an insulating material such as a polymer resin and / or glass. For example, the substrate SUB may include polyimide. In this case, the substrate SUB can be a flexible substrate capable of withstanding bending, folding, and / or rolling.

[0146] A thin-film transistor layer (TFTL), including a display transistor DT and a capacitor C1 for each of the sub-pixels SP, can be disposed on a substrate SUB. The TFTL may include a display transistor DT, a first anode connection electrode ANDE1, a second anode connection electrode ANDE2, a buffer film BF, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a first planarization layer 160, and a second planarization layer 180.

[0147] The buffer film (BF) can be disposed on the substrate (SUB). The buffer film (BF) can be formed from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0148] The display transistor DT can be disposed on the buffer film BF. The display transistor DT may include a display active layer DACT, a display gate electrode DG, a first display electrode (e.g., the first electrode of the display transistor DT) DSD1, and a second display electrode (e.g., the second electrode of the display transistor DT) DSD2.

[0149] The active display layer DACT, first display electrode DSD1, and second display electrode DSD2 of the display transistor DT can be disposed on the buffer film BF. The active display layer DACT can include silicon semiconductors such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first display electrode DSD1 and the second display electrode DSD2 can be made conductive by doping the silicon semiconductor with ions or impurities. The active display layer DACT overlaps with the display gate electrode DG in a third direction (e.g., the Z-axis direction), and the first display electrode DSD1 and the second display electrode DSD2 may not overlap with the display gate electrode DG in the third direction (e.g., the Z-axis direction). The third direction (e.g., the Z-axis direction) can be defined as the thickness direction of the substrate SUB or the display panel 100 (see [link to documentation]). Figure 1 The thickness direction of the layer. The functional layer including the active layer DACT can be disposed between the buffer film BF and the gate insulating film 130.

[0150] The gate insulating film 130 can be disposed on the display active layer DACT, the first display electrode DSD1, and the second display electrode DSD2 of the display transistor DT. The gate insulating film 130 can be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0151] The display gate electrode DG and the first capacitor electrode CAE1 of the display transistor DT and capacitor C1 can be disposed on the gate insulating film 130. The display gate electrode DG can overlap with the display active layer DACT in a third direction (e.g., the Z-axis direction). The first capacitor electrode CAE1 can overlap with the second capacitor electrode CAE2 in a third direction (e.g., the Z-axis direction). Each of the display gate electrode DG and the first capacitor electrode CAE1 can be formed of a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their suitable alloys. The first capacitor electrode CAE1 can include the same material as the display gate electrode DG. A first gate metal layer including the display gate electrode DG and the first capacitor electrode CAE1 can be disposed between the gate insulating film 130 and the first interlayer insulating film 141.

[0152] The first interlayer insulating film 141 can be disposed on the display gate electrode DG and the first capacitor electrode CAE1. The first interlayer insulating film 141 can be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0153] The second capacitor electrode CAE2 can be disposed on the first interlayer insulating film 141. Because the first interlayer insulating film 141 has a suitable dielectric constant (e.g., a predetermined dielectric constant), the capacitor C1 can be formed from the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the first interlayer insulating film 141 disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2. The second capacitor electrode CAE2 can be formed from a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a suitable alloy thereof. A second gate metal layer including the second capacitor electrode CAE2 can be disposed between the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0154] The second interlayer insulating film 142 can be disposed on the second capacitor electrode CAE2. The second interlayer insulating film 142 can be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0155] The first anode connection electrode ANDE1 can be disposed on the second interlayer insulating film 142. The first anode connection electrode ANDE1 can be connected to the second display electrode DSD2 via a first anode contact hole ANCT1 that exposes the second display electrode DSD2 of the display transistor DT through (e.g., through) the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first anode connection electrode ANDE1 can be formed of a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or a suitable alloy thereof.

[0156] A connection electrode CE may be disposed on the second interlayer insulating film 142. The connection electrode CE may be connected to the first display electrode DSD1 via a connection electrode contact hole CECT that exposes the first display electrode DSD1 of the display transistor DT through (e.g., penetrating) the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The connection electrode CE may be formed of a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a suitable alloy thereof. In an embodiment, the connection electrode CE may comprise the same material as the first anode connection electrode ANDE1. A first data metal layer comprising the first anode connection electrode ANDE1 and the connection electrode CE may be disposed between the second interlayer insulating film 142 and the first planarization layer 160.

[0157] A first planarization layer 160 for planarization can be disposed on the first anode connection electrode ANDE1 and the connection electrode CE. The first planarization layer 160 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0158] A second anode connection electrode ANDE2 may be disposed on the first planarization layer 160. The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 via a second anode contact hole ANCT2 that exposes the first anode connection electrode ANDE1 by passing through (e.g., penetrating) the first planarization layer 160. The second anode connection electrode ANDE2 may be formed of a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a suitable alloy thereof. A second data metal layer including the second anode connection electrode ANDE2 may be disposed between the first planarization layer 160 and the second planarization layer 180.

[0159] A second planarization layer 180 for planarization can be disposed on the second anode connection electrode ANDE2. The second planarization layer 180 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0160] The light-emitting element layer (EML) can be disposed on the second planarization layer 180. The EML can include light-emitting elements and a dam 190. Each of the light-emitting elements can include a pixel electrode 171, a light-emitting layer 172, and a common electrode 173. The common electrode 173 can be commonly connected to multiple other light-emitting elements.

[0161] Pixel electrode 171 may be formed on the second planarization layer 180. Pixel electrode 171 may be connected to the second anode connection electrode ANDE2 via a third anode contact hole ANCT3 that exposes the second anode connection electrode ANDE2 by passing through (e.g., penetrating) the second planarization layer 180.

[0162] In the top-emitting structure in which light is emitted in the direction of the common electrode 173 based on the light-emitting layer 172, the pixel electrode 171 can be formed of a metallic material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of indium tin oxide (ITO) and aluminum (ITO / Al / ITO), an APC alloy, and / or a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0163] The dam 190 can be formed to divide the pixel electrode 171 on the second planarization layer 180, thereby defining a light-emitting region EA. The light-emitting region EA represents the area where the pixel electrode 171, the light-emitting layer 172, and the common electrode 173 are sequentially stacked such that holes from the pixel electrode 171 recombine with electrons from the common electrode 173 in the light-emitting layer 172, thereby emitting light. The dam 190 can be formed to cover the edge of the pixel electrode 171. The dam 190 can be formed from an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0164] The light-emitting layer 172 can be formed on the pixel electrode 171 and the embankment 190. The light-emitting layer 172 may include an organic material for emitting light of a desired color (e.g., a predetermined color). For example, the light-emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0165] A common electrode 173 can be formed on the light-emitting layer 172. The common electrode 173 can be formed to cover the light-emitting layer 172. The common electrode 173 can be commonly formed on the light-emitting layer 172. Figure 6The diagram shows a common layer in all light-emitting regions EA. A capping layer CPL can be formed on the common electrode 173. The capping layer CPL can be defined as belonging to the light-emitting element layer EML.

[0166] In the top-emitting structure, the common electrode 173 can be formed of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO), or a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 is formed of a semi-transparent conductive material, the luminous efficiency can be improved through the microcavity.

[0167] The encapsulation layer TFEL can be disposed on the common electrode 173. The encapsulation layer TFEL may include at least one inorganic film for preventing oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the encapsulation layer TFEL may include at least one organic film for protecting the light-emitting element layer EML from particles such as dust. For example, the encapsulation layer TFEL may include a first inorganic layer TFE1, an organic layer TFE2, and a second inorganic layer TFE3.

[0168] A first inorganic layer TFE1 can be disposed on the capping layer CPL, an organic layer TFE2 can be disposed on the first inorganic layer TFE1, and a second inorganic layer TFE3 can be disposed on the organic layer TFE2. The first inorganic layer TFE1 and the second inorganic layer TFE3 can be formed by alternating stacks of multiple inorganic layers, including silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide layers. The organic layer TFE2 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin, etc.

[0169] In some embodiments, a filler layer, a sealing material, and an encapsulation substrate may be provided instead of the encapsulation layer TFEL. In this case, the encapsulation substrate may be an insulating substrate containing an insulating material such as glass or plastic. The filler layer may be an air layer in a vacuum state, but this disclosure is not limited thereto. The sealing material may be disposed in the non-display area of ​​the display panel 100 and may surround the display area DA (e.g., around the periphery of the display area DA).

[0170] Figure 7 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line II-II'. Figure 8 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line III-III'. Figure 9 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line IV-IV'. Figures 7 to 9 In the figures, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and therefore, their redundant descriptions need not be repeated below.

[0171] refer to Figure 5A and Figure 7 The second test connection TECL2 and the fourth test connection TECL4 can be disposed on the first interlayer insulating film 141. A second gate metal layer including the second test connection TECL2 and the fourth test connection TECL4 can be disposed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 can be configured to cover the second test connection TECL2 and the fourth test connection TECL4. The second test connection TECL2 and the fourth test connection TECL4 can comprise the same material as the second capacitor electrode CAE2 described above.

[0172] The first connection electrode DEMSD111 of the first demultiplexing switching element for achieving the first color and the first connection electrode DEMSD121 of the second demultiplexing switching element for achieving the first color can be disposed on the second interlayer insulating film 142. Furthermore, the first connection electrode DEMSD112 of the first demultiplexing switching element for achieving the second color and the first connection electrode DEMSD113 of the first demultiplexing switching element for achieving the third color can be disposed on the second interlayer insulating film 142. The first connection electrodes DEMSD112 and DEMSD113 of the first demultiplexing switching element for achieving the second color can be disposed between the first connection electrode DEMSD111 of the first demultiplexing switching element for achieving the first color and the first connection electrode DEMSD121 of the second demultiplexing switching element for achieving the first color.

[0173] The first connection electrode DEMSD111 of the first demultiplexing switch element used to achieve the first color can pass through the first test contact hole TECT1 formed in the second interlayer insulating film 142. The first connection electrode DEMSD111 of the first demultiplexing switch element used to achieve the first color can be connected to the fourth test connection line TECL4 exposed by the first test contact hole TECT1.

[0174] The first connection electrode DEMSD121 of the second demultiplexing switch element used to achieve the first color can pass through the second test contact hole TECT2 formed in the second interlayer insulating film 142. The first connection electrode DEMSD121 of the second demultiplexing switch element used to achieve the first color can be connected to the second test connection line TECL2 exposed by the second test contact hole TECT2.

[0175] A first data metal layer, including a first connection electrode DEMSD111 for a first demultiplexing switching element to achieve a first color, a first connection electrode DEMSD121 for a second demultiplexing switching element to achieve a first color, a first connection electrode DEMSD112 for a first demultiplexing switching element to achieve a second color, and a first connection electrode DEMSD113 for a first demultiplexing switching element to achieve a third color, can be disposed between a second interlayer insulating film 142 and a first planarization layer 160. The first planarization layer 160 can be configured to cover these electrodes of the first data metal layer. These electrodes of the first data metal layer can include the same material as the first anode connection electrode ANDE1 described above.

[0176] The first power line PSL1 and the 21st data line DL21 can be disposed on the first planarization layer 160. The 21st data line DL21 can pass through a 21st data line contact hole DLCT21 formed in the first planarization layer 160 (e.g., penetrating the first planarization layer 160). The 21st data line DL21 can be connected to the first connection electrode DEMSD121 of the second demultiplexing switching element for realizing the first color, which is exposed by the 21st data line contact hole DLCT21.

[0177] The first power line PSL1 may overlap with the first connection electrode DEMSD111 of the first demultiplexing switch element for realizing the first color, the first connection electrode DEMSD121 of the second demultiplexing switch element for realizing the first color, the first connection electrode DEMSD112 of the first demultiplexing switch element for realizing the second color, and the first connection electrode DEMSD113 of the first demultiplexing switch element for realizing the third color.

[0178] The first power line PSL1 can be connected to any one of the plurality of pads. The first power line PSL1 can receive a first power supply voltage from the driving circuit via the circuit board. In some embodiments, the display device may further include a second power line. The second power line can be connected to any one of the plurality of pads. The second power line can receive a second power supply voltage from the driving circuit via the circuit board. In this case, the first power supply voltage can be a voltage having a potential lower than the second power supply voltage. For example, the second power supply voltage can be a high-potential driving voltage, and the first power supply voltage can be a low-potential driving voltage.

[0179] A second data metal layer, including the first power line PSL1 and the 21st data line DL21, can be disposed between the first planarization layer 160 and the second planarization layer 180. The second planarization layer 180 can be configured to cover the first power line PSL1 and the 21st data line DL21. The first power line PSL1 and the 21st data line DL21 can comprise the same material as the material of the second anode connection electrode ANDE2 described above.

[0180] refer to Figure 5A and Figure 8 The first active test layer of the first test switch element TET1 can be disposed on the buffer film BF. The first active test layer may include the first electrode TESD11 of the first test switch element TET1, the second electrode TESD22 of the first test switch element TET1, and the channels TEACT11 and TEACT12 of the first test switch element TET1 disposed between the first electrode TESD11 and the second electrode TESD22.

[0181] The first test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD11 and the second electrode TESD22 of the first test switch element TET1 may be made conductive by doping the silicon semiconductor with ions or impurities. The first test active layer overlaps with the test gate electrode TEG in a third direction (e.g., the Z-axis direction), and the first electrode TESD11 and the second electrode TESD22 of the first test switch element TET1 may not overlap with the test gate electrode TEG in a third direction (e.g., the Z-axis direction).

[0182] The first test switch element TET1 may include a plurality of transistors connected in series. The first test switch element TET1 may include an eleventh test switch element TET11 and a twelfth test switch element TET12. The eleventh test switch element TET11 may include an eleventh test active layer, and the twelfth test switch element TET12 may include a twelfth test active layer.

[0183] The 11th test active layer may include the first electrode TESD11 of the 11th test switching element TET11, the second electrode TESD12 of the 11th test switching element TET11, and the channel TEACT11 of the 11th test switching element TET11 disposed between the first electrode TESD11 and the second electrode TESD12.

[0184] The 11th test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD11 and the second electrode TESD12 of the 11th test switching element TET11 may be made conductive by doping the silicon semiconductor with ions or impurities. The 11th test active layer overlaps with the 11th test gate electrode TEG11 in a third direction (e.g., the Z-axis direction), and the first electrode TESD11 and the second electrode TESD12 of the 11th test switching element TET11 may not overlap with the 11th test gate electrode TEG11 in a third direction (e.g., the Z-axis direction).

[0185] The 12th test active layer may include the first electrode TESD21 of the 12th test switching element TET12, the second electrode TESD22 of the 12th test switching element TET12, and the channel TEACT12 of the 12th test switching element TET12 disposed between the first electrode TESD21 and the second electrode TESD22.

[0186] The 12th test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD21 and the second electrode TESD22 of the 12th test switching element TET12 may be made conductive by doping the silicon semiconductor with ions or impurities. The 12th test active layer overlaps with the 12th test gate electrode TEG12 in a third direction (e.g., the Z-axis direction), and the first electrode TESD21 and the second electrode TESD22 of the 12th test switching element TET12 may not overlap with the 12th test gate electrode TEG12 in a third direction (e.g., the Z-axis direction).

[0187] When multiple transistors are connected in series, the second electrode TESD12 of the 11th test switch element TET11 can be connected to the first electrode TESD21 of the 12th test switch element TET12.

[0188] A functional layer, including the first test active layer, can be disposed between the buffer film BF and the gate insulating film 130. The gate insulating film 130 can be configured to cover the first test active layer. The first test active layer can include the same material as the material of the active layer DACT described above.

[0189] The test gate electrode TEG can be disposed on the gate insulating film 130. Multiple test gate electrode TEGs can be formed. For example, the test gate electrode TEGs may include an 11th test gate electrode TEG11 and a 12th test gate electrode TEG12.

[0190] A first gate metal layer, including the 11th test gate electrode TEG11 and the 12th test gate electrode TEG12, can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the 11th test gate electrode TEG11 and the 12th test gate electrode TEG12. The 11th test gate electrode TEG11 and the 12th test gate electrode TEG12 can comprise the same material as the material used for the gate electrode DG described above.

[0191] The first test connection TECL1 and the second test connection TECL2 can be disposed on the first interlayer insulating film 141. A second gate metal layer, including the first test connection TECL1 and the second test connection TECL2, can be disposed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 can be configured to cover the first test connection TECL1 and the second test connection TECL2. The first test connection TECL1 and the second test connection TECL2 can comprise the same material as the second capacitor electrode CAE2 described above.

[0192] The first test connection electrode TECE1 and the second test connection electrode TECE2 can be disposed on the second interlayer insulating film 142.

[0193] The first test connection electrode TECE1 can pass through the 11th test connection contact hole TETCT11 formed in the second interlayer insulating film 142 (e.g., penetrating the second interlayer insulating film 142). The first test connection electrode TECE1 can be connected to the first test connection line TECL1 exposed by the 11th test connection contact hole TETCT11.

[0194] The first test connection electrode TECE1 can pass through the 12th test connection contact hole TETCT12 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130 (e.g., penetrating the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130). The first test connection electrode TECE1 can be connected to the first test active layer exposed by the 12th test connection contact hole TETCT12.

[0195] The second test connection electrode TECE2 can pass through the 21st test connection contact hole TETCT21 formed in the second interlayer insulating film 142 (e.g., penetrating the second interlayer insulating film 142). The second test connection electrode TECE2 can be connected to the second test connection line TECL2 exposed by the 21st test connection contact hole TETCT21.

[0196] The second test connection electrode TECE2 can pass through the 22nd test connection contact hole TETCT22 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130 (e.g., penetrating the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130). The second test connection electrode TECE2 can be connected to the first test active layer exposed by the 22nd test connection contact hole TETCT22.

[0197] refer to Figure 5A and Figure 9 The second active test layer of the second test switch element TET2 can be disposed on the buffer film BF. The second active test layer may include the first electrode TESD13 of the second test switch element TET2, the second electrode TESD24 of the second test switch element TET2, and the channels TEACT21 and TEACT22 of the second test switch element TET2 disposed between the first electrode TESD13 and the second electrode TESD24.

[0198] The second test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD13 and the second electrode TESD24 of the second test switch element TET2 may be made conductive by doping the silicon semiconductor with ions or impurities. The second test active layer overlaps with the test gate electrode TEG in a third direction (e.g., the Z-axis direction), and the first electrode TESD13 and the second electrode TESD24 of the second test switch element TET2 may not overlap with the test gate electrode TEG in a third direction (e.g., the Z-axis direction).

[0199] The second test switch element TET2 may include a plurality of transistors connected in series. The second test switch element TET2 may include a 21st test switch element TET21 and a 22nd test switch element TET22. The 21st test switch element TET21 may include a 21st test active layer, and the 22nd test switch element TET22 may include a 22nd test active layer.

[0200] The 21st test active layer may include the first electrode TESD13 of the 21st test switching element TET21, the second electrode TESD14 of the 21st test switching element TET21, and the channel TEACT21 of the 21st test switching element TET21 disposed between the first electrode TESD13 and the second electrode TESD14.

[0201] The 21st test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD13 and the second electrode TESD14 of the 21st test switching element TET21 may be made conductive by doping the silicon semiconductor with ions or impurities. The 21st test active layer overlaps with the 21st test gate electrode TEG21 in a third direction (e.g., the Z-axis direction), and the first electrode TESD13 and the second electrode TESD14 of the 21st test switching element TET21 may not overlap with the 21st test gate electrode TEG21 in a third direction (e.g., the Z-axis direction).

[0202] The 22nd test active layer may include the first electrode TESD23 of the 22nd test switching element TET22, the second electrode TESD24 of the 22nd test switching element TET22, and the channel TEACT22 of the 22nd test switching element TET22 disposed between the first electrode TESD23 and the second electrode TESD24.

[0203] The 22nd test active layer may include a silicon semiconductor such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or amorphous silicon. The first electrode TESD23 and the second electrode TESD24 of the 22nd test switching element TET22 may be made conductive by doping the silicon semiconductor with ions or impurities. The 22nd test active layer overlaps with the 22nd test gate electrode TEG22 in a third direction (e.g., the Z-axis direction), and the first electrode TESD23 and the second electrode TESD24 of the 22nd test switching element TET22 may not overlap with the 22nd test gate electrode TEG22 in a third direction (e.g., the Z-axis direction).

[0204] When multiple transistors are connected in series, the second electrode TESD21 of the 21st test switch element TET21 can be connected to the first electrode TESD23 of the 22nd test switch element TET22.

[0205] A functional layer, including a second test active layer, can be disposed between the buffer film BF and the gate insulating film 130. The gate insulating film 130 can be configured to cover the second test active layer. The second test active layer can include the same material as the material of the active layer DACT described above.

[0206] The third test connection line TECL3 and the test gate electrode TEG can be disposed on the gate insulating film 130. The test gate electrode TEG can be formed as multiple test gate electrode TEGs. For example, the test gate electrode TEGs may include a 21st test gate electrode TEG21 and a 22nd test gate electrode TEG22.

[0207] A first gate metal layer, including the third test connection line TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22, can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the third test connection line TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22. The third test connection line TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22 can comprise the same material as the material used for the display gate electrode DG described above.

[0208] The fourth test connection TECL4 can be disposed on the first interlayer insulating film 141. A second gate metal layer including the fourth test connection TECL4 can be disposed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 can be configured to cover the fourth test connection TECL4. The fourth test connection TECL4 can comprise the same material as the second capacitor electrode CAE2 described above.

[0209] The third test connection electrode TECE3 and the fourth test connection electrode TECE4 can be disposed on the second interlayer insulating film 142.

[0210] The third test connection electrode TECE3 can pass through the 31st test connection contact hole TETCT31 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141 (e.g., penetrating the second interlayer insulating film 142 and the first interlayer insulating film 141). The third test connection electrode TECE3 can be connected to the third test connection line TECL3 exposed by the 31st test connection contact hole TETCT31.

[0211] The third test connection electrode TECE3 can pass through the 32nd test connection contact hole TETCT32 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130 (e.g., penetrating the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130). The third test connection electrode TECE3 can be connected to the second test active layer exposed by the 32nd test connection contact hole TETCT32.

[0212] The fourth test connection electrode TECE4 can pass through the 41st test connection contact hole TETCT41 formed in the second interlayer insulating film 142 (e.g., penetrating the second interlayer insulating film 142). The fourth test connection electrode TECE4 can be connected to the fourth test connection line TECL4 exposed by the 41st test connection contact hole TETCT41.

[0213] The fourth test connection electrode TECE4 can pass through the 42nd test connection contact hole TETCT42 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130 (e.g., penetrating the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130). The fourth test connection electrode TECE4 can be connected to the second test active layer exposed by the 42nd test connection contact hole TETCT42.

[0214] refer to Figure 8 and Figure 9 The first test connection line TECL1, the second test connection line TECL2, and the fourth test connection line TECL4 can all be formed on the first interlayer insulating film 141. The third test connection line TECL3 can be formed on the gate insulating film 130.

[0215] In an embodiment, the second test connection line TECL2 may be formed on the same layer (e.g., in the middle or on top) as the fourth test connection line TECL4, and the first test connection line TECL1 may be formed on a different layer (e.g., in the middle or on top) as the third test connection line TECL3. The path used to transmit the data voltage output from the demultiplexing switch element to the test switch element consists of the second test connection line TECL2 and the fourth test connection line TECL4, which can be formed of the same material to improve test accuracy and reduce skewness deviation, etc. As illustrated in the plan view above, the first test connection line TECL1 and the third test connection line TECL3 may be formed of different materials to facilitate the design and layout of the circuit.

[0216] Figure 10 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line II-II'. Figure 11 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line III-III'. Figure 12 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line IV-IV'. Figures 10 to 12 In the figures, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and therefore, their redundant descriptions need not be repeated below.

[0217] Figures 10 to 12 The illustrated embodiment is the same as the one referenced above. Figures 7 to 9The difference in the described embodiment may be that the second test connection TECL2, the third test connection TECL3, and the fourth test connection TECL4 can be formed on the gate insulating film 130, and the first test connection TECL1 can be formed on the first interlayer insulating film 141. Conversely, referring to the above... Figures 7 to 9 In the described embodiment, the first test connection line TECL1, the second test connection line TECL2 and the fourth test connection line TECL4 can be formed on the first interlayer insulating film 141, and the third test connection line TECL3 can be formed on the gate insulating film 130.

[0218] refer to Figure 5A and Figure 10 The second test connection TECL2 and the fourth test connection TECL4 can be disposed on the gate insulating film 130. A first gate metal layer including the second test connection TECL2 and the fourth test connection TECL4 can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the second test connection TECL2 and the fourth test connection TECL4. The second test connection TECL2 and the fourth test connection TECL4 can comprise the same material as the material used for the display gate electrode DG described above.

[0219] The first connection electrode DEMSD111 of the first demultiplexing switch element for realizing the first color can pass through the first test contact hole TECT1 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142 (e.g., penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142).

[0220] The first connection electrode DEMSD121 of the second demultiplexing switch element used to achieve the first color can pass through the second test contact hole TECT2 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142 (e.g., penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142).

[0221] refer to Figure 5A and Figure 11 The test gate electrode TEG and the second test connection line TECL2 can be disposed on the gate insulating film 130.

[0222] A first gate metal layer, including the 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection line TECL2, can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection line TECL2. The 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection line TECL2 can comprise the same material as the material used for the display gate electrode DG described above.

[0223] The first test connection line TECL1 can be set on the first interlayer insulating film 141.

[0224] The first test connection electrode TECE1 and the second test connection electrode TECE2 can be disposed on the second interlayer insulating film 142.

[0225] The second test connection electrode TECE2 can pass through the 21st test connection contact hole TETCT21 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141 (e.g., penetrating the second interlayer insulating film 142 and the first interlayer insulating film 141). The second test connection electrode TECE2 can be connected to the second test connection line TECL2 exposed by the 21st test connection contact hole TETCT21.

[0226] refer to Figure 5A and Figure 12 The third test connection line TECL3, the fourth test connection line TECL4, and the test gate electrode TEG can be disposed on the gate insulating film 130.

[0227] A first gate metal layer, including the third test connection line TECL3, the fourth test connection line TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22, can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the third test connection line TECL3, the fourth test connection line TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22. The third test connection line TECL3, the fourth test connection line TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22 can comprise the same material as the material used for the display gate electrode DG described above.

[0228] The third test connection electrode TECE3 and the fourth test connection electrode TECE4 can be disposed on the second interlayer insulating film 142.

[0229] The fourth test connection electrode TECE4 can pass through the 41st test connection contact hole TETCT41 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141 (e.g., penetrating the second interlayer insulating film 142 and the first interlayer insulating film 141).

[0230] refer to Figure 11 and Figure 12 The second test connection line TECL2, the third test connection line TECL3, and the fourth test connection line TECL4 can all be formed on the gate insulating film 130. The first test connection line TECL1 can be formed on the first interlayer insulating film 141.

[0231] Figure 13 Along in the display device according to embodiments of the present disclosure Figure 5A A cross-sectional view taken from line V-V'.

[0232] refer to Figure 5A and Figure 13 The active resistive layer RPACT can be formed on the buffer film BF. At least a portion of the active resistive layer RPACT can overlap with the first resistive connection electrode RPCE1 and the second resistive connection electrode RPCE2. A functional layer including the active resistive layer RPACT can be disposed between the buffer film BF and the gate insulating film 130. The gate insulating film 130 can be configured to cover the active resistive layer RPACT. The active resistive layer RPACT can include the same material as the active layer DACT shown above, but this disclosure is not limited thereto.

[0233] The first resistive connection electrode RPCE1 and the second resistive connection electrode RPCE2 can be disposed on the second interlayer insulating film 142. The first resistive connection electrode RPCE1 can pass through the first set of resistive contact holes RPCT1, RPCT2, and RPCT3 formed in the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130 (e.g., penetrating the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130). The first resistive connection electrode RPCE1 can be connected to the resistive active layer RPACT exposed by the first set of resistive contact holes RPCT1, RPCT2, and RPCT3.

[0234] The second resistive connection electrode RPCE2 can pass through a second set of resistive contact holes RPCT4, RPCT5, and RPCT6 formed in the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130 (e.g., penetrating the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130). The second resistive connection electrode RPCE2 can be connected to the resistive active layer RPACT exposed by the second set of resistive contact holes RPCT4, RPCT5, and RPCT6.

[0235] The first group of resistive contact holes RPCT1, RPCT2, and RPCT3, and the second group of resistive contact holes RPCT4, RPCT5, and RPCT6 can each include multiple resistive contact holes, and the number of contact holes included in the first group of resistive contact holes RPCT1, RPCT2, and RPCT3 can be the same as the number of contact holes included in the second group of resistive contact holes RPCT4, RPCT5, and RPCT6. Because multiple contact holes are formed, the signal from the test gate pad TGP can be transmitted to the test switching element more smoothly, even though the resistive active layer RPACT has high resistance. Furthermore, since the number of contact holes included in the first group of resistive contact holes RPCT1, RPCT2, and RPCT3 is the same as the number of contact holes included in the second group of resistive contact holes RPCT4, RPCT5, and RPCT6, the electrostatic discharge function performed by the resistive active layer RPACT can be performed uniformly on both sides, thus improving the reliability of the display device.

[0236] Figure 14 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line VI-VI'.

[0237] refer to Figure 5A and Figure 14 The 111th demultiplexing connection DEML111 can be disposed on the gate insulating film 130. A first gate metal layer including the 111th demultiplexing connection DEML111 can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the 111th demultiplexing connection DEML111. The 111th demultiplexing connection DEML111 can comprise the same material as the material used for the display gate electrode DG described above.

[0238] The 13th demultiplexing connection DEML13 can be disposed on the first interlayer insulating film 141. A second gate metal layer including the 13th demultiplexing connection DEML13 can be disposed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 can be configured to cover the 13th demultiplexing connection DEML13. The 13th demultiplexing connection DEML13 can comprise the same material as the second capacitor electrode CAE2 described above.

[0239] The second connection electrode DEMSD211 and the 12th demultiplexing connection line DEML12 of the first demultiplexing switching element for realizing the first color can be disposed on the second interlayer insulating film 142. The first clock line CL1 and the second clock line CL2 can be disposed on the second interlayer insulating film 142. The first clock line CL1 and the second clock line CL2 can be sequentially disposed between the second connection electrode DEMSD211 and the 12th demultiplexing connection line DEML12 of the first demultiplexing switching element for realizing the first color.

[0240] The second connection electrode DEMSD211 of the first demultiplexing switching element for realizing the first color can pass through the 11th demultiplexing contact hole DECT11 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141 (e.g., penetrating the second interlayer insulating film 142 and the first interlayer insulating film 141). The second connection electrode DEMSD211 of the first demultiplexing switching element for realizing the first color can be connected to the 111th demultiplexing connection line DEML111 exposed by the 11th demultiplexing contact hole DECT11.

[0241] The 12th demultiplexed connection line DEML12 can pass through the 11th demultiplexed connection contact hole DEMCT11 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141 (e.g., penetrating the second interlayer insulating film 142 and the first interlayer insulating film 141). The 12th demultiplexed connection line DEML12 can be connected to the 111th demultiplexed connection line DEML111 exposed by the 11th demultiplexed connection contact hole DEMCT11.

[0242] The 12th demultiplexed connection line DEML12 can pass through the first demultiplexed connection contact hole DEMCT1 formed in the second interlayer insulating film 142 (e.g., penetrating the second interlayer insulating film 142). The 12th demultiplexed connection line DEML12 can be connected to the 13th demultiplexed connection line DEML13 exposed by the first demultiplexed connection contact hole DEMCT1.

[0243] A first data metal layer, including the second connection electrode DEMSD211 and the 12th demultiplexing connection line DEML12 of the first demultiplexing switching element for realizing the first color, can be disposed between the second interlayer insulating film 142 and the first planarization layer 160. The first planarization layer 160 can be configured to cover the second connection electrode DEMSD211 and the 12th demultiplexing connection line DEML12. The second connection electrode DEMSD211 and the 12th demultiplexing connection line DEML12 of the first demultiplexing switching element for realizing the first color comprise the same material as the first anode connection electrode ANDE1 described above.

[0244] The first power line PSL1 can be disposed on the first planarization layer 160. The first power line PSL1 can overlap with the second connection electrode DEMSD211, the 12th demultiplexing connection line DEML12, the first clock line CL1, the second clock line CL2, and the 111th demultiplexing connection line DEML111, which are used to implement the first color demultiplexing switching element. A second data metal layer including the first power line PSL1 can be disposed between the first planarization layer 160 and the second planarization layer 180. The second planarization layer 180 can be configured to cover the first power line PSL1. The first power line PSL1 can include the same material as the second anode connection electrode ANDE2 described above.

[0245] Figure 15 Along in the display device according to embodiments of the present disclosure Figure 5A The cross-sectional view taken from line VII-VII'.

[0246] refer to Figure 5A and Figure 15 The 121st demultiplexing connection DEML121 and the 23rd demultiplexing connection DEML23 can be disposed on the gate insulating film 130. The 131st demultiplexing connection DEML131 can be disposed on the gate insulating film 130. The 131st demultiplexing connection DEML131 can be disposed between the 121st demultiplexing connection DEML121 and the 23rd demultiplexing connection DEML23.

[0247] A first gate metal layer, including the 121st demultiplexed connection DEML121, the 23rd demultiplexed connection DEML23, and the 131st demultiplexed connection DEML131, can be disposed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 can be configured to cover the 121st demultiplexed connection DEML121, the 23rd demultiplexed connection DEML23, and the 131st demultiplexed connection DEML131. The 121st demultiplexed connection DEML121, the 23rd demultiplexed connection DEML23, and the 131st demultiplexed connection DEML131 can comprise the same material as the display gate electrode DG described above.

[0248] The second connecting electrode DEMSD212 and the 22nd demultiplexing connecting line DEML22 of the first demultiplexing switching element for realizing the second color can be disposed on the second interlayer insulating film 142. The first clock line CL1, the second clock line CL2, and the 12th demultiplexing connecting line DEML12 can be sequentially disposed between the second connecting electrode DEMSD212 and the 22nd demultiplexing connecting line DEML22.

[0249] The second connection electrode DEMSD212 of the first demultiplexing switching element for realizing the second color can pass through the 12th demultiplexing contact hole DECT12 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142 (e.g., penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142). The second connection electrode DEMSD212 of the first demultiplexing switching element for realizing the second color can be connected to the 121st demultiplexing connection line DEML121 exposed by the 12th demultiplexing contact hole DECT12.

[0250] The 22nd demultiplexed connection line DEML22 can pass through the 12th demultiplexed connection contact hole DEMCT12 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142 (e.g., penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142). The 22nd demultiplexed connection line DEML22 can be connected to the 121st demultiplexed connection line DEML121 exposed by the 12th demultiplexed connection contact hole DEMCT12.

[0251] The 22nd demultiplexing connection line DEML22 can pass through the second demultiplexing connection contact hole DEMCT2 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142 (e.g., penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142). The 22nd demultiplexing connection line DEML22 can be connected to the 23rd demultiplexing connection line DEML23 exposed by the second demultiplexing connection contact hole DEMCT2.

[0252] A first data metal layer, including a second connection electrode DEMSD212, a 22nd demultiplexed connection line DEML22, a 12th demultiplexed connection line DEML12, a first clock line CL1, and a second clock line CL2 for implementing a second color, can be disposed between a second interlayer insulating film 142 and a first planarization layer 160. The first planarization layer 160 can be configured to cover the second connection electrode DEMSD212, the 22nd demultiplexed connection line DEML22, the 12th demultiplexed connection line DEML12, the first clock line CL1, and the second clock line CL2 for implementing a second color. The second connection electrode DEMSD212, the 22nd demultiplexed connection line DEML22, the 12th demultiplexed connection line DEML12, the first clock line CL1, and the second clock line CL2 for implementing a second color can comprise the same material as the aforementioned first anode connection electrode ANDE1.

[0253] The first power line PSL1 can be disposed on the first planarization layer 160. The first power line PSL1 can overlap with the second connection electrode DEMSD212, the 22nd demultiplexed connection line DEML22, the 12th demultiplexed connection line DEML12, the first clock line CL1, the second clock line CL2, the 121st demultiplexed connection line DEML121, the 131st demultiplexed connection line DEML131, and the 23rd demultiplexed connection line DEML23, which are used to implement the second color.

[0254] A second data metal layer, including the first power line PSL1, can be disposed between the first planarization layer 160 and the second planarization layer 180. The second planarization layer 180 can be configured to cover the first power line PSL1. The first power line PSL1 can include the same material as the second anode connection electrode ANDE2 described above.

[0255] refer to Figure 5D , Figure 14 and Figure 15 At least one of the multiple demultiplexing connection lines DEML111, DEML12, and DEML13 (e.g., DEML13) connecting the first data pad to the first group of demultiplexing switch elements can be disposed on a different layer from at least one of the multiple demultiplexing connection lines DEML121, DEML22, and DEML23 (e.g., DEML23) connecting the second data pad to the first group of demultiplexing switch elements. At least one of the multiple demultiplexing connection lines DEML121, DEML22, and DEML23 (e.g., DEML23) connecting the second data pad to the first group of demultiplexing switch elements can be disposed on a different layer from at least one of the multiple demultiplexing connection lines DEML131, DEML32, and DEML33 (e.g., DEML33) connecting the third data pad to the first group of demultiplexing switch elements.

[0256] Demultiplexing lines DEML13 (13th) and DEML23 (23rd) can be placed on different layers. Demultiplexing lines DEML23 (23rd) and DEML33 (33rd) can be placed on different layers. Demultiplexing lines DEML13 (13th) and DEML33 (33rd) can be placed on the same layer. Because these layers of the demultiplexing lines are arranged as described above, the lines can be arranged more easily, and an efficient design area can be provided.

[0257] The display device according to some embodiments of this disclosure can be applied to a variety of suitable electronic devices. The electronic device according to the embodiments includes the above-described display device, and may further include modules or devices having additional functions besides those of the display device.

[0258] Figure 16 This is a block diagram of an electronic device according to an embodiment of the present disclosure. Figure 17 The figure shows a schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0259] refer to Figure 16 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0260] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0261] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can output image information via the display screen by processing the received signals.

[0262] The power module 14 may include a power supply module such as a power adapter or battery device. The power supply module can supply power to the display module 11. The power module 14 may further include a power conversion module. The power conversion module can convert the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0263] At least one of the components of the electronic device 10 may be included in the display device according to the above embodiment. Additionally, some of the modules described above may be included in the display device, while others may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided as another device in the electronic device besides the display device.

[0264] refer to Figure 17 The various electronic devices to which the display device according to embodiments of the present disclosure is applied may include electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e for displaying images. Additionally, the various electronic devices to which the display device according to embodiments of the present disclosure is applied may include wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules, such as vehicle dashboards, central instrument panels, central information displays (CIDs) mounted on dashboards, and interior mirror displays.

[0265] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects in each embodiment should typically be considered as applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly stated otherwise. Therefore, it is to be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined by the claims and their equivalents.

Claims

1. A display device, comprising: Multiple sub-pixels; Multiple data lines are electrically connected to the multiple sub-pixels; Multiple data pads are electrically connected to the multiple data lines; Multiple test pads, including a first test pad and a second test pad, wherein the first test pad and the second test pad are separated from the multiple data pads; The first set of demultiplexing switching elements connects the first set of data lines in the plurality of data lines to the plurality of data pads; The second set of demultiplexing switching elements connects the second set of data lines in the plurality of data lines to the plurality of data pads; as well as The first test switch element is located between the first electrode of any of the first demultiplexing switch elements included in the first group of demultiplexing switch elements and the first test pad.

2. The display device according to claim 1, wherein, Except for any one of the first demultiplexing switching elements included in the first group of demultiplexing switching elements, the other first demultiplexing switching elements are electrically disconnected from the first test switching element.

3. The display device according to claim 1, further comprising: The second test switch element is located between the first electrode of any of the second demultiplexing switch elements included in the second group of demultiplexing switch elements and the second test pad, and Wherein, except for any one of the second demultiplexing switching elements included in the second group of demultiplexing switching elements, the other second demultiplexing switching elements are electrically disconnected from the second test switching element.

4. The display device according to claim 3, further comprising: A resistor is connected to the gate electrode of the first test switch element and the gate electrode of the second test switch element.

5. The display device according to claim 4, further comprising: An electrostatic discharge circuit is electrically connected to the plurality of data pads, the plurality of test pads, and the resistor.

6. The display device according to claim 1, wherein, The first set of demultiplexing switching elements includes multiple transistors connected in parallel with each other, and The second set of demultiplexing switching elements includes multiple transistors connected in parallel with each other.

7. The display device according to claim 3, wherein, The first test switch element includes a plurality of transistors connected in series with each other, and The second test switch element includes a plurality of transistors connected in series with each other.

8. The display device according to claim 3, wherein, The plurality of sub-pixels includes: The first group of sub-pixels is connected to the first group of demultiplexing switch elements via the first group of data lines; and The second group of sub-pixels is connected to the second group of demultiplexing switch elements via the second group of data lines. Specifically, any one of the multiple first sub-pixels in the first group of sub-pixels implements the first color and is connected to any one of the first demultiplexing switching elements in the first demultiplexing switching elements, and Wherein, any one of the plurality of second sub-pixels included in the second group of sub-pixels implements the first color and is connected to any one of the second demultiplexing switching elements in the second demultiplexing switching elements.

9. The display device according to claim 8, wherein, Any one of the plurality of first sub-pixels is connected to the first electrode of any one of the first demultiplexing switching elements, and Wherein, any one of the plurality of second sub-pixels is connected to the first electrode of any one of the second demultiplexing switching elements.

10. An electronic device comprising: The display module is configured to display images; A power supply module is configured to supply power to the display module; as well as The processor is configured to transmit data signals and control signals to the display module. The display module includes: Multiple sub-pixels; Multiple data lines are electrically connected to the multiple sub-pixels; Multiple data pads are electrically connected to the multiple data lines; Multiple test pads, including a first test pad and a second test pad, wherein the first test pad and the second test pad are separated from the multiple data pads; The first set of demultiplexing switching elements connects the first set of data lines in the plurality of data lines to the plurality of data pads; The second set of demultiplexing switching elements connects the second set of data lines in the plurality of data lines to the plurality of data pads; and The first test switch element is located between the first electrode of any of the first demultiplexing switch elements included in the first group of demultiplexing switch elements and the first test pad.

11. The electronic device of claim 10, further comprising a resistive active layer, in, The first test switch element includes a first test active layer and a first test gate electrode located on a gate insulating film covering the first test active layer. The active resistive layer is electrically connected to the first test gate electrode of the first test switch element, and The first test active layer includes: The first electrode is connected to the first electrode of any one of the first demultiplexing switching elements; The second electrode is connected to the first test pad; and The channel is located between the first electrode of the first test active layer and the second electrode of the first test active layer.

12. The electronic device according to claim 11, wherein, The first test active layer and the resistive active layer are located on the same layer as each other.

13. The electronic device according to claim 11, further comprising: The second test switch element is located between the first electrode of any of the second demultiplexing switch elements included in the second group of demultiplexing switch elements and the second test pad. The second test switch element includes a second test active layer and a second test gate electrode located on the gate insulating film covering the second test active layer. The active resistive layer is electrically connected to the second test gate electrode of the second test switch element, and The second test active layer includes: The first electrode is connected to the first electrode of any one of the second demultiplexing switching elements; The second electrode is connected to the second test pad; and The channel is located between the first electrode of the second test active layer and the second electrode of the second test active layer.

14. The electronic device according to claim 13, wherein, The first electrode of the first test switch element is connected to the first electrode of any one of the first demultiplexing switch elements via a second test connection line. The second electrode of the first test switch element is connected to the first test pad via a first test connection line. The first electrode of the second test switch element is connected to the first electrode of any one of the second demultiplexing switch elements via a fourth test connection line. The second electrode of the second test switch element is connected to the second test pad via a third test connection line. The second test connection line and the fourth test connection line are located on the same layer as each other, and The first test connection line and the third test connection line are located on different layers.

15. The electronic device of claim 11, further comprising: The first power supply line is configured to be supplied with a first power supply voltage. In the plan view, the first power line is separated from the first test switch element.

16. The electronic device according to claim 15, wherein, The first power line is separated from the active layer of the resistor in the plan view, and In the plan view, the first power line overlaps with the first set of demultiplexing switch elements and the second set of demultiplexing switch elements.

17. The electronic device of claim 11, further comprising: The first resistor connection electrode is connected to the active resistor layer through a plurality of first set of resistor contact holes; as well as The second resistor connection electrode is connected to the active resistor layer through multiple second sets of resistor contact holes.

18. The electronic device according to claim 17, wherein, The number of the plurality of first group resistor contact holes connecting the first resistor connection electrode to the resistor active layer is the same as the number of the plurality of second group resistor contact holes connecting the second resistor connection electrode to the resistor active layer.

19. The electronic device according to claim 17, wherein, The resistance of the active resistive layer is above 1000Ω and below 10000Ω.

20. The electronic device according to any one of claims 10 to 19, wherein, The plurality of data pads includes a first data pad and a second data pad, and Wherein, at least one of the multiple demultiplexing connection lines connecting the first data pad to the first group of demultiplexing switch elements is located on a different layer from at least one of the multiple demultiplexing connection lines connecting the second data pad to the first group of demultiplexing switch elements.

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