Display panel, display control method thereof and display device

Abstract

The application discloses a display panel, a display control method thereof and a display device. In the Nth frame, the reset stage corresponding to the first sub-pixel is located before the compensation stage, and the reset stage corresponding to the second sub-pixel is located before and after the compensation stage, so that when the driving transistor in the first sub-pixel and the driving transistor in the second sub-pixel respectively drive the corresponding light-emitting devices to emit light, the leakage direction between the control end of the driving transistor in the first sub-pixel and the first node is opposite to the leakage direction between the control end of the driving transistor in the second sub-pixel and the first node, thereby neutralizing the brightness variation caused by the potential variation of the control end of the driving transistor in the first sub-pixel and the potential variation of the control end of the driving transistor in the second sub-pixel, so that the influence of the leakage on the display brightness is improved, and the flicker problem can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its display control method and display device. Background Technology

[0002] When using pixel driving circuits to drive light-emitting devices for display, the control terminal potential of the driving transistor can fluctuate due to leakage current, causing changes in display brightness. When the display panel operates at a lower refresh rate, the brightness fluctuations caused by leakage current are more pronounced, leading to flickering issues. Summary of the Invention

[0003] This application provides a display panel and its display control method and display device, which are used to improve the impact of leakage current on display brightness and can be used to improve flickering problems.

[0004] To achieve the above objectives, this application provides a display panel including multiple sub-pixels and multiple pixel groups. The multiple sub-pixels include multiple first sub-pixels and multiple second sub-pixels; each sub-pixel includes a light-emitting device, a driving transistor for generating a driving current to drive the light-emitting device to emit light, a first switching module electrically connected between a control terminal of the driving transistor and a first node, a second switching module electrically connected to the first node, and a first reset module. The first and second switching modules are used to compensate the threshold voltage of the driving transistor during a compensation phase, and the first reset module is used to reset the potential of the first node during a reset phase. The multiple pixel groups include adjacent first pixel groups and second pixel groups, each first pixel group including multiple first sub-pixels, and each second pixel group including multiple second sub-pixels. In the Nth frame, for each first sub-pixel, the reset phase is located before the compensation phase; in the Nth frame, for each second sub-pixel, the reset phase is located before and after the compensation phase; when the driving transistors in the first and second sub-pixels drive the corresponding light-emitting devices to emit light, the leakage direction between the control terminal of the driving transistor in the first sub-pixel and the corresponding first node is opposite to the leakage direction between the control terminal of the driving transistor in the second sub-pixel and the corresponding first node; N≥1.

[0005] This application also provides a display control method for any of the above-mentioned display panels. The display control method includes: in the Nth frame, controlling sub-pixels in a plurality of pixel groups to sequentially enter a corresponding reset stage, so as to reset the potential of the corresponding first node through a first reset module in each sub-pixel; controlling each sub-pixel to enter a corresponding compensation stage after the corresponding reset stage, so as to compensate the threshold voltage of the driving transistor of each sub-pixel; controlling each second sub-pixel to enter the corresponding reset stage again after the corresponding compensation stage, so as to reset the potential of the corresponding first node through a first reset module in the second sub-pixel; controlling the driving transistor of each sub-pixel to generate a driving current in a corresponding light-emitting stage, so as to drive the corresponding light-emitting device to emit light using the driving current. In the light-emitting stage corresponding to the first sub-pixel, the control terminal of the driving transistor in the first sub-pixel leaks current with the corresponding first node in a first leakage direction; in the light-emitting stage corresponding to the second sub-pixel, the control terminal of the driving transistor in the second sub-pixel leaks current with the corresponding first node in a second leakage direction, the first leakage direction and the second leakage direction being opposite.

[0006] This application also provides a display device, including any of the above-mentioned display panels and a source driver, wherein the source driver is electrically connected to the display panel and the source driver is configured to provide corresponding data signals to a plurality of sub-pixels, so that the driving transistor of each sub-pixel generates a driving current according to the corresponding data signal.

[0007] The above technical solution, by placing the reset phase corresponding to the first sub-pixel before the compensation phase and the reset phase corresponding to the second sub-pixel before and after the compensation phase in the Nth frame, can make the potential of the first node in the second sub-pixel different from the potential of the first node in the first sub-pixel after the second reset phase of the second sub-pixel. This allows the driving transistors in the first and second sub-pixels to drive their respective light-emitting devices to emit light, ensuring that the leakage current direction between the control terminal of the driving transistor in the first sub-pixel and the first node is opposite to that between the control terminal of the driving transistor in the second sub-pixel and the first node. This neutralizes the brightness variation caused by the change in the control terminal potential of the driving transistor in the first sub-pixel and the brightness variation caused by the change in the control terminal potential of the driving transistor in the second sub-pixel, thereby improving the impact of leakage current on display brightness and can be used to improve flicker problems. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of this disclosure; Figures 2A-2C This is a schematic block diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure; Figures 3A-3B This is a circuit structure diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure; Figures 4A-4D for Figure 3A The timing diagram corresponding to the pixel driving circuit is shown below; Figures 5A-5D for Figure 3B The timing diagram corresponding to the pixel driving circuit is shown below; Figure 6 This is a schematic diagram of voltage changes at the first node and the control terminal of the driving transistor in an exemplary embodiment of this disclosure; Figures 7A-7B This is a flowchart illustrating a display control method according to an exemplary embodiment of the present disclosure; Figure 8 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure.

[0010] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0012] It should be noted that the electrical connection referred to in this application can refer to a direct connection or an indirect connection. An indirect connection can be a connection between connected modules, devices, or nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals. The descriptions of "first," "second," etc., involved in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" can explicitly or implicitly include at least one of those features. Furthermore, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. The technical solutions between various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] Figure 1 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of the present disclosure. This application provides a display panel including multiple sub-pixels (Spx) and multiple pixel groups.

[0015] Multiple subpixels Spx can include multiple first subpixels Spx1 and multiple second subpixels Spx2.

[0016] Multiple pixel groups include adjacent first pixel group PM1 and second pixel group PM2, each first pixel group PM1 includes multiple first sub-pixels Spx1, and each second pixel group PM2 includes multiple second sub-pixels Spx2.

[0017] Each sub-pixel Spx includes a light-emitting device LE and a pixel driving circuit. The pixel driving circuit is electrically connected to the light-emitting device LE and is used to control the light-emitting device LE to emit light.

[0018] Optionally, the light-emitting device LE can be at least one of organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes.

[0019] Figures 2A-2CThis is a schematic block diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. The pixel driving circuit may include a driving module 10, a first switching module 20, a second switching module 30, and a first reset module 40.

[0020] The driving module 10 is electrically connected to the light-emitting device LE, and the driving module 10 is configured to generate a driving current to drive the light-emitting device LE to emit light.

[0021] In some embodiments, the driving module 10 includes a driving transistor Tdr, which is used to generate a driving current to drive the light-emitting device LE to emit light.

[0022] The first switch module 20 is electrically connected between the control terminal of the driving transistor Tdr and the first node No1. The first switch module 20 is configured to control the signal transmission between the control terminal of the driving transistor Tdr and the first node No1.

[0023] The second switch module 30 is electrically connected to the first node No1. The first switch module 20 and the second switch module 30 are used to compensate the threshold voltage of the drive transistor Tdr during the compensation phase tC.

[0024] The first reset module 40 is electrically connected to the first node No1. The first reset module 40 is used to reset the potential of the first node No1 during the reset phase tn.

[0025] When the driving transistor Tdr drives the light-emitting device LE to emit light, a leakage path exists at the control terminal of the driving transistor Tdr, which affects the brightness of the light-emitting device LE. Therefore, to reduce the impact of leakage, in the Nth frame, for each first sub-pixel Spx1, the reset phase tn is placed before the compensation phase tC; in the Nth frame, for each second sub-pixel Spx2, the reset phase tn is placed before and after the compensation phase tC, N≥1. This is so that after the second reset phase tn of the second sub-pixel Spx2, the potential of the first node No1 in the second sub-pixel Spx2 is different from the potential of the first node No1 in the first sub-pixel Spx1, thereby causing the driving transistor Tdr in the first sub-pixel Spx1 and the second sub-pixel Spx2 to... When the corresponding light-emitting device LE is driven to emit light, the leakage direction between the control terminal of the driving transistor Tdr in the first sub-pixel Spx1 and the corresponding first node No1 can be reversed, and the leakage direction between the control terminal of the driving transistor Tdr in the second sub-pixel Spx2 and the corresponding first node No1 can be reversed. This neutralizes the brightness variation caused by the potential change of the control terminal of the driving transistor Tdr in the first sub-pixel Spx1 and the brightness variation caused by the potential change of the control terminal of the driving transistor Tdr in the second sub-pixel Spx2, thereby improving the impact of leakage on display brightness and can be used to improve flicker problems.

[0026] Taking a P-type transistor as an example, the following explanation is provided. In the Nth frame, corresponding to the reset phase tn of each sub-pixel Spx, the first reset module 40 resets the potential of the first node No1 in sub-pixel Spx, so that the first node No1 has a first voltage. Afterwards, each sub-pixel Spx enters the compensation phase tC. In the compensation phase tC, the first switch module 20 and the second switch module 30 compensate the threshold voltage of the driving transistor Tdr, so that the control terminal of the driving transistor Tdr is written with the threshold voltage information of the driving transistor Tdr, and the voltage of the first node No1 changes to a second voltage, which is higher than the voltage of the control terminal of the driving transistor Tdr. That is, at the end of the compensation phase tC, the voltage of the first node No1 of each sub-pixel Spx is higher than the voltage of the control terminal of the driving transistor Tdr. After the compensation phase tC, the second sub-pixel Spx2 enters the reset phase tn again, causing the potential of the first node No1 in the second sub-pixel Spx2 to change to the first voltage, which is lower than the voltage of the control terminal of the driving transistor Tdr. At the end of the reset phase tn, the voltage of the first node No1 of the second sub-pixel Spx2 is lower than the voltage of the control terminal of the driving transistor Tdr in the second sub-pixel Spx2. When the driving transistors Tdr in the first sub-pixel Spx1 and the second sub-pixel Spx2 drive the corresponding light-emitting devices LE to emit light, the leakage current between the control terminal of the driving transistor Tdr in the first sub-pixel Spx1 and the first node No1 can be made to leak in a first leakage direction, while the leakage current between the control terminal of the driving transistor Tdr in the second sub-pixel Spx2 and the first node No1 can be made to leak in a second leakage direction. The first leakage direction and the second leakage direction are opposite, so that the brightness change caused by the potential change of the control terminal of the driving transistor Tdr in the first sub-pixel Spx1 is neutralized by the brightness change caused by the potential change of the control terminal of the driving transistor Tdr in the second sub-pixel Spx2, thereby making the overall display effect of the display panel similar and improving the flicker problem.

[0027] It should be noted that, for each sub-pixel Spx, before the corresponding compensation stage tC, at least one of the aforementioned reset stages tn may be included. In the Nth frame, for each second sub-pixel Spx2, after the corresponding compensation stage tC, at least one of the aforementioned reset stages tn may be included.

[0028] In some embodiments, if the reset phase tn corresponding to the first sub-pixel Spx1 is placed before the corresponding compensation phase tC in each frame, and the reset phase tn corresponding to the second sub-pixel Spx2 is placed before and after the corresponding compensation phase tC, then the potential difference between the first node No1 of the first sub-pixel Spx1 and the first node No1 of the second sub-pixel Spx2 in each frame can easily cause differences in the characteristic offsets of some devices in the first sub-pixel Spx1 and some devices in the second sub-pixel Spx2, thereby causing problems such as horizontal lines in the display. Therefore, to improve problems such as horizontal lines in the display, the control timing of the first sub-pixel Spx1 and the control timing of the second sub-pixel Spx2 can be reversed in different frames.

[0029] Optionally, in the N+A frame, for each second sub-pixel Spx2, the reset phase tn is located before the compensation phase tC. In the N+A frame, for each first sub-pixel Spx1, the reset phase tn is located before and after the compensation phase tC. This is so that when each sub-pixel Spx drives the corresponding light-emitting device LE to emit light in the N+A frame, the leakage direction between the control terminal of the driving transistor Tdr of each sub-pixel Spx and the corresponding first node No1 is opposite to the leakage direction in the Nth frame. This allows the brightness variation of each sub-pixel Spx in the Nth frame to be neutralized by the brightness variation in the N+A frame. Moreover, the potential of the first node No1 in each sub-pixel Spx in the N+A frame is different from that in the Nth frame. This can shorten the time that the device electrically connected to the first node No1 is subjected to the same bias stress for a long time, thereby helping to reduce the characteristic offset of the device electrically connected to the first node No1 and helping to maintain better performance of the device electrically connected to the first node No1. Furthermore, it helps to reduce the characteristic offset difference between the device electrically connected to the first node No1 of the first sub-pixel Spx1 in the first sub-pixel Spx1 and the device electrically connected to the first node No1 of the second sub-pixel Spx2 in the second sub-pixel Spx2, thereby helping to improve problems such as horizontal stripes in the display. Where A≥1.

[0030] In some embodiments, to reduce the power consumption of the display panel, the display panel is operated at a lower refresh rate. When the display panel operates at a lower refresh rate, the driving transistor Tdr needs to drive the light-emitting device LE for a longer period of time, resulting in a longer leakage current duration at the control terminal of the driving transistor Tdr. This longer leakage current duration makes changes in display brightness more noticeable to the human eye, leading to more pronounced flickering. In this application, by neutralizing the display effects of the first pixel group PM1 and the second pixel group PM2 within at least one frame, the display difference caused by leakage current can be reduced, thereby improving flickering. Furthermore, by controlling the leakage current direction from the control terminal of the driving transistor Tdr in the sub-pixel Spx in different frames to the first node No1, the improvement effect on display difference can be further enhanced.

[0031] It should be noted that when the display panel displays at a lower refresh rate, the refresh rate of the display panel is the first refresh rate, which can be equal to 30Hz, 45Hz or 60Hz, etc.

[0032] It should be understood that the display panel can also display at a second refresh rate. This second refresh rate is higher than the first refresh rate, and can be equal to 120Hz, 240Hz, or 360Hz, etc.

[0033] In some embodiments, a display cycle of the display panel includes a write frame and at least one hold frame. Corresponding to the write frame, the control terminal of the driving transistor Tdr in each sub-pixel Spx receives the corresponding data signal during the corresponding data write phase tw. Corresponding to the hold frame, the control terminal of the driving transistor Tdr in at least one sub-pixel Spx does not receive the corresponding data signal. The Nth frame and the N+Ath frame are located in different display cycles, and both the Nth frame and the N+Ath frame are write frames, thereby improving the display effect while reducing the power consumption of the display panel.

[0034] In some embodiments, corresponding to a write frame, the first switching module 20 of each sub-pixel Spx connects the signal transmission between the control terminal of the first node No1 and the driving transistor Tdr during the corresponding reset phase tn before the compensation phase tC; and the first switching module 20 of each sub-pixel Spx connects the signal transmission between the control terminal of the first node No1 and the driving transistor Tdr during the corresponding data write phase tw or compensation phase tC. Corresponding to a hold frame, the first switching module 20 of at least one sub-pixel Spx disconnects the signal transmission between the control terminal of the first node No1 and the driving transistor Tdr, so that the data signal written to the control terminal of the driving transistor Tdr of that sub-pixel Spx in the write frame is not cleared.

[0035] Optionally, the time duration between the (N+A)-th frame and the N-th frame is less than or equal to the persistence of vision duration of the human eye, so as to reduce the probability that the human eye perceives the flicker problem.

[0036] In some embodiments, the persistence of vision duration of the human eye is about 0.4 seconds. Therefore, in order to utilize the persistence of vision effect of the human eye to reduce the probability that the flicker problem caused by leakage is perceived by the human eye, the time duration between the (N+A)-th frame and the N-th frame can be made less than 0.4 seconds. That is, the time duration between the end moment of the N-th frame and the start moment of the (N+A)-th frame is less than 0.4 seconds.

[0037] Optionally, the value range of A can be obtained by combining the persistence of vision duration of the human eye and the frequency of the data signal received by the sub-pixel Spx corresponding to one display period or the refresh frequency of the display panel.

[0038] For example, in some embodiments, the refresh frequency of the display panel is f, one display period of the display panel is T, and the persistence of vision duration of the human eye is Te, then T = 1 / f, and T×A < Te. Taking the refresh frequency of the display panel as 30 Hz as an example, one display period of the display panel corresponds to 0.0334 seconds. Therefore, 1≤A≤11.

[0039] It should be noted that one display period of the display panel may not include the hold frame. When the display panel does not include the hold frame, still at the N-th frame, for each first sub-pixel Spx1, the reset stage tn corresponding thereto is located before the corresponding compensation stage tC, and for each second sub-pixel Spx2, the reset stage tn corresponding thereto is located before and after the corresponding compensation stage tC. At the (N+A)-th frame, for each second sub-pixel Spx2, the reset stage tn corresponding thereto is located before the corresponding compensation stage tC, and for each first sub-pixel Spx1, the reset stage tn corresponding thereto is located before and after the corresponding compensation stage tC. Where A≥1, and the time duration between the (N+A)-th frame and the N-th frame can be less than or equal to the persistence of vision duration of the human eye.

[0040] Optionally, at the reset stage tn where each sub-pixel Spx is located before the compensation stage tC, the first reset module 40 can also be reused to cooperate with the first switch module 20 to reset the control end of the driving transistor Tdr, so as to increase the light emitting duration of the light emitting device LE. However, it should be noted that the reset stage tn provided in the present application mainly refers to the stage of resetting the potential of the first node No1, and the operation of resetting the potential of the control end of the driving transistor Tdr can be selectively added to some of the reset stages tn.

[0041] Optionally, to improve the flicker reduction effect, the first pixel group PM1 and the second pixel group PM2 are arranged alternately along the first direction Dr1. Each first pixel group PM1 may include at least one first pixel unit PU1, and each first pixel unit PU1 includes a plurality of first sub-pixels Spx1 arranged along the second direction Dr2. Each second pixel group PM2 includes at least one second pixel unit PU2, and each second pixel unit PU2 includes a plurality of second sub-pixels Spx2 arranged along the second direction Dr2. The first direction Dr1 and the second direction Dr2 intersect, with the plurality of first pixel units PU1 arranged along the first direction Dr1 and the plurality of second pixel units PU2 arranged along the first direction Dr1.

[0042] In some embodiments, the first direction Dr1 is one of the row direction and the column direction, and the second direction Dr2 is the other of the row direction and the column direction. It should be noted that... Figure 1 The illustration uses only the first direction Dr1 as the column direction and the second direction Dr2 as the row direction as an example, but this is not intended to limit this application.

[0043] Optionally, since the more first pixel units PU1 each pixel group includes, the farther some first pixel units PU1 are from the second pixel group PM2, the weaker the leakage current improvement effect of the second sub-pixel Spx2 of the second pixel group PM2 on the first sub-pixel Spx1 becomes. Therefore, to achieve a better flicker reduction effect, each first pixel group PM1 can include one first pixel unit PU1, and each second pixel group PM2 can include one second pixel unit PU2, such as... Figure 1 As shown, the leakage current corresponding to the first pixel group PM1 located at an odd position along the first direction Dr1 can be neutralized by the leakage current corresponding to the second pixel group PM2 located at an even position, so as to further improve the flicker reduction effect.

[0044] In some embodiments, each first pixel group PM1 includes one first pixel unit PU1, and each second pixel group PM2 includes two second pixel units PU2, so that the leakage current corresponding to the two second pixel units PU2 in each second pixel group PM2 can be neutralized by the leakage current corresponding to the first pixel group PM1 located on both sides of the second pixel group PM2, thereby improving the flicker reduction effect. Similarly, in other embodiments, each first pixel group PM1 includes two first pixel units PU1, and each second pixel group PM2 includes one second pixel unit PU2, so that the leakage current corresponding to the two first pixel units PU1 in each first pixel group PM1 can be neutralized by the leakage current corresponding to the second pixel group PM2 located on both sides of the first pixel group PM1, thereby improving the flicker reduction effect. In some other embodiments, each first pixel group PM1 includes two first pixel units PU1, and each second pixel group PM2 includes two second pixel units PU2, so that the leakage current corresponding to the two first pixel units PU1 in each first pixel group PM1 can be neutralized by the leakage current corresponding to the second pixel group PM2 located on both sides of the first pixel group PM1, and the leakage current corresponding to the two second pixel units PU2 in each second pixel group PM2 can be neutralized by the leakage current corresponding to the first pixel group PM1 located on both sides of the second pixel group PM2, thereby improving the flicker reduction effect.

[0045] In order to make the potential of the first node No1 in the first sub-pixel Spx1 and the potential of the first node No1 in the second sub-pixel Spx2 have different reset times in the same frame, corresponding driving circuits can be set for the first reset module 40 of the first pixel group PM1 and the first reset module 40 of the second pixel group PM2 respectively.

[0046] In some embodiments, the display panel includes a first gate driver GM1 and a second gate driver GM2, such as Figure 1 As shown.

[0047] The first gate driver GM1 includes multiple cascaded first gate driving circuits GA. Each first gate driving circuit GA is electrically connected to multiple first sub-pixels Spx1 of a first pixel group PM1. Each first gate driving circuit GA is configured to provide a first scan signal GS1 to the first reset module 40 of the corresponding first sub-pixel Spx1, so that the first reset module 40 in the corresponding first sub-pixel Spx1 controls the signal transmission between the first reset line RL1 and the corresponding first node No1 according to the first scan signal GS1.

[0048] The second gate driver GM2 includes multiple cascaded second gate driving circuits GB. Each second gate driving circuit GB is electrically connected to multiple second sub-pixels Spx2 of a second pixel group PM2. Each second gate driving circuit GB is configured to provide a second scan signal GS2 to the first reset module 40 of the corresponding second sub-pixel Spx2, so that the first reset module 40 in the corresponding second sub-pixel Spx2 controls the signal transmission between the first reset line RL1 and the corresponding first node No1 according to the corresponding second scan signal GS2.

[0049] Optionally, when each first pixel group PM1 includes a first pixel unit PU1 and each second pixel group PM2 includes a second pixel unit PU2, each first gate driving circuit GA is electrically connected to a plurality of first sub-pixels Spx1 in a first pixel unit PU1, and each second gate driving circuit GB is electrically connected to a plurality of second sub-pixels Spx2 in a second pixel unit PU2, so as to control the neutralization of the leakage current corresponding to the first pixel group PM1 located at odd positions along the first direction Dr1 and the leakage current corresponding to the second pixel group PM2 located at even positions.

[0050] Similarly, when each first pixel group PM1 includes one first pixel unit PU1 and each second pixel group PM2 includes two second pixel units PU2, each first gate driving circuit GA is electrically connected to a plurality of first sub-pixels Spx1 in a first pixel unit PU1, and each second gate driving circuit GB is electrically connected to a plurality of second sub-pixels Spx2 included in the two second pixel units PU2 in a second pixel group PM2. Likewise, when each first pixel group PM1 includes two first pixel units PU1 and each second pixel group PM2 includes one second pixel unit PU2, each first gate driving circuit GA is electrically connected to a plurality of first sub-pixels Spx1 included in the two first pixel units PU1 in a first pixel group PM1, and each second gate driving circuit GB is electrically connected to a plurality of second sub-pixels Spx2 included in a second pixel unit PU2. Similarly, when each first pixel group PM1 includes two first pixel units PU1 and each second pixel group PM2 includes two second pixel units PU2, each first gate driving circuit GA is electrically connected to a plurality of first sub-pixels Spx1 included by the two first pixel units PU1 in a first pixel group PM1, and each second gate driving circuit GB is electrically connected to a plurality of second sub-pixels Spx2 included by the two second pixel units PU2 in a second pixel group PM2.

[0051] By setting a first gate driver GM1 and a second gate driver GM2, it is possible to independently reset and control the potential of the first node No1 in the first sub-pixel Spx1 and the potential of the first node No1 in the second sub-pixel Spx2, while enabling multiple first sub-pixels Spx1 in the same first pixel group PM1 to share the first scan signal GS1, and multiple second sub-pixels Spx2 in the same second pixel group PM2 to share the second scan signal GS2. This helps to reduce the number of control signals applied to the display panel, thereby helping to reduce the power consumption of the display panel.

[0052] Optionally, to enable each sub-pixel Spx to generate a driving current based on the corresponding data signal, at least one sub-pixel Spx may further include a data writing module 50, such as... Figures 2A-2C As shown. The data writing module 50 is electrically connected to the corresponding driving transistor Tdr, and the data writing module 50 is configured to transmit the corresponding data signal to the control terminal of the corresponding driving transistor Tdr.

[0053] Optionally, to control the timing of light emission from the light-emitting device LE, at least one sub-pixel Spx may further include a light emission control module 60, such as... Figures 2A-2C As shown. The light-emitting control module 60 is electrically connected to the corresponding driving transistor Tdr and the light-emitting device LE. The light-emitting control module 60 is configured to control the on / off state of the driving current flow path.

[0054] In some embodiments, when the sub-pixel Spx drives the corresponding light-emitting device LE to emit light, the light-emitting control module 60 controls the connection of the path through which the driving current flows, so that the corresponding light-emitting device LE is driven by the driving current to emit light.

[0055] Optionally, to reduce the impact of residual charge on the brightness of the light-emitting device (LE), at least one sub-pixel Spx may further include a second reset module 70, such as... Figures 2A-2C As shown. The second reset module 70 is electrically connected to the anode of the corresponding light-emitting device LE, and the second reset module 70 is configured to reset the potential of the anode of the light-emitting device LE.

[0056] In some embodiments, before the sub-pixel Spx drives the corresponding light-emitting device LE to emit light, the second reset module 70 resets the potential of the anode of the light-emitting device LE.

[0057] Optionally, to enable the driving transistor Tdr to continuously drive the light-emitting device LE with the driving current, at least one sub-pixel Spx may also include a storage module 80, such as... Figures 2A-2C As shown. The storage module 80 is electrically connected to the control terminal of the driving transistor Tdr, and the storage module 80 is configured to maintain the potential of the control terminal of the driving transistor Tdr.

[0058] Optionally, to compensate for the threshold voltage of the driving transistor Tdr, in each sub-pixel Spx, the first source-drain terminal of the driving transistor Tdr is electrically connected to the first voltage terminal VDD, and the second switch module 30 is electrically connected between the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr and the first node No1.

[0059] Optionally, when the first switch module 20 and the second switch module 30 compensate for the threshold voltage of the driving transistor Tdr, the potential variation of the control terminal of the driving transistor Tdr can be controlled by signals such as the data signal corresponding to the sub-pixel Spx, the voltage signal supplied by the voltage terminal, or the reset signal supplied by the reset line. The circuit design of the pixel driving circuit can differ when different signals are used to control the potential variation of the control terminal of the driving transistor Tdr.

[0060] To facilitate understanding of this application, an illustrative example is given using data signals to control the potential change at the control terminal of the driving transistor Tdr.

[0061] Please continue reading. Figure 2B The data writing module 50 can be electrically connected between the other of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr and the data line that transmits the corresponding data signal Vda. The data writing module 50 is configured to control the signal transmission between the first source-drain terminal of the driving transistor Tdr and the corresponding data line according to the corresponding second gate control signal Scan2.

[0062] In some embodiments, the data writing module 50 is configured to transmit the data signal Vda to the control terminal of the driving transistor Tdr according to the second gate control signal Scan2 during the data writing phase tw, so as to charge the control terminal of the driving transistor Tdr using the data signal Vda, thereby enabling the control terminal of the driving transistor Tdr to include the threshold voltage information of the driving transistor Tdr. The data writing phase tw and the compensation phase tC are the same phase.

[0063] Optionally, the light-emitting control module 60 of the pixel driving circuit may include a first light-emitting control unit 601 and a second light-emitting control unit 602, such as... Figure 2B As shown. The first light-emitting control unit 601 is electrically connected between the first voltage terminal VDD and the first source-drain terminal of the driving transistor Tdr, and the second light-emitting control unit 602 is electrically connected between the anode of the light-emitting device LE and the second source-drain terminal of the driving transistor Tdr. The first light-emitting control unit 601 and the second light-emitting control unit 602 are configured to control the on / off state of the driving current flow path according to the corresponding light-emitting control signal EM1.

[0064] In some embodiments, the storage module 80 may be electrically connected between the first voltage terminal VDD and the control terminal of the driving transistor Tdr.

[0065] Optionally, at least one sub-pixel Spx may also include a third reset module 901, which is electrically connected to the first source-drain terminal of the driving transistor Tdr. The third reset module 901 is configured to reset the potential of the first source-drain terminal of the driving transistor Tdr to further improve the flicker reduction effect.

[0066] It should be noted that in some embodiments, the third reset module 901 may be omitted.

[0067] In the design where the data signal Vda is transmitted to the control terminal of the corresponding driving transistor Tdr via the first switch module 20 and the second switch module 30, when a display cycle of the corresponding display panel includes a hold frame, the first switch module 20 of at least one sub-pixel Spx can disconnect the signal transmission between the first node No1 and the control terminal of the driving transistor Tdr during the hold frame, so that the control terminal of the driving transistor Tdr of the sub-pixel Spx will not write new data signals during the hold frame, thereby allowing the sub-pixel Spx to be displayed with the data signals written in the write frame during the hold frame.

[0068] When the first power supply signal supplied by the first voltage terminal VDD controls the potential change of the control terminal of the driving transistor Tdr, the first power supply signal can be transmitted to the control terminal of the corresponding driving transistor Tdr through the first switch module 20 and the second switch module 30 during the compensation stage tC, so as to charge the control terminal of the driving transistor Tdr with the first power supply signal, thereby enabling the control terminal of the driving transistor Tdr to include the threshold voltage information of the driving transistor Tdr.

[0069] When the first power supply signal supplied by the first voltage terminal VDD controls the potential change of the control terminal of the driving transistor Tdr, the data writing module 50 can be electrically connected to the control terminal of the driving transistor Tdr. The data signal Vda can be directly transmitted to the control terminal of the driving transistor Tdr, or it can be written to the control terminal of the driving transistor Tdr through coupling.

[0070] Please continue reading. Figure 2C The following example illustrates how the data signal Vda is coupled and written to the control terminal of the driving transistor Tdr.

[0071] The storage module 80 includes a first storage unit 801 and a second storage unit 802. The first storage unit 801 is electrically connected to a first voltage terminal VDD, and the first storage unit 801 and the second storage unit 802 are electrically connected to a second node No2. The second storage unit 802 is electrically connected between the second node No2 and the control terminal of the driving transistor Tdr. The data writing module 50 is electrically connected between the second node No2 and the data line that transmits the corresponding data signal Vda. The data writing module 50 is configured to control the signal transmission between the second node No2 and the corresponding data line according to the corresponding strobe control signal SW, so that the data signal Vda is coupled to the control terminal of the driving transistor Tdr via the second storage unit 802 during the data writing phase tw.

[0072] Optionally, since the first power signal is used to charge the control terminal of the driving transistor Tdr during the compensation phase, the light-emitting control module 60 can be omitted between the first voltage terminal VDD and the first source-drain terminal of the driving transistor Tdr to reduce the control complexity of the pixel driving circuit and the number of devices included in the pixel driving circuit. To control the timing of the light emission of the light-emitting device LE, the light-emitting control module 60 of the pixel driving circuit can be electrically connected between the anode of the light-emitting device LE and the second source-drain terminal of the driving transistor Tdr. The light-emitting control module 60 is configured to control the on / off state of the driving current flow path according to the corresponding light-emitting control signal EM1.

[0073] Optionally, to reduce the impact of residual charge on the accuracy of luminous brightness of the second node No2, at least one sub-pixel Spx may also include a fourth reset module 902, which is electrically connected to the second node No2 and is configured to reset the potential of the second node No2.

[0074] During the compensation phase, when the first power signal is used to charge the control terminal of the driving transistor Tdr, the data signal Vda can be transmitted to the control terminal of the driving transistor Tdr without passing through the first switch module 20 and the second switch module 30. Therefore, the compensation of the threshold voltage of the driving transistor Tdr is not limited by the duration of the data writing phase, which can help improve the compensation accuracy of the threshold voltage of the driving transistor Tdr. When a display cycle of the corresponding display panel includes a hold frame, the data writing module 50 of at least one sub-pixel Spx can disconnect the signal transmission between the second node No2 and the corresponding data line during the hold frame. This prevents the control terminal of the driving transistor Tdr of the sub-pixel Spx from writing new data signals during the hold frame, allowing the sub-pixel Spx to be displayed with the data signal written in the write frame during the hold frame.

[0075] Optionally, the modules and units included in the pixel driving circuit can be implemented using one or more components such as switching devices and capacitors. For ease of understanding this application, [further details are provided]. Figure 2B and Figure 2C The circuit design shown in the schematic diagram will be used as an example for explanation.

[0076] like Figures 3A-3B This is a circuit structure diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure.

[0077] Optionally, the first switching module 20 may include a first transistor T1, which includes a control terminal configured to receive a first gate control signal Scan1, a first source-drain terminal electrically connected to the first node No1, and a second source-drain terminal electrically connected to the control terminal of the driving transistor Tdr.

[0078] Optionally, the second switching module 30 may include a second transistor T2, which includes a control terminal configured to receive the second gate control signal Scan2, a first source-drain terminal electrically connected to one of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the first node No1.

[0079] Optionally, the first reset module 40 may include a first reset transistor Ti1, which includes a first source-drain terminal electrically connected to the first reset line RL1 and a second source-drain terminal electrically connected to the first node No1. The control terminal of the first reset transistor Ti1 in the first sub-pixel Spx1 is configured to receive a first scan signal GS1, and the control terminal of the first reset transistor Ti1 in the second sub-pixel Spx2 is configured to receive a second scan signal GS2.

[0080] In some embodiments, level variations in the first scan signal GS1 couple to the potential of the first node No1 of the corresponding first sub-pixel Spx1, and level variations in the second scan signal GS2 couple to the potential of the first node No1 of the corresponding second sub-pixel Spx2, adversely affecting the flicker reduction effect. Therefore, to further improve the stability of the first node No1, each first reset module 40 may further include a first capacitor C1, which is electrically connected between the corresponding first node No1 and the first reset line RL1.

[0081] Optionally, the second reset module 70 includes a second reset transistor Ti2. The second reset transistor Ti2 includes a control terminal configured to receive a third gate control signal Scan3, a first source-drain terminal electrically connected to the second reset line RL2, and a second source-drain terminal electrically connected to the anode of the light-emitting device LE. The second reset transistor Ti2 is configured to control the signal transmission between the second reset line RL2 and the anode of the light-emitting device LE according to the third gate control signal Scan3.

[0082] In some embodiments, the data writing module 50 may include a data transistor Tda, which includes a control terminal configured to receive a corresponding second gate control signal Scan2, a first source-drain terminal electrically connected to a corresponding data line, and a second source-drain terminal electrically connected to the other of the first source-drain terminal and the second source-drain terminal of the corresponding driving transistor Tdr. Figure 2B and Figure 3A As shown.

[0083] In some embodiments, the first light-emitting control unit 601 of the light-emitting control module 60 includes a first light-emitting control transistor Ts1. The first light-emitting control transistor Ts1 includes a control terminal configured to receive a corresponding light-emitting control signal EM1, a first source-drain terminal electrically connected to a first voltage terminal VDD, and a second source-drain terminal electrically connected to the first source-drain terminal of a corresponding driving transistor Tdr. The first light-emitting control transistor Ts1 is configured to control the signal transmission between the first source-drain terminal of the driving transistor Tdr and the first voltage terminal VDD according to the corresponding light-emitting control signal EM1. Figure 2B and Figure 3A As shown.

[0084] In some embodiments, the second light-emitting control unit 602 of the light-emitting control module 60 includes a second light-emitting control transistor Ts2. The second light-emitting control transistor Ts2 includes a control terminal configured to receive a corresponding light-emitting control signal EM1, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the anode of the corresponding light-emitting device LE. The second light-emitting control transistor Ts2 is configured to control the signal transmission between the second source-drain terminal of the driving transistor Tdr and the anode of the corresponding light-emitting device LE according to the corresponding light-emitting control signal EM1. Figure 2B and Figure 3A As shown.

[0085] In some embodiments, the third reset module 901 includes a third reset transistor Ti3. The third reset transistor Ti3 includes a control terminal configured to receive a third gate control signal Scan3, a first source-drain terminal electrically connected to a third reset line RL3, and a second source-drain terminal electrically connected to the first source-drain terminal of a driving transistor Tdr. The third reset transistor Ti3 is configured to control the signal transmission between the third reset line RL3 and the first source-drain terminal of the driving transistor Tdr according to the third gate control signal Scan3. Figure 2B and Figure 3A As shown.

[0086] In some embodiments, the storage module 80 includes a second capacitor C2, which is electrically connected between the first voltage terminal VDD and the control terminal of the driving transistor Tdr, such as Figure 2B and Figure 3A As shown.

[0087] In other embodiments, the storage module 80 includes a first storage unit 801 and a second storage unit 802. The first storage unit 801 includes a third capacitor C3, and the second storage unit 802 includes a fourth capacitor C4. The third capacitor C3 is electrically connected between the first voltage terminal VDD and the corresponding second node No2, and the fourth capacitor C4 is electrically connected between the second node No2 and the control terminal of the corresponding driving transistor Tdr. Figure 2C and Figure 3B As shown.

[0088] In other embodiments, the data writing module 50 may include a data transistor Tda, which includes a control terminal configured to receive a gating control signal SW, a first source-drain terminal electrically connected to a corresponding data line, and a second source-drain terminal electrically connected to a corresponding second node No2. The data transistor Tda is configured to control the signal transmission between the second node No2 and the corresponding data line according to the gating control signal SW. Figure 2C and Figure 3B As shown.

[0089] In other embodiments, the light-emitting control module 60 includes a light-emitting control transistor Ts. The light-emitting control transistor Ts includes a control terminal configured to receive a light-emitting control signal EM1, a first source-drain terminal electrically connected to the second source-drain terminal of a driving transistor Tdr, and a second source-drain terminal electrically connected to the anode of a corresponding light-emitting device LE. The light-emitting control transistor Ts is configured to control the signal transmission between the second source-drain terminal of the driving transistor Tdr and the anode of the corresponding light-emitting device LE according to the light-emitting control signal EM1. Figure 2C and Figure 3B As shown.

[0090] In some embodiments, the fourth reset module 902 includes a fourth reset transistor Ti4. The fourth reset transistor Ti4 includes a control terminal configured to receive a first gate control signal Scan1, a first source-drain terminal electrically connected to a fourth reset line RL4, and a second source-drain terminal electrically connected to a second node No2. The fourth reset transistor Ti4 is configured to control the signal transmission between the second source-drain terminal of the driving transistor Tdr and the corresponding second node No2 according to the first gate control signal Scan1. Figure 2C and Figure 3B As shown.

[0091] It should be noted that, Figures 3A-3B It is the pixel driving circuit corresponding to a single sub-pixel Spx. Figures 3A-3B This explanation uses the example of electrically connecting the cathode of the light-emitting device (LE) to the second voltage terminal (VSS). However, in practical applications, the driving transistor (Tdr) can be electrically connected between the cathode of the LE and the second voltage terminal (VSS). Furthermore, Figures 2B-2C and Figures 3A-3B This application is merely an illustrative example of some embodiments of the pixel driving circuit and is not intended to limit the scope of this application. Any changes made by those skilled in the art to the implementation of the modules and units included in the pixel driving circuit, the connection relationships of the modules and units and the signals applied, or the addition or deletion of the number of modules and units included in the pixel driving circuit, based on actual needs, are permitted and included in this application.

[0092] Furthermore, the transistors included in the pixel driving circuit can be either P-type or N-type transistors. Each transistor in the pixel driving circuit can be implemented as a bipolar junction transistor (BJT), a field-effect transistor (FET), or a thin-film transistor (TFT). When the transistor is implemented as a FET or TFT, the control terminal can be the gate, the first source / drain terminal can be one of the source and drain, and the second source / drain terminal can be the other of the source and drain. When the transistor is implemented as a BJT, the control terminal can be the base, the first source / drain terminal can be one of the collector and emitter, and the second source / drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The oxide semiconductor materials include indium gallium zinc oxide or indium zinc oxide.

[0093] Figures 4A-4D for Figure 3A The timing diagram corresponding to the pixel driving circuit shown is as follows: Figures 5A-5D for Figure 3B The timing diagram corresponding to the pixel driving circuit shown is as follows: Figure 6This is a schematic diagram illustrating the voltage changes at the control terminals of the first node No1 and the driving transistor Tdr in an exemplary embodiment of this disclosure. For ease of understanding, the reset stage tn before the compensation stage tC is designated as the first reset stage tn1, and the reset stage tn after the compensation stage tC is designated as the second reset stage tn2. Figures 3A-3B The transistors shown are P-type transistors, combined with Figures 4A-4D , Figures 5A-5D and Figure 6 The working principle of neutralizing the leakage current of the first sub-pixel Spx1 and the second sub-pixel Spx2 to improve flicker is explained. Figures 4A-4D and Figures 5A-5D In this context, LCS represents the trend of brightness variation. Figure 6 The horizontal axis represents time, in microseconds; the vertical axis represents voltage, in volts.

[0094] Please continue reading. Figure 3A , Figure 4A and Figure 6 In the Nth frame F(N), each first sub-pixel Spx1 has a corresponding first reset phase tn1, compensation phase tC (i.e., data writing phase tw), anode reset phase tnA, and light emission phase tL. The voltage change of the first node No1 in each first sub-pixel Spx1 is as follows: Figure 6 As shown in waveform V1, the voltage change at the control terminal of the driving transistor Tdr in each first sub-pixel Spx1 is as follows: Figure 6 The waveform V2 is shown in the figure.

[0095] During the first reset phase tn1, the first scan signal GS1 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line RL1 resets the potential of the first node No1.

[0096] Furthermore, during the first reset phase tn1, the light emission control signal EM1, the second gate control signal Scan2, and the third gate control signal Scan3 can be set to high level, the first gate control signal Scan1 can be set to low level, the first transistor T1 can be turned on, and the first reset signal transmitted by the first reset line RL1 can reset the potential of the control terminal of the driving transistor Tdr.

[0097] During the compensation phase tC, the light emission control signal EM1, the third gate control signal Scan3, and the first scan signal GS1 are at high levels, while the first gate control signal Scan1 and the second gate control signal Scan2 are at low levels. The data transistor Tda, the first transistor T1, and the second transistor T2 are turned on, and the data signal charges the control terminal of the driving transistor Tdr. The threshold voltage of the driving transistor Tdr is written to the control terminal of the driving transistor Tdr.

[0098] During the anode reset phase tnA, the third gate control signal Scan3 is low, while the light emission control signal EM1, the first gate control signal Scan1, the second gate control signal Scan2, and the first scan signal GS1 are high. The second reset transistor Ti2 and the third reset transistor Ti3 are turned on. The second reset signal transmitted by the second reset line RL2 resets the potential of the anode of the light-emitting device LE, and the third reset signal transmitted by the third reset line RL3 resets the potential of the first source-drain terminal of the driving transistor Tdr.

[0099] During the light-emitting stage tL, the light-emitting control signal EM1 is at a low level, while the first gate control signal Scan1, the second gate control signal Scan2, the third gate control signal Scan3, and the first scan signal GS1 are at a high level. The first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are turned on, and the light-emitting device LE of the first sub-pixel Spx1 emits light.

[0100] Please continue reading. Figure 3A , Figure 4B and Figure 6 In frame N, F(N), each second sub-pixel Spx2 has a corresponding first reset phase tn1, compensation phase tC (i.e., data writing phase tw), second reset phase tn2, and light emission phase tL. The voltage change of the first node No1 in each second sub-pixel Spx2 is as follows: Figure 6 As shown in waveform V3, the voltage change at the control terminal of the driving transistor Tdr in each first sub-pixel Spx1 is as follows: Figure 6 The waveform V2 is shown in the figure.

[0101] During the first reset phase tn1, the second scan signal GS2 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line resets the potential of the first node No1.

[0102] Furthermore, during the first reset phase tn1, the light emission control signal EM1, the second gate control signal Scan2, and the third gate control signal Scan3 can be set to high level, the first gate control signal Scan1 can be set to low level, the first transistor T1 can be turned on, and the first reset signal transmitted by the first reset line RL1 can reset the potential of the control terminal of the driving transistor Tdr.

[0103] During the compensation phase tC, the light emission control signal EM1, the third gate control signal Scan3, and the second scan signal GS2 are at high levels, while the first gate control signal Scan1 and the second gate control signal Scan2 are at low levels. The data transistor Tda, the first transistor T1, and the second transistor T2 are turned on. The data signal Vda charges the control terminal of the driving transistor Tdr, and the threshold voltage of the driving transistor Tdr is written to the control terminal of the driving transistor Tdr.

[0104] During the second reset phase tn2, the second scan signal GS2 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line RL1 resets the potential of the first node No1.

[0105] Furthermore, during the second reset phase tn2, the third gate control signal Scan3 can be set to a low level, while the light emission control signal EM1, the first gate control signal Scan1, and the second gate control signal Scan2 are set to a high level. The second reset transistor Ti2 and the third reset transistor Ti3 are turned on, and the second reset signal transmitted by the second reset line RL2 resets the potential of the anode of the light emission device LE. The third reset signal transmitted by the third reset line RL3 resets the potential of the first source-drain terminal of the driving transistor Tdr.

[0106] It should be understood that the anode reset phase tnA of the second sub-pixel Spx2 may not be in the same time period as the second reset phase tn2.

[0107] During the light-emitting stage tL, the light-emitting control signal EM1 is at a low level, while the first gate control signal Scan1, the second gate control signal Scan2, the third gate control signal Scan3, and the first scan signal GS1 are at a high level. The first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are turned on, and the light-emitting device LE of the first sub-pixel Spx1 emits light.

[0108] Therefore, corresponding to the Nth frame F(N), when the driving transistor Tdr of the first sub-pixel Spx1 drives the corresponding light-emitting device LE to emit light, the direction of leakage current flow is from the first node No1 to the control terminal of the driving transistor Tdr. The brightness of the light-emitting device LE controlled by the driving transistor Tdr decreases over time, as shown below. Figure 4A The curve LCS is shown in the figure. Corresponding to frame N, F(N), when the driving transistor Tdr of the second sub-pixel Spx2 drives the corresponding light-emitting device LE to emit light, the leakage current flows from the control terminal of the driving transistor Tdr to the first node No1. The brightness of the light-emitting device LE controlled by the driving transistor Tdr increases over time, as shown in the figure. Figure 4BThe curve LCS is shown in the figure. Flickering is improved by making the brightness changes of the first sub-pixel Spx1 and the second sub-pixel Spx2 in opposite directions.

[0109] Reference Figures 4A-4B The relevant descriptions can be used to obtain the corresponding... Figures 4C-4D The working principle of the first sub-pixel Spx1 and the second sub-pixel Spx2 corresponding to the N+A frame F(N+A) will not be elaborated here.

[0110] Because the first sub-pixel Spx1 exhibits opposite brightness change trends in frame N (N) and frame N+A (N+A), and the second sub-pixel Spx2 also exhibits opposite brightness change trends in frame N (N) and frame N+A (N+A), flicker can be further improved. Furthermore, the bias stress experienced by the first transistor T1 in each sub-pixel Spx in frame N (N) and frame N+A (N+A) is opposite, which can compensate for the characteristic offset of the first transistor T1. This reduces the difference between the characteristic offset of the first transistor T1 in the first sub-pixel Spx1 and the characteristic offset of the first transistor T1 in the second sub-pixel Spx2, which helps to improve problems such as horizontal lines in the display.

[0111] Please continue reading. Figure 3B , Figure 5A and Figure 6 In the Nth frame F(N), each first sub-pixel Spx1 has a corresponding first reset phase tn1, compensation phase tC, data writing phase tw, anode reset phase tnA, and light emission phase tL. The voltage change of the first node No1 in each first sub-pixel Spx1 is as follows: Figure 6 As shown in waveform V1, the voltage change at the control terminal of the driving transistor Tdr in each first sub-pixel Spx1 is as follows: Figure 6 The waveform V2 is shown in the figure.

[0112] During the first reset phase tn1, the first scan signal GS1 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line RL1 resets the potential of the first node No1.

[0113] In addition, during the first reset phase tn1, the gating control signal SW, the second gate control signal Scan2, the light emission control signal EM1, and the third gate control signal Scan3 can be set to high level, the first gate control signal Scan1 can be set to low level, the first transistor T1 can be turned on, and the first reset signal can reset the potential of the control terminal of the driving transistor Tdr.

[0114] During the compensation phase tC, the gating control signal SW, the first scan signal GS1, the light emission control signal EM1, and the third gate control signal Scan3 are at high levels, while the second gate control signal Scan2 and the first gate control signal Scan1 are at low levels. The fourth reset transistor Ti4, the first transistor T1, and the second transistor T2 are turned on. The fourth reset signal transmitted by the fourth reset line RL4 resets the potential of the second node No2. The first power supply signal charges the control terminal of the driving transistor Tdr, and the threshold voltage of the driving transistor Tdr is written to the control terminal of the driving transistor Tdr.

[0115] During the data writing stage tw: the second gate control signal Scan2, the first gate control signal Scan1, the first scan signal GS1, the light emission control signal EM1, and the third gate control signal Scan3 are at high level, the gating control signal SW is at low level, the data transistor Tda is turned on, and the data signal Vda is coupled to the control terminal of the driving transistor Tdr through the third capacitor C3, so that the control terminal of the driving transistor Tdr writes the data signal.

[0116] During the anode reset phase tnA, the second gate control signal Scan2, the first gate control signal Scan1, the first scan signal GS1, the light emission control signal EM1, and the gating control signal SW are at high levels, the third gate control signal Scan3 is at low level, the second reset transistor Ti2 is turned on, and the second reset signal transmitted by the second reset line RL2 resets the anode of the light-emitting device LE.

[0117] During the light-emitting stage tL: the light-emitting control signal EM1 is low, the first gate control signal Scan1, the second gate control signal Scan2, the third gate control signal Scan3, the first scan signal GS1, and the gating control signal SW are high, the light-emitting control transistor Ts is turned on, and the light-emitting device LE is driven by the driving current to emit light.

[0118] Please continue reading. Figure 3B , Figure 5B and Figure 6 In frame N, F(N), each second sub-pixel Spx2 has a corresponding first reset phase tn1, compensation phase tC, second reset phase tn2, data writing phase tw, anode reset phase tnA, and light emission phase tL. The voltage change of the first node No1 in each second sub-pixel Spx2 is as follows: Figure 6 As shown in waveform V3, the voltage change at the control terminal of the driving transistor Tdr in each second sub-pixel Spx2 is as follows: Figure 6 The waveform V2 is shown in the figure.

[0119] During the first reset phase tn1, the second scan signal GS2 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line RL1 resets the potential of the first node No1.

[0120] In addition, during the first reset phase tn1, the gating control signal SW, the second gate control signal Scan2, the light emission control signal EM1, and the third gate control signal Scan3 can be set to high level, the first gate control signal Scan1 can be set to low level, the first transistor T1 can be turned on, and the first reset signal can reset the potential of the control terminal of the driving transistor Tdr.

[0121] During the compensation phase tC, the gating control signal SW, the second scan signal GS2, the light emission control signal EM1, and the third gate control signal Scan3 are at high levels, while the second gate control signal Scan2 and the first gate control signal Scan1 are at low levels. The fourth reset transistor Ti4, the first transistor T1, and the second transistor T2 are turned on. The fourth reset signal transmitted by the fourth reset line RL4 resets the potential of the second node No2. The first power supply signal charges the control terminal of the driving transistor Tdr, and the threshold voltage of the driving transistor Tdr is written to the control terminal of the driving transistor Tdr.

[0122] During the second reset phase tn2, the second scan signal GS2 is at a low level, the first reset transistor Ti1 is turned on, and the first reset signal transmitted by the first reset line RL1 resets the potential of the first node No1.

[0123] During the data writing stage tw: the second gate control signal Scan2, the first gate control signal Scan1, the second scan signal GS2, the light emission control signal EM1, and the third gate control signal Scan3 are at high level, the gating control signal SW is at low level, the data transistor Tda is turned on, and the data signal Vda is coupled to the control terminal of the driving transistor Tdr through the third capacitor C3, so that the control terminal of the driving transistor Tdr writes the data signal.

[0124] During the anode reset phase tnA, the second gate control signal Scan2, the first gate control signal Scan1, the second scan signal GS2, the light emission control signal EM1, and the gating control signal SW are at high levels, the third gate control signal Scan3 is at low level, the second reset transistor Ti2 is turned on, and the second reset signal transmitted by the second reset line RL2 resets the anode of the light-emitting device LE.

[0125] During the light-emitting stage tL: the light-emitting control signal EM1 is low, the first gate control signal Scan1, the second gate control signal Scan2, the third gate control signal Scan3, the second scan signal GS2, and the gating control signal SW are high, the light-emitting control transistor Ts is turned on, and the light-emitting device LE is driven by the driving current to emit light.

[0126] It should be noted that since the data signal is coupled to the control terminal of the driving transistor Tdr via the second node No2, the partial overlap between the second reset phase tn2 and the data write phase tw does not affect the writing of the data signal to the control terminal of the driving transistor Tdr. In some embodiments, the second reset phase tn2 and the data write phase tw may or may not overlap.

[0127] Therefore, as with the aforementioned corresponding Nth frame F(N), the brightness changes of the first sub-pixel Spx1 and the second sub-pixel Spx2 show opposite trends, and the neutralization of the brightness changes of the first sub-pixel Spx1 and the second sub-pixel Spx2 can improve flicker.

[0128] Reference Figures 5A-5B The relevant descriptions can be used to obtain the corresponding... Figures 5C-5D The working principle of the first sub-pixel Spx1 and the second sub-pixel Spx2 corresponding to the N+A frame F(N+A) is not described in detail here. As mentioned before, the first sub-pixel Spx1 has opposite brightness change trends in the Nth frame F(N) and the N+A frame F(N+A), and the second sub-pixel Spx2 has opposite brightness change trends in the Nth frame F(N) and the N+A frame F(N+A). This can further improve flicker and help improve problems such as horizontal lines in the display.

[0129] Furthermore, in this application, each sub-pixel Spx has only one leakage path at its control terminal, which helps to further reduce the impact of leakage on the potential of the control terminal of the driving transistor Tdr.

[0130] It should be noted that the sub-pixels Spx in each pixel group can be sequentially scanned using a row-by-row scanning method, as described above. Figures 4A-4D or Figures 5A-5D The aforementioned stage. In row scanning, when the second direction Dr2 is the row direction, there is a certain phase difference between the time periods corresponding to sub-pixels Spx in row m and those corresponding to sub-pixels Spx in row m+B. Multiple sub-pixels Spx in the same row are in the same working time period at the same moment. m≥1, B≥1.

[0131] Figures 7A-7B This is a flowchart illustrating a display control method according to an exemplary embodiment of this disclosure. This application also provides a display control method for use in any of the aforementioned display panels.

[0132] In some embodiments, the display control method includes: In the Nth frame, the sub-pixels Spx in multiple pixel groups are controlled to enter the corresponding reset phase tn in sequence, so that the potential of the corresponding first node No1 is reset by the first reset module 40 in each sub-pixel Spx. Each sub-pixel Spx is controlled to enter the corresponding compensation stage tC after the corresponding reset stage tn, so as to compensate the threshold voltage of the driving transistor Tdr of each sub-pixel Spx. Each second sub-pixel Spx2 is controlled to re-enter the corresponding reset stage tn after the corresponding compensation stage tC, so that the potential of the corresponding first node No1 is reset by the first reset module 40 in the second sub-pixel Spx2. The driving transistor Tdr of each sub-pixel Spx generates a driving current during the corresponding light-emitting stage tL, so as to drive the corresponding light-emitting device LE to emit light, such as... Figure 7A As shown.

[0133] Specifically, during the light-emitting stage tL corresponding to the first sub-pixel Spx1, the control terminal of the driving transistor Tdr in the first sub-pixel Spx1 leaks current with the corresponding first node No1 in a first leakage direction; during the light-emitting stage tL corresponding to the second sub-pixel Spx2, the control terminal of the driving transistor Tdr in the second sub-pixel Spx2 leaks current with the corresponding first node No1 in a second leakage direction, and the first leakage direction and the second leakage direction are opposite.

[0134] In some embodiments, the display control method further includes: In the N+A frame, the sub-pixels Spx in multiple pixel groups are controlled to enter the corresponding reset phase tn in sequence, so as to reset the potential of the corresponding first node No1 through the first reset module 40 in each sub-pixel Spx; where A≥1.

[0135] Each sub-pixel Spx is controlled to enter the corresponding compensation stage tC after the corresponding reset stage tn, so as to compensate the threshold voltage of the driving transistor Tdr of each sub-pixel Spx. Each first sub-pixel Spx1 is controlled to re-enter the corresponding reset stage tn after the corresponding compensation stage tC, so that the potential of the corresponding first node No1 is reset by the first reset module 40 in the first sub-pixel Spx1. The driving transistor Tdr of each sub-pixel Spx generates a driving current during the corresponding light-emitting stage tL, so as to drive the corresponding light-emitting device LE to emit light, such as... Figure 7B As shown.

[0136] In some embodiments, the display control method further includes: in the reset phase tn corresponding to each sub-pixel Spx, which is located before the compensation phase tC, resetting the potential of the control terminal of the driving transistor Tdr through the first reset module 40 and the first switch module 20.

[0137] In some embodiments, the display control method further includes: Control each sub-pixel Spx during the corresponding compensation stage tC or the data writing stage tw after the compensation stage tC, and transmit the corresponding data signal to the control terminal of the driving transistor Tdr. Each sub-pixel Spx is controlled to enter the anode reset phase tnA after the corresponding compensation phase tC or data writing phase tw, so as to reset the potential of the anode of the light-emitting device LE; and, Each sub-pixel Spx is controlled to enter the light-emitting stage tL after the corresponding anode reset stage tnA, so as to drive the corresponding light-emitting device LE to emit light using the driving current generated by the driving transistor Tdr.

[0138] In some embodiments, the anode reset stage tnA and the reset stage tn, which is located after the compensation stage tC, are the same stage.

[0139] It should be noted that the working principle of each stage in the display control method can be obtained by referring to the description of each stage in the display panel embodiment, and will not be repeated here.

[0140] Since the display control method of this application uses any of the above-mentioned display panels, the display control method of this application has at least all the beneficial effects brought about by the technical solutions of the above-mentioned display panels, which will not be described in detail here.

[0141] Figure 8 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. The present application also provides a display device including any of the above-mentioned display panels.

[0142] In some embodiments, the display device further includes a source driver electrically connected to the display panel, the source driver being configured to provide corresponding data signals to a plurality of sub-pixels Spx, such that the driving transistor Tdr of each sub-pixel Spx generates a driving current according to the corresponding data signal.

[0143] In some embodiments, the display device further includes a timing controller configured to transmit corresponding control signals to the source driver, the first gate driver GM1, and the second gate driver GM2, so that the source driver generates corresponding data signals and the first gate driver GM1 and the second gate driver GM2 generate corresponding scan signals.

[0144] It should be noted that the display device may also include components not shown, such as a graphics processor and a power management chip.

[0145] Since the display device of this application uses any of the above-mentioned display panels, the display device of this application has at least all the beneficial effects brought about by the technical solutions of the above-mentioned display panels, which will not be elaborated here.

[0146] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels, including multiple first sub-pixels and multiple second sub-pixels; Each sub-pixel includes a light-emitting device, a driving transistor for generating a driving current to drive the light-emitting device to emit light, a first switching module electrically connected between the control terminal of the driving transistor and the first node, a second switching module electrically connected to the first node, and a first reset module. The first switching module and the second switching module are used to compensate the threshold voltage of the driving transistor during the compensation phase, and the first reset module is used to reset the potential of the first node during the reset phase. Multiple pixel groups, including adjacent first pixel groups and second pixel groups, each first pixel group including multiple first sub-pixels, and each second pixel group including multiple second sub-pixels; In the Nth frame, for each first sub-pixel, the reset phase is located before the compensation phase; in the Nth frame, for each second sub-pixel, the reset phase is located before and after the compensation phase; when the driving transistors in the first and second sub-pixels respectively drive the corresponding light-emitting devices to emit light, the leakage direction between the control terminal of the driving transistor in the first sub-pixel and the corresponding first node is opposite to the leakage direction between the control terminal of the driving transistor in the second sub-pixel and the corresponding first node, and N≥1.

2. The display panel according to claim 1, characterized in that, In the N+A frame, for each second sub-pixel, the reset phase is located before the compensation phase; in the N+A frame, for each first sub-pixel, the reset phase is located before and after the compensation phase; wherein, A≥1.

3. The display panel according to claim 2, characterized in that, A display cycle of the display panel includes a write frame and at least one hold frame; corresponding to the write frame, the control terminal of the driving transistor in each sub-pixel receives a corresponding data signal during the corresponding data write phase; corresponding to the hold frame, the control terminal of the driving transistor in at least one sub-pixel does not receive the corresponding data signal. The Nth frame and the N+Ath frame are located in different display cycles, and both the Nth frame and the N+Ath frame are the write frames.

4. The display panel according to claim 2, characterized in that, The duration between the N+Ath frame and the Nth frame is less than or equal to the persistence of vision in the human eye.

5. The display panel according to claim 1, characterized in that, The first pixel group and the second pixel group are arranged alternately along a first direction. Each first pixel group includes at least one first pixel unit, and each first pixel unit includes a plurality of first sub-pixels arranged along a second direction. Each second pixel group includes at least one second pixel unit, and each second pixel unit includes a plurality of second sub-pixels arranged along the second direction. Wherein, the first direction and the second direction intersect, a plurality of first pixel units are arranged along the first direction, and a plurality of second pixel units are arranged along the first direction.

6. The display panel according to claim 5, characterized in that, The display panel includes: A first gate driver includes a plurality of cascaded first gate driving circuits, each first gate driving circuit being electrically connected to a plurality of first sub-pixels of a first pixel group, each first gate driving circuit being configured to provide a first scan signal to a first reset module of a corresponding first sub-pixel, such that the first reset module in the corresponding first sub-pixel controls signal transmission between a first reset line and a corresponding first node according to the first scan signal; and... The second gate driver includes a plurality of cascaded second gate driving circuits. Each second gate driving circuit is electrically connected to a plurality of second sub-pixels of a second pixel group. Each second gate driving circuit is configured to provide a second scan signal to the first reset module of the corresponding second sub-pixel, so that the first reset module in the corresponding second sub-pixel controls the signal transmission between the first reset line and the corresponding first node according to the corresponding second scan signal.

7. The display panel according to any one of claims 1 to 6, characterized in that, In each sub-pixel, the first source-drain terminal of the driving transistor is electrically connected to the first voltage terminal, and the second switching module is electrically connected between the second source-drain terminal of the driving transistor and the first node.

8. The display panel according to claim 7, characterized in that, The first switching module includes a first transistor, which includes a control terminal configured to receive a first gate control signal, a first source-drain terminal electrically connected to the first node, and a second source-drain terminal electrically connected to the control terminal of the driving transistor. The second switching module includes a second transistor, which includes a control terminal configured to receive a second gate control signal, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor, and a second source-drain terminal electrically connected to the first node. The first reset module includes a first reset transistor, which includes a first source-drain terminal electrically connected to a first reset line and a second source-drain terminal electrically connected to the first node. In this configuration, the control terminal of the first reset transistor in the first sub-pixel is configured to receive a first scan signal, and the control terminal of the first reset transistor in the second sub-pixel is configured to receive a second scan signal.

9. The display panel according to claim 8, characterized in that, Each of the first reset modules includes a first capacitor, which is electrically connected between the corresponding first node and the first reset line.

10. The display panel according to claim 7, characterized in that, Each of the sub-pixels further includes: The data writing module is electrically connected to the corresponding driving transistor and is configured to transmit the corresponding data signal to the control terminal of the corresponding driving transistor. The light-emitting control module is electrically connected to the corresponding driving transistor and the light-emitting device, and is configured to control the on / off state of the driving current flow path; The second reset module, electrically connected to the anode of the corresponding light-emitting device, is configured to reset the potential of the anode of the light-emitting device; and The storage module is electrically connected to the control terminal of the driving transistor and is configured to maintain the potential of the control terminal of the driving transistor.

11. The display panel according to claim 10, characterized in that, The data writing module is electrically connected between the first source / drain terminal of the driving transistor and the data line that transmits the corresponding data signal. The data writing module is configured to control the signal transmission between the first source / drain terminal of the driving transistor and the corresponding data line according to the corresponding second gate control signal. The light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is electrically connected between the first voltage terminal and the first source-drain terminal of the driving transistor, and the second light-emitting control unit is electrically connected between the anode of the light-emitting device and the second source-drain terminal of the driving transistor. The first light-emitting control unit and the second light-emitting control unit are configured to control the on / off state of the driving current flow path according to the corresponding light-emitting control signal. The storage module is electrically connected between the first voltage terminal and the control terminal of the driving transistor.

12. The display panel according to claim 11, characterized in that, Each of the sub-pixels further includes: The third reset module is electrically connected to the first source-drain terminal of the driving transistor and is configured to reset the potential of the first source-drain terminal of the driving transistor.

13. The display panel according to claim 12, characterized in that, The data writing module includes a data transistor, which includes a control terminal configured to receive a corresponding second gate control signal, a first source / drain terminal electrically connected to the corresponding data line, and a second source / drain terminal electrically connected to the first source / drain terminal of the corresponding driving transistor. The first light-emitting control unit includes a first light-emitting control transistor, which includes a control terminal configured to receive the light-emitting control signal, a first source-drain terminal electrically connected to the first voltage terminal, and a second source-drain terminal electrically connected to the first source-drain terminal of the corresponding driving transistor. The second light-emitting control unit includes a second light-emitting control transistor, which includes a control terminal configured to receive the light-emitting control signal, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor, and a second source-drain terminal electrically connected to the anode of the corresponding light-emitting device. The second reset module includes a second reset transistor, which includes a control terminal configured to receive a third gate control signal, a first source / drain terminal electrically connected to a second reset line, and a second source / drain terminal electrically connected to the anode of the light-emitting device. The third reset module includes a third reset transistor, which includes a control terminal configured to receive the third gate control signal, a first source-drain terminal electrically connected to the third reset line, and a second source-drain terminal electrically connected to the first source-drain terminal of the driving transistor. The storage module includes a second capacitor, which is electrically connected between the first voltage terminal and the control terminal of the driving transistor.

14. The display panel according to claim 10, characterized in that, The light-emitting control module is electrically connected between the anode of the light-emitting device and the second source-drain terminal of the driving transistor. The light-emitting control module is configured to control the on / off state of the driving current flow path according to the corresponding light-emitting control signal. The storage module includes a first storage unit and a second storage unit. The first storage unit is electrically connected to the first voltage terminal, and the first storage unit and the second storage unit are electrically connected to a second node. The second storage unit is electrically connected between the second node and the control terminal of the driving transistor. The data writing module is electrically connected between the second node and the data line that transmits the corresponding data signal. The data writing module is configured to control the signal transmission between the second node and the corresponding data line according to the corresponding gating control signal.

15. The display panel according to claim 14, characterized in that, Each of the sub-pixels may further include: The fourth reset module is electrically connected to the second node and is configured to reset the potential of the second node.

16. The display panel according to claim 15, characterized in that, The data writing module includes a data transistor, which includes a control terminal configured to receive the gating control signal, a first source-drain terminal electrically connected to the corresponding data line, and a second source-drain terminal electrically connected to the corresponding second node. The light-emitting control module includes a light-emitting control transistor, which includes a control terminal configured to receive the light-emitting control signal, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor, and a second source-drain terminal electrically connected to the anode of the corresponding light-emitting device. The second reset module includes a second reset transistor, which includes a control terminal configured to receive a third gate control signal, a first source / drain terminal electrically connected to a second reset line, and a second source / drain terminal electrically connected to the anode of the light-emitting device. The fourth reset module includes a fourth reset transistor, which includes a control terminal configured to receive a first gate control signal, a first source-drain terminal electrically connected to a fourth reset line, and a second source-drain terminal electrically connected to the second node. The first storage unit includes a third capacitor, which is electrically connected between the first voltage terminal and the corresponding second node; The second storage unit includes a fourth capacitor, which is electrically connected between the second node and the control terminal of the corresponding driving transistor.

17. A display control method, characterized in that, For a display panel as described in any one of claims 1 to 16, the display control method includes: In the Nth frame, the sub-pixels in the multiple pixel groups are controlled to sequentially enter the corresponding reset phase, so as to reset the potential of the corresponding first node through the first reset module in each sub-pixel; Each sub-pixel is controlled to enter a corresponding compensation phase after the corresponding reset phase, so as to compensate the threshold voltage of the driving transistor of each sub-pixel. Each second sub-pixel is controlled to re-enter the corresponding reset phase after the corresponding compensation phase, so as to reset the potential of the corresponding first node through the first reset module in the second sub-pixel; The driving transistor of each sub-pixel is controlled to generate the driving current in the corresponding light-emitting stage, so as to drive the corresponding light-emitting device to emit light using the driving current; Specifically, during the light-emitting stage corresponding to the first sub-pixel, the control terminal of the driving transistor in the first sub-pixel leaks current with the corresponding first node in a first leakage direction; during the light-emitting stage corresponding to the second sub-pixel, the control terminal of the driving transistor in the second sub-pixel leaks current with the corresponding first node in a second leakage direction, wherein the first leakage direction and the second leakage direction are opposite.

18. The display control method according to claim 17, characterized in that, Also includes: In the N+A frame, the sub-pixels in the multiple pixel groups are controlled to sequentially enter the corresponding reset phase, so as to reset the potential of the corresponding first node through the first reset module in each sub-pixel; where A≥1; Each sub-pixel is controlled to enter a corresponding compensation phase after the corresponding reset phase, so as to compensate the threshold voltage of the driving transistor of each sub-pixel. Each first sub-pixel is controlled to re-enter the corresponding reset phase after the corresponding compensation phase, so as to reset the potential of the corresponding first node through the first reset module in the first sub-pixel; The driving transistor of each sub-pixel is controlled to generate the driving current in the corresponding light-emitting stage, so as to drive the corresponding light-emitting device to emit light using the driving current.

19. The display control method according to claim 17 or 18, characterized in that, Also includes: In the reset phase corresponding to each sub-pixel, which is located before the compensation phase, the potential of the control terminal of the driving transistor is reset by the first reset module and the first switch module.

20. The display control method according to claim 17 or 18, characterized in that, Also includes: Control each sub-pixel to transmit the corresponding data signal to the control terminal of the driving transistor during the corresponding compensation stage or the data writing stage after the compensation stage; Each sub-pixel is controlled to enter the anode reset stage after the corresponding compensation stage or data writing stage, so as to reset the potential of the anode of the light-emitting device; as well as, Each sub-pixel is controlled to enter the light-emitting stage after the corresponding anode reset stage, so as to drive the corresponding light-emitting device to emit light using the driving current generated by the driving transistor.

21. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 16; as well as A source driver, electrically connected to the display panel, is configured to provide corresponding data signals to a plurality of sub-pixels, such that the driving transistor of each sub-pixel generates the driving current according to the corresponding data signal.

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