Pixel circuit and driving method thereof

Abstract

The present application relates to display technical field, especially disclose a kind of pixel circuit and driving method thereof, first switch module and the second switch module are parallel between the second end of the drive module and the first end of the light emitting module, the first initialization module is connected with the first end of the light emitting module, first initialization module according to first scanning signal transmission first initialization signal to the first end of light emitting module, first switch module is according to first scanning signal to turn on or disconnect the connection between the second end of drive module and the first end of light emitting module, second switch module is used to according to light emitting control signal to turn on or disconnect the connection between the second end of drive module and the first end of light emitting module;The level of first scanning signal and the level of light emitting control signal are simultaneously in the on level in the at least part period of time when keeping frame. Above-mentioned pixel circuit, can be used to realize the initialization of the second end of drive module and the first end of light emitting module using first initialization signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method. Background Technology

[0002] With the continuous development of display technology and the increasing demands of consumers for display panels, the functions integrated into display panels are becoming more and more numerous. However, at this stage, the display performance of display panels needs to be improved. Summary of the Invention

[0003] Therefore, it is necessary to provide a pixel circuit and its driving method to address the problems existing in the current pixel circuit.

[0004] A pixel circuit includes a driving module, a first switching module, a second switching module, a first initialization module, and a light-emitting module. The first switching module and the second switching module are connected in parallel between a second terminal of the driving module and a first terminal of the light-emitting module. The first initialization module is connected to the first terminal of the light-emitting module. The first initialization module is used to transmit a first initialization signal to the first end of the light-emitting module according to the first scan signal; The first switch module is used to turn on or off the connection between the second terminal of the driving module and the first terminal of the light-emitting module according to the first scan signal; wherein, the first initialization module and the first switch module have the same turn-on level; The second switch module is used to turn on or off the connection between the second end of the drive module and the first end of the light-emitting module according to the light-emitting control signal; The pixel circuit includes a write frame and a hold frame in one working cycle. The write frame includes a non-light-emitting phase and a light-emitting phase. The level of the first scan signal is on during at least a portion of the non-light-emitting phase, and the level of the light-emitting control signal is kept off during the non-light-emitting phase. The levels of the first scan signal and the light-emitting control signal are simultaneously on during at least a portion of the hold frame.

[0005] In one possible implementation, the non-light-emitting stage includes at least a first initialization stage. In the first initialization stage, the first initialization module transmits the first initialization signal to the first end of the light-emitting module according to the first scan signal, the first switching module turns on the connection between the second end of the driving module and the first end of the light-emitting module according to the first scan signal, and the second switching module turns off according to the light-emitting control signal.

[0006] In one possible implementation, the holding frame includes at least a second initialization phase, in which the first initialization module transmits the first initialization signal to the first end of the light-emitting module according to the first scan signal, the first switching module connects the second end of the driving module and the first end of the light-emitting module according to the first scan signal, and the second switching module is turned on according to the light-emitting control signal.

[0007] In one possible implementation, the pixel circuit further includes a data writing module, a storage module, and a threshold compensation module; The first end of the storage module is connected to the control end of the driver module at a first node, the second end of the storage module is connected to the data writing module at a second node, and the threshold compensation module is connected between the first node and the second end of the driver module. The data writing module is configured to transmit a data signal to the second node according to the second scan signal; the threshold compensation module is configured to control the conduction or disconnection between the first node and the second terminal of the driving module according to the second scan signal; and the storage module is configured to store the threshold-compensated data signal according to the potential changes at the first node and the second node. The driving module is used to output a driving signal based on the signal at the first node.

[0008] In one possible implementation, the driving module includes a first transistor, the gate of the first transistor being connected to the first node as the control terminal of the driving module, the first electrode of the first transistor being connected to a first power line as the first terminal of the driving module, and the second electrode of the first transistor being connected to the threshold compensation module as the second terminal of the driving module.

[0009] In one possible implementation, the data writing module includes a second transistor, the gate of the second transistor being connected to the second scan signal as the control terminal of the data writing module, the first terminal of the second transistor being connected to the data signal as the first terminal of the data writing module, and the second terminal of the second transistor being connected to the second node as the second terminal of the data writing module.

[0010] In one possible implementation, the threshold compensation module includes a third transistor, the gate of which serves as the control terminal of the threshold compensation module and is connected to the second scan signal, the first electrode of which serves as the first terminal of the threshold compensation module and is connected to the first node, and the second electrode of which serves as the second terminal of the threshold compensation module and is connected to the second terminal of the driving module.

[0011] In one possible implementation, the third transistor is a dual-gate transistor, wherein both the first gate and the second gate of the third transistor are connected to the second scan signal. In one possible implementation, the storage module includes a first capacitor, the first terminal of which is connected to the first node as the first end of the storage module, and the second terminal of the second capacitor is connected to the second node as the second end of the storage module.

[0012] In one possible implementation, the first switching module includes a fourth transistor, the gate of which serves as the control terminal of the first switching module and is connected to the first scan signal, the first electrode of which serves as the first terminal of the first switching module and is connected to the second terminal of the driving module, and the second electrode of which serves as the second terminal of the first switching module and is connected to the first terminal of the light-emitting module.

[0013] In one possible implementation, the first initialization module includes a fifth transistor, the gate of which serves as the control terminal of the first initialization module and is connected to the first scan signal, the first electrode of which serves as the first terminal of the first initialization module and is connected to the first initialization signal, and the second electrode of which serves as the second terminal of the first initialization module and is connected to the first terminal of the light-emitting module.

[0014] In one possible implementation, the second switching module includes a sixth transistor, the gate of which serves as the control terminal of the second switching module and is connected to the light emission control signal, the first terminal of which serves as the first terminal of the second switching module and is connected to the second terminal of the driving module, and the second terminal of which serves as the second terminal of the second switching module and is connected to the first terminal of the light emission module.

[0015] In one possible implementation, the pixel circuit further includes: The second initialization module, connected to the second node, is used to transmit the second initialization signal to the second node according to the light emission control signal.

[0016] In one possible implementation, the second initialization module includes a seventh transistor, the gate of which serves as the control terminal of the second initialization module and is connected to the signal, the first terminal of which serves as the first terminal of the second initialization module and is connected to the second initialization signal, and the second terminal of which serves as the second terminal of the second initialization module and is connected to the second node.

[0017] In one possible implementation, the non-light-emitting stage includes at least a first initialization stage. In the first initialization stage, the first initialization module is turned on according to the first scan signal, the first switch module is turned on according to the first scan signal, the data writing module is turned on according to the second scan signal and transmits the data signal to the second node, the threshold compensation module is turned on according to the second scan signal, the second switch module is turned off according to the light-emitting control signal, and the second initialization module is turned off according to the light-emitting control signal.

[0018] In one possible implementation, after the first initialization phase, the non-light-emitting phase includes a threshold compensation phase, in which the first switching module is turned off according to the first scan signal, the first initialization module is turned off according to the first scan signal, the data writing module is turned on according to the second scan signal, the threshold compensation module is turned on according to the second scan signal, the second switching module is turned off according to the light-emitting control signal, and the second initialization module is turned off according to the light-emitting control signal.

[0019] In one possible implementation, after the threshold compensation phase, the write frame includes a light emission phase, in which the first switch module is turned off according to the first scan signal, the first initialization module is turned off according to the first scan signal, the data writing module is turned off according to the second scan signal, the threshold compensation module is turned off according to the second scan signal, the second switch module is turned on according to the light emission control signal, and the second initialization module is turned on according to the light emission control signal.

[0020] In one possible implementation, the hold frame includes at least a second initialization phase. In the second initialization phase, the first initialization module is turned on according to the first scan signal, the first switch module is turned on according to the first scan signal, the data writing module is turned off according to the second scan signal, the threshold compensation module is turned off according to the second scan signal, the second switch module is turned on according to the light emission control signal, and the second initialization module is turned on according to the light emission control signal. In one possible implementation, when the pixel circuit operates in the write frame, the level of the first initialization signal is a first level; when the pixel circuit operates in the hold frame, the level of the first initialization signal is a second level; wherein, the first level is less than zero, the second level is greater than zero, or, the first level is equal to the second level, and the first level is less than zero.

[0021] In one possible implementation, the pixel circuit includes at least one write frame and a plurality of hold frames in one working cycle. When the pixel circuit operates in the write frame, the level of the first initialization signal is a first level. When the pixel circuit operates in at least a portion of the hold frames, the level of the first initialization signal is a first level. When the pixel circuit operates in at least a portion of the hold frames, the level of the first initialization signal is a second level. The first level and the second level are not equal.

[0022] In one possible implementation, the first voltage level is less than zero, and the second voltage level is greater than zero.

[0023] A driving method for a pixel circuit, used to drive a pixel circuit as described in any of the above embodiments, wherein a working cycle of the pixel circuit includes a write frame, the write frame including at least a first initialization stage, a threshold compensation stage, and a light emission stage, the driving method comprising: During the first initialization phase, the level of the first scanning signal is controlled to be on, and the light emission control signal is controlled to be off. During the threshold compensation stage, the level of the first scanning signal is controlled to be at the cutoff level, and the light emission control signal is controlled to be at the cutoff level. During the light emission stage, the level of the first scanning signal is controlled to be at the cutoff level, and the light emission control signal is controlled to be at the on level.

[0024] In one possible implementation, the driving method further includes: During the first initialization phase, the level of the second scan signal is controlled to be on. During the threshold compensation phase, the level of the second scan signal is controlled to be on. During the light emission phase, the level of the second scanning signal is controlled to be at the cutoff level.

[0025] In one possible implementation, the pixel circuit includes a hold frame in one operating cycle, the hold frame including at least a second initialization phase, and the driving method further includes: During the second initialization phase, the first scanning signal is controlled to be at the on level, the second scanning signal is controlled to be at the off level, and the light emission control signal is controlled to be at the on level.

[0026] In one possible implementation, when the pixel circuit operates in the write frame, the level of the first initialization signal is a first level; when the pixel circuit operates in the hold frame, the level of the first initialization signal is a second level; wherein, the first level is less than zero and the second level is greater than zero, or, the first level is equal to the second level and the first level is less than zero. In one possible implementation, the pixel circuit includes at least one write frame and a plurality of hold frames in one working cycle. When the pixel circuit operates in the write frame, the level of the first initialization signal is a first level. When the pixel circuit operates in at least a portion of the hold frames, the level of the first initialization signal is a first level. When the pixel circuit operates in at least a portion of the hold frames, the level of the first initialization signal is a second level. The first level and the second level are not equal.

[0027] In one possible implementation, the first voltage level is less than zero, and the second voltage level is greater than zero. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of one pixel circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application; Figure 3 A schematic diagram of the circuit structure of one pixel circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of this application; Figure 5 A schematic diagram of another pixel circuit structure provided in an embodiment of this application; Figure 6 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the signal timing of a pixel circuit in the write frame and hold frame provided in an embodiment of this application; Figure 8 A schematic diagram of the signal timing of another pixel circuit in the write frame and hold frame provided in an embodiment of this application; Figure 9 This is a schematic diagram of the signal timing of another pixel circuit in the write frame and different holding frames provided in the embodiments of this application; Figure 10 This is a flowchart illustrating the driving method of the pixel circuit in one embodiment of this application. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0033] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0034] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] Figure 1 This is a schematic diagram of the structure of one pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may include a driving module 100, a first switching module 200, a second switching module 300, a first initialization module 400, and a light-emitting module 500. The driving module 100 can be located between the first power line and the light-emitting module 500, and the light-emitting module 500 can be located between the second end of the driving module 100 and the second power line. The first power line can be used to provide a first power signal VDD to the driving module 100, and the second power line can be used to provide a second power signal VSS to the second end of the light-emitting module 500. A first switch module 200 and a second switch module 300 are connected in parallel between the second end of the driving module 100 and the first end of the light-emitting module 500.

[0036] The first switch module 200 can be configured to turn on or off the connection between the second terminal of the drive module 100 and the first terminal of the light-emitting module 500 according to the first scan signal S1. The second switch module 300 can be configured to turn on or off the connection between the second terminal of the drive module 100 and the first terminal of the light-emitting module 500 according to the light-emitting control signal EM. The first initialization module 400 can be connected to the first terminal of the light-emitting module 500, and the first initialization module 400 can be configured to transmit a first initialization signal Vref1 to the first terminal of the light-emitting module 500 according to the first scan signal S1.

[0037] In this embodiment, a first power line is used to transmit a first power signal VDD, and a second power line is used to transmit a second power signal VSS. In one feasible implementation, the first power signal VDD is greater than the second power signal VSS. For example, the first power signal VDD can be a positive voltage, and the second power signal VSS can be a negative voltage.

[0038] In some specific embodiments, the first end of the first switch module 200 can be connected to the second end of the drive module 100. The control end of the first switch module 200 can be connected to the first scan line, which can output a first scan signal S1 to the control end of the first switch module 200. The second end of the first switch module 200 can be connected to the first end of the light-emitting module 500, so that the first switch module 200 can turn on or off the connection between the second end of the drive module 100 and the light-emitting module 500 according to the first scan signal S1.

[0039] The first end of the second switch module 300 can be connected to the second end of the drive module 100. The control end of the second switch module 300 can be connected to the light emission control signal line. The light emission control signal line can output the light emission control signal EM to the control end of the second switch module 300. The second end of the second switch module 300 can be connected to the first end of the light emission module 500. Thus, the second switch module 300 can turn on or off the connection between the second end of the drive module 100 and the first end of the light emission module 500 according to the light emission control signal EM.

[0040] The first terminal of the first initialization module 400 can be connected to a first initialization signal line, which can output a first initialization signal Vref1 to the first terminal of the first initialization module 400. The control terminal of the first initialization module 400 can be connected to a first scan line to receive a first scan signal S1. The second terminal of the first initialization module 400 can be connected to the first terminal of the light-emitting module 500, so that the first initialization module 400 can transmit the first initialization signal Vref1 to the first terminal of the light-emitting module 500 according to the first scan signal S1.

[0041] A pixel circuit can include at least write frames in a single duty cycle, which are display frames that update pixel data. A pixel circuit can also include hold frames in a single duty cycle, which are display frames that do not update but only maintain the current image. The combination of write and hold frames can achieve dynamic refresh rates and reduce power consumption. Specifically, the pixel circuit can operate at different refresh rates. At high refresh rates, each display frame is a write frame; at low refresh rates, at least one display frame can be designed as a write frame, and the others as hold frames. The distinction between high and low refresh rates can be set according to different application requirements. For example, a refresh rate greater than or equal to 120Hz is considered a high refresh rate, and a refresh rate lower than 120Hz is considered a low refresh rate.

[0042] In this embodiment, the write frame may include a non-light-emitting phase and a light-emitting phase. The level of the first scan signal S1 can be configured to be on during at least a portion of the non-light-emitting phase, so that the first switch module 200 and the first initialization module 400 can be turned on according to the first scan signal S1 during at least a portion of the non-light-emitting phase. After the first initialization module 400 is turned on, it transmits the first initialization signal Vref1 to the first terminal of the light-emitting module 500. At the same time, since the first switch module 200 turns on the first terminal of the light-emitting module 500 and the second terminal of the driving module 100, the first initialization signal Vref1 can also be transmitted to the second terminal of the driving module 100. That is, during at least a portion of the non-light-emitting phase, the first initialization signal Vref1 can initialize the first terminal of the light-emitting module 500 and the second terminal of the driving module 100.

[0043] The level of the light emission control signal EM can be configured to remain at the cutoff level during the non-light emission phase. That is, during the non-light emission phase, the second switch module 300 can remain in the cutoff state according to the light emission control signal EM.

[0044] Furthermore, the levels of the first scan signal S1 and the light emission control signal EM can be simultaneously configured to be on during at least a portion of the holding frame. The first switch module 200, the first initialization module 400, and the second switch module 300 can be simultaneously turned on according to the first scan signal S1 and the light emission control signal EM during at least a portion of the holding frame. After the first initialization module 400 is turned on, it transmits the first initialization signal Vref1 to the first terminal of the light emission module 500. Simultaneously, since the first switch module 200 and the second switch module 300 turn on the first terminal of the light emission module 500 and the second terminal of the driving module 100, the first initialization signal Vref1 can also be transmitted to the second terminal of the driving module 100. That is, during at least a portion of the holding frame, the first initialization signal Vref1 can also initialize the first terminal of the light emission module 500 and the second terminal of the driving module 100.

[0045] The pixel circuit provided in this application uses the first initialization signal Vref1 to simultaneously initialize the second end of the driving module 100 and the first end of the light-emitting module 500, eliminating signal residue in the previous frame and avoiding inter-frame potential changes, thereby improving the screen-switching flicker problem and optimizing the display effect.

[0046] With the continuous development of display technology, the demand for high refresh rate products is increasing. Currently, due to the slow charging speed of write-type pixel circuits, they are not suitable for high refresh rate applications. Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a data writing module 600, a storage module 700, and a threshold compensation module 800.

[0047] The first end of the storage module 700 can be connected to the control end of the driver module 100 at the first node N1, and the second end of the storage module 700 can be connected to the data writing module 600 at the second node N2. The threshold compensation module 800 can be connected between the first node N1 and the second end of the driver module 100.

[0048] The data writing module 600 can be configured to transmit the data signal Vdata to the second node N2 according to the second scan signal S2. The threshold compensation module 800 can be configured to turn on or off the connection between the first node N1 and the second terminal of the driving module 100 according to the second scan signal S2. The storage module 700 can be configured to store the threshold-compensated data signal according to the potential changes at the first node N1 and the second node N2. The driving module 100 can output a driving signal according to the signal at the first node N1.

[0049] In some specific implementations, the first end of the data writing module 600 can be connected to a data line, and the data line can output a data signal Vdata to the first end of the data writing module 600. The control end of the data writing module 600 can be connected to a second scan line to receive a second scan signal S2. The second end of the data writing module 600 can be connected to a second node N2, so that the data writing module 600 can transmit the data signal Vdata to the second node N2 according to the control of the second scan signal S2. The first end of the threshold compensation module 800 can be connected to a first node N1. The control end of the threshold compensation module 800 can be connected to a second scan line to receive the second scan signal S2. The second end of the threshold compensation module 800 can be connected to the second end of the driving module 100, so that the threshold compensation module 800 can control the connection or disconnection between the first node N1 and the second end of the driving module 100 according to the second scan signal S2.

[0050] In the pixel circuit provided in this application, the threshold compensation module 800 is connected between the control terminal and the second terminal of the driving module 100. After being turned on according to the second scan signal S2, it can write the threshold information of the driving module 100 into the first node N1. The data writing module 600 transmits the data signal Vdata to the second node N2 after being turned on according to the second scan signal S2, so that the storage module 700 can store the threshold-compensated data signal Vdata. Furthermore, the storage module 700 can instantaneously couple the threshold-compensated data signal Vdata to the control terminal of the driving module 100 through coupling. It is evident that the pixel circuit described above can achieve fast data writing through coupling, making it suitable for high refresh rate products.

[0051] This application proposes a coupled driving scheme suitable for high refresh rate applications. Through the cooperation of the driving module 100, the data writing module 600, the storage module 700, the threshold compensation module 800, and the timing of various input signals, it can not only realize the functions of resetting the devices in the circuit and threshold compensation of the driving module 100, but also be well applied to high refresh rate product applications.

[0052] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0053] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0054] Figure 3 This is a schematic diagram of the circuit structure of one pixel circuit provided in an embodiment of this application. In one possible implementation, the driving module 100 may include a first transistor M1. The gate of the first transistor M1 can be connected to the first node N1 as the control terminal of the driving module 100. The first terminal of the first transistor M1 can be connected to a first power line as the first terminal of the driving module 100. The first power line can output a first power signal VDD to the first terminal of the first transistor M1. The second terminal of the first transistor M1 can be connected to the first terminal of the first switching module 200, the first terminal of the second switching module 300, and the second terminal of the threshold compensation module 800 as the second terminal of the driving module 100.

[0055] In one possible implementation, the data writing module 600 may include a second transistor M2. The gate of the second transistor M2 can be used as the control terminal of the data writing module 600 to connect to the second scan signal S2. The first terminal of the second transistor M2 can be used as the first terminal of the data writing module 600, and the second terminal of the second transistor M2 can be used as the second terminal of the data writing module 600. The gate of the second transistor M2 can be connected to a second scan line to connect to the second scan signal S2. The first terminal of the second transistor M2 can be connected to a data line to connect to the data signal Vdata. The second terminal of the second transistor M2 can be connected to a second node N2.

[0056] In one possible implementation, the threshold compensation module 800 may include a third transistor M3. The gate of the third transistor M3 can serve as the control terminal of the threshold compensation module 800, the first terminal of the third transistor M3 can serve as the first terminal of the threshold compensation module 800, and the second terminal of the third transistor M3 can serve as the second terminal of the threshold compensation module 800. The gate of the third transistor M3 can be connected to a second scan line to receive a second scan signal S2, the first terminal of the third transistor M3 can be connected to a first node N1, and the second terminal of the third transistor M3 can be connected to the second terminal of the driving module 100.

[0057] In one possible implementation, the third transistor M3 can be a dual-gate transistor, with both its first and second gates connected to the second scan signal S2. Dual-gate transistors offer advantages such as a steeper subthreshold swing SS, lower leakage current, and stronger gate control capability, resulting in a more stable compensation point potential and better compensation for the threshold voltage Vth.

[0058] In one possible implementation, the first switching module 200 may include a fourth transistor M4. The gate of the fourth transistor M4 can serve as the control terminal of the first switching module 200, the first electrode of the fourth transistor M4 can serve as the first terminal of the first switching module 200, and the second electrode of the fourth transistor M4 can serve as the second terminal of the first switching module 200. The gate of the fourth transistor M4 can be connected to a first scan line to receive a first scan signal S1, the first electrode of the fourth transistor M4 can be connected to the second terminal of the driving module 100, and the second electrode of the fourth transistor M4 can be connected to the first terminal of the light-emitting module 500.

[0059] In one possible implementation, the first initialization module 400 may include a fifth transistor M5. The gate of the fifth transistor M5 can serve as the control terminal of the first initialization module 400, the first electrode of the fifth transistor M5 can serve as the first terminal of the first initialization module 400, and the second electrode of the fifth transistor M5 can serve as the second terminal of the first initialization module 400. The gate of the fifth transistor M5 can be connected to a first scan line to receive a first scan signal S1. The first electrode of the fifth transistor M5 can be connected to a first initialization signal line, which can transmit a first initialization signal Vref1 to the first electrode of the fifth transistor M5. The second electrode of the fifth transistor M5 can be connected to the first terminal of the light-emitting module 500.

[0060] In one possible implementation, the second switching module 300 may include a sixth transistor M6. The gate of the sixth transistor M6 can serve as the control terminal of the second switching module 300, the first terminal of the sixth transistor M6 can serve as the first terminal of the second switching module 300, and the second terminal of the sixth transistor M6 can serve as the second terminal of the second switching module 300. The gate of the sixth transistor M6 can be connected to a light-emitting control signal line to receive a light-emitting control signal EM. The first terminal of the sixth transistor M6 can be connected to the second terminal of the driving module 100, and the second terminal of the sixth transistor M6 can be connected to the first terminal of the light-emitting module 500.

[0061] In one possible implementation, the light-emitting module 500 may include a light-emitting diode (OLED) D1. The OLED (Organic Light-Emitting Diode) may include an anode and a cathode. The anode of the OLED D1, serving as the first terminal of the light-emitting module 500, can be connected to the second terminals of the first switching module 200, the second switching module 300, and the first initialization module 400. The cathode of the OLED D1, serving as the second terminal of the light-emitting module 500, can be connected to a second power supply line. When a driving signal output by the driving module 100 is transmitted to the OLED D1, the OLED D1 can emit light with a brightness corresponding to the driving signal.

[0062] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a second initialization module 900. The second initialization module 900 may be connected to the second node N2, and the second initialization module 900 may be configured to transmit a second initialization signal Vref2 to the second node N2 according to the light emission control signal EM. In some embodiments, the first end of the second initialization module 900 may be connected to a second initialization signal line, and the second initialization signal line may output the second initialization signal Vref2 to the first end of the second initialization module 900. The control end of the second initialization module 900 may be connected to the light emission control signal line, and the light emission control signal line may output the light emission control signal EM to the control end of the second initialization module 900. The second end of the second initialization module 900 may be connected to the second node N2, so that the second initialization module 900 may transmit the second initialization signal Vref2 to the second node N2 according to the light emission control signal EM.

[0063] Figure 5This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. In one possible implementation, the second initialization module 900 may include a seventh transistor M7. The gate of the seventh transistor M7 can serve as the control terminal of the second initialization module 900, the first terminal of the seventh transistor M7 can serve as the first terminal of the second initialization module 900, and the second terminal of the seventh transistor M7 can serve as the second terminal of the second initialization module 900. The gate of the seventh transistor M7 can be connected to the light emission control signal line to receive the light emission control signal EM, the first terminal of the seventh transistor M7 can be connected to the second initialization signal line to receive the second initialization signal Vref2, and the second terminal of the seventh transistor M7 can be connected to the second node N2.

[0064] Figure 5 The pixel circuit shown is a 7T1C structure, in which the first transistor M1 is a DTFT (Driver Thin Film Transistor), and the remaining transistors are all STFTs (Switch Thin Film Transistors). All seven transistors can also be P-type transistors.

[0065] Coupled-type circuits can instantaneously couple data signals to the gate of the driving transistor, thus allowing for greater use of coupled-type pixel circuits in high refresh rate applications. However, during frame switching (such as switching from high frequency to low frequency or vice versa), pixel circuits may experience screen flicker (i.e., unexpected brightness jumps) due to sudden changes in node potential.

[0066] In related technologies, high refresh rate products using coupling circuits typically require additional signal lines and transistors on top of the 7T1C to solve the screen flicker problem, resulting in insufficient layout space. However, the pixel circuit provided in this application improves the screen flicker problem by simultaneously initializing the second terminal and control terminal of the driving module 100 using the first initialization signal Vref1 and the second initialization signal Vref2, eliminating signal residue from the previous frame and avoiding inter-frame potential abrupt changes. Furthermore, compared to related technologies, the pixel circuit provided in this application does not add additional TFTs and signal lines, which is more conducive to layout design.

[0067] The first terminal of the second transistor M2 is connected to the data signal Vdata. The second terminal of the second transistor M2 is connected to the second terminal of the seventh transistor M7 and the second terminal of the first capacitor C1 at the second node N2. The first terminal of the seventh transistor M7 is connected to the second initialization signal Vref2. The gate of the first transistor M1 is connected to the first terminal of the third transistor M3 and the first terminal of the first capacitor C1 at the first node N1. The first terminal S of the first transistor M1 is connected to the first power supply line. The second terminal D of the first transistor M1 is connected to the second terminals of the third transistor M3, the fourth transistor M4, and the sixth transistor M6. The gates of the second transistor M2 and the third transistor M3 are both connected to the second scan signal S2. The second terminals of the fourth transistor M4, the sixth transistor M6, and the fifth transistor M5 are all connected to the anode of the light-emitting diode D1. The cathode of the light-emitting diode D1 is connected to the second power supply line to receive the second power supply signal VSS. The first terminal of the fifth transistor M5 is connected to the first initialization signal Vref1. The gates of the fourth transistor M4 and the fifth transistor M5 are both connected to the first scan signal S1, and the gates of the seventh transistor M7 and the sixth transistor M6 are both connected to the light emission control signal EM.

[0068] In one possible implementation, the pixel circuit may include at least a write frame in one operating cycle, which is a display frame that updates the pixel data. The operation of one display frame may include a first initialization phase t1, a threshold compensation phase t2, and an emission phase t3.

[0069] Figure 6 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in one embodiment of this application. It can be applied to, for example... Figure 5 The pixel circuit shown in this embodiment is combined with Figure 5 and Figure 6 The operation of a pixel circuit provided in one embodiment of this application will be described in detail, but this should not be construed as limiting the scope of the invention. In this embodiment, the transistors in the pixel circuit are all P-type transistors, therefore the on-level is low and the off-level is high.

[0070] In the first initialization phase t1, the level of the first scan signal S1 can be a conducting level, and the level of the second scan signal S2 can also be a conducting level. The second transistor M2 and the third transistor M3 are turned on according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are turned on according to the first scan signal S1. Additionally, the level of the light emission control signal EM can be a cutoff level, and the sixth transistor M6 and the seventh transistor M7 are turned off according to the light emission control signal EM.

[0071] In the first initialization phase t1, the data signal Vdata is transmitted to the second node N2 through the second transistor M2, and the potential at N2 is VN2 = Vdata. The first initialization signal Vref1 is transmitted to the anode of the light-emitting diode D1 through the fifth transistor M5, thus initializing the anode of the light-emitting diode D1. It is then transmitted to the drain D of the first transistor M1 through the fourth transistor M4, and also to the first node N1 through the third transistor M3. That is, the gate G, drain D of the first transistor M1, and the anode of the light-emitting diode D1 are all reset by the first initialization signal Vref1, and the potentials at points G and D are VG = VD = Vref1.

[0072] In one possible implementation, after the first initialization phase t1, the frame writing phase may include a threshold compensation phase t2. In the threshold compensation phase t2, the level of the first scan signal S1 may be a cutoff level, and the level of the second scan signal S2 may be a conduction level. The second transistor M2 and the third transistor M3 are turned on according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are turned off according to the first scan signal S1. Additionally, the level of the light emission control signal EM may be a cutoff level, and the sixth transistor M6 and the seventh transistor M7 are turned off according to the light emission control signal EM.

[0073] During the threshold compensation phase t2, the second transistor M2 continuously transmits the data voltage Vdata to the second node N2, and the potential at the second node N2 remains VN2 = Vdata. The first transistor M1 is in a conducting state according to the signal at its control terminal. Therefore, the first power supply voltage VDD is transmitted sequentially through the first transistor M1 and the third transistor M3 to the first node N1, charging the first node N1. The potential at the first node N1 gradually rises until it reaches the critical turn-off condition of the first transistor M1, that is, the potential at the first node N1 is adjusted to VN1 = VDD + Vth. At this time, the first transistor M1 turns off, and Vh is the threshold voltage of the first transistor M1. It can be seen that the threshold information of the first transistor M1 (i.e., the driving transistor) is written to the first node N1. At this time, the voltage difference across the first capacitor C1 is VDD + Vth - Vdata.

[0074] In one possible implementation, after the threshold compensation phase t2, the write frame may include a light emission phase t3. In the light emission phase t3, the levels of the first scan signal S1 and the second scan signal S2 can be off levels. The second transistor M2 and the third transistor M3 are off according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are off according to the first scan signal S1. Additionally, the level of the light emission control signal EM can be on level, and the sixth transistor M6 and the seventh transistor M7 are on according to the light emission control signal EM.

[0075] During the light-emitting phase t3, the second initialization signal Vref2 is transmitted to the second node N2 through the seventh transistor M7. That is, the potential at the second node N2 changes from Vdata to Vref2. At this time, the first terminal of the first capacitor C1 is in a floating-point state, and the potential at the first terminal of the first capacitor C1 (first node N1) will change with the potential change at the second terminal (second node N2), i.e., the voltage change at the second node N2 is Vdata. Vref2 will be coupled to the first node N1 by the first capacitor C1, that is, the potential at the first node N1 will jump to VN1=VDD+Vth+Vref2-Vdata. It can be seen that during the light emission stage t3, the storage module 700 can instantly transmit the data signal after threshold compensation to the control terminal of the driver module 100.

[0076] After the first capacitor C1 completes the data writing, the first transistor M1 can generate a drive signal based on its gate and source voltages. The drive current output by the first transistor M1 is: ID= (1 / 2)μ*cox*(W / L)* (Vgs-Vth) 2 Where μ is the electron mobility of the first transistor M1, cox is the channel capacitance per unit area of ​​the first transistor M1, W / L is the aspect ratio of the first transistor M1, and Vth is the threshold voltage of the first transistor M1.

[0077] The gate voltage of the first transistor M1 is VG = VDD + Vth + Vref² - Vdata, and the source voltage of the first transistor M1 is VS = VDD. That is, the voltage difference between the gate and source of the first transistor M1 is Vgs = Vth + Vref² - Vdata. Therefore, Vgs - Vth = Vref² - Vdata, meaning the driving current is a function of (Vref² - Vdata). This function does not include VDD, VSS, or Vth. It is evident that the driving current output by this pixel circuit is not affected by the differences in VDD, VSS, and Vth at different locations on the display panel, indicating good compensation for VDD, VSS, and Vth.

[0078] The drive current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1 through the sixth transistor M6, so that the light-emitting diode D1 emits light according to the drive current ID.

[0079] The aforementioned pixel circuit utilizes a threshold compensation module 800 to write the threshold information of the driving module 100 into the first node N1. The storage module 700 stores the threshold-compensated data signal based on the potential changes at the terminals of the first node N1 and the second node N2. During the light-emitting stage t3, the storage module 700 can instantaneously couple the data signal to the control terminal of the driving module 100, thus enabling wider application in high refresh rate applications. Simultaneously, the first initialization signal Vref1 and the second initialization signal Vref2 can initialize both the second terminal and the control terminal of the driving module 100, eliminating signal residue from the previous frame and preventing inter-frame potential abrupt changes, thereby improving the screen-switching flicker problem. Furthermore, the pixel circuit provided in this embodiment does not add additional TFTs and signal lines compared to related technologies, which is more beneficial for layout design.

[0080] Figure 7 This is a schematic diagram of the signal timing of a pixel circuit in the write frame and hold frame provided in an embodiment of this application, which can be applied to, for example... Figure 5 The pixel circuit shown in this embodiment is combined with Figure 5 and Figure 7 The operation of a pixel circuit provided in one embodiment of this application will be described in detail, but this should not be construed as limiting the scope of the invention. In this embodiment, the transistors in the pixel circuit are all P-type transistors, therefore the on-level is low and the off-level is high.

[0081] The hold frame may include at least a second initialization phase t4, in which the level of the second scan signal S2 may be a cutoff level, and the level of the first scan signal S1 may be a conduction level. The second transistor M2 and the third transistor M3 are cut off according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are turned on according to the first scan signal S1. Additionally, the level of the light emission control signal EM may be a conduction level, and the seventh transistor M7 and the sixth transistor M6 are turned on according to the light emission control signal EM.

[0082] In the second initialization phase t4, the first initialization signal Vref1 is first transmitted to the anode of LED D1 through the fifth transistor M5 to initialize the anode of LED D1, and then transmitted to the drain D of the first transistor M1 through the fourth transistor M4. That is, both the drain D of the first transistor M1 and the anode of LED D1 are reset by the first initialization signal Vref1, and the potentials of the anode and point D of LED D1 are both Vref1.

[0083] In one possible implementation, the holding frame may further include a light-emitting phase, during which the levels of the second scan signal S2 and the first scan signal S1 can be off levels. The second transistor M2 and the third transistor M3 are off according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are off according to the first scan signal S1. Additionally, the level of the light-emitting control signal EM can be on level, and the seventh transistor M7 and the sixth transistor M6 are on according to the light-emitting control signal EM. The first transistor M1 outputs a drive current based on the voltage at its gate and source. The drive current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1 through the sixth transistor M6, thereby causing the light-emitting diode D1 to emit light according to the drive current ID.

[0084] In one possible implementation, please refer to Figure 7 When the pixel circuit operates in the write frame, the level of the first initialization signal Vref1 is the first level V1; when the pixel circuit operates in the hold frame, the level of the first initialization signal Vref1 is the second level V2, where the first level V1 is less than the second level V2. Specifically, the first level V1 can be less than zero, and the second level V2 can be greater than zero, that is, the first level V1 can be low, and the second level V2 can be high. In the second initialization stage t4 of the hold frame, the high-level first initialization signal Vref1 is transmitted to the anode of the light-emitting diode D1 through the fifth transistor M5, and to the second terminal of the first transistor M1 through the fourth transistor M4, resetting the anode of the light-emitting diode D1 and the second terminal of the first transistor M1 to the high level V2, thereby resetting the anode of the light-emitting diode D1 and the second terminal D of the first transistor M1 and improving the screen flicker problem.

[0085] In some other implementations, Figure 8 This is a signal timing diagram of another pixel circuit provided in an embodiment of this application during the write frame and hold frame. The first level V1 is equal to the second level V2, and both the first level V1 and the second level V2 are less than zero. That is, when the pixel circuit is operating in the write frame and hold frame, the level of the first initialization signal Vref1 is low. In the second initialization stage t4 of the hold frame, the low-level first initialization signal Vref1 is transmitted to the second terminal of the first transistor M1. Since the second terminal of the first transistor M1 is reset in each write frame at various frequencies, the screen flicker problem can also be reduced.

[0086] In one possible implementation, Figure 9This is a schematic diagram of the signal timing of a pixel circuit in a write frame and different holding frames, provided in an embodiment of this application. When the pixel circuit is working in a write frame, the level of the first initialization signal Vref1 is maintained at the first level V1. When the pixel circuit is working in at least a partially holding frame, the level of the first initialization signal Vref1 is the first level V1. When the pixel circuit is working in at least a partially holding frame, the level of the first initialization signal Vref1 is the second level V2. The first level V1 and the second level V2 are not equal.

[0087] In one possible implementation, the first level V1 is less than the second level V2, and the first level V1 can be less than zero, while the second level V2 can be greater than zero, that is, the first level V1 is a low potential and the second level V2 is a high potential.

[0088] By setting the first initialization signal Vref1 to a high level during some hold frames and a low level during others, the high-level first initialization signal Vref1 during some hold frames can effectively initialize the second electrode of the first transistor M1, thus solving the screen flickering problem. The low-level first initialization signal Vref1 during some hold frames can effectively initialize the anode of the light-emitting diode D1, preventing the LED D1 from exhibiting a black-to-bright AOD (Always On Display) issue.

[0089] In practical applications, the first initialization signal Vref1 can be designed as different alternating signals to achieve different functions, depending on the specific circuit requirements. For example, when the pixel circuit is operating in a hold frame, the first initialization signal Vref1 outputs an alternating signal in a mode where the level alternates between high and low; or, the first initialization signal Vref1 outputs an alternating signal in a mode where it is high in two hold frames and low in one hold frame; or, the first initialization signal Vref1 continuously operates in a mode where it is high in the first hold frame and low in the second hold frame for a certain period of time, and then remains high in the remaining hold frames where the circuit state is stable.

[0090] This invention also provides a display panel that may include the pixel circuits described in any of the above embodiments. The display panel may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0091] This invention also provides a display device, which may include the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0092] The present invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments. The pixel circuit may include a first initialization stage t1, a threshold compensation stage t2, and an emission stage t3 during the operation of a display frame. Figure 10 This is a flowchart illustrating a pixel circuit driving method in one embodiment of the present application. In one possible implementation, the pixel circuit driving method may include the following steps S100 to S300.

[0093] Step S100: In the first initialization phase, the level of the first scanning signal is controlled to be on, and the light emission control signal is controlled to be off.

[0094] At the first initialization node t1, the level of the first scan signal S1 can be a conducting level, and the level of the light emission control signal EM can be a cut-off level. The fourth transistor M4 and the fifth transistor M5 are turned on according to the first scan signal S1, while the seventh transistor M7 and the sixth transistor M6 are turned off according to the light emission control signal EM. The first initialization signal Vref1 is transmitted through the fifth transistor M5 to the anode of the light-emitting diode D1, thus initializing the anode of D1. It is then transmitted through the fourth transistor M4 to the drain D of the first transistor M1, also initializing the drain D of the first transistor M1.

[0095] In one possible implementation, during the first initialization phase t1, the level of the second scan signal S2 can be an on level, and the second transistor M2 and the third transistor M3 are turned on according to the second scan signal S2. The second transistor M2 transmits the data signal Vdata to the second node N2. Simultaneously, since the third transistor M3 connects the first node N1 and the second terminal of the first transistor M1, the first initialization signal Vref1 can also be transmitted to the first node N1 through the third transistor M3. That is, the gate G, drain D of the first transistor M1, and the anode of the light-emitting diode D1 are all reset by the first initialization signal Vref1, and the potentials at points G and D are VG=VD=Vref1.

[0096] Step S200: During the threshold compensation stage, the level of the first scanning signal is controlled to be at the cutoff level, and the light emission control signal is controlled to be at the cutoff level.

[0097] During the threshold compensation stage t2, the level of the first scan signal S1 can be a cutoff level, and the level of the light emission control signal EM can be a cutoff level. The fourth transistor M4 and the fifth transistor M5 are cut off according to the first scan signal S1, and the seventh transistor M7 and the sixth transistor M6 are cut off according to the light emission control signal EM.

[0098] In one possible implementation, during the threshold compensation stage t2, the level of the second scan signal S2 can be an on level, and the second transistor M2 and the third transistor M3 are turned on according to the second scan signal S2. The second transistor M2 transmits the data signal Vdata to the second node N2, and the third transistor M3 turns on the connection between the first node N1 and the second terminal of the first transistor M1.

[0099] During the threshold compensation phase t2, the potential at the second node N2 remains VN2 = Vdata. The first transistor M1 is in a conducting state according to the signal at its control terminal. The first power supply voltage VDD is transmitted sequentially through the first transistor M1 and the third transistor M3 to the first node N1, charging it. The potential at the first node N1 gradually rises until it reaches the critical turn-off condition of the first transistor M1, i.e., the potential at the first node N1 is adjusted to VN1 = VDD + Vth. At this time, the first transistor M1 turns off, and Vh is the threshold voltage of the first transistor M1. It can be seen that the threshold information of the first transistor M1 (i.e., the driving transistor) is written into the first node N1. At this time, the voltage difference across the first capacitor C1 is VDD + Vth - Vdata.

[0100] Step S300: During the light emission stage, the level of the first scanning signal is controlled to be cut off, and the light emission control signal is controlled to be on.

[0101] During the light-emitting stage t3, the level of the first scan signal S1 can be a cutoff level, and the level of the light-emitting control signal EM can be a conduction level. The fourth transistor M4 and the fifth transistor M5 are cut off according to the first scan signal S1, and the seventh transistor M7 and the sixth transistor M6 are turned on according to the light-emitting control signal EM.

[0102] In one possible implementation, during the light emission stage t3, the level of the second scan signal S2 can be a cutoff level, and the second transistor M2 and the third transistor M3 are turned off according to the second scan signal S2.

[0103] During the light-emitting phase t3, the second initialization signal Vref2 is transmitted to the second node N2 through the seventh transistor M7. That is, the potential at the second node N2 changes from Vdata to Vref2. At this time, the first terminal of the first capacitor C1 is in a floating-point state, and the potential at the first terminal of the first capacitor C1 (first node N1) will change with the potential change at the second terminal (second node N2), i.e., the voltage change at the second node N2 is Vdata. Vref2 will be coupled to the first node N1 by the first capacitor C1, that is, the potential at the first node N1 will jump to VN1=VDD+Vth+Vref2-Vdata. It can be seen that during the light emission stage t3, the storage module 700 can instantly transmit the data signal after threshold compensation to the control terminal of the driver module 100.

[0104] After the first capacitor C1 completes the data writing, the first transistor M1 can generate a drive signal based on its gate and source voltages. The drive current output by the first transistor M1 is: ID= (1 / 2)μ*cox*(W / L)* (Vgs-Vth) 2 Where μ is the electron mobility of the first transistor M1, cox is the channel capacitance per unit area of ​​the first transistor M1, W / L is the aspect ratio of the first transistor M1, and Vth is the threshold voltage of the first transistor M1.

[0105] The gate voltage of the first transistor M1 is VG = VDD + Vth + Vref² - Vdata, and the source voltage of the first transistor M1 is VS = VDD. That is, the voltage difference between the gate and source of the first transistor M1 is Vgs = Vth + Vref² - Vdata. Therefore, Vgs - Vth = Vref² - Vdata, meaning the driving current is a function of (Vref² - Vdata). This function does not include VDD, VSS, or Vth. It is evident that the driving current output by this pixel circuit is not affected by the differences in VDD, VSS, and Vth at different locations on the display panel, indicating good compensation for VDD, VSS, and Vth. The driving current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1 through the sixth transistor M6, causing the light-emitting diode D1 to emit light according to the driving current ID.

[0106] When the driving method of the pixel circuit described above is applied to the pixel circuit, the third transistor M3 writes the threshold information of the first transistor M1 into the first node N1 during the threshold compensation stage t2. The first capacitor C1 can store the threshold-compensated data signal according to the potential changes at the first node N1 and the second node N2. At the same time, during the light emission stage t3, the first capacitor C1 can instantaneously couple the data signal to the gate of the first transistor M1. Therefore, the pixel circuit and its driving method are more suitable for high refresh rate product applications. Meanwhile, during the first initialization stage t1, the fifth transistor M5 transmits the first initialization signal Vref1 to the pixel circuit, which can simultaneously initialize the second electrode and gate of the first transistor M1 and the anode of the light-emitting diode D1 to eliminate signal residue from the previous frame, avoid inter-frame potential abrupt changes, and thus improve the screen flicker problem.

[0107] In one possible implementation, the pixel circuit may further include a hold frame during one operating cycle. The hold frame may include at least a second initialization phase t4, in which the level of the second scan signal S2 may be off, and the level of the first scan signal S1 may be on. The second transistor M2 and the third transistor M3 are off according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are on according to the first scan signal S1. Additionally, the level of the light emission control signal EM may be on, and the seventh transistor M7 and the sixth transistor M6 are on according to the light emission control signal EM.

[0108] In the second initialization phase t4, the first initialization signal Vref1 is first transmitted to the anode of LED D1 through the fifth transistor M5 to initialize the anode of LED D1, and then transmitted to the drain D of the first transistor M1 through the fourth transistor M4. That is, both the drain D of the first transistor M1 and the anode of LED D1 are reset by the first initialization signal Vref1, and the potentials of the anode and point D of LED D1 are both Vref1.

[0109] In one possible implementation, the holding frame may further include a light-emitting phase, during which the levels of the second scan signal S2 and the first scan signal S1 can be off levels. The second transistor M2 and the third transistor M3 are off according to the second scan signal S2, and the fourth transistor M4 and the fifth transistor M5 are off according to the first scan signal S1. Additionally, the level of the light-emitting control signal EM can be on level, and the seventh transistor M7 and the sixth transistor M6 are on according to the light-emitting control signal EM. The first transistor M1 outputs a drive current based on the voltage at its gate and source. The drive current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1 through the sixth transistor M6, thereby causing the light-emitting diode D1 to emit light according to the drive current ID.

[0110] In one possible implementation, please refer to Figure 7 When the pixel circuit operates in the write frame, the level of the first initialization signal Vref1 is the first level V1; when the pixel circuit operates in the hold frame, the level of the first initialization signal Vref1 is the second level V2, where the first level V1 is less than the second level V2. Specifically, the first level V1 can be less than zero, and the second level V2 can be greater than zero, that is, the first level V1 can be low, and the second level V2 can be high. In the second initialization stage t4 of the hold frame, the high-level first initialization signal Vref1 is transmitted to the anode of the light-emitting diode D1 through the fifth transistor M5, and to the second terminal of the first transistor M1 through the fourth transistor M4, resetting the anode of the light-emitting diode D1 and the second terminal of the first transistor M1 to the high-level Vref1, thereby resetting the anode of the light-emitting diode D1 and the second terminal D of the first transistor M1 and improving the screen flicker problem.

[0111] For some other implementations, please refer to Figure 8 The first level V1 is equal to the second level V2, and both the first level V1 and the second level V2 are less than zero. That is, when the pixel circuit is operating in the write frame and the hold frame, the level of the first initialization signal Vref1 is low. In the second initialization stage t4 of the hold frame, the low-level first initialization signal Vref1 is transmitted to the second terminal of the first transistor M1. Since the second terminal of the first transistor M1 is reset in each write frame at each frequency, the screen switching flicker problem can also be reduced.

[0112] In one possible implementation, please refer to Figure 9 When the pixel circuit operates in the write frame mode, the level of the first initialization signal Vref1 remains at the first level V1. When the pixel circuit operates in at least the partially held frame mode, the level of the first initialization signal Vref1 is the first level V1, and the level of the first initialization signal Vref1 is the second level V2, wherein the first level V1 and the second level V2 are not equal. In one possible implementation, the first level V1 is less than the second level V2, and the first level V1 may be less than zero, while the second level V2 may be greater than zero; that is, the first level V1 is a low potential, and the second level V2 is a high potential.

[0113] By setting the first initialization signal Vref1 to a high level during some hold frames and a low level during others, the high level of Vref1 during some hold frames allows for effective initialization of the second electrode of the first transistor M1, thus resolving the screen flickering issue. Conversely, the low level of Vref1 during some hold frames allows for effective initialization of the anode of the light-emitting diode D1, which can lead to a problem where the AOD (Ambient Light Discharge) appears too bright.

[0114] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0115] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, The system includes a driver module, a first switch module, a second switch module, a first initialization module, and a light-emitting module. The first switch module and the second switch module are connected in parallel between the second terminal of the driver module and the first terminal of the light-emitting module. The first initialization module is connected to the first terminal of the light-emitting module. The first initialization module is used to transmit a first initialization signal to the first end of the light-emitting module according to the first scan signal; The first switch module is used to turn on or off the connection between the second terminal of the driving module and the first terminal of the light-emitting module according to the first scan signal; wherein, the first initialization module and the first switch module have the same turn-on level; The second switch module is used to turn on or off the connection between the second end of the drive module and the first end of the light-emitting module according to the light-emitting control signal; The pixel circuit includes a write frame and a hold frame in one working cycle. The write frame includes a non-light-emitting phase and a light-emitting phase. The level of the first scan signal is on during at least a portion of the non-light-emitting phase, and the level of the light-emitting control signal is kept off during the non-light-emitting phase. The levels of the first scan signal and the light-emitting control signal are simultaneously on during at least a portion of the hold frame.

2. The pixel circuit according to claim 1, characterized in that, The non-light-emitting stage includes at least a first initialization stage. In the first initialization stage, the first initialization module transmits the first initialization signal to the first end of the light-emitting module according to the first scan signal. The first switching module turns on the connection between the second end of the driving module and the first end of the light-emitting module according to the first scan signal. The second switching module turns off according to the light-emitting control signal. Preferably, the holding frame includes at least a second initialization phase. In the second initialization phase, the first initialization module transmits the first initialization signal to the first end of the light-emitting module according to the first scan signal, the first switching module connects the second end of the driving module and the first end of the light-emitting module according to the first scan signal, and the second switching module is turned on according to the light-emitting control signal.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a data writing module, a storage module, and a threshold compensation module; The first end of the storage module is connected to the control end of the driver module at a first node, the second end of the storage module is connected to the data writing module at a second node, and the threshold compensation module is connected between the first node and the second end of the driver module. The data writing module is configured to transmit a data signal to the second node according to the second scan signal; the threshold compensation module is configured to control the conduction or disconnection between the first node and the second terminal of the driving module according to the second scan signal; and the storage module is configured to store the threshold-compensated data signal according to the potential changes at the first node and the second node. The driving module is used to output a driving signal based on the signal at the first node.

4. The pixel circuit according to claim 3, characterized in that, The driving module includes a first transistor, the gate of the first transistor is connected to the first node as the control terminal of the driving module, the first electrode of the first transistor is connected to the first power line as the first terminal of the driving module, and the second electrode of the first transistor is connected to the threshold compensation module as the second terminal of the driving module. Preferably, the data writing module includes a second transistor, the gate of the second transistor serves as the control terminal of the data writing module and is connected to the second scan signal, the first electrode of the second transistor serves as the first terminal of the data writing module and is connected to the data signal, and the second electrode of the second transistor serves as the second terminal of the data writing module and is connected to the second node. Preferably, the threshold compensation module includes a third transistor, the gate of the third transistor is connected to the second scan signal as the control terminal of the threshold compensation module, the first electrode of the third transistor is connected to the first node as the first terminal of the threshold compensation module, and the second electrode of the third transistor is connected to the second terminal of the driving module as the second terminal of the threshold compensation module. Preferably, the third transistor is a dual-gate transistor, and both the first gate and the second gate of the third transistor are connected to the second scan signal; Preferably, the storage module includes a first capacitor, the first terminal of the first capacitor being connected to the first node as the first end of the storage module, and the second terminal of the second capacitor being connected to the second node as the second end of the storage module; the first switching module includes a fourth transistor, the gate of the fourth transistor being connected to the first scan signal as the control terminal of the first switching module, the first terminal of the fourth transistor being connected to the second end of the driving module as the first end of the first switching module, and the second terminal of the fourth transistor being connected to the first end of the light-emitting module as the second end of the first switching module; Preferably, the first initialization module includes a fifth transistor, the gate of the fifth transistor is connected to the first scan signal as the control terminal of the first initialization module, the first electrode of the fifth transistor is connected to the first initialization signal as the first terminal of the first initialization module, and the second electrode of the fifth transistor is connected to the first terminal of the light-emitting module as the second terminal of the first initialization module. The second switching module includes a sixth transistor. The gate of the sixth transistor serves as the control terminal of the second switching module and is connected to the light emission control signal. The first electrode of the sixth transistor serves as the first terminal of the second switching module and is connected to the second terminal of the driving module. The second electrode of the sixth transistor serves as the second terminal of the second switching module and is connected to the first terminal of the light emission module.

5. The pixel circuit according to claim 2 or 3, characterized in that, The pixel circuit also includes: The second initialization module is connected to the second node and is used to transmit the second initialization signal to the second node according to the light emission control signal; Preferably, the second initialization module includes a seventh transistor, the gate of the seventh transistor is connected to the signal as the control terminal of the second initialization module, the first terminal of the seventh transistor is connected to the second initialization signal as the first terminal of the second initialization module, and the second terminal of the seventh transistor is connected to the second node as the second terminal of the second initialization module.

6. The pixel circuit according to claim 5, characterized in that, The non-light-emitting stage includes at least a first initialization stage. In the first initialization stage, the first initialization module is turned on according to the first scan signal, the first switch module is turned on according to the first scan signal, the data writing module is turned on according to the second scan signal and transmits the data signal to the second node, the threshold compensation module is turned on according to the second scan signal, the second switch module is turned off according to the light-emitting control signal, and the second initialization module is turned off according to the light-emitting control signal. Preferably, after the first initialization stage, the non-light-emitting stage includes a threshold compensation stage, in which the first switching module is turned off according to the first scan signal, the first initialization module is turned off according to the first scan signal, the data writing module is turned on according to the second scan signal, the threshold compensation module is turned on according to the second scan signal, the second switching module is turned off according to the light-emitting control signal, and the second initialization module is turned off according to the light-emitting control signal. Preferably, after the threshold compensation stage, the write frame includes a light emission stage, in which the first switch module is turned off according to the first scan signal, the first initialization module is turned off according to the first scan signal, the data writing module is turned off according to the second scan signal, the threshold compensation module is turned off according to the second scan signal, the second switch module is turned on according to the light emission control signal, and the second initialization module is turned on according to the light emission control signal. Preferably, the holding frame includes at least a second initialization phase, in which the first initialization module is turned on according to the first scan signal, the first switch module is turned on according to the first scan signal, the data writing module is turned off according to the second scan signal, the threshold compensation module is turned off according to the second scan signal, the second switch module is turned on according to the light emission control signal, and the second initialization module is turned on according to the light emission control signal.

7. The pixel circuit according to claim 1, characterized in that, When the pixel circuit operates in the write frame, the level of the first initialization signal is a first level; when the pixel circuit operates in the hold frame, the level of the first initialization signal is a second level; wherein, the first level is less than zero and the second level is greater than zero, or, the first level is equal to the second level and the first level is less than zero.

8. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes at least one write frame and multiple hold frames in one working cycle. When the pixel circuit operates in the write frame, the level of the first initialization signal is a first level. When the pixel circuit operates in at least some of the hold frames, the level of the first initialization signal is a first level. When the pixel circuit operates in at least some of the hold frames, the level of the first initialization signal is a second level. The first level and the second level are not equal. Preferably, the first voltage level is less than zero, and the second voltage level is greater than zero.

9. A driving method for a pixel circuit, characterized in that, The driving method is used to drive a pixel circuit as described in any one of claims 1 to 8, wherein a write frame is included in one operating cycle of the pixel circuit, and the write frame includes at least a first initialization phase, a threshold compensation phase, and a light emission phase. During the first initialization phase, the level of the first scanning signal is controlled to be on, and the light emission control signal is controlled to be off. During the threshold compensation stage, the level of the first scanning signal is controlled to be at the cutoff level, and the light emission control signal is controlled to be at the cutoff level. During the light emission stage, the level of the first scanning signal is controlled to be at the cutoff level, and the light emission control signal is controlled to be at the on level.

10. The driving method for the pixel circuit according to claim 9, characterized in that, The driving method further includes: During the first initialization phase, the level of the second scan signal is controlled to be on. During the threshold compensation phase, the level of the second scan signal is controlled to be on. During the light emission phase, the level of the second scanning signal is controlled to be at the cutoff level; Preferably, the pixel circuit includes a holding frame in one operating cycle, the holding frame including at least a second initialization phase, and the driving method further includes: In the second initialization phase, the first scanning signal is controlled to be at the on level, the second scanning signal is controlled to be at the off level, and the light emission control signal is controlled to be at the on level. Preferably, when the pixel circuit operates in the write frame, the level of the first initialization signal is a first level; when the pixel circuit operates in the hold frame, the level of the first initialization signal is a second level; wherein, the first level is less than zero and the second level is greater than zero, or, the first level is equal to the second level and the first level is less than zero; Preferably, the pixel circuit includes at least one write frame and multiple hold frames in one working cycle. When the pixel circuit operates in the write frame, the level of the first initialization signal is a first level. When the pixel circuit operates in at least some of the hold frames, the level of the first initialization signal is a first level. When the pixel circuit operates in at least some of the hold frames, the level of the first initialization signal is a second level. The first level and the second level are not equal. Preferably, the first voltage level is less than zero, and the second voltage level is greater than zero.

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