Display unit control method, system, and storage medium

Abstract

The application provides a display unit control method, system and storage medium. The method comprises: receiving a plurality of data packets transmitted via a serial link; intercepting data packets belonging to each control channel based on each control channel and the start symbol; extracting a delay amount and control object data in the corresponding data packet for each control channel; determining a target display unit corresponding to the control channel based on the control object data, and parameter data code corresponding to the target display unit; generating a driving signal corresponding to the target display unit based on the parameter data code in the data packet; adding a display unit position symbol to the driving signal of the target display unit based on the target display unit; the display unit position symbol is used to verify that the display unit driven by the driving signal is the target display unit; and transmitting the driving signal based on the delay amount and a preset delay correction value.

Description

Technical Field

[0001] This application relates to the field of intelligent lighting and LED (light-emitting diode) matrix display control, and in particular to a control method, system and storage medium for a display unit. Background Technology

[0002] In the field of intelligent lighting and display control technology, high-density matrix LED pixel lamps have been widely used in various scenarios such as engineering decoration, commercial advertising displays, and landscape lighting due to their excellent display effects and flexibility. Such systems typically consist of a master control device and multiple cascaded column control channels to drive N×N matrix-arranged pixel units. During data transmission in multi-cascaded display systems, parallel wiring or fixed address mapping is usually used to control each display unit. When using parallel wiring, a separate data line needs to be configured for each display unit, which not only complicates the wiring but also significantly increases the number of lines as the display scale expands, leading to high hardware costs, wiring difficulties, and decreased system reliability. Summary of the Invention

[0003] This application provides a control method, system, and storage medium for a display unit, which helps to improve its stability in long-link cascading, adaptability to irregular matrices, and compatibility with hardware platforms.

[0004] In a first aspect, embodiments of this application provide a control method for a display unit, comprising: receiving a plurality of data packets transmitted via a serial link; the plurality of data packets being data packets included in a total data frame, each data packet including a start symbol; each data packet corresponding to a control channel; based on each control channel and the start symbol, intercepting data packets belonging to each control channel; for each control channel, extracting a delay amount and control object data from the corresponding data packets; based on the control object data, determining a target display unit corresponding to the control channel and a parameter data code corresponding to the target display unit, the target display unit including a plurality of pixels; based on the parameter data code in the data packets, generating a drive signal corresponding to the target display unit; based on the target display unit, adding a display unit position symbol to the drive signal of the target display unit; the display unit position symbol being used to verify that the display unit driven by the drive signal is the target display unit; and sending the drive signal based on the delay amount and a preset delay correction value.

[0005] In one embodiment, generating a drive signal corresponding to the target display unit based on the parameter data code in the data packet includes: converting the parameter data code into data in a target format, the target format including a return-to-zero code format; and generating the drive signal based on the data in the target format.

[0006] In one embodiment, converting the parameter data code into data in the target format includes: converting the RGB information corresponding to the parameter data code into a bit stream; determining the duration of a high level or the duration of a low level based on the bit stream; generating a return-to-zero (RZ) code waveform based on the bit stream and the duration of the high level or the duration of the low level; and generating the target format data based on the RZ code waveform.

[0007] In one implementation, generating a return-to-zero (RZ) code waveform based on the bit stream and the duration of a high level or a low level includes: obtaining initial values ​​for the RZ code waveform and a system clock; setting a state machine based on the system clock, the state machine being used to generate the RZ code waveform; and generating the RZ code waveform based on the state machine, the bit stream, and the duration of a high level or a low level.

[0008] In one embodiment, generating the drive signal based on the data in the target format includes: performing power enhancement and voltage conversion on the data in the target format to obtain a converted signal; performing waveform shaping on the converted signal based on a preset resistor to obtain a signal in the target format; and converting the signal in the target format into a drive signal within a set current range.

[0009] In one embodiment, the parameter data code includes at least one of the following: column pixel length code, column pixel RGB data code, and column pixel grayscale code.

[0010] In one embodiment, the operating modes of the control channel include a first operating mode and a second operating mode; wherein, in the first operating mode, the data refresh rate is greater than a first preset threshold, and in the second operating mode, the data refresh rate is less than a second preset threshold, the second preset threshold corresponding to a system resource consumption threshold.

[0011] In one embodiment, adding a display unit position symbol to the drive signal of the target display unit based on the target display unit includes: determining a position range in the drive signal of the target unit based on the format and position of a predefined position symbol; merging and encoding the display unit position symbol and the brightness data in the position range; determining a mapping table based on the position encoding; and adding the mapping table to the drive signal so that the receiving end can determine the display unit position symbol in the merged encoding based on the mapping table.

[0012] Secondly, embodiments of this application provide a control system for a display unit, comprising: a main control device configured to generate and send a total data frame, wherein the total data frame is composed of multiple data packets directly concatenated, each data packet using a unified and fixed identification code as a start character; multiple control channels, wherein the control channels are communicatively connected to form a serial link, each control channel including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the control channel executes the control method provided in any embodiment of this application; and multiple display units, each corresponding to one of the multiple control channels and driven by a drive signal output by the corresponding control channel.

[0013] Thirdly, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program that, when executed, implements the method as described in the first or second aspect.

[0014] Fourthly, a computer program product is provided, including a computer program that, when executed, implements the method as described in the first or second aspect.

[0015] This application employs a technical feature where "the total data frame is directly concatenated from multiple data packets corresponding one-to-one with multiple control channels, and each data packet uses a unified and fixed identification code as its start character." This eliminates the complex frame start flag, frame end flag, and global configuration segment found in traditional data frame structures, making the data protocol extremely simple and significantly improving data transmission efficiency. Furthermore, since each data packet follows the unified rule of starting with a unified and fixed identification code, it provides a clear and unambiguous data location method for each control channel, greatly reducing parsing complexity and enhancing the system's parsing compatibility and scalability across different hardware platforms. Moreover, this application employs a technical feature where "in each control channel, the total data frame is continuously monitored, and when an identification code is detected, data packets belonging to that control channel are extracted from the total data frame," enabling each control channel to autonomously identify and extract its own data. This distributed processing capability allows channels to work asynchronously, eliminating reliance on a precise global synchronization signal and fundamentally preventing overall synchronization failures caused by signal delays or drift over long links. Furthermore, by employing the technique of "forwarding the remaining total data frames after interception to subsequent cascaded control channels," this application achieves pipelined transparent data transmission in the serial link. Each channel processes only its own task and passes unprocessed data losslessly to the next level. This enables efficient and reliable data transmission across cascaded links of arbitrary length, providing a core guarantee for supporting large-scale, long-link cascaded applications. Moreover, by employing the technique of "generating drive signals based on data in the intercepted data packets and outputting drive signals to drive the display units connected to this control channel," this application completes the localized conversion and output of data into drive signals. This feature ensures that the generation of drive signals is based on accurate locally intercepted data, providing a terminal guarantee for achieving stable and reliable display effects. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a control method provided in an embodiment of this application; Figure 2 This is a framework diagram of the overall system architecture of this application; Figure 3 This is a logical framework diagram of the internal structure of a single-column control channel in this application; Figure 4 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0017] Matrix display control technology refers to the control technology for data allocation, scanning drive, brightness control, and synchronous display of multiple display units arranged in rows and columns. It is widely used in LED displays, LCD display modules, OLED panels, mini LED backlights, automotive displays, advertising screens, and industrial display equipment. The core objective of matrix display technology is to achieve efficient, synchronous, and stable driving of a large number of display units under limited hardware resources and transmission bandwidth. Matrix display control technology may suffer from drawbacks such as complex protocols, susceptibility to synchronization issues over long links, and difficulty in adapting to irregular shapes. The root cause lies in its centralized, rigid control architecture. This architecture relies on a global frame structure and synchronization signals, making it unsuitable for distributed and differentiated application requirements. Therefore, this application creatively proposes a flexible control method based on "distributed autonomous interception and forwarding guided by a unified identification code." By delegating control to each node, it enables them to operate autonomously according to simple and unified rules, thereby fundamentally solving the inherent problems of poor stability, insufficient flexibility, and low compatibility of centralized architectures.

[0018] Therefore, embodiments of this application provide a control method for a matrix display unit, including as follows: Figure 1 The steps are shown.

[0019] Step S11: Receive multiple data packets transmitted via a serial link; the multiple data packets are the data packets included in the total data frame, each data packet includes a start symbol; each data packet corresponds to a control channel.

[0020] In this embodiment, the display control system transmits a total data frame via a serial link. The total data frame includes multiple data packets, each corresponding to a different control channel. Each control channel can identify the boundaries of data packets from the serially transmitted data stream based on a start symbol and obtain its own data content, thereby achieving cascaded display control of multiple control channels. The total data frame can be: the complete set of display data within a single display cycle. Data packets can be: data units encapsulated for a specific control channel. The start symbol can be a preset identifier set at the beginning of a data packet to identify its starting boundary. A control channel can refer to a logical path or physical link used to transmit control data for a specific display unit. Each control channel has a unique channel identifier used to identify and extract data packets belonging to that channel from the total data frame. A display system contains multiple control channels, which are independent of each other and can be connected in parallel or cascaded.

[0021] Step S12: Based on each control channel and the start symbol, extract the data packets belonging to each control channel.

[0022] In the embodiments of this application, the control channel refers to a control unit, control link, or logical control path used to receive display data, generate drive signals, and drive the corresponding display unit to display.

[0023] Step S13: For each control channel, extract the delay amount and control object data from the corresponding data packet.

[0024] The delay parameter can refer to a parameter indicating the offset of the output timing of a control channel relative to a global synchronization reference. The delay parameter can be a value in time units (such as microseconds or clock cycles) or an index value used for table lookup. The purpose of the delay parameter is to compensate for the transmission path delay differences between different control channels, achieving synchronous refresh of multiple display units. Control object data can refer to the set of parameters used to generate the drive signals for the display units, and can include at least one of the following: brightness value, RGB component values, color temperature value, duty cycle parameter, scan line number, and display pattern index. The control object data, after conversion, generates drive signals that control the optical output or mechanical action of the display units connected to that channel. The return-to-zero code format is characterized by the signal level necessarily returning to a low level after completing a high-level representation within each bit cycle. Cascading can refer to the connection method where multiple control channels are physically connected end-to-end.

[0025] Step S14: Based on the controlled object data, determine the target display unit corresponding to the control channel and the parameter data code corresponding to the target display unit. The target display unit includes multiple pixels.

[0026] A target display unit refers to a physical display device connected to a specific control channel for presenting visual information. A target display unit contains multiple independently controllable pixels and can be an LED dot matrix module, an LCD segment, an OLED microdisplay, a digital tube array, or a display array composed of multiple discrete light-emitting elements. The target display unit is the final load object of the driving signals. Parameter data codes refer to a digital encoding sequence describing the display state (brightness, color, grayscale, etc.) of each pixel within the target display unit. The parameter data codes are arranged according to a preset pixel order, with each pixel corresponding to one or more data bytes. After conversion, the parameter data codes generate driving signals, updating the display content pixel by pixel.

[0027] Step S15: Based on the parameter data code in the data packet, generate a drive signal corresponding to the target display unit.

[0028] In the embodiments of this application, the driving signal can refer to a physical electrical signal that is used to directly act on the electrodes or driving ports of the display unit. The driving signal can be an analog signal (such as voltage amplitude, current magnitude) or a digital signal (such as PWM waveform, parallel data bus timing).

[0029] Step S16: Based on the target display unit, add a display unit position symbol to the drive signal of the target display unit; the display unit position symbol is used to verify that the display unit driven by the drive signal is the target display unit.

[0030] In this embodiment, the display unit location identifier can refer to an information field embedded in the drive signal, used to uniquely identify or verify the identity of the target display unit. The display unit location identifier can take the form of digital encoding, a specific pulse sequence, a frequency signature, or a time slot marker. The display unit location identifier differs from the control channel identification code: the channel identification code is used for data packet routing and interception, while the display unit location identifier is used for physical verification after the drive signal is output.

[0031] Step S17: Based on the delay amount and the preset delay correction value, send the drive signal.

[0032] In this embodiment, the delay correction value is used to correct the delay amount.

[0033] The method provided in this application embodiment realizes accurate interception and independent control of multi-channel data in cascaded links, eliminates cumulative timing misalignment in cascaded links through delay compensation, realizes efficient batch driving of multi-pixel display units, realizes physical identity verification of driving signals through display unit position symbols, and improves system robustness and enhances system diagnosability and maintainability through the collaborative mechanism of delay amount and preset delay correction value.

[0034] In one embodiment, generating a drive signal corresponding to the target display unit based on the parameter data code in the data packet includes: converting the parameter data code into data in a target format, the target format including a return-to-zero code format; and generating the drive signal based on the data in the target format.

[0035] In one embodiment, converting the parameter data code into data in the target format includes: converting the RGB information corresponding to the parameter data code into a bit stream; determining the duration of a high level or the duration of a low level based on the bit stream; generating a return-to-zero (RZ) code waveform based on the bit stream and the duration of the high level or the duration of the low level; and generating the target format data based on the RZ code waveform.

[0036] In one implementation, generating a return-to-zero (RZ) code waveform based on the bit stream and the duration of a high level or a low level includes: obtaining initial values ​​for the RZ code waveform and a system clock; setting a state machine based on the system clock, the state machine being used to generate the RZ code waveform; and generating the RZ code waveform based on the state machine, the bit stream, and the duration of a high level or a low level.

[0037] In one embodiment, generating the drive signal based on the data in the target format includes: performing power enhancement and voltage conversion on the data in the target format to obtain a converted signal; performing waveform shaping on the converted signal based on a preset resistor to obtain a signal in the target format; and converting the signal in the target format into a drive signal within a set current range.

[0038] In one implementation, the data packet comprises the unified identification code and subsequent configurable data segments.

[0039] In one implementation, the configurable data segment includes parameter data codes for configuring the display unit.

[0040] In one embodiment, the parameter data code is used to make the display units connected to different control channels correspond to different numbers of pixels, so as to adapt to irregular matrix display.

[0041] In one embodiment, the parameter data code includes at least one of the following: column pixel length code, column pixel RGB data code, and column pixel grayscale code.

[0042] In one embodiment, the operating modes of the control channel include a first operating mode and a second operating mode; wherein, in the first operating mode, the data refresh rate is greater than a first preset threshold, and in the second operating mode, the data refresh rate is less than a second preset threshold, the second preset threshold corresponding to a system resource consumption threshold.

[0043] In one embodiment of this application, the control method for the display unit can be applied to a matrix display unit.

[0044] In one embodiment, adding a display unit position symbol to the drive signal of the target display unit based on the target display unit includes: determining a position range in the drive signal of the target unit based on the format and position of a predefined position symbol; merging and encoding the display unit position symbol and the brightness data in the position range; determining a mapping table based on the position encoding; and adding the mapping table to the drive signal so that the receiving end can determine the display unit position symbol in the merged encoding based on the mapping table.

[0045] Furthermore, in one embodiment of this application, the control method for the display unit may include the following steps.

[0046] In some embodiments, this application provides a control method for a matrix display unit, comprising the following steps: receiving a total data frame transmitted via a serial link, wherein the total data frame is composed of all single-column data packets directly spliced ​​together, without a frame start marker, a frame end marker, or a global configuration segment; each single-column data packet begins with a unified and fixed column identification code (prefix), which can be freely combined with any data code thereafter, and the number, length, and format of the data packet segments are not limited; the column control channel continuously detects the data stream, and when a unified column identification code (prefix) is detected, it begins to capture the complete data packet of the current column; the remaining subsequent column data after capture is transparently forwarded to the subsequent control channel; the captured data packet of the current column is converted into a return-to-zero code format, and a standard row scanning pulse drive signal for driving all row pixels of the current column is generated based on the return-to-zero code; after the return-to-zero code conversion is completed, the drive signal is output row by row according to the normal standard timing sequence to achieve stable and uniform display.

[0047] It should be noted that the above-described embodiment using "columns" as control units is a typical implementation of this application, used to clearly illustrate the principles of the embodiments of this application. However, those skilled in the art should understand that the control architecture of "distributed autonomous interception and forwarding based on unified identification codes" proposed in the embodiments of this application has universality. The key point of the embodiments of this application is that multiple control channels are cascaded, and each channel intercepts data packets specific to its own channel by identifying a unified identification code and forwards the remaining data. This principle is also applicable to controlling other forms of display units or device groups, for example, in a matrix using "rows" as control units, or in a system controlling multiple device nodes arranged in a non-matrix form. Therefore, this application is not limited to the single form of "column control" described above.

[0048] In some embodiments, the control method logic flow can be mainly executed by cascaded column control channels, and its specific steps include the following steps S101 to S108.

[0049] S101: After the system is powered on or reset, the control channel completes initialization and enters the working state, and the logic flow starts.

[0050] S102: Continuous monitoring serial data flow control channel continuously listens to the input data flow in the serial link and waits for the data to arrive.

[0051] S103: Determine whether a "unified identification code" has been detected. The control channel will compare the input data with the preset, unified and fixed identification code (or guide code) in real time.

[0052] If not detected: the process returns to step S102 to continue monitoring the data flow.

[0053] If detected: This means a potential data packet start point has been detected, and the process proceeds to step S104.

[0054] S104: Determine if a local ID is matched. Upon detecting a unified identification code, immediately perform critical identity authentication. The control channel reads the identification information immediately following the identification code (e.g., the channel address or column number in the data packet) and compares it with its own stored local ID.

[0055] If a match is found: This indicates that the current data packet belongs to this channel, and the process proceeds to step S105 to start receiving complete data packets.

[0056] If there is no match: it indicates that the data packet belongs to another channel, and the process jumps to step S106 to continue monitoring the data stream to find the next identification code (i.e., skip this data packet).

[0057] S105: Receive and process data packets in this column. For data packets that match the local data, the control channel continues to receive subsequent data until the next unified identification code is detected. At this point, it is determined that the data packet has been received completely. Subsequently, the channel converts the received raw data (such as RGB data) into the standard Return-to-Zero (RZ) code format.

[0058] S106: Transparent forwarding of remaining data After completing data processing in this channel or identifying a mismatched data packet, the control channel will perform signal shaping and regeneration on the subsequent data stream (starting from the next identification code) and transparently forward it to the next control channel in the cascaded link.

[0059] S107: Generate and output drive signals. For the matched and processed data packets, the control channel generates drive signals according to the standard timing based on the converted return-to-zero code data and outputs them to the pixel units connected to this channel.

[0060] S108: Return to monitoring status. After completing the above operations, the control flow returns to step S102 to continue monitoring the data stream and achieve continuous screen refresh.

[0061] This process employs a distributed logic of "authentication first, processing later." Each control channel first quickly determines the ownership of a data packet and only performs in-depth processing on packets belonging to it, thereby greatly improving processing efficiency and ensuring the stability of the cascaded link and the independence of each channel's operation.

[0062] Furthermore, it should be noted that the above-described process, which includes the step of "determining whether a local ID matches," is a preferred method for achieving precise addressing. In other embodiments of this application, a simpler sequential allocation mode can also be adopted. In this mode, when the first control channel in the cascaded link detects the first unified identification code, it assumes that subsequent data packets belong to this channel and receives, converts, and outputs them, while forwarding the remaining data stream; subsequent control channels follow suit, each intercepting and processing the data packets immediately following the next identification code. This method, which does not require matching a specific local ID, still uses the "unified identification code" for data packet partitioning and distributed processing, and can also achieve the core objective of this application, especially suitable for applications where control channels strictly correspond in physical order.

[0063] In some embodiments, "transparent forwarding" may refer to not parsing or modifying the forwarded data content, but may include physical layer processing such as shaping, regenerating and amplifying the signal waveform.

[0064] In some embodiments, the "zero code" can be a zero code RZ similar to WS2812, which before conversion is a preamble code + length code + RGB data code and grayscale code, and after conversion is: RGB data code.

[0065] In some embodiments, the return-to-zero code (WS2812 type) conversion is implemented by hardware timing circuitry, without the need for MCU software involvement, without consuming computing resources, without increasing latency, without limiting refresh rate, and can be stably implemented with low-cost hardware.

[0066] In some embodiments, a single-column data packet includes, but is not limited to, column pixel length code, column pixel RGB data code, and column pixel grayscale code. It should be noted that any data combination format that begins with a unified column identification code (prefix code) is within the scope of protection of this application.

[0067] In some embodiments, the control mode includes a high-speed mode and a low-speed mode: the high-speed mode improves the overall data processing and output refresh rate; the low-speed mode reduces system overhead and improves compatibility with low-end hardware.

[0068] In some embodiments, the unified column identifier (guide code) is a fixed identifier used to locate the beginning of all column data packets; the column pixel length code is used to independently configure the number of effective row pixels in this column, adapting to non-uniform length displays of irregular matrices.

[0069] In some embodiments, this application disables the reset synchronization mechanism based on data silence duration to avoid long link timing drift, frame drops, and synchronization failure.

[0070] In some embodiments, when outputting drive signals row by row within the same column, a return-to-zero code standard is used to drive the image, ensuring low flicker.

[0071] In some embodiments, the "column control channel" can be implemented based on MCU and dedicated IC hardware. Regardless of input or output, the hardware only needs a single bus for data transmission. Preferably, the column control channel is implemented using simple digital logic circuits, resulting in extremely low hardware costs. It can be implemented using ASIC, CPLD, or discrete logic, and the overall cost during mass production is significantly lower than that of traditional centralized drive solutions.

[0072] In some embodiments, the total data frame = column 1 data packet + column 2 data packet + ... + column N data packet (no frame start flag, no frame end flag, no global configuration segment); the "column identification code" can be a fixed one byte, followed by the column length code, RGB data code, and grayscale code, with clear boundaries to prevent misidentification; the column control channel continuously detects the data stream, and when a unified preamble is detected, it begins to intercept the complete data packet for that column; the rules for determining the complete data packet in this patent are as follows: When the column control channel detects a column identifier, it begins receiving data for that column; when the next column identifier is detected, it considers the data packet for that column to have ended, and all data prior to the previous column identifier constitutes the complete data packet for that column.

[0073] It should be noted that the embodiments of this application ensure data transparency through a state machine mechanism, eliminating the need for escape characters, byte padding, and verification. The column control channel only identifies the preamble in the idle listening state; once it enters the data receiving state, even if the same bit sequence as the preamble appears in the RGB / grayscale data, it is treated as ordinary display data and will not trigger new data packet judgment, avoid truncation, synchronization errors, or garbled characters. The protocol has inherent data transparency. For example, assuming the preamble is 0x55, if the length code and RGB or grayscale code that follow it contain 0x55, it only represents its specific value and will not trigger preamble recognition. This is because each preamble is followed by a length code, which determines the boundaries of the subsequent RGB and grayscale data.

[0074] In some embodiments, to avoid the accumulation of errors across frames, this application implements the following mechanism: if the preamble of a column is damaged due to interference, the data of the control channels of this column and subsequent columns is directly discarded without refreshing; since there is a low-level reset interval between frames, after the reset is completed, all column control channels automatically return to the initial listening state and re-receive the data of the new frame, the error will not continue to the next frame, and the system can quickly recover itself.

[0075] In some embodiments, the present application embodiments can automatically lock the correct data packet during power-on, hot-plugging, and dynamic reconfiguration. Specifically, each column of channels in the present application embodiments adopts a serial, step-by-step transmission structure, rather than parallel reception; a fixed reset low level exists between frames. After power-on or interference, the channel only needs to wait for the next preamble and inter-frame reset to automatically synchronize, unaffected by power-on in the middle, and can accurately lock the data packet belonging to itself. Dynamic configuration instructions and display data are transmitted on the same link, and the channel is automatically identified without interfering with normal display.

[0076] In some embodiments, each column control channel of this application includes signal shaping, level conversion, and timing regeneration. After each stage, the signal is completely restored to the standard level and timing, with no jitter accumulation and no deviation amplification. It can support long-distance, multi-cascade scenarios without signal quality degradation.

[0077] In some embodiments, the present application adopts a hierarchical forwarding architecture, which has obvious advantages. The length of each column can be configured independently, and it supports irregular matrices and flexible screens. If a column of LED beads (WS2812) is damaged, it will only affect that column and will not affect other channels. The wiring is simpler and the system is more robust, which is something that traditional single-chain structures cannot achieve.

[0078] In some embodiments, the specific parameters and performance differences between the two modes of "high-speed / low-speed dual mode" are as follows: High-speed mode: Data transmission rate is 2.5 Mbps, full screen refresh rate is ≥300 Hz, smooth and flicker-free picture, suitable for long cascaded links and high refresh rate display scenarios.

[0079] Low-speed mode: Data transmission rate is 800 kbps, full screen refresh rate is ≥60 Hz, timing requirements are relaxed, suitable for low-cost hardware and short-distance transmission scenarios.

[0080] The two modes are fully compatible in terms of data packet format, preamble recognition rules, data interception logic, and drive output timing, with only the transmission rate differing. Mode switching is completed by the master controller issuing configuration commands through the data link, and the column control channel identifies and takes effect in real time. The switching process is uninterrupted, with no data loss or synchronization errors.

[0081] In some embodiments, the driving timing of this application embodiment can adopt the commercially available WS2812B class return-to-zero code single-wire serial timing, not a custom timing. The key parameters are as follows: Bit 0 encoding: high level 0.4µs ​​± 0.1µs, low level 0.85µs ± 0.1µs; Bit 1 encoding: high level 0.85µs ± 0.1µs, low level 0.4µs ​​± 0.1µs; Reset code (inter-frame reset): low level ≥ 50µs; Data rate: 800kbps (standard mode) / 2500kbps (high-speed mode); Single lamp data format: GRB 24bit, each bit is a return-to-zero code structure.

[0082] In some embodiments, a matrix display control system is also provided, comprising: a main control device configured to generate and send a total data frame, wherein the total data frame is composed of multiple data packets directly spliced ​​together, and each data packet uses a unified and fixed identification code as a start character; multiple control channels, which are communicatively connected to form a serial link, each control channel including a processor and a memory, the memory storing a computer program, and when the computer program is executed by the processor, causing the control channel to execute the control method of this application; and multiple display units, which are connected one-to-one with the multiple control channels and are driven by the drive signals output by the corresponding control channels.

[0083] In some embodiments, the serial link is composed of multiple cascaded column control channels.

[0084] In some embodiments, such as Figure 2 The overall architecture of the system is shown, which consists of core components formed by cascading parts. These core components include a main control device, multi-level column control channels, and matrix pixel units.

[0085] Main control device: As the control center of the system, it is responsible for generating display data, including a tiered lighting control data generation and transmission module. The tiered lighting control data may include multiple data packets as described in the above embodiments. The image information to be displayed is organized into a specific data format by columns.

[0086] Multi-level column control channel: This is the execution unit in this embodiment of the application. Multiple column control channels (including column 1 control channel, column 2 control channel, column 3 control channel, etc.) are cascaded sequentially through a serial link to form a data transmission chain. Each column control channel is responsible for driving one column of pixel units.

[0087] N×N matrix pixel unit: A display array composed of light-emitting diodes (LEDs), for example, including columns 1, 2 to N, each column including N rows. Each column of pixel units is directly driven by a corresponding column control channel.

[0088] Downlink data stream (control commands): The master control device sends the generated total data frame to the first column control channel via a serial link. This total data frame is directly assembled from the data packets of all columns, without any additional frame headers or trailers.

[0089] Data pipeline processing: After receiving the data stream, each column control channel intercepts the data packets belonging to its own channel and then transparently forwards the remaining data packets to the next cascaded column control channel. Data is transmitted sequentially along the link in this manner until the last channel.

[0090] Drive output: Each column control channel generates a drive signal based on the captured data of its column, and outputs it in parallel to the connected column of pixel units, ultimately controlling the display of the entire matrix screen.

[0091] Architecture features: This architecture adopts a distributed control mode of "master control distribution and column channel autonomous processing", which simplifies wiring through serial cascading and realizes efficient control of large-scale pixel arrays.

[0092] In some embodiments, Figure 3 This reveals the logical functional modules and their collaborative relationships within a single column control channel, with reference to... Figure 3 As shown, the data receiving module within a single column control channel is responsible for receiving the serial data stream from the preceding stage of the cascaded link. Its function is to continuously listen to the data stream and send the data to subsequent modules for processing. A preamble matching and protocol parsing module is also included within the single column control channel: it continuously monitors the data stream and compares it with a preset unified column identification code (preamble). A data interception module for this column is also included within the single column control channel: once a matching preamble is detected, this module is activated and begins executing the data interception logic. This module continuously receives data until the next preamble is detected, at which point it determines that the data packet for this column has been received completely and buffers the complete data packet.

[0093] Each column control channel also includes a transparent forwarding module for remaining data: this module activates immediately after successfully intercepting the data packet for that column. It transparently forwards all subsequent data streams (i.e., data belonging to other downstream columns) starting from the next preamble. "Transparent" means that the forwarding process may involve signal shaping and regeneration to ensure data quality, but without altering the data content. This is crucial for ensuring cascade stability.

[0094] Each column control channel also includes a drive signal conversion and generation module: this module receives the captured raw data packets for that column. Its function is to convert the raw data into standard Return-to-Zero (RZ) code to meet the timing requirements of general-purpose LED driver chips. After conversion, the module generates drive signals according to the standard timing sequence.

[0095] The single column control channel is also equipped with a row scanning pulse output module: this module outputs the generated drive signal in parallel to all pixel units (LEDs) connected to this channel, directly controlling their on / off state, color and brightness.

[0096] Its internal logic flow includes: after the data stream enters the single-column control channel, it sequentially goes through "receiving and listening, identification and interception, (simultaneously) transparent forwarding, conversion and generation of driver, and output driver" to realize the control of the display unit. 。

[0097] In some embodiments, the display unit includes pixel units such as light-emitting diode (LED) pixel lamps.

[0098] In some embodiments, the display units are arranged in an N×N matrix, and the corresponding column control channels drive the output row by row. Of course, the matrix can also be a heterogeneous matrix, and each column does not have to be of equal length.

[0099] In some embodiments, a display device is also provided, including a control system for the display unit of this application.

[0100] In some embodiments, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the control method of this application.

[0101] The following will further describe the specific implementation methods of the embodiments of this application. The implementation methods are merely illustrative and are not limited to the following examples.

[0102] This embodiment uses an 8×8 full-color RGB matrix pixel screen as a specific example for detailed description.

[0103] The system consists of a main control device, 8-level column control channels, and 8×8 matrix pixel units. The column control channels are cascaded to form a serial link. The pixel drive adopts a return-to-zero code direct drive method and does not use row scanning drive.

[0104] In one embodiment of this application, the control system of the display unit includes: a pixel array: 8×8 full-color RGB pixels, totaling 64 pixels; column control channels: 8-level cascaded channels, each channel driving one column of 8 pixels. The control system adopts WS2812-like return-to-zero code single-wire timing drive; and single serial bus cascaded transmission.

[0105] The total data frame consists of: column 1 data packet + column 2 data packet + … + column 8 data packet, no frame header, no frame trailer, and no global configuration segment.

[0106] The single-column data packet format includes: a uniform fixed preamble (equivalent to a start character), column length (equivalent to latency), RGB data, and grayscale data. The RGB data and grayscale data can be equivalent to parameter data codes. The data packet may also include subsequent data segments. These subsequent data segments can be equivalent to the control object data in the aforementioned embodiments.

[0107] When generating the total data frame, the main control device generates 8 groups (or N groups, where N is an integer greater than or equal to 1) of single-column data packets according to the screen to be displayed: a unified fixed preamble is added to each column of data packets; the length of the column is followed by the writing of the effective number of pixels in the column; the RGB data and grayscale data of the corresponding number of pixels are written; the 8 column data packets are directly spliced ​​together to form a complete total data frame; and the total data frame is continuously sent through the serial bus at a set rate.

[0108] When the main control device sends the total data frame, the serial data rate can be configured by the main control command to be high-speed 2.5Mbps or low-speed 800kbps; the full screen refresh rate is ≥300Hz, with no flickering or tearing; the grayscale level is 256 levels, with smooth and uniform color transition.

[0109] During the display process, the system is first powered on, and each column control channel enters the data listening state; the main controller continuously sends the total data frame by frame; each column control channel detects the unified preamble in the data stream; when the preamble is detected, data reception begins, and when the next preamble is detected, the data packet for this column is determined to be finished; after interception, the remaining subsequent data is transparently forwarded to the subsequent channel after signal shaping, level conversion, and timing regeneration; the data for this column is converted into a return-to-zero code driving timing sequence, and the pixels of this column are driven to light up according to the normal timing sequence; the 8 column control channels work in parallel to complete the full-screen refresh display.

[0110] The system in this embodiment employs a data content-based synchronization mechanism, achieving reset synchronization without relying on data silence duration. When the channel detects a unified preamble, it determines it as the start of a column data packet and begins receiving data. When the next preamble is detected, it automatically determines the end of the previous column data packet, thus distinguishing the data boundaries of different columns within the same frame. Even if the same value as the preamble appears in the intermediate RGB or grayscale data, it will not cause misjudgment: the channel only considers the preamble, which is the beginning of the data packet, as a valid start marker. Identical values ​​appearing within a data segment are treated as ordinary pixel data and will not trigger resynchronization or cause conflicts. After the channel intercepts the data in this column, it shapes and forwards the subsequent data, while simultaneously converting the data in this column into a zero-code timing-driven pixel, achieving a display effect of no row scanning, no flicker, and independent controllable single point.

[0111] The methods and systems provided in this application offer highly flexible protocols and strong compatibility: A unified preamble is used as the starting identifier for column data packets, allowing for free combination of column length, RGB data, grayscale data, and configuration information without fixed format constraints. This provides broad protection and adaptability to various LED driver structures and display scenarios. Data packets have no frame headers or trailers, resulting in high transmission efficiency and simplified parsing logic: The total data frame is simply composed of directly concatenated column data packets, without additional frame headers, trailers, or global configuration segments, minimizing data overhead and increasing transmission efficiency. Parsing only requires identifying the preamble, resulting in lower hardware resource consumption and faster system response. Redundant timing delays are eliminated, lowering the hardware adaptation threshold: Complex timing designs such as delay misalignment and phase shift are eliminated, reducing the requirements for master clock accuracy. Low-cost MCUs and simple hardware platforms can operate stably, offering stronger compatibility. In this application example, a WS2812 class return-to-zero code driver is used to improve image uniformity and reduce line scan flicker in principle: the driving timing is a complete bit cycle consisting of high and low levels, and automatically returns to zero level after each bit data transmission, with no DC bias, no level residue, and no brightness accumulation error; compared with traditional line scan drivers, there is no interference from the line selection switch and the line-by-line refresh gap, eliminating dark lines and low-gray jitter in line scans from the root, resulting in higher image uniformity and no visible flicker. Based on data content synchronization combined with signal shaping and forwarding, long-link stability is significantly enhanced: a pure data synchronization mechanism of "determining the end of the column when the next preamble is detected" is adopted, eliminating the reset synchronization that depends on the data silence time, avoiding synchronization failure caused by long-distance transmission delay drift; data forwarding includes signal shaping, level conversion, and timing regeneration, which can repair signal attenuation step by step, greatly improving cascading distance and transmission reliability. The embodiments of this application can adapt to standard matrices and irregular matrices, and have a wider range of applications: each column of data packet can independently carry column length information, supports free configuration of the number of pixels in each column, and is perfectly compatible with standard N×N matrices, irregular matrices with unequal column lengths, and curved and flexible lamps, greatly improving the shape adaptation capability.

[0112] Some embodiments of this application provide a computer-readable storage medium applied to an electronic device 1400, wherein the computer-readable storage medium stores a computer program that, when executed by a processor, implements the aforementioned decoding method.

[0113] Electronic device 1400 may include: a communication interface 1110, a memory 1120, and a processor 1130; the various components are coupled together via a bus system 1140. It is understood that the bus system 1140 is used to implement communication between these components. In addition to a data bus, the bus system 1140 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 4 The general designated all buses as Bus System 1140. Among them, The communication interface 1110 is used for receiving and sending signals during the process of sending and receiving information with other external network elements.

[0114] Memory 1120 is used to store computer programs.

[0115] The processor 1130 is configured to execute the compressor control method for a refrigeration device provided in any embodiment of this application when running the computer program.

[0116] It is understood that the memory 1120 in some embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The memory 1120 of the systems and methods described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0117] The processor 1130 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the processor 1130 or by software instructions. The steps of the method disclosed in some embodiments of this application can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 1120, and the processor 1130 is used to read information from memory 1120 and, in conjunction with its hardware, complete the steps of the above compressor control method.

[0118] It is understood that the embodiments described in this application can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof.

[0119] In some embodiments, as another example, the processor 1130 is also configured to execute the compressor control method described in the foregoing embodiments when running the computer program.

[0120] Understandably, in some embodiments of this application, a "unit" can be a portion of a circuit, a portion of a processor, a portion of a program or software, etc., and can also be a module or a non-modular component. Furthermore, the components in this embodiment can be integrated into a single processing unit, or each unit can exist physically separately, or two or more units can be integrated into a single unit. The integrated unit described above can be implemented in hardware or as a software functional module.

[0121] If the integrated unit is implemented as a software functional module and not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0123] The sequence numbers in some embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method for a display unit, characterized in that, include: Receive multiple data packets transmitted via a serial link; The plurality of data packets are the data packets included in the total data frame, and each data packet includes a start character; each data packet corresponds to a control channel; Based on each control channel and the start symbol, extract the data packets belonging to each control channel; For each control channel, extract the delay amount and control object data from the corresponding data packet; Based on the controlled object data, the target display unit corresponding to the control channel and the parameter data code corresponding to the target display unit are determined. The target display unit includes multiple pixels. Based on the parameter data code in the data packet, a drive signal corresponding to the target display unit is generated; Based on the target display unit, a display unit position symbol is added to the drive signal of the target display unit; the display unit position symbol is used to verify that the display unit driven by the drive signal is the target display unit. The drive signal is sent based on the delay amount and the preset delay correction value.

2. The method according to claim 1, characterized in that, The step of generating a drive signal corresponding to the target display unit based on the parameter data code in the data packet includes: The parameter data code is converted into data in a target format, including a return-to-zero code format. The drive signal is generated based on the data in the target format.

3. The method according to claim 2, characterized in that, The step of converting the parameter data code into data in the target format includes: Convert the RGB information corresponding to the parameter data code into a bit stream; Based on the bit stream, determine the duration of the high level or the duration of the low level; Based on the bit stream and the duration of the high level or the duration of the low level, a waveform in return-to-zero code format is generated. Based on the waveform of the return-to-zero code format, data in the target format is generated.

4. The method according to claim 3, characterized in that, The step of generating a return-to-zero code waveform based on the bit stream and the duration of the high level or the duration of the low level includes: Obtain the initial values ​​of the waveform in return-to-zero code format, as well as the system clock; A state machine is set up based on the system clock, and the state machine is used to generate the waveform in the return-to-zero code format; Based on the state machine, the bit stream, and the duration of the high level or the duration of the low level, a waveform in return-to-zero code format is generated.

5. The method according to claim 2, characterized in that, The generation of the drive signal based on the data in the target format includes: The target format data is subjected to power enhancement and voltage conversion to obtain a converted signal; Based on a preset resistor, the waveform of the converted signal is shaped to obtain the signal in the target format; The target format signal is converted into a drive signal within a set current range.

6. The control method according to claim 1, characterized in that, The parameter data code includes at least one of the following: column pixel length code, column pixel RGB data code, and column pixel grayscale code.

7. The control method according to claim 1, characterized in that, The control channel has two operating modes: a first operating mode and a second operating mode. In the first operating mode, the data refresh rate is greater than a first preset threshold. In the second operating mode, the data refresh rate is less than a second preset threshold, which corresponds to a system resource consumption threshold.

8. The control method according to claim 1, characterized in that, The step of adding a display unit position symbol to the drive signal of the target display unit based on the target display unit includes: Based on the format and position of the predefined position symbol, the position range in the drive signal of the target unit is determined; The display unit location symbol and the brightness data in the location range are combined and encoded; Based on the position encoding, a mapping table is determined, and the mapping table is added to the driving signal, so that the receiving end can determine the display unit position symbol in the merged encoding based on the mapping table.

9. A control system for a display unit, characterized in that, include: The main control device is configured to generate and send a total data frame, which is composed of multiple data packets directly concatenated, and each data packet uses a unified and fixed identification code as the start character. Multiple control channels are communicatively connected to form a serial link. Each control channel includes a processor and a memory. The memory stores a computer program. When the computer program is executed by the processor, the control channel performs the control method according to any one of claims 1 to 8. Multiple display units are connected to multiple control channels one by one and are driven by the drive signals output by the corresponding control channels.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the control method according to any one of claims 1 to 8.

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