Display control system, method, display chip and storage medium

Abstract

The application discloses a display control system, a method, a display chip and a storage medium, and belongs to the technical field of display. The display control system comprises N data processing devices, an i-th data processing device receives an i-th data packet of a current frame, intercepts the i-th data packet, obtains a plurality of pixel point data corresponding to an i-th row pixel matrix and an i+1-th data packet, the i+1-th data packet comprises a data set corresponding to an i+1-th row pixel matrix to an N-th row pixel matrix, the i-th data processing device sequentially transmits the plurality of pixel point data corresponding to the i-th row pixel matrix to a plurality of pixel units in the i-th row pixel matrix, and transmits the i+1-th data packet to an i+1-th data processing device, so that the plurality of pixel units in the i-th row pixel matrix display corresponding display according to the plurality of pixel point data corresponding to the i-th row pixel matrix. Each row of pixel point data is independently transmitted, and the reliability of the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display control system, method, display chip, and storage medium. Background Technology

[0002] With the development of smart display and Internet of Things technologies, light emitting diode (LED) matrix light source systems have been widely used in the display field. Among them, LED matrix light source systems are display or lighting arrays composed of multiple LED pixel units arranged in a rectangular row and column manner.

[0003] In practical applications, large-scale LED pixel matrices are constructed by connecting the data ports of thousands of pixel units through a specific electrical topology. These data ports are typically connected in series or in parallel.

[0004] In series connection mode, the electrical topology typically uses an S-shaped routing pattern. If any pixel unit in the series circuit experiences an open or short circuit, the entire data path will be severed, preventing all subsequent pixel units from illuminating or displaying, resulting in low display reliability. In parallel connection mode, the bus load effect increases significantly. The equivalent input capacitance and input admittance of the bus increase dramatically with the number of pixel units. This large capacitive load leads to severe signal attenuation and waveform distortion during charging and discharging, further reducing display reliability. Summary of the Invention

[0005] This application provides a display control system, method, display chip, and storage medium, which improves the reliability of display effects. The technical solution is as follows: In a first aspect, a display control system is provided, comprising N data processing devices, where N is a positive integer greater than 1, each of the N data processing devices being connected to N rows of pixel matrices, each row of the pixel matrix comprising multiple pixel units; i is a positive integer greater than 1 and less than N; the i-th data processing device receives the i-th data packet of the current frame sent by the (i-1)-th data processing device, and intercepts the i-th data packet to obtain multiple pixel data corresponding to the i-th row of the pixel matrix and the (i+1)-th data packet; the (i+1)-th data packet comprises a set of data corresponding to the (i+1)-th to the N-th row of the pixel matrix; the i-th data processing device sequentially transmits the multiple pixel data corresponding to the i-th row of the pixel matrix to the multiple pixel units in the i-th row of the pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device; so that the multiple pixel units in the i-th row of the pixel matrix display accordingly based on the multiple pixel data corresponding to the i-th row of the pixel matrix.

[0006] In a second aspect, a display chip is provided, the display chip including a display control system as described in the first aspect, and an N-row pixel matrix.

[0007] Thirdly, a display control method is provided, which is applied to a display control system as described in the first aspect above. The display control system includes N data processing devices, where N is a positive integer greater than 1. The N data processing devices are respectively connected to N rows of pixel matrices, and each row of pixel matrices includes multiple pixel units; i is a positive integer greater than 1 and less than N. The display control method includes: receiving the i-th data packet of the current frame sent by the (i-1)-th data processing device through the i-th data processing device; intercepting the i-th data packet to obtain multiple pixel data corresponding to the i-th row of pixel matrices and the (i+1)-th data packet; the (i+1)-th data packet includes a data set corresponding to the (i+1)-th to the N-th row of pixel matrices; sequentially transmitting the multiple pixel data corresponding to the i-th row of pixel matrices to multiple pixel units in the i-th row of pixel matrices through the i-th data processing device; and transmitting the (i+1)-th data packet to the (i+1)-th data processing device; so that the multiple pixel units in the i-th row of pixel matrices are displayed according to the multiple pixel data corresponding to the i-th row of pixel matrices.

[0008] Fourthly, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the third aspect above.

[0009] Fifthly, a computer program product containing instructions is provided that, when run on a computer, causes the computer to perform the method described in the third aspect above.

[0010] This application provides a display control system, method, display chip, and storage medium. According to the solution provided in this application, the display control system includes N data processing devices, where N is a positive integer greater than 1. Each of the N data processing devices is connected to one row of a pixel matrix, and each row of the pixel matrix includes multiple pixel units. i is a positive integer greater than 1 and less than N. The number of pixel units in each row of the pixel matrix can be the same or different. By constructing the display control system with an N-row pixel matrix layout, the bus load effect can be reduced, and the problem of mutual interference in series loops can be minimized. The i-th data processing device is connected to the (i-1)-th data processing device, the (i+1)-th data processing device, and the i-th row of the pixel matrix. Adding data processing devices facilitates the interception of data in the current row and the forwarding (or transparent transmission) of the remaining data. The i-th data processing device receives the i-th data packet of the current frame sent by the (i-1)-th data processing device, and intercepts the i-th data packet to obtain multiple pixel data corresponding to the i-th row of the pixel matrix and the (i+1)-th data packet. The (i+1)-th data packet includes the data set corresponding to the (i+1)-th to N-th row of the pixel matrix. The i-th data processing device sequentially transmits the multiple pixel data corresponding to the i-th row of the pixel matrix to multiple pixel units in the i-th row of the pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device, so that the multiple pixel units in the i-th row of the pixel matrix can be displayed according to the multiple pixel data corresponding to the i-th row of the pixel matrix. This scheme adopts a multi-row pixel matrix layout, which reduces the capacitive load; each row of the pixel matrix is ​​independent of each other, and the pixel data of each row is transmitted independently. If one pixel unit fails, it will not affect the illumination or display of other rows of the pixel matrix, thus improving the reliability of the display effect. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a series connection method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a parallel connection method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a display control system provided in an embodiment of this application; Figure 4 This is a schematic diagram of a data transmission method provided in an embodiment of this application; Figure 5 This is a schematic diagram of another data transmission method provided in an embodiment of this application; Figure 6 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application; Figure 7 This is a flowchart of a data processing method provided in an embodiment of this application; Figure 8 This is a schematic diagram of an input communication protocol format provided in an embodiment of this application; Figure 9 This is a schematic diagram of an output communication protocol format provided in an embodiment of this application; Figure 10 This is a schematic diagram illustrating another data transmission method provided in an embodiment of this application; Figure 11 This is a flowchart of a display control method provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0014] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0015] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant regulations and standards of the relevant organizations and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0016] Before providing a detailed explanation of the embodiments of this application, the application scenarios and related technologies of the embodiments of this application will be described first.

[0017] The display control system provided in this application embodiment can be applied to LED display screens, LED matrix panels, pixelated lighting fixtures, advertising signs, automotive taillight arrays, matrix light source systems, and other LED display control fields. The display control system can also be applied to terminal devices with large pixel display unit pitches, such as game consoles, learning machines, and smart wearable devices.

[0018] For example, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a series connection method provided in an embodiment of this application. The electrical topology adopts an S-shaped routing method, and the number of pixel units in each row needs to be consistent in order to facilitate regular routing. Figure 1 The diagram shows 3×N pixel units distributed in 3 rows (rows A, B, and C), with each row containing N pixel units. Data frames pass sequentially through the N pixel units in each row, illuminating or displaying all 3×N pixel units simultaneously. The series connection method presents the following data transmission problem: an open or short circuit in any pixel unit in the series loop will affect the illumination or display of the entire data path, resulting in low reliability of the display effect.

[0019] For example, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a parallel connection method provided in an embodiment of this application. Figure 2 The diagram shows 3×N pixel units distributed in 3 rows (row A, row B, and row C), with each row containing N pixel units. The following data transmission problems exist in the parallel connection method: (1) Large capacitor loads cause severe signal attenuation and waveform distortion during charging and discharging; (2) Parallel buses are similar to multi-branch transmission lines, and the impedance discontinuity of each branch causes signal reflection. The reflected waves are superimposed on the original signal, causing bit errors, resulting in signal reflection and crosstalk; (3) The data signal emitted by the driver arrives at all pixel units simultaneously, making it difficult to achieve unicast or multicast for specific pixel units. If software addressing is used, each pixel unit requires additional decoding and storage circuitry, which can easily lead to addressing conflicts and rampant data broadcasting.

[0020] Based on this, embodiments of this application provide a display control system with a simple connection method, reliable data transmission, and support for the control of irregularly shaped LED matrix light sources. For example... Figure 3 As shown, Figure 3 This is a schematic diagram of a display control system provided in an embodiment of this application. Figure 3The topology of the display control system is shown. The display control system includes N data processing devices, where N is a positive integer greater than 1. Each of the N data processing devices is connected to one row of a pixel matrix, and each row of the pixel matrix includes multiple pixel units. i is a positive integer greater than 1 and less than N. The number of pixel units in each row of the pixel matrix can be the same or different. The data processing devices can also be called data forwarding chips, and the pixel units can be called LED current driving chips. By constructing the display control system with an N-row pixel matrix layout, the bus load effect can be reduced, and the mutual interference problems in series loops can be minimized. The i-th data processing device is connected to the (i-1)-th data processing device, the (i+1)-th data processing device, and the i-th row of the pixel matrix. Adding data processing devices facilitates the interception of data in the current row and the forwarding (or transparent transmission) of the remaining data. The i-th data processing device receives the i-th data packet of the current frame sent by the (i-1)-th data processing device, and truncates the i-th data packet to obtain multiple pixel data corresponding to the i-th row pixel matrix and the (i+1)-th data packet. The (i+1)-th data packet includes the data set corresponding to the (i+1)-th to the N-th row pixel matrix. The i-th data processing device sequentially transmits the multiple pixel data corresponding to the i-th row pixel matrix to multiple pixel units in the i-th row pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device, so that the multiple pixel units in the i-th row pixel matrix can be displayed according to the multiple pixel data corresponding to the i-th row pixel matrix.

[0021] In one possible implementation, the i-th data processing device generates multiple display data corresponding to the i-th row pixel matrix according to the multiple pixel data corresponding to the i-th row pixel matrix in accordance with the output communication protocol; and sequentially sends the multiple display data corresponding to the i-th row pixel matrix to the multiple pixel units in the i-th row pixel matrix; so that the multiple pixel units in the i-th row pixel matrix can display accordingly according to the multiple display data corresponding to the i-th row pixel matrix.

[0022] This scheme employs a multi-row pixel matrix layout, reducing capacitor load and improving signal reliability during charging and discharging. Multiple pixel units in the i-th row of the pixel matrix have a one-to-one correspondence with the corresponding pixel data points in the i-th row; one pixel unit corresponds to one pixel data point. Thus, the operating mode of a pixel unit (e.g., display or not display, bright or dark) can be controlled by controlling the pixel data, enabling unicast or multicast for specific pixel units. Each row of the pixel matrix is ​​independent, and pixel data in each row is transmitted independently. A failure in one pixel unit will not affect the illumination or display of other rows of the pixel matrix, improving the reliability of the display effect.

[0023] The above Figure 3The diagram illustrates N data processing devices (represented as data processing device 1, data processing device 2, data processing device 3... data processing device N) and N rows of pixel matrices (represented as row 1, row 2, row 3... row N), connected in a simple manner. The number of pixel units in each row of the pixel matrix can be the same or different. For example, the first row may contain M pixel units, the second row P pixel units, the third row K pixel units, and the Nth row R pixel units. M, P, K, and R can be equal or unequal; of course, M, P, K, and R can all be equal to N. Thus, the structure of the N-row pixel matrix can be a square matrix, a rectangular matrix, or an irregularly shaped matrix. In other words, this display control system supports not only the control of rectangular LED light sources but also the control of irregularly shaped LED matrix light sources.

[0024] Figure 3 In the diagram, DO1 (data output1) represents data output path 1, which is used to send the captured data of this row to multiple pixel units for display; DO2 (data output2) represents data output path 2, which is used to forward (or pass through) the remaining data.

[0025] The display control system provided in this application embodiment can be applied to LED matrix light source systems, and can present high-quality images or light effects. Data is transmitted through each pixel unit or group of pixel units, realizing the integration of display, lighting and communication.

[0026] In some embodiments, the display control system further includes a data bus transmission module; the data bus transmission module is connected to the first data processing device; the data bus transmission module receives the entire frame data of the current frame sent by the image acquisition device, encapsulates the entire frame data of the current frame according to a preset encapsulation format to obtain the first data packet of the current frame, and transmits the first data packet to the first data processing device (i.e., the first data processing device); the first data packet includes the data set corresponding to the first row of pixel matrix to the Nth row of pixel matrix; that is, the first data packet includes the entire frame data of the current frame. The first data processing device intercepts the first data packet to obtain multiple pixel data corresponding to the first row of pixel matrix and a second data packet; the second data packet includes the data set corresponding to the second row of pixel matrix to the Nth row of pixel matrix. The first data processing device sequentially transmits the multiple pixel data corresponding to the first row of pixel matrix to multiple pixel units in the first row of pixel matrix, and transmits the second data packet to the second data processing device, so that the multiple pixel units in the first row of pixel matrix are displayed according to the multiple pixel data corresponding to the first row of pixel matrix, and so on. By using a multi-row pixel matrix layout, the capacitive load is reduced; each row of the pixel matrix is ​​independent of the others, and the data of each row of pixels is transmitted independently, which improves the reliability of the display effect.

[0027] For example, based on the above Figure 3 ,like Figure 4 As shown, Figure 4 This is a schematic diagram illustrating a data transmission method provided in an embodiment of this application. Figure 4The complete data frame of the display control system shown (i.e., the entire frame data of the current frame) includes data packets from row 1 to row N. The data frame can be an image frame or a video frame. The data bus transmission module is used for data frame bus input, encapsulating the complete data frame of the display control system to obtain the first data packet. The first data packet includes data packets from row 1 to row N (i.e., the data set corresponding to the pixel matrices from row 1 to row N). The first data packet is transmitted to data processing device 1, which intercepts it, and DO2 outputs the second data packet. The second data packet includes data packets from row 2 to row N (i.e., the data set corresponding to the pixel matrices from row 2 to row N). Data processing device 2 intercepts the second data packet, and DO2 outputs the third data packet; the third data packet includes data packets from row 3 to row N (i.e., the data set corresponding to the pixel matrices from row 3 to row N). Data processing device 3 intercepts the third data packet, and DO2 outputs the fourth data packet; the fourth data packet includes data packets from the fourth row to the Nth row (i.e., the data set corresponding to the pixel matrix from the fourth row to the Nth row). Similarly, data processing device N-1 intercepts the (N-1)th data packet, and DO2 outputs the Nth data packet; the Nth data packet includes data packets from the Nth row (i.e., the data set corresponding to the pixel matrix in the Nth row).

[0028] In some embodiments, the (i+1)th data processing device continues to intercept the ith data packet until the last data processing device (the Nth data processing device) receives the Nth data packet sent by the (N-1)th data processing device. The Nth data packet includes multiple pixel data corresponding to the Nth row of the pixel matrix. The Nth data processing device sequentially transmits the multiple pixel data corresponding to the Nth row of the pixel matrix to multiple pixel units in the Nth row of the pixel matrix, so that the multiple pixel units in the Nth row of the pixel matrix can be displayed according to the multiple pixel data corresponding to the Nth row of the pixel matrix. By using a multi-row pixel matrix layout, the capacitive load is reduced; each row of the pixel matrix is ​​independent of each other, and the pixel data of each row is transmitted independently, improving the reliability of the display effect.

[0029] For example, based on the above Figure 4 ,like Figure 5 As shown, Figure 5This is a schematic diagram illustrating another data transmission method provided in an embodiment of this application. The pixel units in the first row of the pixel matrix include pixel units 1-1 to 1-M; the pixel data corresponding to the first row of the pixel matrix includes pixel data 1-1 to 1-M. The pixel units in the second row of the pixel matrix include pixel units 2-1 to 2-P; the pixel data corresponding to the second row of the pixel matrix includes pixel data 2-1 to 2-P. The pixel units in the third row of the pixel matrix include pixel units 3-1 to 3-K; the pixel data corresponding to the third row of the pixel matrix includes pixel data 3-1 to 3-K. The pixel units in the Nth row of the pixel matrix include pixel units N-1 to NR; the pixel data corresponding to the Nth row of the pixel matrix includes pixel data N-1 to NR.

[0030] After the data bus transmission module completes sending the complete data frame (i.e., the entire frame of the current frame), the data processing device 1 transmits the multiple pixel data corresponding to the first row of the pixel matrix, DO1, to the 1-1 pixel unit. The 1-1 pixel unit displays the data based on the 1-1 pixel data. The remaining pixel data is then transmitted to the 1-2 pixel unit, and the 1-2 pixel unit displays the data based on the 1-2 pixel data. This process continues until the 1-M pixel unit displays the data based on the 1-M pixel data.

[0031] Similarly, the data processing device 2 transmits the multiple pixel data corresponding to the second row of the pixel matrix to the 2-1 pixel unit via DO1. The 2-1 pixel unit displays the data based on the 2-1 pixel data. The remaining pixel data is then transmitted to the 2-2 pixel unit until the 2-P pixel unit displays the data based on the 2-P pixel data.

[0032] Similarly, the data processing device 3 transmits the multiple pixel data corresponding to the third row of the pixel matrix to the 3-1 pixel unit via DO1. The 3-1 pixel unit displays the data based on the 3-1 pixel data. The remaining pixel data is then transmitted to the 3-2 pixel unit, and so on, until the 3-K pixel unit displays the data based on the 3-K pixel data.

[0033] Similarly, the data processing device N transmits the data of multiple pixels corresponding to the Nth row of the pixel matrix, DO1, to the N-1 pixel unit. The N-1 pixel unit displays the data based on the N-1 pixel data. The remaining pixel data is then transmitted to the N-2 pixel unit, and so on, until the NR pixel unit displays the data based on the NR pixel data.

[0034] In this embodiment, by adding N data processing devices, the data of the current row is intercepted, transmitted to multiple pixel units of the current row for display via DO1, and the remaining data is forwarded (or transparently transmitted) via DO2. The display logic of each row of pixel matrix is ​​independent of each other, and the data of each row of pixels is transmitted independently, which improves the reliability of data transmission.

[0035] In some embodiments, the data bus transmission module encapsulates the entire frame data of the current frame according to at least one of the following: the data length corresponding to each row of the pixel matrix in the N-row pixel matrix, the identification code belonging to the data frame to be processed, and the preset verification method, to obtain the first data packet of the current frame.

[0036] Predefined data protocol, as described above Figure 4 and Figure 5 As shown, the total data frame (i.e., the entire data of the current frame) includes the first row of data packets + the second row of data packets + the third row of data packets + ... + the Nth row of data packets. The structure of each row of data packets can be set as follows. Taking the first row of data packets as an example, the structure of the first row of data packets is set to 1-1 pixel data to 1-M pixel data. The structure of each row of data packets can also include at least one of the following: data length, identification code belonging to the data frame to be processed, and preset verification method.

[0037] The identification code indicates whether the data frame belongs to the data processing device. The identification code can be a unique identifier pre-agreed upon by the data bus transmission module and the data processing device, representing that the data is a data frame to be processed. The same identification code can be used for each data packet. During encapsulation, the data bus transmission module encapsulates the identification code along with the pixel data before transmission. During data transmission, other data may be mixed with the DO2 output. When intercepting data, the data processing device can determine whether the received identification information belongs to the data frame to be processed, thereby improving the effectiveness and reliability of data processing.

[0038] The data length indicates the amount of data that the data processing device needs to extract, that is, the amount of pixel data output by DO1. The data length can be predetermined based on the number of pixel units included in each row of the pixel matrix. For example, the data length of the first row of the pixel matrix is ​​M, and the data length of the Nth row of the pixel matrix is ​​R.

[0039] The preset verification method can be a checksum, cyclic redundancy check (CRC), parity check, Hamming code, block check character (BCC), etc., used to verify whether the data packet has been correctly received. The specific form of the preset verification method can be pre-agreed upon by the data bus transmission module and the data processing device. The data bus transmission module uses the preset verification method for encryption, and the data processing device uses the preset verification method for decryption to verify whether the data has been correctly received. For each data packet, the checksum after encryption using the preset verification method is usually different.

[0040] For example, taking the encapsulation of the first row of data packets using data length, an identification code belonging to the data frame to be processed, and a preset verification method as an example, the structure of the first row of data packets is: identification code (optional) + data length (optional) + 1-1 pixel data to 1-M pixel data + data verification (optional). Similarly, after encapsulating N rows of data packets, the first data packet of the current frame is obtained. By increasing the data length, identification code, and preset verification method in the encapsulation process, the effectiveness and reliability of data transmission are improved.

[0041] In some embodiments, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a data processing device provided in an embodiment of this application. Each data processing device includes a receiving module 100, a protocol parsing module 200 (also referred to as a data protocol parsing module), a data buffer module 300 (also referred to as a pixel data buffer module), and a protocol generation and output module 400. Figure 6 The DIN shown indicates the received i-th data packet. The receiving module 100 receives the i-th data packet according to the input communication protocol; the protocol parsing module 200 parses the i-th data packet to obtain the data set corresponding to the i-th row of the pixel matrix to the N-th row of the pixel matrix (i.e., the i-th row of data packets to the N-th row of data packets). Multiple pixel data points are extracted from the data set corresponding to the i-th row of the pixel matrix to the N-th row of the pixel matrix as multiple pixel data points corresponding to the i-th row of the pixel matrix. For example, if the first row of the pixel matrix includes M pixel units, M pixel data points are extracted as the first row of data packets, and so on, extracting P pixel data points as the second row of data packets, K pixel data points as the third row of data packets, and so on, until the last R pixel data points are extracted as the N-th row of data packets.

[0042] The protocol parsing module 200 also uses the remaining data after interception (including the data set corresponding to the pixel matrix from row i+1 to row N) as the (i+1)th data packet. This data is then transmitted to the receiving module in the (i+1)th data processing device via DO2.

[0043] The data caching module 300 caches the data of multiple pixels corresponding to the i-th row of the pixel matrix as the data packet for this row. The protocol generation and output module 400 generates multiple display data corresponding to the i-th row of the pixel matrix according to the output communication protocol based on the multiple pixel data corresponding to the i-th row of the pixel matrix; and sends the multiple display data corresponding to the i-th row of the pixel matrix sequentially to the multiple pixel units in the i-th row of the pixel matrix through DO1; so that the multiple pixel units in the i-th row of the pixel matrix can display accordingly based on the multiple display data corresponding to the i-th row of the pixel matrix.

[0044] Because the data transmission protocol differs from the data display protocol, pixel data needs to be converted into a protocol that the pixel unit (i.e., the LED current driver chip) can recognize. Thus, the pixel unit displays the data based on the converted pixel data (i.e., the display data). One pixel unit corresponds to one piece of display data, as described above. Figure 4 and Figure 5 The 1-M pixel unit shown corresponds to 1-M pixel data, the 2-P pixel unit corresponds to 2-P pixel data, the 3-K pixel unit corresponds to 3-K pixel data, and the NR pixel unit corresponds to NR pixel data.

[0045] In this embodiment, after the receiving module 100 in the data processing device 1 receives the complete data frame (i.e., the first data packet) of the display control system according to the input communication protocol, the protocol parsing module 200 in the data processing device 1 parses the first data packet, caches the data packet content belonging to the pixel data of the current row in the data cache module 300, and then organizes the data packet content belonging to the pixel data of the current row into an output communication protocol that the pixel unit can recognize through the protocol generation output module 400, and sends the display data generated according to the output communication protocol to the pixel unit. This process is repeated to complete the data transmission, thus achieving the effectiveness and reliability of data transmission.

[0046] In some embodiments, such as Figure 6 As shown, each data processing device also includes a data shaping module 500; the data shaping module 500 is connected after the protocol parsing module 200. The data shaping module 500 shapes the data set corresponding to the pixel matrix from the (i+1)th row to the Nth row to obtain the (i+1)th data packet. This data packet is then transmitted to the receiving module in the (i+1)th data processing device via DO2.

[0047] In this embodiment, the first data packet is initially transmitted in a reference data format. However, during data transmission, data format distortion may occur, such as changes in duty cycle, amplitude reduction, or phase shift. Therefore, after each interception by the protocol parsing module, the data shaping module shapes the data set, correcting it to a data packet consistent with the reference data format, thereby improving the reliability and effectiveness of data transmission.

[0048] In some embodiments, the protocol parsing module 200 parses the i-th data packet to obtain a parsing result and a data set corresponding to the pixel matrices from the i-th row to the N-th row. The parsing result includes at least one of identification information, the i-th row checksum, and the i-th row data length. The protocol parsing module 200 determines whether the identification information is an identifier indicating that the current frame belongs to the data frame to be processed, that is, whether the identification information matches the identifier. If the identification information indicates that the current frame belongs to the data frame to be processed (the identification information matches the identifier), the protocol parsing module 200 states that the data belongs to the data frame to be processed, and identifies the data in the data set corresponding to the pixel matrices from the i-th row to the N-th row based on the data length of the i-th row, obtaining multiple pixel data points corresponding to the i-th row pixel matrix. The protocol parsing module 200 uses the data length to identify the data set and extracts multiple pixel data points with the same data length. The data caching module 300 caches the data of multiple pixels corresponding to the i-th row pixel matrix if the data of multiple pixels corresponding to the i-th row pixel matrix is ​​correctly received based on the check code of the i-th row and the preset verification method.

[0049] In this embodiment, the parsing process for the i-th data packet is the reverse of the encapsulation process described above. Verification is performed using the parsed identification information and checksum, and identification is performed using the data length, thereby improving the effectiveness and reliability of data transmission.

[0050] In some embodiments, if the protocol parsing module 200 indicates that the current frame does not belong to the data frame to be processed (the identification information is inconsistent with the identification code), or if it determines, based on the check code of the i-th row, that multiple pixel data points corresponding to the i-th row pixel matrix have not been correctly received, it indicates that an abnormality has occurred in the data transmission process. For example, the data is corrupted, or other data has been mixed in. Based on this, the processing of the current frame is abandoned. The protocol parsing module 200 can notify the receiving module 100 by notification, for example, that the current frame processing is complete, so that the receiving module 100 can continue to receive the i-th data packet of the next frame of the current frame sent by the (i-1)-th data processing device according to the input communication protocol. Alternatively, the protocol parsing module 200 can be temporarily idle, waiting for the receiving module 100 to receive the i-th data packet of the next frame of the current frame sent by the (i-1)-th data processing device according to the input communication protocol.

[0051] In this embodiment, if the i-th data packet is abnormal (for example, the identification information indicates that the current frame does not belong to the data frame to be processed, or multiple pixel data points are not received correctly), then the data in this row will no longer be intercepted, nor will the remaining data be forwarded (or transparently transmitted). That is, the intercepted multiple pixel data points will not be transmitted to multiple pixel units in the i-th row pixel matrix, nor will the remaining data be transmitted to the (i+1)-th data processing device. However, the pixel matrices from the first row to the (i-1)-th row before this will not be affected. By adding a verification process, the effectiveness and reliability of data transmission are improved.

[0052] For example, based on the above Figure 6 This application provides a data processing procedure for a data processing device, such as... Figure 7 As shown, Figure 7 This is a flowchart of a data processing method provided in an embodiment of this application.

[0053] S101, The receiving module receives the i-th data packet according to the input communication protocol.

[0054] S102, the protocol parsing module parses the i-th data packet to obtain the parsing result and the data set corresponding to the pixel matrix from the i-th row to the N-th row; the parsing result includes the identification information, the check code of the i-th row and the length of the i-th row data.

[0055] S103. The protocol parsing module determines whether the identification information is an identifier code indicating that the current frame belongs to the data frame to be processed.

[0056] If yes, proceed to S104. If no, proceed to S109.

[0057] S104. The protocol parsing module identifies the data in the data set corresponding to the pixel matrix from the i-th row to the N-th row based on the length of the i-th row data, and obtains the data of multiple pixels corresponding to the i-th row pixel matrix.

[0058] S105. The protocol parsing module verifies whether the data of multiple pixels is received correctly based on the checksum and the preset verification method.

[0059] If yes, proceed to S106. If no, proceed to S109.

[0060] S106. The data caching module caches the data of multiple pixels corresponding to the i-th row of the pixel matrix.

[0061] S107. The protocol generation and output module generates multiple display data corresponding to the i-th row pixel matrix according to the multiple pixel data corresponding to the i-th row pixel matrix in accordance with the output communication protocol; and sends the multiple display data corresponding to the i-th row pixel matrix to the multiple pixel units in the i-th row pixel matrix in sequence through DO1.

[0062] S108, the data shaping module shapes the data set corresponding to the pixel matrix from the (i+1)th row to the Nth row to obtain the (i+1)th data packet, which is then transmitted to the receiving module in the (i+1)th data processing device via DO2.

[0063] It should be noted that S106-S107 and S108 can be executed simultaneously or sequentially. For example, S106-S107 can be executed first, followed by S108, or S108 can be executed first, followed by S106-S107. This embodiment of the application does not impose any restrictions on this.

[0064] S109. The receiving module continues to receive the i-th data packet of the next frame of the current frame sent by the (i-1)-th data processing device according to the input communication protocol.

[0065] After S109, continue executing S102-S108 until the last data frame is displayed, and then the process ends.

[0066] In this example, the protocol parsing module parses the total data frame (i.e., the i-th data packet), checks if the identification information is correct, and if so, identifies the data length and verifies whether multiple pixel data points have been correctly received. If multiple pixel data points have been correctly received, row data buffering is performed. The protocol generation and output module generates and transmits truncated data through DO1, and the data shaping module generates (or transmits) the remaining data through DO2. Furthermore, if the identification information is incorrect or multiple pixel data points have not been correctly received, a new data frame is received again, improving the effectiveness and reliability of data transmission.

[0067] In some embodiments, the input communication protocol and the output communication protocol are return-to-zero (RZ) code transmission protocols; in the RZ code transmission protocol, the duration of the symbol period is inversely correlated with the data transmission rate; the sampling time of the data frame is located at the half-time of the symbol period, and a frame end marker is included between two adjacent data frames; the level transition times of 0 code and 1 code are located in the first half-cycle and the second half-cycle of the symbol period, respectively.

[0068] In one implementation, based on the Return-to-Zero (RZ) code transmission protocol, the receiving module can also be called the RZ code receiving module.

[0069] In one implementation, the level transition time for code 0 is located at 1 / 4 of the symbol period, and the level transition time for code 1 is located at 3 / 4 of the symbol period.

[0070] In this embodiment of the application, the data processing device can use the Return-to-Zero (RZ) code transmission protocol to transmit data. The data transmission rate can be selected from 100 kilobits per second (kbps) to 2.5 megabits per second (Mbps). The RZ code transmission protocol is as follows: each symbol starts with a high level, and each symbol must also have a low level. The width of the high level determines whether the symbol is a "0" or a "1".

[0071] Input communication protocol format as follows Figure 8 As shown, Figure 8 This is a schematic diagram of an input communication protocol format provided in an embodiment of this application. Figure 8 The input code pattern is shown, with a symbol period of T. T is inversely correlated with the data transmission rate; the smaller T is, the higher the data transmission rate, and vice versa. H represents high level, and L represents low level. The level transition of the 0 code occurs in the first half of the period, and the level transition of the 1 code occurs in the second half of the period. Of course, the level transition of the 0 code can also occur in the second half of the period, and correspondingly, the level transition of the 1 code can occur in the first half of the period, as long as the 0 and 1 codes can be distinguished.

[0072] The sampling time of the data frame is T / 2. Thus, the level transition times of code 0 and code 1 are located before and after the sampling time, respectively. For example, the level transition time of code 0 is located at T / 4, and the level transition time of code 1 is located at 3T / 4, which can improve data reliability.

[0073] Taking 800kbps return-to-zero code data as an example, the format requirements of the input communication protocol at an 800kbps return-to-zero code protocol rate are shown in Table 1 below.

[0074] Table 1

[0075] The sum of T0H and T0L for code 0 equals T, and the sum of T1H and T1L for code 1 equals T. In Table 1 above, due to signal attenuation during data transmission, a minimum value for T0H needs to be set; since the sampling time of the data frame is at T / 2, a maximum value for T0H needs to be set to reduce the impact on sampling. The minimum value for T1H needs to be set greater than the maximum value for T0H to distinguish between code 0 and code 1; since each symbol has a low level, a minimum value for T1L also needs to be set. In Table 1 above, the maximum value of T0H (400) is less than 1200 / 2, located in the first half of the symbol period, while the minimum value of T1H (650) is greater than 1200 / 2, located in the second half of the symbol period.

[0076] like Figure 8 As shown, a frame end marker is included between two adjacent data frames, which can be represented by a Reset signal. The Reset signal is low (L), and the Reset code (which can be represented by the symbol Trst) is located after the 0 or 1 code, used to separate two adjacent data frames. The input communication protocol timing is: Trst + first data packet + second data packet + ... + Nth data packet + Trst. The data transmission order is either high-order bit first or low-order bit first, which is not limited in this embodiment. The data length of each data packet is: 1 bit (Byte) identification information 0x96 + 2 bytes data length + N bytes pixel data + 1 byte check code. Among them, the 2 bytes data length represents the number of pixels carried by the data processing device DO1, that is, it carries N pixels and the data length is N. The pixel data includes R / G / B (red, green, and blue primary colors) pulse width modulation (PWM) dimming data.

[0077] The data transmission rate of the Return-to-Zero (ROZ) code transmission protocol output by DO1 can be selected from 100kbps to 2.5Mbps; in one implementation, the data transmission rate can be selected as 800kbps. The output communication protocol format is as follows: Figure 9 As shown, Figure 9 This is a schematic diagram of an output communication protocol format provided in an embodiment of this application. The high level time of code 1 is 750ns (i.e., T1H is 0.75 us) and the low level time is 450ns (i.e., T1L is 0.45 us); the high level time of code 0 is 300ns (i.e., T0H is 0.3 us) and the low level time is 900ns (i.e., T0L is 0.9 us).

[0078] It should be noted that the high-level time of code 1 in the input communication protocol and the high-level time of code 1 in the output communication protocol can be the same or different. Correspondingly, the high-level time of code 0 in the input communication protocol and the high-level time of code 0 in the output communication protocol can be the same or different. This application does not impose any restrictions on this.

[0079] In this embodiment, the input and output communication protocols employ a return-to-zero (RZ) code transmission protocol. Each symbol is separated by a low-level (i.e., zero-level) interval to reduce signal interference and improve data transmission stability. An end-of-frame marker is included between adjacent data frames to ensure the accuracy and stability of data transmission. The sampling time of the data frame is located at the halfway point of the symbol period, and the level transition times for 0 and 1 symbols (i.e., level returning to zero) are located before and after the sampling time, respectively, reducing the impact on sampling. In each symbol period, the signal level must return to zero. This encoding method effectively reduces the bit error rate and enhances the reliability of data transmission.

[0080] Based on the above Figures 3-9 ,like Figure 10 As shown, Figure 10 This is a schematic diagram illustrating another data transmission method provided in an embodiment of this application. Figure 10 Taking N=3 as an example, the data processing process of data processing device 1, data processing device 2 and data processing device 3 on data frames (including the (n-1)th frame, the nth frame and the (n+1)th frame) is shown. The (n-1)th frame, the nth frame and the (n+1)th frame are separated by the Trst symbol. The N in the N data processing devices is not related to the n in the nth frame. It is just a symbol to represent a positive integer.

[0081] The data bus transmission module is used for data frame bus input, transmitting the first data packet of the (n-1)th frame to data processing device 1. This data packet includes a first row of data packets, a second row of data packets, and a third row of data packets. Data processing device 1 intercepts the first data packet of the (n-1)th frame and outputs the first row of pixel data of the (n-1)th frame through DO1. This row includes M pixel data points: 1-1 pixel data to 1-M pixel data. Data processing device 1 outputs the second data packet of the (n-1)th frame through DO2. This row includes a second row of data packets. Data processing device 2 intercepts the second data packet of the (n-1)th frame and outputs the second row of pixel data of the (n-1)th frame through DO1. This row includes P pixel data points: 2-1 pixel data to 2-P pixel data. Data processing device 2 outputs the third data packet of the (n-1)th frame through DO2. This third row includes data packets.

[0082] After the interval Trst, the data bus transmission module transmits the first data packet of the nth frame to data processing device 1. Data processing device 1 intercepts the first data packet of the nth frame, outputs the first row of pixel data of the nth frame through DO1, and outputs the second data packet of the nth frame through DO2. Data processing device 2 intercepts the second data packet of the nth frame, outputs the second row of pixel data of the nth frame through DO1, and outputs the third data packet of the nth frame through DO2. Data processing device 3 intercepts the third data packet of the nth frame, outputs the third row of pixel data of the nth frame through DO1, and outputs no data through DO2.

[0083] Similarly, after the interval Trst, the data bus transmission module transmits the first data packet of the (n+1)th frame to data processing device 1. Data processing device 1 outputs the first row of pixel data of the (n+1)th frame through DO1, and the second data packet of the (n+1)th frame through DO2. Data processing device 2 intercepts the second data packet of the (n+1)th frame, outputs the second row of pixel data of the (n+1)th frame through DO1, and outputs the third data packet of the (n+1)th frame through DO2. Data processing device 3 intercepts the third data packet of the (n+1)th frame, outputs the third row of pixel data of the (n+1)th frame through DO1, and outputs no data through DO2.

[0084] The above Figure 10 The data streams for the first, second, and third rows of pixels are shown, and the timing of the data streams for adjacent data frames is described. For the data bus transmission module and DO2 output, 2.5MHz or 800KHz can be selected, and for DO1 output, 800KHz can be selected.

[0085] In this example, for each data frame, the data processing device intercepts the data in that row and forwards (or transmits through) the remaining data. Each row of the pixel matrix is ​​independent of the others, and the data for each row of pixels is transmitted independently, improving the reliability of the display effect.

[0086] This application provides a driving scheme for a display control system, the above-mentioned Figure 3 The diagram illustrates the connection method between N data processing devices and N rows of pixel matrix in the display control system. Figure 4 , Figure 5 and Figure 10 The above illustrates the drive data transmission method. Figure 8 and Figure 9The protocol data structure (i.e., the communication protocol format) is shown. The data processing device intercepts the data packets belonging to the pixels in the current row as the data for that row, and then forwards the remaining data directly to the next cascaded data processing device via DO2. The data is transmitted sequentially in this manner until the last data processing device. Each row of the pixel matrix is ​​independent of each other, and the data of each row of pixels is transmitted independently, which improves the reliability of the display effect.

[0087] It should be noted that the display control system provided in the above embodiments is only illustrated by the division of the above functional modules when transmitting data and controlling the display pixel data. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0088] The functional units and modules in the above embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of the embodiments of this application.

[0089] Based on the display control system provided in any of the above embodiments, this application provides a display chip, which includes N data processing devices and N rows of pixel matrices, where N is a positive integer greater than 1, and each row of pixel matrix includes multiple pixel units; i is a positive integer greater than 1 and less than N; the i-th data processing device receives the i-th data packet of the current frame sent by the (i-1)-th data processing device, and intercepts the i-th data packet to obtain multiple pixel data corresponding to the i-th row of pixel matrix and the (i+1)-th data packet; the (i+1)-th data packet includes the data set corresponding to the (i+1)-th to the N-th row of pixel matrix; the i-th data processing device sequentially transmits the multiple pixel data corresponding to the i-th row of pixel matrix to the multiple pixel units in the i-th row of pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device; the multiple pixel units in the i-th row of pixel matrix display accordingly based on the multiple pixel data corresponding to the i-th row of pixel matrix. This solution adopts a multi-row pixel matrix layout, which reduces the capacitor load; each row of pixel matrix is ​​independent of each other, and the data of each row of pixels is transmitted independently. If one pixel unit fails, it will not affect the lighting or display of other rows of pixel matrix, thus improving the reliability of the display effect.

[0090] The display chip and display control system embodiments provided in the above embodiments belong to the same concept. For the specific working process and technical effects of the above embodiments, please refer to the system embodiment section, which will not be repeated here.

[0091] Based on the display control system provided in any of the above embodiments, this application provides a display control method, such as... Figure 11 As shown, Figure 11 This is a flowchart of a display control method provided in an embodiment of this application. The display control method includes: S201. The i-th data packet of the current frame sent by the (i-1)-th data processing device is received by the i-th data processing device, and the i-th data packet is intercepted to obtain multiple pixel data corresponding to the i-th row pixel matrix and the (i+1)-th data packet; the (i+1)-th data packet includes the data set corresponding to the (i+1)-th row pixel matrix to the N-th row pixel matrix.

[0092] S202, the i-th data processing device sequentially transmits the data of multiple pixels corresponding to the i-th row pixel matrix to multiple pixel units in the i-th row pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device, so that the multiple pixel units in the i-th row pixel matrix are displayed according to the data of multiple pixels corresponding to the i-th row pixel matrix.

[0093] In one possible implementation, the step of sequentially transmitting the data of multiple pixel points corresponding to the i-th row pixel matrix to multiple pixel units in the i-th row pixel matrix via the i-th data processing device can also be implemented as follows: the i-th data processing device generates multiple display data corresponding to the i-th row pixel matrix according to the multiple pixel point data of the i-th row pixel matrix and an output communication protocol; the multiple display data corresponding to the i-th row pixel matrix is ​​sequentially sent to the multiple pixel units in the i-th row pixel matrix; so that the multiple pixel units in the i-th row pixel matrix display accordingly based on the multiple display data corresponding to the i-th row pixel matrix.

[0094] In some embodiments, in the above Figure 11 Following S202, the display control method further includes the following steps: the (i+1)th data processing device continues to intercept the i-th data packet until the Nth data processing device receives the N-th data packet sent by the (N-1)th data processing device; the N-th data packet includes multiple pixel data corresponding to the Nth row pixel matrix; the multiple pixel data corresponding to the Nth row pixel matrix are sequentially transmitted to multiple pixel units in the Nth row pixel matrix; so that the multiple pixel units in the Nth row pixel matrix are displayed accordingly based on the multiple pixel data corresponding to the Nth row pixel matrix.

[0095] In some embodiments, the display control system further includes a data bus transmission module; the data bus transmission module is connected to the first data processing device. The display control method further includes the following steps: encapsulating the entire frame data of the current frame through the data bus transmission module to obtain the first data packet of the current frame, and transmitting the first data packet to the first data processing device; the first data packet includes a data set corresponding to the first row of pixel matrices to the Nth row of pixel matrices; the first data processing device truncates the first data packet to obtain multiple pixel data points corresponding to the first row of pixel matrices and a second data packet; the second data packet includes a data set corresponding to the second row of pixel matrices to the Nth row of pixel matrices.

[0096] In some embodiments, the step of encapsulating the entire frame data of the current frame through the data bus transmission module to obtain the first data packet of the current frame can be implemented in the following way: the entire frame data of the current frame is encapsulated through the data bus transmission module according to at least one of the following: the data length corresponding to each row of the pixel matrix in the N-row pixel matrix, the identification code belonging to the data frame to be processed, and the preset verification method, to obtain the first data packet of the current frame.

[0097] In some embodiments, this application also provides a display method, wherein the i-th data processing device receives the i-th data packet according to an input communication protocol; the i-th data packet is parsed to obtain a data set corresponding to the i-th row pixel matrix to the N-th row pixel matrix; multiple pixel data points are extracted from the data set corresponding to the i-th row pixel matrix to the N-th row pixel matrix as multiple pixel data points corresponding to the i-th row pixel matrix; the data set corresponding to the (i+1)-th row pixel matrix to the N-th row pixel matrix is ​​shaped to obtain the (i+1)-th data packet; the multiple pixel data points corresponding to the i-th row pixel matrix are buffered; multiple display data points corresponding to the i-th row pixel matrix are generated according to the output communication protocol based on the multiple pixel data points corresponding to the i-th row pixel matrix; the multiple display data points corresponding to the i-th row pixel matrix are sequentially sent to multiple pixel units in the i-th row pixel matrix; so that the multiple pixel units in the i-th row pixel matrix are displayed accordingly based on the multiple display data points corresponding to the i-th row pixel matrix.

[0098] In some embodiments, this application also provides a display method in which the i-th data processing device receives the i-th data packet according to an input communication protocol; the i-th data packet is parsed to obtain a parsing result and a data set corresponding to the i-th row pixel matrix to the N-th row pixel matrix; the parsing result includes at least one of identification information, the i-th row checksum, and the i-th row data length; if the identification information indicates that the current frame belongs to the data frame to be processed, identification is performed in the data set corresponding to the i-th row pixel matrix to the N-th row pixel matrix according to the i-th row data length to obtain multiple pixel data corresponding to the i-th row pixel matrix; the data set corresponding to the (i+1)-th row pixel matrix to the N-th row pixel matrix is ​​shaped to obtain the (i+1)-th data packet. If the multiple pixel data corresponding to the i-th row pixel matrix is ​​correctly received according to the i-th row checksum, the multiple pixel data corresponding to the i-th row pixel matrix is ​​buffered. Based on the pixel data corresponding to the i-th row of the pixel matrix, multiple display data corresponding to the i-th row of the pixel matrix are generated according to the output communication protocol; the multiple display data corresponding to the i-th row of the pixel matrix are sent sequentially to the multiple pixel units in the i-th row of the pixel matrix; so that the multiple pixel units in the i-th row of the pixel matrix display accordingly based on the multiple display data corresponding to the i-th row of the pixel matrix.

[0099] In some embodiments, the display method further includes the following steps: if the i-th data processing device determines that the identification information indicates that the current frame does not belong to the data frame to be processed, or if it determines that the data of multiple pixels corresponding to the i-th row pixel matrix has not been correctly received according to the i-th row check code, it continues to receive the i-th data packet of the next frame of the current frame sent by the (i-1)-th data processing device in accordance with the input communication protocol.

[0100] The display control method and the display control system provided in the above embodiments belong to the same concept. For the specific working process and technical effects of the above embodiments, please refer to the system embodiments section, which will not be repeated here.

[0101] Based on the display control method provided in the above embodiments, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the above method embodiments.

[0102] This application provides a computer program product that, when run on a computer, causes the computer to perform the steps described in the various method embodiments above.

[0103] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above method embodiments of this application can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate form. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographing device / terminal device, a recording medium, a computer memory, ROM (Read-Only Memory), RAM (Random Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, and optical data storage devices. The computer-readable storage medium mentioned in this application can be a non-volatile storage medium; in other words, it can be a non-transient storage medium.

[0104] It should be understood that all or part of the steps of the above embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. The computer instructions can be stored in the above-described computer-readable storage medium.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0106] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display control system, characterized in that, The display control system includes N data processing devices, where N is a positive integer greater than 1. The N data processing devices are respectively connected to N rows of pixel matrices, and each row of pixel matrix includes multiple pixel units; i is a positive integer greater than 1 and less than N. The i-th data processing device receives the i-th data packet of the current frame sent by the (i-1)-th data processing device, and extracts the i-th data packet to obtain multiple pixel data corresponding to the i-th row of the pixel matrix and the (i+1)-th data packet. The (i+1)th data packet includes the data set corresponding to the pixel matrix in the (i+1)th row to the pixel matrix in the Nth row; The i-th data processing device sequentially transmits the data of multiple pixels corresponding to the i-th row pixel matrix to multiple pixel units in the i-th row pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device. This allows multiple pixel units in the i-th row of the pixel matrix to be displayed according to the corresponding pixel data of the i-th row of the pixel matrix.

2. The display control system as described in claim 1, characterized in that, The (i+1)th data processing device continues to intercept the ith data packet until the Nth data processing device receives the Nth data packet sent by the (N-1)th data processing device; the Nth data packet includes multiple pixel data corresponding to the Nth row of the pixel matrix; The Nth data processing device sequentially transmits the data of multiple pixels corresponding to the Nth row of the pixel matrix to multiple pixel units in the Nth row of the pixel matrix; This allows multiple pixel units in the Nth row of the pixel matrix to be displayed according to the corresponding pixel data of the Nth row of the pixel matrix.

3. The display control system as described in claim 1, characterized in that, The display control system further includes a data bus transmission module; the data bus transmission module is connected to the first data processing device; The data bus transmission module encapsulates the entire frame data of the current frame to obtain the first data packet of the current frame, and transmits the first data packet to the first data processing device; the first data packet includes the data set corresponding to the pixel matrix from the first row to the Nth row. The first data processing device intercepts the first data packet to obtain multiple pixel data points corresponding to the first row of pixel matrix and a second data packet; the second data packet includes the data set corresponding to the second row of pixel matrix to the Nth row of pixel matrix.

4. The display control system as described in claim 3, characterized in that, The data bus transmission module encapsulates the entire frame data of the current frame according to at least one of the following: the data length corresponding to each row of the pixel matrix in the N-row pixel matrix, the identification code belonging to the data frame to be processed, and the preset verification method, to obtain the first data packet of the current frame.

5. The display control system according to any one of claims 1-4, characterized in that, Each data processing device includes a receiving module, a protocol parsing module, a data buffering module, and a protocol generation and output module; The receiving module receives the i-th data packet according to the input communication protocol; The protocol parsing module parses the i-th data packet to obtain the data set corresponding to the i-th row pixel matrix to the N-th row pixel matrix, and extracts multiple pixel data from the data set corresponding to the i-th row pixel matrix as multiple pixel data corresponding to the i-th row pixel matrix; The data caching module caches the data of multiple pixels corresponding to the i-th row of the pixel matrix; The protocol generation output module generates multiple display data corresponding to the i-th row pixel matrix according to the multiple pixel data corresponding to the i-th row pixel matrix and in accordance with the output communication protocol; and sequentially sends the multiple display data corresponding to the i-th row pixel matrix to multiple pixel units in the i-th row pixel matrix; This allows multiple pixel units in the i-th row pixel matrix to be displayed according to multiple display data corresponding to the i-th row pixel matrix.

6. The display control system as described in claim 5, characterized in that, Each data processing device also includes a data shaping module; The data shaping module performs data shaping on the data set corresponding to the pixel matrix in row i+1 to row N to obtain the data packet in row i+1.

7. The display control system as described in claim 5, characterized in that, The protocol parsing module parses the i-th data packet to obtain the parsing result and the data set corresponding to the pixel matrix from the i-th row to the N-th row; The parsing result includes at least one of the following: identification information, check code of the i-th row, and data length of the i-th row; When the identification information indicates that the current frame belongs to the data frame to be processed, the identification is performed in the data set corresponding to the pixel matrix from the i-th row to the N-th row according to the length of the i-th row data, so as to obtain multiple pixel data corresponding to the i-th row pixel matrix; When the protocol parsing module determines that the data of multiple pixels corresponding to the i-th row pixel matrix has been correctly received based on the i-th row checksum, the data caching module caches the data of multiple pixels corresponding to the i-th row pixel matrix.

8. The display control system as described in claim 7, characterized in that, If the protocol parsing module determines that the identification information indicates that the current frame does not belong to the data frame to be processed, or if the data of multiple pixels corresponding to the pixel matrix in the i-th row is not correctly received according to the i-th row check code, the receiving module continues to receive the i-th data packet of the next frame of the current frame sent by the (i-1)-th data processing device according to the input communication protocol.

9. The display control system as described in claim 5, characterized in that, The input communication protocol and the output communication protocol are return-to-zero code transmission protocols; in the return-to-zero code transmission protocol, the duration of the symbol period is inversely correlated with the data transmission rate; the sampling time of the data frame is located at half the time of the symbol period, and a frame end marker is included between two adjacent data frames; The level transition times for 0 and 1 codes are located in the first half and the latter half of the symbol period, respectively.

10. A display chip, characterized in that, The display chip includes a display control system as described in any one of claims 1-9, and an N-row pixel matrix.

11. A display control method, characterized in that, The method is applied to a display control system as described in any one of claims 1-9 above, the display control system comprising N data processing devices, where N is a positive integer greater than 1, the N data processing devices being respectively connected to N rows of pixel matrices, each row of pixel matrix comprising multiple pixel units; i is a positive integer greater than 1 and less than N; The display control method includes: The i-th data packet of the current frame sent by the (i-1)-th data processing device is received by the i-th data processing device, and the i-th data packet is truncated to obtain multiple pixel data corresponding to the i-th row pixel matrix and the (i+1)-th data packet; the (i+1)-th data packet includes the data set corresponding to the (i+1)-th row pixel matrix to the N-th row pixel matrix. The i-th data processing device sequentially transmits the data of multiple pixels corresponding to the i-th row of the pixel matrix to multiple pixel units in the i-th row of the pixel matrix, and transmits the (i+1)-th data packet to the (i+1)-th data processing device; so that the multiple pixel units in the i-th row of the pixel matrix are displayed according to the data of multiple pixels corresponding to the i-th row of the pixel matrix.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in claim 11.

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