Gate drive circuit and display device including gate driver

Abstract

Disclosed are a gate driving circuit and a display device including a gate driver. The display device includes a display panel configured to display an image, and a gate driver including a shift register configured to generate a signal for controlling a transistor included in the display panel, wherein the shift register includes a first scan transistor turned on to output a first level signal through an output terminal based on a voltage of a Q node, a second scan transistor turned on to output a second level signal through the output terminal based on a voltage of a QB node, a third scan transistor turned on in response to a clock signal applied through a clock signal line to transmit a start signal applied through a start signal line to the Q node, and a CMOS transistor configured to control the QB node based on the voltage of the Q node.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0182712, filed on December 10, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to gate drive circuits (or gate drivers) and display devices including gate drivers. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. As a result, the use of display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0005] The aforementioned display device includes: a display panel comprising subpixels; a driver that outputs a drive signal to drive the display panel; and a power supply that generates power to be supplied to the display panel or the driver.

[0006] When drive signals such as scan signals and data signals are supplied to the sub-pixels formed on the display panel, the aforementioned display device can display an image by allowing the selected sub-pixels to transmit light or emit light directly. Summary of the Invention

[0007] Therefore, this disclosure relates to a gate driver and a display device including the gate driver, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0008] The purpose of this disclosure is to provide a gate driver and a display device including the gate driver, which can reduce the number of transistors used to control QB nodes based on CMOS transistors and solve problems caused by current leakage based on shift registers including oxide semiconductors.

[0009] Another object of this disclosure is to provide a gate driver and a display device including the gate driver, which can improve operational stability and operational reliability based on a shift register including at least one of oxide semiconductor or low-temperature polysilicon semiconductor.

[0010] Further advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon studying the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0011] To achieve these objectives and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; and a gate driver including a shift register configured to generate signals for controlling transistors included in the display panel, wherein the shift register includes: a first scan transistor turned on based on a voltage of a Q node to output a first level signal via an output terminal; a second scan transistor turned on based on a voltage of a QB node to output a second level signal via an output terminal; a third scan transistor turned on in response to a clock signal applied via a clock signal line to transmit a start signal applied via a start signal line to the Q node; and a CMOS transistor configured to control the QB node based on the voltage of the Q node.

[0012] The CMOS transistor may include: a fourth scan transistor having a gate electrode connected to a Q node, a first electrode connected to a first voltage line through which a first voltage is transmitted, and a second electrode connected to a QB node; and a fifth scan transistor having a gate electrode connected to a Q node, a first electrode connected to a second voltage line through which a second voltage is transmitted, and a second electrode connected to a QB node.

[0013] The fourth scanning transistor can be a p-type transistor based on polysilicon semiconductor, and the fifth scanning transistor can be an n-type transistor based on oxide semiconductor.

[0014] The first scan transistor, the second scan transistor, and the third scan transistor can be n-type transistors based on oxide semiconductors.

[0015] The display device may further include: a first scanning capacitor having a first electrode connected to the gate electrode of a first scanning transistor and a second electrode connected to an output terminal; and a second scanning capacitor having a first electrode connected to the gate electrode of a second scanning transistor and a second electrode connected to a second voltage line.

[0016] The gate driver may include: a scan driver configured to supply a scan signal to the display panel; and an transmit control signal driver configured to supply a transmit control signal to the display panel, and a shift register may be included in at least one of the scan driver and the transmit control signal driver.

[0017] The gate driver may include: a first scan driver configured to supply a first scan signal to a display panel; a second scan driver configured to supply a second scan signal to the display panel; a third scan driver configured to supply a third scan signal to the display panel; a fourth scan driver configured to supply a fourth scan signal to the display panel; and a transmit control signal driver configured to supply a transmit control signal to the display panel, and the shift register may be included in at least one of the first scan driver, the third scan driver, the fourth scan driver, and the transmit control signal driver.

[0018] In another aspect of this disclosure, the gate drive circuit includes: a first scan transistor that is turned on based on the voltage of the Q node to output a first level signal through an output terminal; a second scan transistor that is turned on based on the voltage of the QB node to output a second level signal through an output terminal; a third scan transistor that is turned on in response to a clock signal applied through a clock signal line to transmit a start signal applied through a start signal line to the Q node; and a CMOS transistor configured to control the QB node based on the voltage of the Q node.

[0019] The CMOS transistor may include: a fourth scan transistor having a gate electrode connected to a Q node, a first electrode connected to a first voltage line through which a first voltage is transmitted, and a second electrode connected to a QB node; and a fifth scan transistor having a gate electrode connected to a Q node, a first electrode connected to a second voltage line through which a second voltage is transmitted, and a second electrode connected to a QB node.

[0020] The first, second, third, and fifth scanning transistors can be n-type transistors based on oxide semiconductors, and the fourth scanning transistor can be a p-type transistor based on polysilicon semiconductors.

[0021] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. These drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0023] Figure 1 This is a schematic block diagram illustrating the display device;

[0024] Figure 2 This is a block diagram illustrating the configuration of the gate driver in a display device;

[0025] Figure 3 It is a cross-sectional view of the stacked structure of the display panel;

[0026] Figure 4 This is a diagram illustrating the circuit configuration of a sub-pixel according to the present disclosure;

[0027] Figure 5 and Figure 6 This illustrates the basis of this disclosure. Figure 4 A diagram of the driving waveform of the display panel implemented by sub-pixels;

[0028] Figure 7 It is used to describe based on Figure 4 A diagram illustrating the driving characteristics of the display panel implemented by subpixels;

[0029] Figure 8 This is a circuit configuration diagram of the shift register according to the first embodiment. Figure 9 It is shown Figure 8 The diagram shows the drive waveform of the shift register. Figure 10 and Figure 11 It shows that according to Figure 9 The operating state of the shift register shown in the driving waveform, and Figure 12 The output state of the shift register according to the first embodiment is shown;

[0030] Figure 13 This is a circuit configuration diagram of the shift register according to the second embodiment; and

[0031] Figure 14 This is a circuit configuration diagram of the shift register according to the third embodiment. Detailed Implementation

[0032] The display device according to this disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, a light-emitting display device that directly emits light based on inorganic light-emitting diodes or organic light-emitting diodes is used as an example of a display device.

[0033] Furthermore, the light-emitting display device described below can be implemented in the form of an n-type thin-film transistor, a p-type thin-film transistor, or both n-type and p-type thin-film transistors. A thin-film transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode through which charge carriers are supplied to the transistor. In a thin-film transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the thin-film transistor. In other words, charge carriers flow from the source to the drain in a thin-film transistor.

[0034] In the case of a p-type thin-film transistor (TFT), holes act as charge carriers, and therefore the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. Because holes flow from the source to the drain in a p-type TFT, current flows from the source to the drain. Conversely, in the case of an n-type TFT, electrons act as charge carriers, and therefore the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. Because electrons flow from the source to the drain in an n-type TFT, current flows from the drain to the source. However, the source and drain of a TFT can be changed depending on the applied voltage. To reflect this, in the following description, one of the source and drain is described as the first electrode, and the other is described as the second electrode.

[0035] Figure 1 This is a block diagram schematically showing a display device. Figure 2 This is a block diagram illustrating the configuration of the gate driver in a display device.

[0036] like Figure 1 As shown, the display device 10 may include: a display panel 100 including a plurality of sub-pixels P; a controller 200; a gate driver (gate drive circuit) 300 that supplies gate signals to the plurality of sub-pixels P; a data driver (data drive circuit) 400 that supplies data signals (or data voltages) to the plurality of sub-pixels P; and a power supply 500 that supplies power to the plurality of sub-pixels P.

[0037] The display panel 100 may include an active area in which sub-pixels P are positioned (see reference). Figure 2 AA in the middle) and non-active regions (refer to Figure 2 In the active region AA, the non-active region is positioned around the active region AA and the gate driver 300 and the data driver 400 are disposed in the non-active region.

[0038] In the display panel 100, multiple gate lines GL and multiple data lines DL intersect each other, and multiple sub-pixels P can be connected to the gate lines GL and data lines DL. Specifically, a sub-pixel P can receive a gate signal from the gate driver 300 through the gate line GL, receive a data voltage (data signal) from the data driver 400 through the data line DL, and receive a high-level voltage EVDD and a low-level voltage EVSS from the power supply 500.

[0039] Gate line GL can transmit scan signal SC and transmit control signal EM to multiple sub-pixels P, and data line DL can transmit data voltage Vdata to multiple sub-pixels P. According to various embodiments, gate line GL may include multiple scan lines SCL for supplying scan signal SC and multiple transmit control lines EML for supplying transmit control signal EM. Multiple sub-pixels P can receive voltages Vini, Var, and Vobs from multiple voltage lines VL. The voltages Vini, Var, and Vobs applied through the multiple voltage lines VL will be described below.

[0040] Each of the multiple sub-pixels P may include a sub-pixel driving circuit. The sub-pixel driving circuit may include multiple switching elements, driving elements, capacitors, etc. The switching elements and driving elements, etc., may be configured as thin-film transistors. The switching transistors can be switched according to the scan signal SC supplied via the scan line SCL and the emission control signal EM supplied via the emission control line EML. The driving transistors can control the amount of current supplied to the light-emitting element OLED (controlling the emission level) according to the data voltage Vdata.

[0041] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in transparent display devices that display images on a screen and where the actual objects in the background are visible. The display panel 100 can also be implemented as a flexible display panel. A flexible display panel can use a plastic substrate. Each of the plurality of sub-pixels P can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels for color representation. Each of the plurality of sub-pixels P may also include a white sub-pixel.

[0042] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a single touch sensor or by multiple subpixels P. The touch sensor may be implemented as an on-cell type or add-on type touch sensor disposed on the screen of the display panel, or as an in-cell type touch sensor built into the display panel 100.

[0043] The controller 200 can process externally input RGB image data to suit the size and resolution of the display panel 100 and supply it to the data driver 400. The controller 200 can use external synchronization signals, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, to generate a gate control signal GCS and a data control signal DCS. The controller 200 can control the operating timing of the gate driver 300 by supplying the gate control signal GCS to the gate driver 300. The controller 200 can control the operating timing of the data driver 400 by supplying the data control signal DCS to the data driver 400. The controller 200 can use the gate control signal GCS and the data control signal DCS to synchronize the operating timing of the gate driver 300 with the operating timing of the data driver 400.

[0044] The controller 200 can be configured to be combined with various processors, such as microprocessors, mobile processors, and application processors, depending on the device mounted thereon. The host system located in front of the controller 200 can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system.

[0045] The controller 200 can control the operation timing of the display panel driver at a frame frequency of input frame frequency × i Hz (where i is a positive integer greater than 0) by multiplying the input frame frequency by i. The input frame frequency can be 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Progressive Line Inverter) system.

[0046] The controller 200 can drive the display panel 100 at various refresh rates. The controller 200 can drive the display panel 100 in a variable refresh rate (VRR) mode, in which the display panel can switch between a first refresh rate and a second refresh rate.

[0047] For example, controller 200 can drive display panel 100 at various refresh rates by simply changing the rate of the clock signal, configuring the synchronization signal to generate horizontal or vertical blanking, or driving gate driver 300 in a mask manner. Vertical blanking can be defined as a period of time used to match the input timing of data signals and the output (display) timing of images on the display panel. Vertical blanking can repeat within a frame cycle, and various signals used for the operation of the display device can be synchronized during this period.

[0048] The voltage level of the gate control signal GCS output from controller 200 can be converted into on-state and off-state voltages by a level shifter (not shown) and supplied to gate driver 300. The level shifter can convert the low-level voltage of the gate control signal GCS to a gate low voltage VGL, and the high-level voltage of the gate control signal GCS to a gate high voltage VGH. The gate control signal GCS may include a start pulse signal and a shift clock signal.

[0049] The gate driver 300 can supply a gate signal to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driver 300 can be disposed on one or both sides of the display panel 100 in a gate in-panel (GIP) structure.

[0050] The gate driver 300 can sequentially output gate signals to multiple gate lines GL under the control of the controller 200. The gate driver 300 can sequentially supply gate signals to gate lines GL by using a shift register to shift the gate signals.

[0051] In an organic light-emitting display device, the gate signal may include a scan signal SC and an emission control signal EM. The scan signal SC may include a scan pulse that oscillates between a gate low voltage VGL and a gate high voltage VGH. The emission control signal EM may include an emission control signal pulse that oscillates between a gate on voltage VEL and a gate off voltage VEH. The scan pulse can select the sub-pixel P on the line to which the data voltage Vdata will be written. The emission control signal EM can define the emission time of the sub-pixel P.

[0052] The gate driver 300 may include a transmit control signal driver 310 and at least one scan driver 320. The transmit control signal driver 310 may output transmit control signal pulses in response to a start pulse and a shift clock from the controller 200, and may shift the transmit control signal pulses sequentially according to the shift clock. At least one scan driver 320 may output scan pulses in response to a start pulse and a shift clock from the controller 200, and may shift the scan pulses according to the shift clock timing.

[0053] The data driver 400 can convert image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and output the data voltage Vdata through the data line DL.

[0054] although Figure 1 A data driver 400 is shown disposed on one side of the display panel 100, but the number and position of the data drivers 400 are not limited thereto. That is, the data driver 400 may consist of multiple integrated circuits (ICs) disposed on one side of the display panel 100.

[0055] Power supply 500 can use a DC-DC converter to generate the DC power required to drive the sub-pixel array and display panel driver of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 500 can receive a DC input voltage applied from a host system (not shown) and generate DC voltages, such as gate voltages VGL, VEL, VGH, and VEH, high-level voltage EVDD, and low-level voltage EVSS.

[0056] like Figure 1 and Figure 2 As shown, the gate driver 300 may include an emit control signal driver 310 and a scan driver 320. The scan driver 320 may include first scan drivers to fourth scan drivers 321, 322, 323 and 324. In addition, the second scan driver 322 may include odd-numbered second scan drivers 322_O and even-numbered second scan drivers 322_E.

[0057] The shift registers constituting the gate driver 300 can be configured to be symmetrical on both sides of the active region AA. The shift registers on one side can be included in the second scan drivers 322_O and 322_E, the fourth scan driver 324, and the transmit control signal driver 310, while the shift registers on the other side can be included in the first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323. Figure 2 An example is shown where odd-numbered second scan drivers 322_O and even-numbered second scan drivers 322_E are shared by odd-numbered and even-numbered subpixels. Therefore, the transmit control signal driver 310 and the first through fourth scan drivers 321, 322, 323, and 324 can be configured differently, and this disclosure is not limited thereto.

[0058] The shift register stages STG1 to STGn may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n), third scan signal generators SC3(1) to SC3(n), fourth scan signal generators SC4(1) to SC4(n) and transmit control signal generators EM(1) to EM(n).

[0059] The first scan signal generators SC1(1) to SC1(n) can output the first scan signal through the first scan line SC1 of the display panel 100. The second scan signal generators SC2(1) to SC2(n) can output the second scan signal through the second scan line SC2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) can output the third scan signal through the third scan line SC3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) can output the fourth scan signal through the fourth scan line SC4 of the display panel 100. The transmit control signal generators EM(1) to EM(n) can output the transmit control signal through the transmit control line EM of the display panel 100.

[0060] The bias voltage line VobsL for transmitting the bias voltage Vobs, the first initialization voltage line ViniL for transmitting the first initialization voltage Vini, and the second initialization voltage line VaralL for transmitting the second initialization voltage Var can be disposed between the gate driver 300 and the active region AA.

[0061] In the accompanying drawings, the bias voltage line VobsL, the first initialization voltage line ViniL, and the second initialization voltage line VaralL are shown as being located on either the left or right side of the active region AA, but this disclosure is not limited thereto, and they may be located on both sides, and even if they are located on one side, their location is not limited to the left or right side.

[0062] Furthermore, one or more optical regions OA1 and OA2 can be disposed within the active region AA. Optical regions OA1 and OA2 can be configured to overlap with one or more optoelectronic devices, such as imaging devices (image sensors) and detection sensors such as proximity sensors and illuminance sensors.

[0063] Optical regions OA1 and OA2 can have light-transmitting structures for the operation of the optoelectronic device, and therefore can have a certain level or higher transmittance. In other words, the number of pixels per unit area in optical regions OA1 and OA2 can be less than the number of pixels per unit area in the general area of ​​the active region AA excluding optical regions OA1 and OA2. That is, the resolution of optical regions OA1 and OA2 can be lower than the resolution of the general area in the active region AA.

[0064] In optical regions OA1 and OA2, a light-transmitting structure can be formed by patterning the cathode in areas where no subpixels are set. In this case, the cathode to be patterned can be removed using a laser, or the cathode can be selectively formed and patterned using a material such as a cathode deposition prevention layer.

[0065] Furthermore, the light-transmitting structures in optical regions OA1 and OA2 can be formed separately by forming a light-emitting element and a sub-pixel driving circuit included in the sub-pixel. In other words, the light-emitting element of the sub-pixel is positioned on optical regions OA1 and OA2, and multiple transistors constituting the sub-pixel driving circuit are disposed on the periphery of optical regions OA1 and OA2, and therefore the light-emitting element and the sub-pixel driving circuit can be electrically connected through a transparent metal layer.

[0066] Figure 3 This is a cross-sectional view showing the stacked structure of the display panel.

[0067] like Figure 3 As shown, transistors TFT1 and TFT2 for driving the light-emitting element OLED disposed in the active region AA, and a first capacitor CST, can be disposed on the substrate 111 of the display panel 100. Transistors TFT1 and TFT2 may include switching thin-film transistors or driving transistors containing polycrystalline semiconductor materials and oxide thin-film transistors containing oxide semiconductor materials. In this case, the thin-film transistor containing polycrystalline semiconductor materials is referred to as polycrystalline thin-film transistor TFT1, and the thin-film transistor containing oxide semiconductor materials is referred to as oxide thin-film transistor TFT2. For example, polycrystalline thin-film transistor TFT1 can be connected to the light-emitting element OLED, and oxide thin-film transistor TFT2 can be connected to the first capacitor CST.

[0068] The substrate 111 may include a first substrate layer 111a, a second substrate layer 111b, and a third substrate layer 111c. The first substrate layer 111a and the third substrate layer 111c may be formed using an organic film including polyimide, and the second substrate layer 111b located between the first substrate layer 111a and the third substrate layer 111c may be formed using an inorganic film including silicon oxide (SiO2).

[0069] A lower buffer layer 112a can be formed on the substrate 111. The lower buffer layer 112a can be formed by stacking multiple layers of silicon oxide (SiO2) to block moisture and other substances that may penetrate from the outside. An auxiliary buffer layer 112b can be additionally formed on the lower buffer layer 112a to protect the device from moisture penetration.

[0070] A polycrystalline thin-film transistor (TFT) 1 can be formed on a substrate 111. The TFT 1 can use a polycrystalline semiconductor for its active layer. The TFT 1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes can move. A first gate insulating layer 113 can be disposed between the first gate electrode GE1 and the first active layer ACT1, and the first gate insulating layer 113 can be formed by stacking inorganic layers such as silicon oxide (SiO2) films or silicon nitride (SiNx) films into a single layer or multiple layers.

[0071] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side of the first channel region. The first source region and the first drain region are conductive regions in which the intrinsic polycrystalline semiconductor material is doped with impurity ions of Group 5 or Group 3, such as phosphorus (P) or boron (B), at a predetermined concentration. The first channel region is a region that maintains the intrinsic state of the polycrystalline semiconductor material and can provide a path for the movement of electrons or holes.

[0072] According to one embodiment, the polycrystalline thin-film transistor TFT1 can be implemented as a top-gate structure with the first gate electrode GE1 positioned on the first active layer ACT1. Therefore, the first electrode CST1 of the first capacitor CST and the light-shielding layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS through a single mask process, the number of mask processes can be reduced.

[0073] The first gate electrode GE1 can be formed of a metallic material. For example, the first gate electrode GE1 can be a single layer or multiple layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, but this disclosure is not limited thereto. A first interlayer insulating layer 114 can be disposed on the first gate electrode GE1. The first interlayer insulating layer 114 can be formed of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0074] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially stacked on a first interlayer insulating layer 114, and the polycrystalline thin-film transistor TFT1 may include a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 117 and respectively connected to a first source region and a first drain region.

[0075] The first source electrode SD1 and the first drain electrode SD2 may be a single layer or multiple layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but this disclosure is not limited thereto.

[0076] The upper buffer layer 115 can separate the second active layer ACT2 of the oxide thin film transistor TFT2 formed of oxide semiconductor material from the first active layer ACT1 formed of polycrystalline semiconductor material, and can provide a basis for forming the second active layer ACT2.

[0077] The second gate insulating layer 116 can cover the second active layer ACT2 of the oxide thin-film transistor TFT2. Since the second gate insulating layer 116 is formed on the second active layer ACT2 made of an oxide semiconductor material, an inorganic film can be used to form the second gate insulating layer 116. For example, the second gate insulating layer 116 can be formed of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0078] The second gate electrode GE2 can be formed of a metallic material. For example, the second gate electrode GE2 can be a single layer or multiple layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but this disclosure is not limited thereto.

[0079] The oxide thin-film transistor TFT2 can be formed on the upper buffer layer 115. The oxide thin-film transistor TFT2 may include a second active layer ACT2 formed of oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 117. The second active layer ACT2 may be formed of oxide semiconductor material and may include an intrinsic second channel region that is undoped and a second source region and a second drain region that are doped and therefore conductive.

[0080] The oxide thin-film transistor TFT2 may further include a light-shielding layer LS located below the upper buffer layer 115 and overlapping with the second active layer ACT2. The light-shielding layer LS can block light incident on the active layer ACT2 to ensure the reliability of the oxide thin-film transistor TFT2. The light-shielding layer LS is formed of the same material as the first gate electrode GE1 and may be formed on the upper surface of the first gate insulating layer 113. The light-shielding layer LS may also be electrically connected to the second gate electrode GE2 to form a dual gate (not shown in the figure).

[0081] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 117 from the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of masking processes.

[0082] Meanwhile, a first capacitor CST can be formed by placing a second electrode CST2 on the first interlayer insulating layer 114 to overlap with the first electrode CST1. The second electrode CST2 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0083] The first capacitor CST can store the data voltage applied through the data line DL for a predetermined time period. The first capacitor CST may include two electrodes facing each other and a dielectric disposed between the two electrodes. A first interlayer insulating layer 114 may be located between the first electrode CST1 and the second electrode CST2.

[0084] The first electrode CST1 or the second electrode CST2 of the first capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin-film transistor TFT2. However, this disclosure is not limited thereto, and the connection relationship of the first capacitor CST can be changed according to the sub-pixel driving circuit.

[0085] The first planarization layer 118 and the second planarization layer 119 can be sequentially disposed on the sub-pixel driving circuit to planarize the surface. The first planarization layer 118 and the second planarization layer 119 can be organic films formed of, for example, polyimide or acrylic resin. The light-emitting element OLED can be formed on the second planarization layer 119.

[0086] An OLED (Light Emitting Diode) may include an anode (AND), a cathode (CAT), and an emissive layer (EML) disposed between the anode (AND) and the cathode (CAT). In the case of a sub-pixel driving circuit that typically uses a low-level voltage applied to the cathode (CAT), the anode (AND) is configured as a separate electrode for each sub-pixel. Conversely, in the case of a sub-pixel driving circuit that typically uses a high-level voltage, the cathode (CAT) may also be configured as a separate electrode for each sub-pixel.

[0087] The light-emitting element OLED can be electrically connected to the driving element via an intermediate electrode CNE disposed on the first planarization layer 118. For example, the anode AND of the light-emitting element OLED and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 constituting the sub-pixel driving circuit can be connected to each other via the intermediate electrode CNE.

[0088] The anode AND can be connected to the intermediate electrode CNE exposed through a contact hole penetrating the second planarization layer 119. The intermediate electrode CNE can be connected to the first source electrode SD1 exposed through a contact hole penetrating the first planarization layer 118.

[0089] The intermediate electrode CNE can be used as a medium to connect the first source electrode SD1 and the anode AND. The intermediate electrode CNE can be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0090] The anode AND can be formed in a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be formed of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed of a single layer or multiple layers of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode AND can be formed in a structure in which the transparent conductive film, the opaque conductive film, and the transparent conductive film are sequentially stacked, or in a structure in which the transparent conductive film and the opaque conductive film are sequentially stacked. The emitter layer EML is formed by sequentially or in reverse stacking a hole-correlated layer, an organic emitter layer, and an electron-correlated layer on the anode AND.

[0091] The dam layer BNK can be a subpixel-defined film that exposes the anode AND of each subpixel. The dam layer BNK can be formed of an opaque material (e.g., black) to prevent optical interference between adjacent subpixels. In this case, the dam layer BNK can include a light-shielding material made of at least one of colored pigments, organic black, and carbon.

[0092] The cathode (CAT) can be formed on the upper and side surfaces of the emissive layer (EML) while facing the anode (AND) and the emissive layer (EML) is placed between the cathode (CAT) and the anode (AND). The cathode (CAT) can be formed to cover the entire active region (AA). When the cathode (CAT) is used in a top-emitting organic light-emitting display device, the cathode (CAT) can be formed from a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0093] An encapsulation layer 120 for inhibiting moisture penetration can be additionally disposed on the cathode (CAT). The encapsulation layer 120 can prevent moisture or oxygen from penetrating from the outside into the emitter layer (EML), which is susceptible to moisture or oxygen. For this purpose, the encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but this disclosure is not limited thereto. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 sequentially stacked.

[0094] The first encapsulation layer 121 and the third encapsulation layer 123 can be formed of an inorganic insulating material capable of low-temperature deposition (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), or aluminum oxide (Al2O3)). Because the first encapsulation layer 121 and the third encapsulation layer 123 are deposited in a low-temperature environment, damage to the high-temperature-sensitive emitter layer (EML) can be prevented during the deposition process of the first encapsulation layer 121 and the third encapsulation layer 123.

[0095] The second encapsulation layer 122 serves as a buffer to alleviate stress between layers caused by bending of the display device 10, and can flatten the steps between layers. The second encapsulation layer 122 can be formed on the substrate 111 on which the first encapsulation layer 121 is formed, using non-photosensitive organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polyethylene or silicon carbide (SiOC) or photosensitive organic insulating materials such as photoreactive acrylic acid, but the present disclosure is not limited thereto.

[0096] When the second encapsulation layer 122 is formed using an inkjet printing method, a dam DAM can be formed to prevent the liquid form of the second encapsulation layer 122 from diffusing to the edge of the substrate 111. The dam DAM can be positioned closer to the edge of the substrate 111 than the second encapsulation layer 122. According to the dam DAM, the second encapsulation layer 122 can be prevented from diffusing to the pad area at the outermost edge of the substrate 111 where conductive pads PADs (shown by reference numerals 158a, 158b, 158c, and 158d) are located.

[0097] The dam DAM is designed to prevent the diffusion of the second encapsulation layer 122. However, if the second encapsulation layer 122 is formed during the process to exceed the height of the dam DAM, the second encapsulation layer 122, as an organic layer, may be exposed to the outside, and thus moisture and the like may easily penetrate into the light-emitting element. Therefore, to prevent this, at least ten dam DAMs can be formed.

[0098] The dam DAM can be disposed on the second interlayer insulating layer 117 of the non-active region NA. The dam DAM can be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. The lower layer of the dam DAM can be formed simultaneously with the formation of the first planarization layer 118, and the upper layer of the dam DAM can be formed simultaneously with the formation of the second planarization layer 119, so that the dam DAM can be formed in a stacked structure. Therefore, the dam DAM can be formed of the same material as the first planarization layer 118 and the second planarization layer 119, but this disclosure is not limited thereto.

[0099] The dam (DAM) can be formed to overlap with the low-level voltage line (EVSS). For example, the low-level voltage line (EVSS) can be located below the region where the dam (DAM) is located in the non-active region NA. The low-level voltage line (EVSS) can be disposed outside the gate driver 300 and can surround the active region AA. For example, the low-level voltage line (EVSS) can be made of the same material as the first gate electrode GE1, but is not limited thereto, and the low-level voltage line (EVSS) can be made of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2. The low-level voltage line (EVSS) can be electrically connected to the cathode CAT to apply the low-level voltage (EVSS) to a plurality of sub-pixels included in the active region AA.

[0100] A touch layer can be disposed on the encapsulation layer 120. In the touch layer, a touch buffer film 151 can be positioned between the touch sensor metal layer, including touch electrode connection lines 152 and 154 and touch electrodes 155 and 156, and the cathode CAT of the light-emitting element OLED. The touch buffer film 151 can prevent chemicals (developing solutions or etching solutions, etc.) used in the manufacturing process of the touch sensor metal layer disposed on the touch buffer film 151 or moisture from the outside from penetrating into the emitter layer EML containing organic materials. Therefore, the touch buffer film 151 can prevent damage to the emitter layer EML, which is susceptible to chemicals or moisture.

[0101] The touch buffer film 151 can be formed of an organic insulating material that can be formed at low temperatures (e.g., 100°C or lower) to prevent damage to the emitter layer EML, which contains organic materials susceptible to high temperatures and has a low dielectric constant of 1 to 3. For example, the touch buffer film 151 can be formed of acrylic, epoxy, or siloxane-based materials. The touch buffer film 151, with its planarization properties due to the organic insulating material, can prevent damage to the encapsulation layer 120 caused by device bending and leakage of touch sensor metal formed on the touch buffer film 151.

[0102] According to the mutual capacitance-based touch sensor structure, touch electrodes 155 and 156 can be disposed on the touch buffer film 151 and can be arranged to cross each other. Touch electrode connecting lines 152 and 154 can electrically connect touch electrodes 155 and 156. Touch electrode connecting lines 152 and 154 and touch electrodes 155 and 156 can be positioned in different layers, with a touch insulating film 153 placed therebetween. Optionally, touch electrode connecting lines 152 and 154 can be arranged to overlap with the embankment layer BNK to prevent a reduction in aperture ratio.

[0103] Touch electrodes 155 and 156 can be electrically connected to a touch driver circuit (not shown) via touch pads PADs through portions of touch electrode connection line 152 passing through the upper and side surfaces of encapsulation layer 120 and the upper and side surfaces of dam DAM. A portion of touch electrode connection line 152 can receive touch drive signals from the touch driver circuit and send them to touch electrodes 155 and 156, and can also send touch sensing signals from touch electrodes 155 and 156 to the touch driver circuit.

[0104] Touch passivation film 157 may be disposed on touch electrodes 155 and 156. Although touch passivation film 157 is shown as being disposed only on touch electrodes 155 and 156, this disclosure is not limited thereto, and touch passivation film 157 may extend to the front or back of the dam DAM, and may also be disposed on touch electrode connection line 152. Color filter (not shown) may be disposed on encapsulation layer 120, and the color filter may be located on the touch layer, or located between encapsulation layer 120 and touch layer.

[0105] Figure 4 This is a diagram illustrating the circuit configuration of a subpixel according to the present disclosure. Figure 5 and Figure 6 This illustrates the basis of this disclosure. Figure 4 The diagram shows the driving waveform of the display panel implemented by the sub-pixels. Figure 7 It is used to describe based on Figure 4 A diagram showing the driving characteristics of the display panel implemented by subpixels.

[0106] like Figure 4 As shown, sub-pixel P may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a driving transistor DT, a first capacitor CST, a second capacitor CBS, and a light-emitting element OLED. Figure 4 In this embodiment, the first transistor T1 and the fifth transistor T5 are implemented as transistors based on n-type oxide semiconductors, and the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the driving transistor DT are implemented as transistors based on p-type polycrystalline semiconductors, but the implementation is not limited to this.

[0107] The first transistor T1 may have a gate electrode connected to a first scan line SC1(n), a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be turned on in response to a first scan signal applied through the first scan line SC1(n). When the first transistor T1 is turned on, the threshold voltage of the driving transistor DT may be sampled.

[0108] The second transistor T2 may have a gate electrode connected to the second scan line SC2(n), a first electrode connected to the data line (DL), and a second electrode connected to the first node (N1). The second transistor T2 may be turned on in response to a second scan signal applied through the second scan line SC2(n). When the second transistor T2 is turned on, the data voltage Vdata applied through the data line DL can be transmitted to the first node N1.

[0109] The third transistor T3 may have a gate electrode connected to the emit control signal line EM(n), a first electrode connected to the high-level voltage line EVDD, and a second electrode connected to the first node N1. The third transistor T3 may be turned on in response to an emit control signal applied through the emit control signal line EM(n). When the third transistor T3 is turned on, a high-level voltage applied through the high-level voltage line EVDD may be transmitted to the first node N1.

[0110] The fourth transistor T4 may have a gate electrode connected to the emission control signal line EM(n), a first electrode connected to the third node N3, and a second electrode connected to the anode of the light-emitting element OLED. The fourth transistor T4 may be turned on in response to an emission control signal applied via the emission control signal line EM(n). When the fourth transistor T4 is turned on, a drive current generated from the driving transistor DT can be transmitted to the light-emitting element OLED. When the fourth transistor T4 is turned on, the light-emitting element OLED can emit light based on the drive current generated from the driving transistor DT.

[0111] The fifth transistor T5 may have a gate electrode connected to the fourth scan line SC4(n), a first electrode connected to the first initialization voltage line Vinil, and a second electrode connected to the second node N2. The fifth transistor T5 may be turned on in response to a fourth scan signal applied through the fourth scan line SC4(n). When the fifth transistor T5 is turned on, the first initialization voltage applied through the first initialization voltage line Vinil can be transmitted to the second node N2. When the fifth transistor T5 is turned on, residual charges present in the gate electrode of the driving transistor DT connected to the second node N2, the second electrode of the first capacitor CST, and the second electrode of the second capacitor CBS can be initialized.

[0112] The sixth transistor T6 may have a gate electrode connected to the third scan line SC3(n), a first electrode connected to the second initialization voltage line VaralL, and a second electrode connected to the anode of the light-emitting element OLED. The sixth transistor T6 may be turned on in response to a third scan signal applied through the third scan line SC3(n). When the sixth transistor T6 is turned on, the second initialization voltage applied through the second initialization voltage line VaralL can be transmitted to the anode of the light-emitting element OLED. When the sixth transistor T6 is turned on, residual charge present in the anode of the light-emitting element OLED can be initialized.

[0113] The seventh transistor T7 may have a gate electrode connected to the third scan line SC3(n), a first electrode connected to the bias voltage line VobsL, and a second electrode connected to the first node N1. The seventh transistor T7 can be turned on in response to a third scan signal applied through the third scan line SC3(n). When the seventh transistor T7 is turned on, the bias voltage applied through the bias voltage line VobsL can be transmitted to the first node N1. When the seventh transistor T7 is turned on, the driving transistor DT connected to the first node N1 can maintain a stronger saturation state through the bias voltage. Therefore, the time required to charge the anode of the light-emitting element OLED during the emission period can be reduced or delayed.

[0114] For example, as the bias voltage Vobs increases, the voltage at the third node N3, which is the drain electrode of the driving transistor DT, increases, and the gate-source voltage or drain-source voltage of the driving transistor DT decreases. Therefore, it is preferable that the bias voltage Vobs is at least higher than the data voltage Vdata. Under such conditions, the magnitude of the drain-source current Id through the driving transistor DT can be reduced, the stress on the driving transistor DT can be reduced, and thus the charging delay at the third node N3 can be eliminated. In other words, if the conduction bias stress operation is performed before sampling the threshold voltage of the driving transistor DT, the hysteresis of the driving transistor DT can be mitigated.

[0115] The driving transistor DT may have a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The driving transistor DT may operate based on the data voltage Vdata stored in the first capacitor CST and may generate a drive current.

[0116] The first capacitor CST may have a first electrode connected to the high-level voltage line EVDD and a second electrode connected to the second node N2. The first capacitor CST may store the data voltage Vdata for a certain period of time and then pass it to the gate electrode of the driving transistor DT.

[0117] The second capacitor CBS may have a gate electrode connected to the second transistor T2, a first electrode connected to the second scan line SC2(n), and a second electrode connected to the second node N2. The second capacitor CBS may be used to compensate for voltage changes at the second node N2 based on a second scan signal applied through the second scan line SC2(n) (e.g., to perform a voltage boost for voltage drop compensation).

[0118] The OLED light-emitting element can have an anode connected to a second electrode of a fourth transistor T4 and a cathode connected to a low-level voltage line EVSS. The OLED light-emitting element can emit light in response to a drive current transmitted through the conducting fourth transistor T4.

[0119] based on Figure 4 The display panel implemented by the sub-pixel P can be based on Figure 5 The driving waveform shown is driven in the first driving mode, and can be based on Figure 6 The driving waveform shown is driven in the second driving mode. The first driving mode can be included in the programming frame for high-speed driving of the display panel, and the second driving mode can be included in the anode reset frame for low-speed driving of the display panel.

[0120] like Figure 5 and Figure 6 As shown, the first scan signal SC1, the second odd-numbered scan signal SC2_O, the second even-numbered scan signal SC2_E, the third scan signal SC3, and the fourth scan signal SC4 can be generated based on the gate high voltage VGH and the gate low voltage VGL, and their pulse shapes can vary according to the driving mode. On the other hand, the transmit control signal EM can be generated based on the gate on voltage VEL and the gate off voltage VEH, and its pulse shape can remain unchanged according to the driving mode.

[0121] However, Figure 5 and Figure 6 The driving waveforms shown are merely examples, and this disclosure is not limited thereto.

[0122] Furthermore, based on Figure 4 The display panel implemented with subpixels should be interpreted as an example corresponding to a type of subpixel P that can be driven based on a gate driver, which will be described below.

[0123] like Figure 1 and Figure 7As shown, the display panel 100 can operate in a variable refresh rate (VRR) mode based on the driving waveform described above. VRR mode is a driving method that reduces power consumption by driving the display panel at a constant driving frequency and then increasing or decreasing the refresh rate required to update the data voltage Vdata according to high-speed or low-speed driving conditions. For example, the display panel 100 can change the driving speed, such as driving one frame at 120 Hz (1 frame = 1 / 120 second), driving one frame at 60 Hz (1 frame = 1 / 60 second), or driving one frame at 24 Hz (1 frame = 1 / 24 second).

[0124] Under high-speed drive conditions such as 120 Hz, each frame may include a refresh frame that can refresh the data voltage Vdata (which can refresh the image). On the other hand, under low-speed drive conditions such as 60 Hz or 24 Hz, the data voltage Vdata may be refreshed every N frames (N is an integer equal to or greater than 1), and an anode reset frame may be included between refresh frames.

[0125] The anode reset frame is a subframe and is operable, making it possible to display a normal image on the display panel 100 even within this frame. However, the anode reset frame can be executed under low-speed drive conditions. Therefore, the anode reset frame is a frame with very little image movement or displays a static image, and thus, the output of the scan signal can be performed only when the output of the data voltage Vdata is stopped, but this disclosure is not limited thereto.

[0126] Figure 8 This is a circuit configuration diagram of the shift register according to the first embodiment. Figure 9 It is shown Figure 8 The diagram shows the drive waveform of the shift register. Figure 10 and Figure 11 It shows that according to Figure 9 The operating state of the shift register shown in the driving waveform, and Figure 12 The output state of the shift register according to the first embodiment is shown.

[0127] like Figure 8 As shown, the Nth shift register (N is any number) according to the first embodiment may include a first scan transistor ST1, a second scan transistor ST2, a third scan transistor ST3, a fourth scan transistor ST4, a fifth scan transistor ST5, a first scan capacitor CBST, and a second scan capacitor CQB.

[0128] The first scanning transistor ST1, the second scanning transistor ST2, the third scanning transistor ST3, and the fifth scanning transistor ST5 can be n-type transistors implemented based on oxide semiconductors. The fourth scanning transistor ST4 can be a p-type transistor implemented based on low-temperature polysilicon (LTPS) semiconductors. n-type transistors have low leakage characteristics, and p-type transistors have high mobility characteristics. Therefore, the Nth shift register according to the first embodiment can have both low leakage and high mobility characteristics.

[0129] The first scan transistor ST1 may have a gate electrode connected to the Q node Q, a first electrode connected to a gate high voltage line (or first voltage line) VGH through which the gate high voltage is transmitted, and a second electrode connected to the output terminal (Gout). The first scan transistor ST1 may be turned on based on the voltage of the Q node Q and may output a first level scan signal based on the gate high voltage.

[0130] The first scan capacitor CBST may have a first electrode connected to the Q node Q and a second electrode connected to the output terminal Gout. The first scan capacitor CBST may perform bootstrapping, causing the voltage at the Q node Q to increase.

[0131] The second scan transistor ST2 may have a gate electrode connected to the QB node QB, a first electrode connected to the gate low voltage line (or second voltage line) VGL through which the gate low voltage is transmitted, and a second electrode connected to the output terminal Gout. The second scan transistor ST2 may be turned on based on the voltage of the QB node QB and may output a second-level scan signal based on the gate low voltage.

[0132] The second scan capacitor CQB may have a first electrode connected to the QB node QB and a second electrode connected to the gate low voltage line VGL. The second scan capacitor CQB can maintain a constant voltage at the QB node QB.

[0133] The third scan transistor ST3 may have a gate electrode connected to the clock signal line CLK through which the clock signal is transmitted, a first electrode connected to the start signal line VST (or the output terminal of the (N-1)th stage) through which the start signal is transmitted, and a second electrode connected to the Q node Q. The third scan transistor ST3 can be turned on in response to the clock signal and transmit the start signal to the Q node Q. Since the third scan transistor ST3 is implemented based on oxide semiconductor, it can prevent high voltage (high Vds) from leaking through the drain and source.

[0134] The fourth scan transistor ST4 may have a gate electrode connected to Q node Q, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to QB node QB. The fourth scan transistor ST4 may be turned on based on the voltage of Q node Q and may transfer the gate high voltage to QB node QB.

[0135] The fifth scan transistor ST5 may have a gate electrode connected to Q node Q, a first electrode connected to a gate low voltage line VGL through which a gate low voltage is transmitted, and a second electrode connected to QB node QB. The fifth scan transistor ST5 may be turned on based on the voltage of Q node Q and may transmit the gate low voltage to QB node QB. The fourth scan transistor ST4 and the fifth scan transistor ST5 may be implemented as CMOS transistors that perform opposite operations based on the voltage of Q node Q.

[0136] like Figure 9 As shown, according to the first embodiment, the Nth shift register can output a scan signal Gout based on the start signal VST and the first clock signal CLK1 by charging and discharging in a manner in which the voltages of Q node Q and QB node QB are opposite to each other. This will be described in more detail below. For reference, Figure 9 The waveforms are shown based on vertical dashed lines in units of one horizontal time interval (1H), which should be interpreted as examples. Additionally, an example is shown where the first clock signal CLK1 and the start signal VST have high and low voltage pulses based on gate high voltage VGH and gate low voltage VGL, which should also be interpreted as examples.

[0137] like Figure 9 and Figure 10 As shown, the third scanning transistor ST3 can be repeatedly turned on and off based on the pulsed first clock signal CLK1 applied through the clock signal line CLK. When turned on, the third scanning transistor ST3 can transmit the start signal VST, which is generated as the gate high voltage VGH, to the Q node Q.

[0138] Q-node Q can be charged based on a gate high voltage VGH transmitted through the third scan transistor ST3. The Q-node before charging (or the Q-node after discharging) can have a gate low voltage (VGL) level, and the Q-node after charging can have a gate high voltage (VGH) level.

[0139] The voltage at node Q can be increased to "VGH + *Vadd(*bootstrap voltage)" by the sum of the gate high voltage VGH and the bootstrap voltage of the first scan capacitor CBST. Here, *Vadd(*bootstrap voltage) means adding the bootstrap voltage of the first scan capacitor CBST to the gate high voltage VGH.

[0140] Therefore, the fourth scan transistor ST4 can withstand voltage variations at the levels of the gate low voltage VGL applied to node Q and the gate high voltage VGH applied to node QB. On the other hand, the fifth scan transistor ST5 can withstand voltage variations at the levels of the additional increase VGH+*Vadd applied to the gate high voltage applied to node Q and the gate low voltage VGL applied to node QB. At this time, the drain-source voltage T3 Vds of the third scan transistor ST3 can be at the levels of the additional increase VGH+*Vadd applied to the gate high voltage applied to node Q and the gate low voltage VGL of the start signal.

[0141] Simultaneously, the first scanning transistor ST1 and the fifth scanning transistor ST5 can be turned on based on the high voltage applied at node Q. At this time, when node Q is charged with a high voltage, node QB can be in a discharging state based on the low gate voltage VGL transmitted through the turned-on fifth scanning transistor ST5. Therefore, the second scanning transistor ST2 can be in a turned-off state. When node Q is charged with a high voltage, the turned-on first scanning transistor ST1 can output a first-level scanning signal based on the high gate voltage VGH through the output terminal Gout.

[0142] like Figure 9 and Figure 11 As shown, the third scan transistor ST3 can be repeatedly turned on and off based on the pulsed first clock signal CLK1 applied through the clock signal line CLK. When the third scan transistor ST3 is turned on, it can transmit the start signal VST, which switches to the gate low voltage VGL, to the Q node Q.

[0143] The Q node Q can be discharged based on the low gate voltage VGL transmitted through the third scan transistor ST3. Therefore, the first scan transistor ST1 and the fifth scan transistor ST5 can be turned off.

[0144] The voltage of Q node Q is switched to the gate low voltage VGL, and thus Q node is discharged, and the fifth scan transistor ST5 is turned off while the fourth scan transistor ST4 is turned on.

[0145] When the fourth scan transistor ST4 is turned on, the QB node QB can be charged based on the high gate voltage VGH. The second scan transistor ST2 can be turned on based on the high voltage applied to the QB node QB. When the QB node QB is charged with a high voltage, the turned-on second scan transistor ST2 can output a second-level scan signal based on the low gate voltage VGL through the output terminal Gout.

[0146] The shift register according to the first embodiment can be configured into multiple stages. The shift register according to the first embodiment is implemented with 10 stages, and simulation is performed. Therefore, as... Figure 12 As shown, it is confirmed that normal output can be performed in the form of the first scan signal Gout1 to the tenth scan signal Gout10.

[0147] The shift register according to the first embodiment may include: Figure 2 In the stages, each stage constitutes at least one of the transmit control signal driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324.

[0148] At the same time, it is used to derive Figure 12 The device specifications (W / L dimensions) of the first scan transistor ST1 to the fifth scan transistor ST5, the first scan capacitor CBST, and the second scan capacitor CQB in the simulation results are merely examples, and this disclosure is not limited thereto.

[0149] Figure 13 This is a circuit configuration diagram of the shift register according to the second embodiment.

[0150] like Figure 13 As shown, the Nth shift register (N is any number) according to the second embodiment may include a first scan transistor ST1, a second scan transistor ST2, a third scan transistor ST3, a fourth scan transistor ST4, a fifth scan transistor ST5, a compensation transistor TA, a first scan capacitor CBST, and a second scan capacitor CQB.

[0151] The first scanning transistor ST1, the second scanning transistor ST2, the third scanning transistor ST3, the fifth scanning transistor ST5, and the compensation transistor TA can be n-type transistors implemented based on oxide semiconductors. The fourth scanning transistor ST4 can be a p-type transistor implemented based on low-temperature polycrystalline silicon (LTPS) semiconductors.

[0152] Due to the connection relationship between the first scanning transistor ST1, the second scanning transistor ST2, the first scanning capacitor CBST, and the second scanning capacitor CQB... Figure 8 The same applies; please refer to the first implementation method.

[0153] The third scanning transistor ST3 may have a gate electrode connected to the clock signal line CLK through which the clock signal is transmitted, a first electrode connected to the start signal line VST (or the output terminal of the (N-1)th stage) through which the start signal is transmitted, and a second electrode connected to node Q2 of Q2. The third scanning transistor ST3 may be turned on in response to the clock signal and transmit the start signal to node Q2 of Q2.

[0154] The fourth scan transistor ST4 may have a gate electrode connected to node Q2, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to node QB. The fourth scan transistor ST4 may be turned on based on the voltage of node Q2 and transfer the gate high voltage to node QB.

[0155] The fifth scan transistor ST5 may have a gate electrode connected to node Q2, a first electrode connected to a gate low voltage line VGL through which a gate low voltage is transmitted, and a second electrode connected to node QB. The fifth scan transistor ST5 may be turned on based on the voltage of node Q2 and transmit the gate low voltage to node QB. The fourth scan transistor ST4 and the fifth scan transistor ST5 may be implemented as CMOS transistors that perform opposite operations based on the voltage of node Q2.

[0156] The compensation transistor TA may have a gate electrode connected to the high-voltage gate line VGH, a first electrode connected to node Q2, and a second electrode connected to node Q. The compensation transistor TA can electrically stabilize nodes Q2 and Q and protect transistors T4 and T5 connected to node Q2 from breakdown. Furthermore, since the third scan transistor ST3 is implemented based on oxide semiconductor, it can prevent high voltage (high Vds) leakage through the drain and source. For this reason, the compensation transistor TA according to the second embodiment can be omitted. However, the compensation transistor TA can be used to electrically stabilize nodes Q and Q2.

[0157] Apart from the compensation transistor TA, the Nth shift register according to the second embodiment is similar to that in the first embodiment and can be operated in a similar manner to the first embodiment. Therefore, for the operation of the Nth shift register according to the second embodiment, please refer to the first embodiment.

[0158] The shift register according to the second embodiment may include: Figure 2 In the stages, each stage constitutes at least one of the transmit control signal driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324.

[0159] Figure 14 This is a circuit configuration diagram of the shift register according to the third embodiment.

[0160] like Figure 14 As shown, the Nth shift register (N is any number) according to the third embodiment may include an eleventh transistor M1, a twelfth transistor M2, a thirteenth transistor M3, a fourteenth transistor M4, a fifteenth transistor M5, a sixteenth transistor M6, a seventeenth transistor M7, a second compensation transistor TB, a third capacitor CQ, and a fourth capacitor CQB.

[0161] The eleventh transistor M1, the twelfth transistor M2, the thirteenth transistor M3, the fourteenth transistor M4, the fifteenth transistor M5, the sixteenth transistor M6, the seventeenth transistor M7, and the second compensation transistor TB can be p-type transistors implemented based on LTPS semiconductors.

[0162] The eleventh transistor M1 may have a gate electrode connected to the Q node Q, a first electrode connected to a first gate clock signal line GCLK1 through which a first gate clock signal is transmitted, and a second electrode connected to the output terminal Gout. The eleventh transistor M1 may be turned on based on the voltage of the Q node Q to output a second level scan signal based on the first gate clock signal.

[0163] The third capacitor CQ may have a first electrode connected to the Q node Q and a second electrode connected to the output terminal Gout. The third capacitor CQ may perform bootstrapping, causing the voltage at the Q node Q to increase.

[0164] The twelfth transistor M2 may have a gate electrode connected to the QB node QB, a first electrode connected to the gate high voltage line VGH through which the gate high voltage is transmitted, and a second electrode connected to the output terminal Gout. The twelfth transistor M2 may be turned on based on the voltage of the QB node QB to output a first level scan signal based on the gate high voltage.

[0165] The thirteenth transistor M3 may have a gate electrode connected to the second gate clock signal line GCLK2 through which the second gate clock signal is transmitted, a first electrode connected to the output terminal S2_Gout(n-1) (or start signal line) of the (N-1)th stage, and a second electrode connected to node Q2 of Q2. The thirteenth transistor M3 may be turned on in response to the second gate clock signal and transmit the output signal (or start signal) of the (N-1)th stage to node Q2 of Q2.

[0166] The fourteenth transistor M4 may have a gate electrode connected to node Q2, a first electrode connected to the second gate clock signal line GCLK2, and a second electrode connected to node QB. The fourteenth transistor M4 may be turned on based on the voltage of node Q2 and transmit the second gate clock signal to node QB.

[0167] The fifteenth transistor M5 may have a gate electrode connected to the second gate clock signal line GCLK2, a first electrode connected to the gate low voltage line VGL through which the gate low voltage is transmitted, and a second electrode connected to the QB node QB. The fifteenth transistor M5 may be turned on in response to the second gate clock signal to transmit the gate low voltage to the QB node QB.

[0168] The sixteenth transistor M6 may have a gate electrode connected to the QB node QB, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the second electrode of the seventeenth transistor M7. The sixteenth transistor M6 may be turned on based on the voltage of the QB node QB to transfer the gate high voltage to the second electrode of the seventeenth transistor M7.

[0169] The seventeenth transistor M7 may have a gate electrode connected to the first gate clock signal line GCLK1, a first electrode connected to node Q2, and a second electrode connected to the second electrode of the sixteenth transistor M6. The seventeenth transistor M7 may be turned on in response to the first gate clock signal to transfer the gate high voltage applied from the sixteenth transistor M6 to node Q2.

[0170] The second compensation transistor TB may have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to node Q2, and a second electrode connected to node Q. The second compensation transistor TB can electrically stabilize nodes Q2 and Q and protect transistors M4 and M7 connected to node Q2 from breakdown.

[0171] The shift register according to the third embodiment may include: Figure 2 In the stages, each stage constitutes at least one of the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E. In other words, the shift register according to the third embodiment can generate an application applied to... Figure 4 The second scan signal of the gate electrode of the second transistor T2 is used to apply the data voltage. Therefore, the first gate clock signal and the second gate clock signal can be applied at the timing of generating and outputting the second scan signal.

[0172] Referring to the first to third embodiments, the gate driver according to this disclosure may include: a first type of shift register comprising oxide semiconductor and cryogenic polysilicon semiconductor; and a second type of shift register comprising cryogenic polysilicon semiconductor. Furthermore, referring to the first and second embodiments, the gate driver according to this disclosure can reduce the number of transistors used to control the QB node based on CMOS transistors. Furthermore, referring to the first and second embodiments, the gate driver according to this disclosure can solve problems caused by current leakage by using a shift register comprising oxide semiconductor.

[0173] This disclosure provides the following advantages: it offers a gate driver and a display device including the gate driver, which can reduce the number of transistors used to control the QB node based on CMOS transistors and solve problems caused by current leakage based on a shift register including oxide semiconductors. Furthermore, this disclosure provides the following advantages: it offers a gate driver and a display device including the gate driver, which can improve operational stability and reliability based on a shift register including at least one of oxide semiconductors or low-temperature polysilicon semiconductors.

[0174] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: Display panel, the display panel being configured to display images; as well as A gate driver, the gate driver including a shift register configured to generate signals for controlling transistors included in the display panel; The shift register includes: A first scanning transistor is turned on based on the voltage of the Q node to output a first level signal through an output terminal; The second scanning transistor is turned on based on the voltage of the QB node to output a second level signal through the output terminal; A third scan transistor, which turns on in response to a clock signal applied via a clock signal line, to transmit a start signal applied via a start signal line to the Q node; and A CMOS transistor configured to control the QB node based on the voltage of the Q node.

2. The display device according to claim 1, wherein, The CMOS transistor includes: a fourth scan transistor having a gate electrode connected to the Q node, a first electrode connected to a first voltage line for transmitting a first voltage, and a second electrode connected to the QB node; and a fifth scan transistor having a gate electrode connected to the Q node, a first electrode connected to a second voltage line for transmitting a second voltage, and a second electrode connected to the QB node.

3. The display device according to claim 2, wherein, The fourth scanning transistor is a p-type transistor based on polysilicon semiconductor, and the fifth scanning transistor is an n-type transistor based on oxide semiconductor.

4. The display device according to claim 3, wherein, The first scanning transistor, the second scanning transistor, and the third scanning transistor are n-type transistors based on oxide semiconductors.

5. The display device according to claim 1, further comprising: A first scanning capacitor has a first electrode connected to the gate electrode of the first scanning transistor and a second electrode connected to the output terminal; as well as The second scanning capacitor has a first electrode connected to the gate electrode of the second scanning transistor and a second electrode connected to the second voltage line.

6. The display device according to claim 1, wherein, The gate driver includes: a scan driver configured to supply a scan signal to the display panel; and an emission control signal driver configured to supply an emission control signal to the display panel. The shift register is included in at least one of the scan driver and the transmit control signal driver.

7. The display device according to claim 1, wherein, The gate driver includes: A first scan driver, configured to supply a first scan signal to the display panel; A second scan driver, configured to supply a second scan signal to the display panel; A third scan driver, the third scan driver being configured to supply a third scan signal to the display panel; A fourth scan driver, configured to supply a fourth scan signal to the display panel; and A transmit control signal driver, configured to supply transmit control signals to the display panel. The shift register is included in at least one of the first scan driver, the third scan driver, the fourth scan driver, and the transmit control signal driver.

8. A gate driving circuit, comprising: A first scanning transistor is turned on based on the voltage of the Q node to output a first level signal through an output terminal; The second scanning transistor is turned on based on the voltage of the QB node to output a second level signal through the output terminal; A third scan transistor, which turns on in response to a clock signal applied via a clock signal line, transmits a start signal applied via a start signal line to the Q node; as well as A CMOS transistor configured to control the QB node based on the voltage of the Q node.

9. The gate driving circuit according to claim 8, wherein, The CMOS transistor includes: a fourth scan transistor having a gate electrode connected to the Q node, a first electrode connected to a first voltage line for transmitting a first voltage, and a second electrode connected to the QB node; and a fifth scan transistor having a gate electrode connected to the Q node, a first electrode connected to a second voltage line for transmitting a second voltage, and a second electrode connected to the QB node.

10. The gate driving circuit according to claim 9, wherein, The first scanning transistor, the second scanning transistor, the third scanning transistor, and the fifth scanning transistor are n-type transistors based on oxide semiconductors, and the fourth scanning transistor is a p-type transistor based on polysilicon semiconductors.

Images