Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are provided. The display device includes a display panel and a circuit board bonded to the display panel. The display panel includes a substrate, a circuit layer, and an element layer. The circuit layer includes a first power line disposed in a display area of the substrate, a power sense line disposed in a non-display area of the substrate, extending from a first side of an edge of the display area to a sub-area of the substrate, and electrically connected to one of the first power lines, and a power sense extension line electrically connected to the power sense line and contacting a side of an edge of the sub-area.

Description

Technical Field

[0001] This disclosure relates to a display device and a method of manufacturing the same. Background Technology

[0002] With the advancement of information-oriented society, the demand for display devices that can display images in various ways is increasing. For example, display devices are implemented in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] The display device can be a flat panel display device, such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of light-emitting display devices can include organic light-emitting display devices that include organic light-emitting elements, inorganic light-emitting display devices that include inorganic light-emitting elements such as inorganic semiconductors, and micro light-emitting display devices that include micro light-emitting elements.

[0004] Organic light-emitting display devices use light-emitting elements to display images, and each of these elements includes a light-emitting layer made of organic light-emitting material. As described above, organic light-emitting display devices use self-emissive elements to display images, and therefore, compared to other display devices, they can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0005] The surface of the display device may include a display area for displaying images and a non-display area surrounding the display area. An emitting area for emitting light with various brightness and colors may be arranged in the display area. Summary of the Invention

[0006] Technical issues

[0007] Methods for manufacturing a display device may include the step of checking whether the light-emitting elements disposed in the emitting area of ​​the display area are properly conductive.

[0008] During the illumination inspection process, static electricity can be introduced through the pads of the connector connected to the inspection device. The problem in this case is that when the charge concentrates in the relatively high-resistance portion of the conductor adjacent to the pad, a breakage defect may easily occur.

[0009] Furthermore, since the insulation layer, including inorganic insulating material, warps at the point where a disconnection defect occurs due to static electricity, a path for oxygen or moisture to penetrate is created, which may reduce the lifespan of the display device.

[0010] In view of the above, this disclosure provides a display device capable of reducing disconnection defects caused by static electricity introduced during lighting inspection, and a method for manufacturing the display device.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] Technical solution

[0013] According to aspects of this disclosure, a display device includes a display panel and a circuit board bonded to the display panel. The display panel includes: a substrate; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. The substrate includes a main region and a sub-region projecting from one side of the main region. The main region includes a display region in which an emitting region is disposed and a non-display region disposed around the display region. The component layer includes light-emitting elements respectively disposed in the emitting region. The circuit layer includes: light-emitting pixel drivers arranged side-by-side with each other in a first direction and a second direction, and electrically connected to the light-emitting elements respectively; a first power line disposed in the display region, extending in the second direction, and transmitting a first power supply to the light-emitting pixel drivers; a power sensing line disposed in the non-display region, extending from a first side of the edge portion of the display region facing the sub-region and adjacent to the sub-region, and electrically connected to one of the first power lines; and a power sensing extension line electrically connected to the power sensing line and contacting one side of the edge portion of the sub-region.

[0014] The circuit layer may also include pads disposed in the sub-region and connected to the circuit board. The pads may include power sensing transmission pads electrically connected to power sensing lines. Power sensing lines are connected to one side of the power sensing transmission pads. Power sensing extension lines may extend from the other side of the power sensing transmission pads to one side of the edge portion of the sub-region.

[0015] The circuit layer may further include a power sensing auxiliary line disposed in the non-display area, extending from a second side of the edge portion of the display area opposite to a first side of the edge portion of the display area to a sub-region, and electrically connected to another first power line in the first power line. The pads may further include power sensing auxiliary pads electrically connected to the power sensing auxiliary line.

[0016] The display device may further include: an encapsulation layer disposed on the component layer; and at least one dam portion disposed in a dam region surrounding the display region in a non-display area. The circuit layer may further include: a first gate insulating layer disposed on a substrate; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a third gate insulating layer disposed on the first interlayer insulating layer; a third gate conductive layer disposed on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer disposed on the second interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. A bypass portion of the power sensing line overlapping the dam region is disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer. A first main portion of the power sensing line disposed between the bypass portion and a first power line is disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer. The power sensing line is disposed on a second main portion between the bypass portion and the power sensing transmission pad, which is disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

[0017] The bypass section can have the form of a clamping section, and the extension direction of the clamping section can be varied.

[0018] The portion of the first main section of the power sensing line adjacent to the bypass section may include a clamping portion, the extension direction of which may vary.

[0019] The total extension length of the clamping section can correspond to the width of the bypass section.

[0020] The encapsulation layer may include: a first encapsulation layer disposed on the component layer; a second encapsulation layer disposed on the first encapsulation layer; and a third encapsulation layer disposed on the first encapsulation layer and covering the second encapsulation layer. Each of the first and third encapsulation layers may include an inorganic insulating material. The second encapsulation layer may include an organic insulating material disposed in a region surrounded by at least one dam portion. The third encapsulation layer contacts the first encapsulation layer at the exterior of the dam region.

[0021] The substrate may also include an inspection pad region connected to one side of the edge portion of the sub-region. The circuit layer may further include: an inspection connection pad, a connector disposed in the inspection pad region and connected to an inspection device that provides an inspection signal for illumination inspection; and an inspection connection line disposed in the inspection pad region and extending from one side of the edge portion of the sub-region. The inspection connection line may include a power sensing dummy line connected to a power sensing extension line.

[0022] Inspecting connection pads may include dummy pads that are electrically connected to the power sensing dummy line.

[0023] The circuit layer may further include: a first power supply line disposed in the non-display area and transmitting the first power supply; and a first power supply extension line electrically connected to the first power supply line and contacting one side of the edge portion of the sub-region. The inspection connection line may further include a first power connection line connected to the first power supply extension line. The inspection connection pad may further include a first power supply pad electrically connected to the first power connection line. A power sensing dummy line is electrically connected to the first power connection line.

[0024] According to an aspect of this disclosure, a method for manufacturing a display device is provided, the method comprising: preparing an inspection panel; performing an illumination inspection on the inspection panel using an inspection device connected to inspection pad areas in the inspection panel; preparing a display panel by removing the inspection pad areas in the inspection panel; and bonding a circuit board to pads in sub-regions of the display panel. In preparing the inspection panel, the inspection panel includes: a substrate; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. The substrate includes: a main region including a display region in which an emitting region is disposed and a non-display region disposed around the display region; and a sub-region protruding from one side of the main region and having a side connected to the inspection pad areas. The component layer includes light-emitting elements respectively disposed in the emitting regions. The circuit layer includes: light-emitting pixel drivers arranged side-by-side in a first direction and a second direction, and electrically connected to light-emitting elements respectively; a first power line disposed in the display area, extending in the second direction, and transmitting a first power supply to the light-emitting pixel drivers; a power sensing line disposed in the non-display area, extending from a first side of the edge portion of the display area facing and adjacent to the sub-region to the sub-region, and electrically connected to one of the first power lines; a power sensing extension line electrically connected to the power sensing line and contacting one side of the edge portion of the sub-region; a check connection pad disposed in the check pad area; and a check connection line disposed in the check pad area and extending from one side of the edge portion of the sub-region. The check connection line includes a power sensing dummy line electrically connected to the power sensing extension line.

[0025] When preparing the inspection panel, the circuit layer may also include pads disposed in the sub-regions and connected to the circuit board. The pads may include power sensing transmission pads electrically connected to power sensing lines. Power sensing lines are connected to one side of the power sensing transmission pads. Power sensing extension lines may extend from the other side of the power sensing transmission pads to one side of the edge portion of the sub-region.

[0026] Inspecting connection pads may include dummy pads that are electrically connected to the power sensing dummy line.

[0027] When preparing the inspection panel, the circuit layer may further include: a first power supply line disposed in a non-display area and transmitting a first power supply; and a first power supply extension line electrically connected to the first power supply line and contacting one side of the edge portion of the sub-area. Inspection connection lines may further include a first power connection line connected to the first power supply extension line. Inspection connection pads may further include a first power supply pad electrically connected to the first power connection line.

[0028] The power sensing dummy line is electrically connected to the first power connection line.

[0029] When preparing the inspection panel, the circuit layer may further include power sensing auxiliary lines disposed in the non-display area, extending from a second side opposite to a first side of the edge portion of the display area to a sub-region, and electrically connected to another first power line in the first power lines. The pads may also include power sensing auxiliary pads electrically connected to the power sensing auxiliary lines.

[0030] When preparing the inspection panel, the inspection panel may further include at least one dam portion disposed in a dam region surrounding the display area in a non-display area. The circuit layer may further include: a first gate insulating layer disposed on a substrate; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a third gate insulating layer disposed on the first interlayer insulating layer; a third gate conductive layer disposed on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer disposed on the second interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. A bypass portion of the power sensing line overlapping the dam region is disposed on one of the first, second, and third gate conductive layers. A first main portion of the power sensing line disposed between the bypass portion and a first power line is disposed on at least one of the first and second source-drain conductive layers. The power sensing line is disposed on a second main portion between the bypass portion and the power sensing transmission pad, which is disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

[0031] The bypass section can have the form of a clamping section, and the extension direction of the clamping section can be varied.

[0032] The portion of the first main section of the power sensing line adjacent to the bypass section may include a clamping portion, the extension direction of which may vary.

[0033] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0034] Beneficial effects

[0035] The display device according to the embodiment may include a display panel and a circuit board. The display panel may include a substrate, a circuit layer, and a component layer. The circuit layer may include a first power line, a power sensing line extending from a first side of the display area to a sub-area and electrically connected to one of the first power lines, and a power sensing extension line electrically connected to the power sensing line and contacting one side of the edge portion of the sub-area.

[0036] In the step of preparing the inspection panel before performing the lighting inspection, the circuit layer of the inspection panel may also include a power sensing dummy line, which is disposed in the inspection pad area, extends from one side of the edge portion of the sub-area, and connects to the power sensing extension line.

[0037] In this way, since the circuit layer includes power sensing extensions and power sensing dummy lines, static electricity introduced around the power sensing transfer pads can not only be introduced to one side of the power sensing line, but also dispersed into the power sensing extensions and power sensing dummy lines.

[0038] Therefore, it can reduce the bursting and breakage defects in the power sensing wire caused by overheating due to static electricity concentration.

[0039] Therefore, it can prevent the creation of oxygen or moisture paths due to the bursting of the power sensing wire, and thus can improve the lifespan of the display device.

[0040] However, the effects of the embodiments according to this disclosure are not limited to those exemplified above, and various other effects are incorporated herein. Attached Figure Description

[0041] Figure 1 and Figure 2 This is a plan view showing a display device according to an embodiment; Figure 3 It is along Figure 2 A sectional view taken by line A-A'; Figure 4 It is shown Figure 2 The layout diagram of part B; Figure 5 yes Figure 4 The equivalent circuit of the light-emitting pixel driver; Figure 6 It is shown Figure 5 A cross-sectional view of the light-emitting element and the first transistor, the second transistor, the fourth transistor, and the sixth transistor; Figure 7 This illustrates an embodiment. Figure 1 The layout diagram of part A; Figure 8 This illustrates an embodiment. Figure 7 A partial plan view of D; Figure 9 It is along Figure 8 A sectional view taken by line E-E'; Figure 10 , Figure 11 and Figure 12 This illustrates various embodiments. Figure 7 A partial plan view of D; Figure 13 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment; Figure 14 This illustrates the preparation according to the embodiment. Figure 13 A floor plan of the inspection panel during the inspection panel procedures; Figure 15 This illustrates an embodiment. Figure 14 The layout diagram of part F; Figure 16 and Figure 17 This illustrates the execution according to the implementation method. Figure 13 The process diagram for the lighting inspection steps; Figure 18 This shows the execution based on the comparison example. Figure 13 The process diagram for the lighting inspection steps; and Figure 19 This illustrates an embodiment according to another method. Figure 14 The layout diagram of part F. Detailed Implementation

[0042] The advantages and features of the present invention, as well as methods for implementing them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete. The present invention is provided to fully inform those skilled in the art to which it pertains of its scope, and the invention is defined only by the scope of the claims.

[0043] When an element or layer is referred to as being "on" another element or layer, it includes cases where the element or layer is directly on top of the other element or where the other element is situated between them. Throughout the specification, the same reference numerals denote the same elements. The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the drawings for illustrating embodiments are illustrative, and the invention is not limited to the details shown.

[0044] Although terms like "first," "second," etc., are used to describe various components, these components are certainly not limited by these terms. These terms are only used to distinguish one component from another. Therefore, it goes without saying that, within the technical spirit of this invention, the "first component" mentioned below can also be the "second component."

[0045] Features of each of the various embodiments of the present invention may be partially or wholly connected or combined with each other, various interlocks and drives are technically possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

[0046] The embodiments will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 and Figure 2 This is a plan view showing a display device according to an embodiment. Figure 3 It is along Figure 2 A sectional view taken by line A-A'. Figure 4 It is shown Figure 2 The layout diagram of part B.

[0048] refer to Figure 1 and Figure 2 The display device 10 can be a device for displaying moving or still images. The display device 10 can be used as a display screen for various devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs).

[0049] Display device 10 can be a light-emitting display device, such as an organic light-emitting display using organic light-emitting diodes, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, and a micro light-emitting display using micro or nano light-emitting diodes (LEDs). In the following description, the case where display device 10 is an organic light-emitting display device will be primarily described; however, this disclosure can be applied to display devices including organic insulating materials, organic light-emitting materials, and metallic materials.

[0050] The display device 10 may be formed as a flat surface, but the implementation is not limited thereto. For example, the display device 10 may include curved portions formed at the left and right ends and having a constant or varying curvature. For example, the display device 10 may be formed flexibly, such that the display device 10 may be bendable, foldable, or rollable.

[0051] The display device 10 may include a substrate 110, a display driving circuit 300, and a circuit board 200.

[0052] The substrate 110 may include a main region MA disposed on the surface on which the image is displayed (hereinafter referred to as the display surface) and a sub-region SBA protruding from one side of the main region MA.

[0053] The main region MA may include a display region DA for displaying images and a non-display region NDA disposed around the display region DA. An emission region EA is arranged within the display region DA to emit light with corresponding color and brightness (see [link to relevant documentation]). Figure 4 ).

[0054] The edge portion of the display area DA may include a first side SD1 and a second side SD2 extending in the first direction DR1 and facing each other, and a third side SD3 and a fourth side SD4 extending in the second direction DR2, connecting the first side SD1 and the second side SD2 and facing each other.

[0055] For example, the first side SD1 and the second side SD2 can have shorter lengths than the third side SD3 and the fourth side SD4. In this case, the display area DA can be set as a quadrilateral-shaped plane.

[0056] As another example, the corner portion where each of the first side SD1 and the second side SD2 meets each of the third side SD3 and the fourth side SD4 can be rounded to have a selected curvature, or be a right angle.

[0057] As another example, the planar shape of the display area DA is not limited to a rectangular shape, but can be formed into another polygonal shape, a circular shape, or an elliptical shape.

[0058] The non-display area NDA can be set at the edge of the main area MA, and can be in a shape that surrounds the display area DA.

[0059] The non-display area NDA may include a dam area DMA surrounding and spaced apart from the display area DA. The dam portion DM1 or DM2 has an annular shape surrounding the display area DA (see [link to documentation]). Figure 8 and Figure 9 At least one of them can be arranged in the dam area DMA.

[0060] Subregions SBA can be bent or folded to face each other and can be adjacent to the first side SD1 of display region DA.

[0061] The subregion SBA may include a curved region BA that has been transformed into a curved shape, and a first subregion SB1 and a second subregion SB2 that are respectively in contact with the two sides of the curved region BA.

[0062] The first sub-region SB1 can be located between the main region MA and the curved region BA. One side of the first sub-region SB1 can contact the non-display area NDA of the main region MA, and the other side of the first sub-region SB1 can contact the curved region BA.

[0063] The second sub-region SB2 can be separated from the main region MA, and the first sub-region SB1 and the curved region BA are located between the second sub-region SB2 and the main region MA.

[0064] When the curved region BA transforms into a curved shape, the second sub-region SB2 can be disposed on the bottom surface of the substrate 110. For example, the second sub-region SB2 can overlap with the main region MA in the thickness direction (e.g., third direction DR3) of the substrate 110 due to the transformation of the curved region BA into a curved shape.

[0065] Figure 1 This shows the sub-region SBA expanded to be positioned side-by-side with the main region MA. On the other hand, Figure 2 and Figure 3 The bending state of the bending region BA in the subregion SBA is shown.

[0066] refer to Figure 3 The display device 10 according to the embodiment may include a display panel 100 through which light for displaying images is emitted and a circuit board 200 bonded to the display panel 100.

[0067] The display device 10 may also include a display driving circuit 300 mounted on a circuit board 200.

[0068] The display panel 100 may include a substrate 110, a circuit layer 120 disposed on the substrate 110, and a component layer 130 disposed on the circuit layer 120.

[0069] The display panel 100 may also include an encapsulation layer 140 disposed on the component layer 130, a touch sensor layer 150 disposed on the encapsulation layer 140, and a polarization layer 160 disposed on the touch sensor layer 150.

[0070] like Figure 1 and Figure 2 As shown, substrate 110 may include a main region MA corresponding to the display surface and a sub-region SBA protruding from one side of the main region MA, and the main region MA may include an emission region EA disposed therein (see...). Figure 4 The display area DA and the non-display area NDA set around the display area DA.

[0071] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that is bendable, foldable, or rollable.

[0072] In another example, the substrate 110 may be formed of an insulating material such as glass.

[0073] Component layer 130 may include light-emitting elements LE respectively disposed in the emission region EA (see Figure 5 and Figure 6 ).

[0074] Circuit layer 120 may include a light-emitting pixel driver EPD electrically connected to the light-emitting element LE of element layer 130 (see [link]). Figure 4 and Figure 5 ).

[0075] The encapsulation layer 140 may be disposed on the element layer 130 and may have a structure in which two or more inorganic films and at least one organic film are stacked alternately on each other.

[0076] The touch sensor layer 150 may include touch electrodes for detecting signals that change according to a person's or object's touch and sensing points in the main area MA where a person's or object's touch occurs.

[0077] The polarization layer 160 can block external light reflected from the touch sensor layer 150, the encapsulation layer 140, the component layer 130 and the circuit layer 120 and their interfaces, and this is to prevent the degradation of image visibility due to external light reflection.

[0078] The display device 10 may also include a cover window (not shown) disposed on the polarization layer 160. The cover window may be attached to the polarization layer 160 by a transparent adhesive member such as an optically transparent adhesive (OCA) film or an optically transparent resin (OCR). The cover window may be made of an inorganic material such as glass or an organic material such as plastic or polymer. Due to the cover window, the touch sensor layer 150, the encapsulation layer 140, the component layer 130, and the circuit layer 120 may be protected from electrical and physical shocks to the display surface.

[0079] The circuit board 200 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0080] Circuit board 200 can be bonded to pad PD disposed in the second sub-region SB2 of substrate 110 by using low-resistance, high-reliability materials such as anisotropic conductive film or superabsorbent polymer (SAP) (see Figure 7 ).

[0081] The display driver circuit 300 can be provided as an integrated circuit chip (IC).

[0082] According to an embodiment, the display driving circuit 300 can be attached to the circuit board 200 using a chip-on-film (COF) method.

[0083] The display driver circuit 300 can send data to the data line DL of the circuit layer 120 (see...). Figure 5 Output data signal.

[0084] The display device 10 may also include a touch driving circuit 400 for driving the touch sensor layer 150.

[0085] refer to Figure 4 The display area DA of the display device 10 may include an emission area EA. For example, the display area DA may also include a non-emission area disposed in the gap between the emission areas EA.

[0086] The light-emitting pixel drivers EPD, which are electrically connected to the light-emitting elements LE in the emission region EA, can be arranged side by side in the main region MA in the first direction DR1 and the second direction DR2.

[0087] The light-emitting pixel driver EPD can be electrically connected to the light-emitting elements LE respectively disposed in the emission region EA of the element layer 130 (see [link]). Figure 5 ).

[0088] The emission region EA can have a rhomboid or rectangular shape in a planar view. However, this is only an example, and the planar shape of the emission region EA according to the implementation is not limited to this. Figure 4 The shape shown is as described. For example, in a planar view, the emission area EA can have a polygonal shape such as a square, pentagon, hexagon, etc., or it can have a circular or elliptical shape that includes curved edge portions.

[0089] The emission region EA may include a first emission region EA1 that emits light of a first color in a selected wavelength band, a second emission region EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission region EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0090] For example, the first color could be red with a wavelength band of about 600 nm to about 750 nm. The second color could be green with a wavelength band of about 480 nm to about 560 nm. The third color could be blue with a wavelength band of about 370 nm to about 460 nm.

[0091] The first launch area EA1 and the third launch area EA3 may be arranged alternately on at least one of the first direction DR1 and the second direction DR2.

[0092] The second launch area EA2 can be arranged side by side on at least one of the first direction DR1 and the second direction DR2.

[0093] For example, the second emission region EA2 can be adjacent to the first emission region EA1 and the third emission region EA3 on the diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0094] The pixels PX that display their own brightness and color can be provided by the first emission region EA1, the second emission region EA2, and the third emission region EA3, which are adjacent to each other among these emission regions EA.

[0095] For example, a pixel PX can be the basic unit used to display various colors, including white with a selected brightness.

[0096] Each pixel PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 that are adjacent to each other. Therefore, each pixel PX can display various colors by mixing the light emitted from the adjacent first emission region EA1, second emission region EA2, and third emission region EA3.

[0097] Figure 5 It is shown Figure 4 The equivalent circuit diagram of the light-emitting pixel driver.

[0098] refer to Figure 5 The light-emitting pixel driver EPD can be electrically connected to the first power supply ELVDD, and one of the light-emitting elements LE in the element layer 130 can be electrically connected between the light-emitting pixel driver EPD in the circuit layer 120 and the second power supply ELVSS.

[0099] For example, the anode electrode of the light-emitting element LE can be electrically connected to the light-emitting pixel driver EPD, and the cathode electrode of the light-emitting element LE can be subjected to a second power supply ELVSS lower than the first power supply ELVDD.

[0100] The capacitor Cel connected in parallel with the light-emitting element LE refers to the parasitic capacitance between the anode and cathode electrodes.

[0101] The circuit layer 120 may also include a first power supply line VDL for transmitting the first power supply ELVDD, a gate initialization voltage line VGIL for transmitting the gate initialization voltage VGINT, and an anode initialization voltage line VAIL for transmitting the anode initialization voltage VAINT.

[0102] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emit control line ECL for transmitting an emit control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0103] The light-emitting pixel driver EPD of circuit layer 120 may include a first transistor T1 configured to generate a drive current for driving the light-emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one capacitor PC1.

[0104] The first transistor T1 can be electrically connected between the first node N1 and the second node N2. The first node N1 can be electrically connected to the first electrode (e.g., the source electrode) of the first transistor T1. The second node N2 can be electrically connected to the second electrode (e.g., the drain electrode) of the first transistor T1.

[0105] The first node N1 can be electrically connected to the first power line VDL through the fifth transistor T5.

[0106] The second node N2 can be electrically connected to the anode electrode of the light-emitting element LE through the sixth transistor T6.

[0107] The first capacitor PC1 can be electrically connected between the first power line VDL and the third node N3. The third node N3 can be electrically connected to the gate electrode of the first transistor T1.

[0108] For example, the gate electrode of the first transistor T1 can be electrically connected to the first power supply line VDL through the first capacitor PC1.

[0109] Therefore, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged into the first capacitor PC1.

[0110] The second transistor T2 can be electrically connected between the data line DL and the first node N1.

[0111] The second transistor T2 can be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0112] For example, the first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0113] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0114] The fifth transistor T5 can be electrically connected between the first node N1 and the first power line VDL.

[0115] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. The fourth node N4 can be electrically connected to the anode electrode of the light-emitting element LE.

[0116] For example, the fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first power supply line VDL.

[0117] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element LE.

[0118] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emit control signal EC on the emit control line ECL.

[0119] When the data signal Vdata of the data line DL is sent to the first electrode of the first transistor T1 through the conducting second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be the voltage difference between the first power supply ELVDD and the data signal Vdata.

[0120] For example, when the voltage difference (e.g., gate-source voltage difference) between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 becomes equal to or greater than the threshold voltage, the first transistor T1 can be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0121] Subsequently, with the fifth transistor T5 and the sixth transistor T6 turned on, the first power supply ELVDD, the first transistor T1, the light-emitting element LE, and the second power supply ELVSS can be connected in series. Therefore, the drain-source current of the first transistor T1, corresponding to the data signal Vdata, can be used as the driving current for the light-emitting element LE.

[0122] Therefore, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0123] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. For example, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0124] The third transistor T3 can be turned on by the gate control signal GC of the gate control line GCL.

[0125] The voltage difference between the second node N2 and the third node N3 can be initialized by turning on the third transistor T3.

[0126] The fourth transistor T4 can be electrically connected between the gate initialization voltage line VGIL and the third node N3. For example, the fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0127] The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0128] The potential of the third node N3 can be initialized by the conducting fourth transistor T4.

[0129] The third transistor T3 and the fourth transistor T4 can be provided as N-type MOSFETs.

[0130] The seventh transistor T7 can be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. For example, the seventh transistor T7 can be electrically connected between the anode electrode of the light-emitting element LE and the anode initialization voltage line VAIL.

[0131] The seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL.

[0132] The potential of the fourth node N4 can be initialized by the conducting seventh transistor T7.

[0133] According to the implementation, among the first transistor T1 to the seventh transistor T7, the third transistor T3 and the fourth transistor T4 can be provided as N-type MOSFETs, and the other transistors T1, T2 and T5 to T7, other than the third transistor T3 and the fourth transistor T4, can be provided as P-type MOSFETs.

[0134] According to an embodiment, circuit layer 120 may include a first semiconductor layer for providing a P-type MOSFET and a second semiconductor layer for providing an N-type MOSFET.

[0135] Figure 6 It is shown Figure 5 A cross-sectional view of the light-emitting element and the first transistor, the second transistor, the fourth transistor and the sixth transistor.

[0136] refer to Figure 6 The display panel 100 of the display device 10 according to the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110 and a component layer 130 on the circuit layer 120.

[0137] The display panel 100 of the display device 10 according to the embodiment may further include an encapsulation layer 140 on the component layer 130, a touch sensor layer 150 on the encapsulation layer 140, and a polarization layer 160 on the touch sensor layer 150.

[0138] The circuit layer 120 may include first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 disposed on the substrate 110; a first gate insulating layer 123 covering the first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26; first gate conductive layers G1, G2, and G6 disposed on the first gate insulating layer 123; a second gate insulating layer 124 covering the first gate conductive layers G1, G2, and G6; second gate conductive layers CAE and LB2 disposed on the second gate insulating layer 124; a first interlayer insulating layer 125 covering the second gate conductive layers CAE and LB2; and a first interlayer insulating layer 125 disposed on the second gate conductive layers CAE and LB2. The second semiconductor layers CH4, E14, and E24 on the first interlayer insulating layer 125, the third gate insulating layer 126 covering the second semiconductor layers CH4, E14, and E24, the third gate conductive layer G4 disposed on the third gate insulating layer 126, the second interlayer insulating layer 127 covering the third gate conductive layer G4, the first source / drain conductive layers ANCE1, VGIL, and DCE disposed on the second interlayer insulating layer 127, the first planarization layer 128 covering the first source / drain conductive layers ANCE1, VGIL, and DCE, the second source / drain conductive layers DL and ANCE2 disposed on the first planarization layer 128, and the second planarization layer 129 covering the second source / drain conductive layers DL and ANCE2.

[0139] According to an embodiment, the circuit layer 120 may further include a barrier layer 121 disposed on the substrate 110, a first light-blocking layer LB1 disposed on the barrier layer 121, and a buffer layer 122 covering the first light-blocking layer LB1. For example, first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 may be disposed on the buffer layer 122.

[0140] The circuit layer 120 may include light-emitting pixel drivers EPDs corresponding to the emission regions EA.

[0141] Each of the light-emitting pixel drivers (EPD) may include a first transistor T1, and second transistors T2 through T7 electrically connected to the first transistor T1 (see [link to EPD]). Figure 5 ) and at least one capacitor PC1 (see Figure 5 ).

[0142] Figure 6 Transistors T1 to T7 of the light-emitting pixel driver EPD are shown (see Figure 5The first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are in the transistor T4.

[0143] The barrier layer 121 and the buffer layer 122 may comprise different inorganic insulating materials.

[0144] The first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 on buffer layer 122 may include a first transistor T1, a second transistor T2, and a fifth transistor T5 provided as P-type MOSFETs (see [link to relevant documentation]). Figure 5 The sixth transistor T6 and the seventh transistor T7 have channel portions CH1, CH2 and CH6, first electrode portions E11, E12 and E16, and second electrode portions E21, E22 and E26.

[0145] The first gate conductive layer on the first gate insulating layer 123 may include a first transistor T1, a second transistor T2, and a fifth transistor T5 provided as a P-type MOSFET (see Figure 5 ), the gate electrodes G1, G2 and G6 of the sixth transistor T6 and the seventh transistor T7.

[0146] Since the fifth transistor T5 and the seventh transistor T7 have the same structure as the first transistor T1, the second transistor T2 and the sixth transistor T6, redundant descriptions will be omitted below.

[0147] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the channel portions CH1, CH2, and CH6 may overlap with the gate electrodes G1, G2, and G6.

[0148] The channel portion CH1 of the first transistor T1 can overlap with the first light-blocking layer LB1 below the buffer layer 122.

[0149] In each of the first transistor T1, the second transistor T2, and the sixth transistor T6, the first electrode portions E11, E12, and E16 can be connected to the end portions of the channel portions CH1, CH2, and CH6, and the second electrode portions E21, E22, and E26 can be connected to the other end portions of the channel portions CH1, CH2, and CH6.

[0150] The first electrode portion E11 of the first transistor T1 can be connected to the second electrode portion E22 of the second transistor T2.

[0151] The second electrode portion E21 of the first transistor T1 can be connected to the first electrode portion E16 of the sixth transistor T6.

[0152] The second gate conductive layer CAE and LB2 on the second gate insulating layer 124 may include a capacitor electrode CAE and a second light blocking layer LB2.

[0153] The capacitor electrode CAE can overlap with the gate electrode G1 of the first transistor T1.

[0154] Therefore, the first capacitor PC1 (see Figure 5 This can be provided by the overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0155] The second semiconductor layers CH4, E14, and E24 on the first interlayer insulating layer 125 may include a third transistor T3 provided as an N-type MOSFET (see [link]). Figure 5 The channel portion CH4, the first electrode portion E14, and the second electrode portion E24 of each of the fourth transistors T4.

[0156] The third gate conductive layer G4 on the third gate insulating layer 126 may include a third transistor T3 provided as an N-type MOSFET (see [link]). Figure 5 ) and the gate electrode G4 of each of the fourth transistor T4.

[0157] In the third transistor T3 (see...) Figure 5 In each of the first transistors T1 and T4, the channel portion CH4 may overlap with the second light-blocking layer LB2 below the first interlayer insulating layer 125.

[0158] The channel portion CH4 of the fourth transistor T4 can overlap with the gate electrode G4 of the fourth transistor T4.

[0159] The first electrode portion E14 of the fourth transistor T4 can be connected to the end portion of the channel portion CH4 of the fourth transistor T4, and the second electrode portion E24 of the fourth transistor T4 can be connected to the other end portion of the channel portion CH4 of the fourth transistor T4.

[0160] Since the third transistor T3 has the same structure as the fourth transistor T4, redundant descriptions will be omitted below.

[0161] The first source / drain conductive layer on the second interlayer insulating layer 127 may include a first anode connection electrode ANCE1, a data connection electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0162] The second source / drain conductive layer on the first planarization layer 128 may include a second anode connection electrode ANCE2 and a data line DL.

[0163] The data connection electrode DCE can be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data connection hole DCH1.

[0164] The data cable DL can be electrically connected to the data connection electrode DCE through the second data connection hole DCH2.

[0165] Therefore, the data line DL can be electrically connected to the first electrode portion E12 of the second transistor T2 via the data connection electrode DCE.

[0166] The anode electrode 131 of the element layer 130 can be disposed on the second planarization layer 129.

[0167] The first anode connection electrode ANCE1 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1.

[0168] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2.

[0169] The anode electrode 131 can be electrically connected to the second anode electrode ANCE2 through the third anode connection hole ANCH3.

[0170] Therefore, the anode electrode 131 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 via the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0171] Each of the first data connection hole DCH1 and the first anode connection hole ANCH1 can penetrate the second interlayer insulating layer 127, the third gate insulating layer 126, the first interlayer insulating layer 125, the second gate insulating layer 124, and the first gate insulating layer 123.

[0172] Each of the second anode connection hole ANCH2 and the second data connection hole DCH2 can penetrate the first planarization layer 128.

[0173] The gate initialization voltage line VGIL can be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0174] The node auxiliary connection electrode NACE can be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0175] Each of the gate initialization voltage connection hole VGCH and the node auxiliary connection hole NACH can penetrate the second interlayer insulating layer 127 and the third gate insulating layer 126.

[0176] The component layer 130 on the circuit layer 120 may include light-emitting elements LE respectively disposed in the emission regions EA1, EA2 and EA3.

[0177] Each of the light-emitting elements LE may include a structure in which a light-emitting layer 133 is disposed between an anode electrode 131 and a cathode electrode 134 facing each other.

[0178] According to an embodiment, the element layer 130 may include an anode electrode 131 disposed in the emission region EA, a pixel defining layer 132 disposed in the non-emission region NEA and covering the edge portion of the anode electrode 131, a spacer layer 132' disposed on a portion of the pixel defining layer 132, a light-emitting layer 133 disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133, the pixel defining layer 132, and the spacer layer 132'.

[0179] In another example, each of the light-emitting elements LE may also include a first common layer 135 disposed between the anode electrode 131 and the light-emitting layer 133 and a second common layer 136 disposed between the light-emitting layer 133 and the cathode electrode 134.

[0180] The encapsulation layer 140 can be disposed on the circuit layer 120 and cover the component layer 130.

[0181] Encapsulation layer 140 can prevent oxygen or moisture from penetrating into component layer 130 and reduce the impact or physical effects on circuit layer 120 and component layer 130.

[0182] The encapsulation layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 is disposed on the circuit layer 120, covers the component layer 130, and includes an inorganic insulating material. The second encapsulation layer 142 is disposed on the first encapsulation layer 141, overlaps with the component layer 130, and includes an organic insulating material. The third encapsulation layer 143 is disposed on the first encapsulation layer 141, covers the second encapsulation layer 142, and includes an inorganic insulating material.

[0183] The touch sensor layer 150 can be disposed on the encapsulation layer 140.

[0184] The polarization layer 160 can be disposed on the touch sensor layer 150.

[0185] As an example, the polarization layer 160 can be attached to the touch sensor layer 150 via an adhesive layer between the polarization layer 160 and the touch planarization layer 153.

[0186] Figure 7 This illustrates an embodiment. Figure 1 The layout diagram of part A.

[0187] refer to Figure 7 The display panel 100 of the display device 10 according to the embodiment may include a substrate 110 and a circuit layer 120 on the substrate 110.

[0188] The substrate 110 may include a main region MA and a sub-region SBA protruding from one side of the main region MA, and the main region MA may include an emission region EA disposed therein (see Figure 4 The display area DA and the non-display area NDA set around the display area DA.

[0189] like Figure 4 and Figure 5 As shown, the circuit layer 120 may include a light-emitting pixel driver EPD, which is arranged side by side on a first direction DR1 and a second direction DR2, and is electrically connected to the light-emitting element LE of the element layer 130, respectively.

[0190] like Figure 7 As shown, circuit layer 120 may further include a first power line VDL, which is disposed in display area DA, extends in the second direction DR2, and carries the first power line ELVDD (see Figure 1). Figure 5 The signal is transmitted to the luminous pixel driver EPD.

[0191] Circuit layer 120 may also include a data line DL, disposed in display area DA, extending in the second direction DR2, adjacent to the first power line VDL, and transmitting data signal Vdata (see...). Figure 5 ).

[0192] According to an embodiment, circuit layer 120 may include a power sensing line VDTL and a power sensing extension line VDTEXL. The power sensing line VDTL is disposed in the non-display area NDA and electrically connected to one of the first power lines VDL. The power sensing extension line VDTEXL is electrically connected to the power sensing line VDTL and contacts one side of the edge portion of the sub-area SBA.

[0193] A power sensing line VDTL can extend from a first side SD1, adjacent to and facing the sub-region SBA, within the edge portion of the display area DA to the sub-region SBA. For example, the power sensing line VDTL can be electrically connected to the portion of a first power line VDL adjacent to the first side SD1.

[0194] According to an embodiment, the circuit layer 120 may also include pads PD disposed in the sub-region SBA and connected to the circuit board 200.

[0195] The pad PD can be located in the second sub-region SB2. For example, the curved region BA of the sub-region SBA can be transformed into a curved shape so that the circuit board 200 connected to the pad PD can be accommodated in the rear surface of the display panel 100.

[0196] The pad PD may include a power sensing transfer pad VDTPD that is electrically connected to the power sensing line VDTL.

[0197] The power sensing line VDTL can extend from the first side SD1 of the display area DA to the sub-area SBA, and can be connected to one side of the power sensing transmission pad VDTPD.

[0198] The power sensing line VDTL may include a dam area DMA (see...) Figure 8 The overlapping bypass portion BYP1, the first main portion MNP11 disposed between a first power line VDL and the bypass portion BYP1, and the second main portion MNP21 disposed between the power sensing transmission pad VDTPD and the bypass portion BYP1.

[0199] The power sensing extension line VDTEXL can extend from the other side of the power sensing transfer pad VDTPD to one side of the edge portion of the sub-region SBA.

[0200] For example, the power sensing transfer pad VDTPD can be set and electrically connected between the power sensing line VDTL and the power sensing extension line VDTEXL.

[0201] According to an embodiment, the circuit layer 120 may further include a power sensing auxiliary line VDTAL, which is disposed in the non-display area NDA and electrically connected to another first power line VDL in the first power line VDL.

[0202] The power sensing auxiliary line VDTAL can extend from the second side SD2, facing the first side SD1, within the edge portion of the display area DA to the sub-area SBA. For example, the power sensing auxiliary line VDTAL can be electrically connected to the portion of another first power line VDL adjacent to the second side SD2.

[0203] The pad PD may also include a power sensing additional pad VDAPD that is electrically connected to the power sensing additional line VDTAL.

[0204] Similar to the power sensing line VDTL, the power sensing supplementary line VDTAL can include a dam region DMA (see [link]). Figure 8 The overlapping bypass portion BYP2, the first main portion MNP12 disposed between another first power line VDL and the bypass portion BYP2, and the second main portion MNP22 disposed between the power sensing additional pad VDAPD and the bypass portion BYP2.

[0205] According to the embodiment, the voltage level at the end of a first power line VDL adjacent to the first side SD1 can be transmitted to the circuit board 200 via the power sensing line VDTL and the power sensing transfer pad VDTPD. Furthermore, the voltage level at the end of another first power line VDL adjacent to the second side SD2 can be transmitted to the circuit board 200 via the power sensing auxiliary line VDTAL and the power sensing auxiliary pad VDAPD. Therefore, it is easy to sense whether the voltage level of the first power supply ELVDD provided to the light-emitting pixel driver EPD via the first power line VDL is normal. Therefore, the correction of the voltage level of the first power supply ELVDD can be facilitated, and the image quality of the display device 10 can be improved.

[0206] The power sensing add-on line VDTAL can extend from the second side SD2, which is away from the sub-region SBA, parallel to the third side SD3, and can be connected to the power sensing add-on pad VDAPD of the sub-region SBA.

[0207] For example, the power sensing line VDTL can be connected from the first side SD1 facing the sub-region SBA to one side of the power sensing transfer pad VDTPD of the sub-region SBA, and therefore can be extended to a shorter length than the power sensing supplementary line VDTAL. As a result, the power sensing line VDTL can be more susceptible to electrostatic discharge (ESD) than the power sensing supplementary line VDTAL.

[0208] According to the implementation, since circuit layer 120 includes a power sensing extension line VDTEXL extending from one side of the power sensing transfer pad VDTPD to one side of the edge portion of the sub-region SBA, electrostatic ESD introduced through the pad PD during illumination inspection (see [link to implementation]) is reduced. Figure 17 It can flow not only to the power sensing line VDTL, but also disperse into the power sensing extension line VDTEXL, thereby preventing the power sensing line VDTL from breaking due to the concentration of electrostatic ESD.

[0209] According to an embodiment, the circuit layer 120 may further include a first power supply line VDSPL and a first power supply extension line VDEXL. The first power supply line VDSPL is disposed in the non-display area NDA, extends to the sub-area SBA, and transmits a first power supply ELVDD. The first power supply extension line VDEXL is electrically connected to the first power supply line VDSPL and contacts one side of the edge portion of the sub-area SBA.

[0210] The pad PD may also include a first power pad VDPD that is electrically connected to the first power supply line VDSPL.

[0211] The first power pad VDPD can be set and electrically connected between the first power supply line VDSPL and the first power supply extension line VDEXL.

[0212] The circuit layer 120 may also include a second power supply line VSSPL and a second power supply extension line VSEXL. The second power supply line VSSPL is disposed in the non-display area NDA, extends to the sub-area SBA, and transmits the second power supply ELVSS. The second power supply extension line VSEXL is electrically connected to the second power supply line VSSPL and contacts one side of the edge portion of the sub-area SBA.

[0213] The pad PD may also include a second power pad VSPD that is electrically connected to the second power supply line VSSPL.

[0214] The second power pad VSPD can be set and electrically connected between the second power supply line VSSPL and the second power extension line VSEXL.

[0215] Pad PD can also include data pad DTPD, which transmits the data signal Vdata of the data line DL.

[0216] The circuit layer 120 may also include a data supply line DTSPL and a data extension line DTEXL. The data supply line DTSPL is disposed in the non-display area NDA and the sub-area SBA and electrically connects the data line DL to the data pad DTPD. The data extension line DTEXL is electrically connected to the data supply line DTSPL, extends from the data pad DTPD, and contacts one side of the edge portion of the sub-area SBA.

[0217] Figure 8 This illustrates an embodiment. Figure 7 Plan view of part D. Figure 9 It is along Figure 8 A sectional view taken from line E-E'.

[0218] like Figure 8 As shown, according to an embodiment, the power sensing line VDTL may include a bypass portion BYP1 that overlaps with the dam region DMA, a first main portion MNP11 electrically connected to one side of the bypass portion BYP1, and a second main portion MNP21 electrically connected to the other side of the bypass portion BYP1.

[0219] refer to Figure 9 The bypass portion BYP1 of the power sensing line VDTL can be disposed on the first gate conductive layers G1, G2, and G6 on the first gate insulating layer 123 (see...). Figure 6 ), the second gate conductive layer CAE and LB2 on the second gate insulating layer 124 (see Figure 6 ) and the third gate conductive layer G4 on the third gate insulating layer 126 (see Figure 6 At least one of them.

[0220] Each of the first main portion MNP11 and the second main portion MNP21 of the power sensing line VDTL can be disposed on the first source / drain conductive layers ANCE1, VGIL, and DCE on the second interlayer insulating layer 127 (see...). Figure 6 ) and the second source / drain conductive layers DL and ANCE2 on the first planarization layer 128 (see Figure 6 At least one of them.

[0221] For example, such as Figure 9 As shown, the bypass portion BYP1 of the power sensing line VDTL can be disposed on the third gate conductive layer on the third gate insulating layer 126.

[0222] The first main portion MNP11 of the power sensing line VDTL may include a first main line layer MNL11 and a second main line layer MNL21. The first main line layer MNL11 is disposed on the first source-drain conductive layer on the second interlayer insulating layer 127 and is electrically connected to one side of the bypass portion BYP1 through the bypass connection hole BYCH. The second main line layer MNL21 is disposed on the second source-drain conductive layer on the first planarization layer 128 and is electrically connected to the first main line layer MNL11.

[0223] For example, the second main portion MNP21 of the power sensing line VDTL may include a first main layer MNL12 and a second main layer MNL22. The first main layer MNL12 is disposed on the first source-drain conductive layer on the second interlayer insulating layer 127 and is electrically connected to the other side of the bypass portion BYP1 through the bypass connection hole BYCH. The second main layer MNL22 is disposed on the second source-drain conductive layer on the first planarization layer 128 and is electrically connected to the first main layer MNL12.

[0224] like Figure 8 As shown, according to an embodiment, the bypass portion BYP1 of the power sensing line VDTL may have an uneven shape including a clamp portion ZG whose extension direction is variable.

[0225] In each of the fixture sections ZG, the extension direction of the bypass section BYP1 can change from the first direction DR1 to the second direction DR2, or it can change from the second direction DR2 to the first direction DR1.

[0226] For example, when the bypass portion BYP1 includes the clamp portion ZG, the total extension length of the power sensing line VDTL can be longer, thereby ensuring that the resistance of the power sensing line VDTL is at or above the threshold for sensing the voltage level of the first power supply ELVDD.

[0227] According to the implementation, similar to the power sensing line VDTL, the first power supply line VDSPL may include a bypass portion BYP3 that overlaps with the dam region DMA, a first main portion MNP13 electrically connected to one side of the bypass portion BYP3, and a second main portion MNP23 electrically connected to the other side of the bypass portion BYP3.

[0228] The first main portion MNP13 of the first power supply line VDSPL can be disposed adjacent to the first side SD1 of the edge portion of the display area DA, and can extend to the bypass portion BYP3 of the first power supply line VDSPL.

[0229] The second main portion MNP23 of the first power supply line VDSPL can extend from the bypass portion BYP3 of the first power supply line VDSPL to the first power supply pad VDSPD.

[0230] According to the implementation, similar to the power sensing line VDTL, the second power supply line VSSPL may include a bypass portion BYP4 that overlaps with the dam region DMA, a first main portion MNP14 electrically connected to one side of the bypass portion BYP4, and a second main portion MNP24 electrically connected to the other side of the bypass portion BYP4.

[0231] The first main section MNP14 of the second power supply line VSSPL can surround the periphery of the display area DA and extend to the bypass section BYP4 of the second power supply line VSSPL.

[0232] The second main portion MNP24 of the second power supply line VSSPL can extend from the bypass portion BYP4 of the second power supply line VSSPL to the second power supply pad VSSPD.

[0233] Each of the bypass portion BYP3 of the first power supply line VDSPL and the bypass portion BYP4 of the second power supply line VSSPL can be disposed on the first gate conductive layers G1, G2, and G6 on the first gate insulating layer 123 (see...). Figure 6 ), the second gate conductive layer CAE and LB2 on the second gate insulating layer 124 (see Figure 6 ) and the third gate conductive layer G4 on the third gate insulating layer 126 (see Figure 6 At least one of them.

[0234] Each of the first main portion MNP13 of the first power supply line VDSPL, the second main portion MNP23 of the first power supply line VDSPL, the first main portion MNP14 of the second power supply line VSSPL, and the second main portion MNP24 of the second power supply line VSSPL can be disposed on the first source / drain conductive layers ANCE1, VGIL, and DCE (see below) on the second interlayer insulating layer 127. Figure 6) or the second source / drain conductive layers DL and ANCE2 on the first planarization layer 128 (see Figure 6 At least one of them.

[0235] According to an embodiment, the circuit layer 120 may also include a plurality of constant voltage supply lines CVSPL1, CVSPL2 and CVSPL3 disposed in the non-display area NDA and the sub-area SBA.

[0236] One of the multiple constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3 can transmit the gate initialization voltage VGINT (see [link to relevant documentation]). Figure 5 ).

[0237] Another of the multiple constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3 can transmit the anode initialization voltage VAINT (see [link to relevant documentation]). Figure 5 ).

[0238] One of the multiple constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3 can transmit one of the gate high and gate low voltages. Gate high and gate low voltages can be provided to generate the scan write signal GW (see [link to CVSPL3]). Figure 5 (1) At least one of the following: transmit control signal EC, gate control signal GC, and bias control signal GB.

[0239] Similar to the power sensing line VDTL, the first constant voltage supply line CVSPL1 among the multiple constant voltage supply lines CVSPL1, CVSPL2 and CVSPL3 may include a bypass portion BYP5 overlapping with the dam region DMA, a first main portion MNP15 electrically connected to one side of the bypass portion BYP5, and a second main portion MNP25 electrically connected to the other side of the bypass portion BYP5.

[0240] Similar to the power sensing line VDTL, the second constant voltage supply line CVSPL2 among the multiple constant voltage supply lines CVSPL1, CVSPL2 and CVSPL3 may include a bypass portion BYP6 overlapping with the dam region DMA, a first main portion MNP16 electrically connected to one side of the bypass portion BYP6, and a second main portion MNP26 electrically connected to the other side of the bypass portion BYP6.

[0241] Similar to the power sensing line VDTL, the third constant voltage supply line CVSPL3 among the multiple constant voltage supply lines CVSPL1, CVSPL2 and CVSPL3 may include a bypass portion BYP7 overlapping with the dam region DMA, a first main portion MNP17 electrically connected to one side of the bypass portion BYP7, and a second main portion MNP27 electrically connected to the other side of the bypass portion BYP7.

[0242] The bypass portions BYP5, BYP6, and BYP7 of multiple constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3 can be disposed on the first gate conductive layers G1, G2, and G6 on the first gate insulating layer 123 (see...). Figure 6 ), the second gate conductive layer CAE and LB2 on the second gate insulating layer 124 (see Figure 6 ) and the third gate conductive layer G4 on the third gate insulating layer 126 (see Figure 6 At least one of them.

[0243] Each of the first main sections MNP15, MNP16, and MNP17 and the second main sections MNP25, MNP26, and MNP27 of the multiple constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3 may be disposed on the first source / drain conductive layers ANCE1, VGIL, and DCE (see below) on the second interlayer insulating layer 127. Figure 6 ) and the second source / drain conductive layers DL and ANCE2 on the first planarization layer 128 (see Figure 6 At least one of them.

[0244] According to the implementation, in each of the first power supply line VDSPL, the second power supply line VSSPL, and the plurality of constant voltage supply lines CVSPL1, CVSPL2, and CVSPL3, the protrusion PRO can be arranged side by side in the edge portion of the bypass portions BYP2, BYP3, BYP4, BYP5, BYP6, and BYP7 that overlap with the dam area DMA, in the portion that does not overlap with the first main portions MNP12, MNP13, MNP14, MNP15, MNP16, and MNP17 and the second main portions MNP22, MNP23, MNP24, MNP25, MNP26, and MNP27.

[0245] For example, the length of the gap between the bypass portions BYP2, BYP3, BYP4, BYP5, BYP6 and BYP7 in the first power supply line VDSPL, the second power supply line VSSPL and the multiple constant voltage supply lines CVSPL1, CVSPL2 and CVSPL3 and the inorganic insulating material can be made longer, thereby delaying the permeation of oxygen or moisture through the periphery of the bypass portions BYP2, BYP3, BYP4, BYP5, BYP6 and BYP7.

[0246] Therefore, the lifespan of the display device 10 can be increased.

[0247] like Figure 9 As shown, according to the embodiment, a first dam portion DM1 surrounding the display area DA and a second dam portion DM2 surrounding the first dam portion DM1 can be arranged in the dam area DMA.

[0248] Each of the first dam section DM1 and the second dam section DM2 may include two or more dam layers DML11, DML21, DML31 and DML41, as well as DML12, DML22 and DML32.

[0249] Each of two or more dam layers DML11, DML21, DML31 and DML41, and DML12, DML22 and DML32, can be disposed on the same layer as one of the first planarization layer 128, the second planarization layer 129, the pixel definition layer 132 and the spacing layer 132'.

[0250] As an example, the first dam section DM1 may include a first dam layer DML11, a second dam layer DML21, a third dam layer DML31, and a fourth dam layer DML41. The first dam layer DML11 is disposed on the same layer as the first planarization layer 128, the second dam layer DML21 is disposed on the same layer as the second planarization layer 129, the third dam layer DML31 is disposed on the same layer as the pixel defining layer 132, and the fourth dam layer DML41 is disposed on the same layer as the spacing layer 132'.

[0251] For example, the second dam portion DM2 may include a first dam layer DML12, a second dam layer DML22, and a third dam layer DML32. The first dam layer DML12 is disposed on the same layer as the second planarization layer 129, the second dam layer DML22 is disposed on the same layer as the pixel limiting layer 132, and the third dam layer DML32 is disposed on the same layer as the spacing layer 132'.

[0252] The second planarization layer 129 may cover the second source / drain conductive layers MNL21 and MNL22 on the first planarization layer 128, and may be spaced apart from at least one of the dam portions DM1 or DM2 of the dam region DMA.

[0253] The pixel limiting layer 132 can be set on the second planarization layer 129.

[0254] Therefore, in the dam region DMA, the second interlayer insulating layer 127 can contact the first encapsulation layer 141 between the second planarization layer 129 and the first dam portion DM1, between the first dam portion DM1 and the second dam portion DM2, and between the second dam portion DM2 and the second planarization layer 129.

[0255] According to an embodiment, the first encapsulation layer 141 of the encapsulation layer 140 may include an inorganic insulating material covering the element layer 130.

[0256] The first encapsulation layer 141 can be disposed in the display area DA and can extend to the dam area DMA of the non-display area NDA.

[0257] The second encapsulation layer 142 may include an organic insulating material diffused in a region surrounded by at least one of the dam portions DM1 or DM2 disposed in the dam region DMA.

[0258] The third encapsulation layer 143 may include an inorganic insulating material covering the second encapsulation layer 142.

[0259] The third encapsulation layer 143 may extend to the dam region DMA of the non-display area NDA and may contact the first encapsulation layer 141.

[0260] Figure 10 , Figure 11 and Figure 12 This illustrates various embodiments. Figure 7 Plan view of part D.

[0261] according to Figure 10 The display device 10 of the embodiment shown in the figure and Figures 7 to 9 The implementation shown is essentially the same, except that the first main portion MNP11' disposed between a first power line VDL and a bypass portion BYP1' in the power sensing line VDTL, instead of the bypass portion BYP1' overlapping with the dam region DMA, has an uneven shape including a clamp portion ZG, and therefore redundant descriptions will be omitted below.

[0262] according to Figure 10 In one implementation, the bypass portion BYP1' of the power sensing line VDTL can be configured as a straight line.

[0263] Given that the bypass portion BYP1' of the power sensing line VDTL is located in at least one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer and has a relatively high resistance, static electricity may easily accumulate.

[0264] For example, as in Figure 8 In the implementation, when the bypass portion BYP1 of the power sensing line VDTL includes a clamp portion ZG, excessive electrostatic discharge (ESD) may occur due to excessive concentration of ESD in the clamp portion ZG of the bypass portion BYP1 (see [link to implementation details]). Figure 17 Overheating can occur, leading to cracking or breakage defects in the bypass section BYP1. For example, due to interface warping defects in the insulation layer around the point where the bypass section BYP1 cracks, oxygen or moisture penetration paths are created, which may significantly reduce the lifespan of the display device 10.

[0265] For example, according to Figure 10 In this implementation, since the bypass portion BYP1' of the power sensing line VDTL is configured as a straight line, even electrostatic discharge (ESD) (see [link to implementation details]) is mitigated. Figure 17Even when introduced into the bypass section BYP1', excessive concentration will not occur, thereby reducing cracking and breakage defects caused by overheating. As a result, the lifespan of the display device 10 can be improved.

[0266] according to Figure 10 In this implementation, the first main portion MNP11' of the power sensing line VDTL can be configured as a concave-convex shape including the clamp portion ZG, instead of configuring the bypass portion BYP1' of the power sensing line VDTL as a straight shape. This ensures that the resistance of the power sensing line VDTL is a threshold or higher for sensing the voltage level of the first power supply ELVDD.

[0267] according to Figure 10 In one implementation, in the first direction DR1, the bypass portion BYP1' of the power sensing line VDTL may have a first width W1, and the clamping portion ZG of the first main portion MNP11' of the power sensing line VDTL may have a first clamping width W_ZG1.

[0268] according to Figure 11 The display device 10 of the embodiment shown in the figure and Figure 10 The implementation is basically the same, except that in the first direction DR1, the bypass portion BYP1' of the power sensing line VDTL has a second width W2 that is greater than the first width W1 to have low resistance, and the clamp portion ZG of the first main portion MNP11' of the power sensing line VDTL has a second clamp width W_ZG2 that is greater than the first clamp width W_ZG1, and therefore redundant descriptions will be omitted below.

[0269] For example, the bypass portion BYP1' of the power sensing line VDTL can have low resistance, thereby further reducing ESD due to electrostatic discharge (see [link to documentation]). Figure 17 This results in a disconnection defect in the bypass section BYP1'.

[0270] Figure 12 The display device 10 of the embodiment shown in the figure and Figure 10 and Figure 11 The implementation is basically the same, except that the protrusion PRO is arranged side by side on the edge of the bypass portion BYP1'' of the power sensing line VDTL, in a portion that does not overlap with the first main portion MNP11' and the second main portion MNP21, and therefore redundant descriptions will be omitted below.

[0271] By doing so, the gap between the bypass portion BYP1'' of the power sensing line VDTL and the inorganic insulating material can be made longer, thereby delaying the penetration of oxygen or moisture through the periphery of the bypass portion BYP1'' of the power sensing line VDTL.

[0272] Therefore, the lifespan of the display device 10 can be further improved.

[0273] Figure 13 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0274] refer to Figure 13 The method of manufacturing the display device 10 according to the embodiment may include preparing an inspection panel 100' (see Figure 14 (Step S10) By using the inspection pad area TPDA connected to the inspection panel 100' (see...) Figure 14 Check the connection pads TPD (see) Figure 15 The connectors ACNT and BCNT of the inspection device (see) Figure 16 The process involves performing an illumination inspection on the inspection panel 100' (step S20), preparing the display panel 100 by removing the inspection pad area TPDA in the inspection panel 100' (step S30), and bonding the circuit board 200 to the pad PD of the sub-area SBA in the display panel 100 (step S40).

[0275] Figure 14 This illustrates the preparation according to the embodiment. Figure 13 The inspection panel floor plan during the inspection panel steps. Figure 15 This illustrates an embodiment. Figure 14 The layout diagram of part F. Figure 16 and Figure 17 This illustrates the execution according to the implementation method. Figure 13 The process diagram for the lighting inspection steps.

[0276] refer to Figure 14 In preparation for inspection panel 100' (see Figure 14 In step S10, the display device 10 according to the embodiment may include an inspection panel 100', and the inspection panel 100' may include a substrate 110, a circuit layer 120 and a component layer 130.

[0277] The substrate 110 of the inspection panel 100' may include not only the main region MA and the sub-region SBA, but also an inspection pad region TPDA connected to one side of the edge portion of the sub-region SBA.

[0278] refer to Figure 15 The circuit layer 120 of the inspection panel 100' may also include inspection connection pads TPD disposed in the inspection pad area TPDA and inspection connection lines CNL disposed in the inspection pad area TPDA and extending from one side of the edge portion of the sub-area SBA.

[0279] Check that at least some of the connection lines CNL can be connected to the check connection pad TPD.

[0280] The connector ACNT for the inspection device that provides inspection signals for illumination inspection (see [link]). Figure 16 It can be connected to the inspection connection pad TPD.

[0281] Checking the connection line CNL may include the power sensing dummy line VDTDL connected to the power sensing extension line VDTEXL.

[0282] The inspection of the connection pad TPD may include the dummy pad DMPD that is electrically connected to the power sensing dummy line VDTDL.

[0283] According to an implementation, the inspection connection line CNL may further include a first power connection line VDCNL connected to the first power extension line VDEXL, a second power connection line VSCNL connected to the second power extension line VSEXL, and a data connection line DTCNL connected to the data extension line DTEXL.

[0284] For example, the inspection connection pad TPD may also include a first power supply pad VDSPD electrically connected to a first power connection line VDCNL, a second power supply pad VSSPD electrically connected to a second power connection line VSCNL, and an inspection data supply pad DTSPD electrically connected to a data connection line DTCNL.

[0285] The first power connection line VDCNL can be connected to the first power extension line VDEXL at the boundary between the sub-region SBA and the inspection pad region TPDA, and can extend to the first power pad VDSPD.

[0286] The second power connection line VSCNL can be connected to the second power extension line VEXL at the boundary between the sub-region SBA and the inspection pad region TPDA, and can extend to the second power pad VSSPD.

[0287] The data connection line DTCNL can be connected to the data extension line DTEXL at the boundary between the sub-region SBA and the inspection pad region TPDA, and can extend to the inspection data supply pad DTSPD.

[0288] According to an embodiment, the power sensing line VDTL can be used to sense the voltage level of the first power supply ELVDD applied to the first side SD1 of the display area DA, and a power sensing auxiliary line VDTAL can be provided in the circuit layer 120 to sense the voltage level of the first power supply ELVDD applied to the second side SD2 of the display area DA. Therefore, the inspection device for illumination inspection does not need to be electrically connected to the power sensing line VDTL and the power sensing auxiliary line VDTAL.

[0289] According to the implementation, unlike the power sensing supplementary line VDTAL disposed in a relatively long path between the second side SD2 and the sub-region SBA, the power sensing line VDTL can be disposed in a relatively short path between the first side SD1 and the sub-region SBA. However, the power sensing line VDTL can have a relatively thin width because it is intended to transmit signals rather than power, and similar to the power sensing supplementary line VDTAL, the power sensing line VDTL may be prone to breakage defects due to electrostatic discharge (ESD) because it includes a clamping portion ZG with a threshold or higher resistance to sense the voltage level of the first power supply ELVDD.

[0290] According to an embodiment, to prevent electrostatic discharge (ESD) from accumulating on the power sensing line VDTL, circuit layer 120 may include a power sensing extension line VDTEXL, a power sensing dummy line VDTDL, and a dummy pad DMPD electrically connected to the power sensing line VDTL and the power sensing transfer pad VDTPD. For example, ESD introduced into the power sensing transfer pad VDTPD can discharge to the power sensing extension line VDTEXL, the power sensing dummy line VDTDL, and the dummy pad DMPD.

[0291] refer to Figure 16 In step S20 of performing the lighting inspection, the A connector ACNT of the inspection device can be connected to the inspection connection pad TPD of the inspection pad area TPDA, and the B connector BCNT of the inspection device can be connected to the pad PD of the second sub-area SB2.

[0292] Therefore, various inspection signals from the inspection device used for lighting inspection can be applied to the inspection connection pad TPD connected to connector A (ACNT) and the pad PD connected to connector B (BCNT).

[0293] However, as Figure 17 As shown, when the B connector BCNT of the inspection device is connected to the pad PD of the second sub-region SB2, electrostatic discharge (ESD) can be introduced into the pad PD.

[0294] Figure 18 This shows the execution based on the comparison example. Figure 13 The process diagram for the lighting inspection steps.

[0295] As in Figure 18In the comparative example REF shown, when the power sense transfer pad VDTPD is only connected to the power sense line VDTL, the electrostatic discharge (ESD) introduced around the power sense transfer pad VDTPD may be concentrated on the power sense line VDTL through the first electrostatic path FL1. At this time, since the bypass portion BYP1 of the power sense line VDTL is located in at least one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer and has relatively high resistance, the ESD from the first electrostatic path FL1 may be concentrated on the bypass portion BYP1 of the power sense line VDTL, causing the bypass portion BYP1 of the power sense line VDTL to overheat, and as a result, a disconnection defect ERR of the power sense line VDTL may occur.

[0296] For example, such as Figure 17 As shown, according to an embodiment, the system includes a power sensing extension line VDTEXL, a power sensing dummy line VDTDL, and a dummy pad DMPD electrically connected to the power sensing line VDTL and the power sensing transfer pad VDTPD. Therefore, electrostatic discharge (ESD) introduced around the power sensing transfer pad VDTPD can be transmitted to the power sensing line VDTL via a first electrostatic path FL1, and can be dispersed into the power sensing extension line VDTEXL, the power sensing dummy line VDTDL, and the dummy pad DMPD via a second electrostatic path FL2.

[0297] Therefore, since the amount of electrostatic ESD introduced into the power sensing line VDTL through the first electrostatic path FL1 can be reduced, the disconnection defect of the power sensing line VDTL due to electrostatic ESD can be reduced.

[0298] Figure 19 This illustrates an embodiment according to another method. Figure 14 The layout diagram of part F.

[0299] Figure 19 The display device 10 of the embodiment shown in the figure and Figure 15 , Figure 16 and Figure 17 The implementation shown is essentially the same, except that the inspection panel 100' does not include the dummy pad DMPD, and the power sensing dummy line VDTDL is electrically connected to the first power connection line VDCNL, and therefore redundant descriptions will be omitted below.

[0300] For example, even without providing a dummy pad DMPD, the electrostatic discharge (ESD) around the power sensing transfer pad VDTPD can be dispersed to one side of the power sensing extension line VDTEXL, the power sensing dummy line VDTDL, the first power connection line VDCNL, and the first power supply pad VDSPD.

[0301] Therefore, since the dummy pad DMPD, which does not need to be connected to the inspection device, can be removed, the structure of the inspection panel 100' can be simplified.

[0302] Subsequently, as Figure 7 As shown, the display panel 100 can be prepared by removing the inspection pad area TPDA from the inspection panel 100' (step S30).

[0303] For example, such as Figure 1 As shown, the display device 10 can be prepared by attaching the circuit board 200 to the display panel 100 (step S40).

[0304] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirit within the equivalent scope is included within the scope of this disclosure.

Claims

1. A display device, comprising: Display panel; as well as The circuit board is attached to the display panel. The display panel includes: Substrate; A circuit layer is disposed on the substrate; and Component layer, disposed on the circuit layer, The substrate includes a main region and a sub-region protruding from one side of the main region. The main area includes: The display area includes a transmission area; and The non-display area is located around the display area. The element layer includes light-emitting elements respectively disposed in the emitting region, and The circuit layer includes: The light-emitting pixel drivers are arranged side by side in a first direction and a second direction, and are electrically connected to the light-emitting elements respectively; A first power line is disposed in the display area, extends in the second direction, and transmits a first power supply to the light-emitting pixel driver; A power sensing line, disposed in the non-display area, extends from a first side of the edge portion of the display area facing the sub-region and adjacent to the sub-region to the sub-region, and is electrically connected to one of the first power lines; and A power sensing extension line is electrically connected to the power sensing line and contacts one side of the edge portion of the sub-region.

2. The display device according to claim 1, wherein, The circuit layer also includes pads disposed in the sub-region and connected to the circuit board. The pads include power sensing transmission pads electrically connected to the power sensing line. The power sensing line is connected to one side of the power sensing transmission pad, and The power sensing extension line extends from the other side of the power sensing transmission pad to one side of the edge portion of the sub-region.

3. The display device according to claim 2, wherein, The circuit layer further includes a power sensing auxiliary line disposed in the non-display area, extending from a second side of the edge portion of the display area opposite to the first side of the edge portion of the display area to the sub-region, and electrically connected to another first power line in the first power line. The pad also includes a power sensing additional pad electrically connected to the power sensing additional line.

4. The display device according to claim 2, further comprising: An encapsulation layer is disposed on the component layer; as well as At least one dam section is disposed in the dam area surrounding the display area within the non-display area. The circuit layer further includes: A first gate insulating layer is disposed on the substrate; A first gate conductive layer is disposed on the first gate insulating layer; A second gate insulating layer covers the first gate conductive layer; The second gate conductive layer is disposed on the second gate insulating layer; A first interlayer insulating layer covers the second gate conductive layer; A third gate insulating layer is disposed on the first interlayer insulating layer; A third gate conductive layer is disposed on the third gate insulating layer; The second interlayer insulating layer covers the third gate conductive layer; The first source / drain conductive layer is disposed on the second interlayer insulating layer; A first planarization layer covers the first source / drain conductive layer; A second source / drain conductive layer is disposed on the first planarization layer; and A second planarization layer covers the second source / drain conductive layer. The bypass portion of the power sensing line that overlaps with the dam region is disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer. The power sensing line is disposed between the bypass portion and the first power line, with the first main portion disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer. The power sensing line is disposed on a second main portion between the bypass portion and the power sensing transmission pad, and is disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

5. The display device according to claim 4, wherein, The bypass portion has the form of a clamping portion, the extension direction of which can be varied.

6. The display device according to claim 4, wherein, The portion of the first main section of the power sensing line adjacent to the bypass section has the form of a clamping portion, the extension direction of which can be varied.

7. The display device according to claim 6, wherein, The total extension length of the clamp portion corresponds to the width of the bypass portion.

8. The display device according to claim 4, wherein, The encapsulation layer includes: A first encapsulation layer is disposed on the component layer; A second encapsulation layer is disposed on the first encapsulation layer; and A third encapsulation layer is disposed on the first encapsulation layer and covers the second encapsulation layer. Each of the first and third encapsulation layers comprises an inorganic insulating material. The second encapsulation layer includes an organic insulating material disposed in the region surrounded by the at least one dam portion, and The third encapsulation layer contacts the first encapsulation layer at the outside of the dam area.

9. The display device according to claim 2, wherein, The substrate also includes an inspection pad area connected to one side of the edge portion of the sub-region, and The circuit layer also includes: The inspection pads are connected to a connector located in the inspection pad area and connected to an inspection device, which provides an inspection signal for illumination inspection; and The inspection connection line is positioned in the inspection pad area and extends from one side of the edge portion of the sub-region. The inspection connection line includes a power sensing dummy line connected to the power sensing extension line.

10. The display device according to claim 9, wherein, The inspection connection pads include dummy pads electrically connected to the power sensing dummy line.

11. The display device according to claim 9, wherein, The circuit layer also includes: A first power supply line is disposed in the non-display area and transmits the first power supply; and A first power extension line is electrically connected to the first power supply line and contacts one side of the edge portion of the sub-region. The inspection connection cable also includes a first power connection cable connected to the first power extension cable. The inspection connection pads also include a first power supply pad electrically connected to the first power connection line, and The power sensing dummy line is electrically connected to the first power connection line.

12. A method for manufacturing a display device, the method comprising: Prepare the inspection panel; An illumination inspection is performed on the inspection panel by using an inspection device connected to the inspection pad area in the inspection panel. The display panel is prepared by removing the inspection pad area in the inspection panel; as well as The circuit board is bonded to the pads of a sub-region in the display panel. When preparing the inspection panel, the inspection panel includes: Substrate; A circuit layer is disposed on the substrate; and Component layer, disposed on the circuit layer, The substrate includes: The main area includes a display area in which the emission area is arranged and a non-display area disposed around the display area; and A sub-region protrudes from one side of the main region and has a side connected to the inspection pad region. The element layer includes light-emitting elements respectively disposed in the emission region. The circuit layer includes: The light-emitting pixel drivers are arranged side by side in a first direction and a second direction, and are electrically connected to the light-emitting elements respectively; A first power line is disposed in the display area, extends in the second direction, and transmits a first power supply to the light-emitting pixel driver; A power sensing line is disposed in the non-display area, extends from a first side of the edge portion of the display area facing the sub-region and adjacent to the sub-region to the sub-region, and is electrically connected to one of the first power lines. A power sensing extension line is electrically connected to the power sensing line and contacts one side of the edge portion of the sub-region; Inspect the connection pads, which are located in the inspection pad area; and The inspection connection line is positioned in the inspection pad area and extends from one side of the edge portion of the sub-region. The inspection connection line includes a power sensing dummy line electrically connected to the power sensing extension line.

13. The method according to claim 12, wherein, When preparing the inspection panel The circuit layer also includes pads disposed in the sub-region and connected to the circuit board. The pads include power sensing transmission pads electrically connected to the power sensing line. The power sensing line is connected to one side of the power sensing transmission pad, and The power sensing extension line extends from the other side of the power sensing transmission pad to one side of the edge portion of the sub-region.

14. The method according to claim 13, wherein, The inspection connection pads include dummy pads electrically connected to the power sensing dummy line.

15. The method according to claim 13, wherein, In preparing the inspection panel, the circuit layer further includes: A first power supply line is disposed in the non-display area and transmits the first power supply; and A first power extension line is electrically connected to the first power supply line and contacts one side of the edge portion of the sub-region. The inspection connection cable also includes a first power connection cable connected to the first power extension cable, and The inspection connection pad also includes a first power supply pad electrically connected to the first power supply connection line.

16. The method according to claim 15, wherein, The power sensing dummy line is electrically connected to the first power connection line.

17. The method according to claim 13, wherein, When preparing the inspection panel The circuit layer further includes a power sensing auxiliary line disposed in the non-display area, extending from a second side of the edge portion of the display area opposite to the first side of the edge portion of the display area to the sub-region, and electrically connected to another first power line in the first power line. The pad also includes a power sensing additional pad electrically connected to the power sensing additional line.

18. The method according to claim 13, wherein, In preparing the inspection panel, the inspection panel further includes at least one dam portion disposed in the dam area surrounding the display area in the non-display area. The circuit layer also includes: A first gate insulating layer is disposed on the substrate; A first gate conductive layer is disposed on the first gate insulating layer; A second gate insulating layer covers the first gate conductive layer; The second gate conductive layer is disposed on the second gate insulating layer; A first interlayer insulating layer covers the second gate conductive layer; A third gate insulating layer is disposed on the first interlayer insulating layer; A third gate conductive layer is disposed on the third gate insulating layer; The second interlayer insulating layer covers the third gate conductive layer; The first source / drain conductive layer is disposed on the second interlayer insulating layer; A first planarization layer covers the first source / drain conductive layer; A second source / drain conductive layer is disposed on the first planarization layer; and A second planarization layer covers the second source / drain conductive layer. The bypass portion of the power sensing line that overlaps with the dam region is disposed on one of the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer. The power sensing line is disposed between the bypass portion and the first power line, with the first main portion disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer. The power sensing line is disposed on a second main portion between the bypass portion and the power sensing transmission pad, and is disposed on at least one of the first source-drain conductive layer and the second source-drain conductive layer.

19. The method according to claim 18, wherein, The bypass portion has the form of a clamping portion, the extension direction of which can be varied.

20. The method according to claim 18, wherein, The portion of the first main section of the power sensing line adjacent to the bypass section has the form of a clamping portion, the extension direction of which can be varied.

Images