Processor hardware monitoring circuit and method based on watchdog device and logic device

Abstract

The application provides a kind of processor hardware monitoring circuit and method based on watchdog device and logic device, watchdog device receives the dog feeding signal of processor, the input end of decoder is connected with the output end of counter respectively, and the corresponding signal is sent by decoder according to the output end of count value;One output end of decoder is connected with the input end of corresponding monostable circuit, and the output end of the monostable circuit sends the interrupt signal to processor;The output end of the maximum count value of decoder is connected with the other output end of monostable circuit connected with standby power module;The output end of AND gate is connected with processor, and the output processor reset signal is sent.The advantages are that pure hardware circuit is used to realize, the reliability is improved, and the cost is effectively reduced;The working state of monitoring star computer processor is realized, and the problems such as star computer software runaway are prevented;It is suitable for low-cost commercial satellite star computer.

Description

Technical Field

[0001] This invention relates to a monitoring circuit and method for a processor of a spaceborne computer, mainly applied to the satellite computer of a low-cost commercial satellite. It is used to monitor the working status of the satellite computer processor, prevent the satellite computer software from crashing, and prevent the satellite from failing to generate a reset signal after crashing, which would ultimately lead to loss of attitude control of the entire satellite. Background Technology

[0002] The satellite operational computer processes satellite platform information, performs remote and telemetry processing, attitude control, orbit control, autonomous thermal control, energy monitoring, solar panel control, and collects status data from platform equipment, as well as manages the satellite's autonomous health. After equipment shutdown, reset, and restart, it can restore critical satellite data, providing the necessary support for satellite operation.

[0003] The processor is the core of the entire satellite computer. The satellite computer provides the hardware environment, and the satellite software runs on the satellite computer. The processor is the carrier for the satellite software to run. The satellite software may crash or get stuck in an infinite loop for some reason. It is necessary to monitor the running status of the processor to prevent the software from crashing and causing the entire satellite's attitude to become out of control.

[0004] Currently, antifuse FPGAs are commonly used as monitoring devices for processors. The processor periodically inputs changing voltage levels to the FPGA pins or writes data to a specific address of the processor (all uniformly defined as a dog-feeding signal). If the dog-feeding time is exceeded, the processor is reset. After generating dog-feeding signals multiple times, the FPGA sends a power switch command to switch the spacecraft computer to the backup spacecraft computer.

[0005] However, antifuse FPGAs have limited logic resources, a small number of I / O ports, and can only be programmed once, making them expensive and unsuitable for commercial aerospace applications. Traditional aerospace processor monitoring suffers from high costs, significant modification costs, and is unsuitable for mass production. Summary of the Invention

[0006] This invention provides a processor hardware monitoring circuit based on a watchdog device and logic devices. It is implemented using pure hardware circuitry and does not involve FPGA. While improving reliability, it can effectively reduce costs. It can monitor the working status of the satellite computer processor, prevent the satellite computer software from crashing, and prevent the satellite from failing to generate a reset signal after crashing, which would eventually lead to loss of attitude control of the entire satellite. It is particularly suitable for satellite computers of low-cost commercial satellites, thus overcoming the shortcomings of the prior art.

[0007] This invention provides a processor hardware monitoring circuit based on a watchdog device and logic devices, comprising: a counter, a watchdog device, a decoder, several monostable circuits, and an AND gate; the watchdog device receives a feed signal from the processor; the input terminals of the decoder are connected to the output terminals of the counter, and the decoder outputs a corresponding signal based on the count value; one output terminal of the decoder is connected to the input terminal of a corresponding monostable circuit, and the output terminal of the monostable circuit sends an interrupt signal to the processor; different output terminals of the AND gate are connected to the input terminals of corresponding monostable circuits, and the output terminals of the monostable circuits are connected to different input terminals of the AND gate; the output terminal of the decoder, which sets the maximum count value, is connected to another output terminal of the monostable circuit, which is then connected to a power supply module; the output terminal of the AND gate is connected to the processor and outputs a processor reset signal.

[0008] Furthermore, the present invention provides a processor hardware monitoring circuit based on a watchdog device and a logic device, which may also have the following features: it further includes a monostable circuit 0; wherein, the input terminal of the monostable circuit 0 is connected to the processor to receive a watchdog clearing count signal; the output terminal of the monostable circuit 0 is connected to the clear terminal of the counter to output a watchdog clearing count signal.

[0009] Furthermore, the present invention provides a processor hardware monitoring circuit based on a watchdog device and logic devices, which may also have the following features: it further includes a JK flip-flop and an OR gate; one input of the OR gate is connected to the output of the watchdog device, the other output is connected to the output of the JK flip-flop, and the output is connected to the CP terminal of the counter; the JK flip-flop will receive the disable / enable watchdog OC instruction and output it to the OR gate.

[0010] Furthermore, the present invention provides a processor hardware monitoring circuit based on a watchdog device and a logic device, which may also have the following features: the number of monostable circuits is four, namely monostable circuit 1, monostable circuit 2, monostable circuit 3 and monostable circuit 4; wherein, the decoder has four output terminals: Y1 terminal, Y2 terminal, Y3 terminal and Y4 terminal; the input terminal of monostable circuit 1 is connected to the Y1 terminal of the decoder, and the output terminal is connected to the processor to send an interrupt signal to the processor; the Y2 terminal, Y3 terminal and Y4 terminal of the decoder are respectively connected to the output terminals of monostable circuit 2, monostable circuit 3 and monostable circuit 4.

[0011] Furthermore, the present invention provides a processor hardware monitoring circuit based on a watchdog device and logic devices, which may also have the following feature: the AND gate has two input terminals that receive a power-on reset signal and an instruction reset signal, respectively.

[0012] In addition, the present invention also provides a processor hardware monitoring method based on a watchdog device and logic devices, comprising the following steps:

[0013] Step S1: Enable the watchdog device and reset the watchdog counter to zero upon power-up;

[0014] Step S2: Determine whether the watchdog device receives the processor's feed signal within the rated time;

[0015] If a feeding signal is received, the watchdog device waits for the next feeding signal; if no feeding signal is received, the watchdog device sends a bite signal.

[0016] Step S3: After receiving the dog-biting signal, the counter starts counting and sends the count value to the decoder.

[0017] Step S4: The decoder sends the corresponding operation signal based on the received value.

[0018] When the count value is 1, an interrupt signal is sent to the processor;

[0019] When the count reaches the set maximum value, a reset signal is sent to the processor, and the backup power supply is turned on.

[0020] If the count value is any other value, a reset signal is sent to the processor.

[0021] Furthermore, the present invention provides a processor hardware monitoring method based on a watchdog device and a logic device, which may also have the following feature: the maximum count value is 4;

[0022] When the count value is 2, a reset signal is sent to the processor;

[0023] When the count value is 3, a reset signal is sent to the processor;

[0024] When the count value is 4, a reset signal is sent to the processor; and the backup power supply is turned on.

[0025] Furthermore, the present invention provides a processor hardware monitoring method based on a watchdog device and logic devices, which may also have the following feature: in step S2, when an enable watchdog signal is received, a watchdog-biting signal is also issued. Attached Figure Description

[0026] Figure 1 This is a processor hardware monitoring circuit diagram based on watchdog devices and logic devices in the embodiment.

[0027] Figure 2 This is a flowchart of the processor hardware monitoring method based on watchdog devices and logic devices in the embodiment. Detailed Implementation

[0028] The present invention will now be further described with reference to the accompanying drawings and specific embodiments.

[0029] Example

[0030] In this embodiment, the processor hardware monitoring circuit based on the watchdog device and logic devices includes: a monostable circuit 0, a counter, a watchdog device, a JK flip-flop, an OR gate, a decoder, a monostable circuit 1, a monostable circuit 2, a monostable circuit 3, a monostable circuit 4, and an AND gate.

[0031] The input of monostable circuit 0 is connected to the processor to receive the dog bite count clearing signal; the output of monostable circuit 0 is connected to the clearing terminal of the counter to output the dog bite count clearing signal.

[0032] The watchdog device receives the feed signal from the processor, and the JK flip-flop receives the enable / disable watchdog OC instruction.

[0033] One input of the OR gate is connected to the output of the watchdog device, the other output is connected to the output of the JK flip-flop, and the output is connected to the CP terminal of the counter.

[0034] The decoder's three inputs are connected to the counter's three outputs, respectively. In this embodiment, the decoder has four outputs: Y1, Y2, Y3, and Y4. Theoretically, the decoder's three inputs can receive binary counting signals from 000 to 111 from the counter. In this embodiment, it receives counting signals from the counter four times.

[0035] When the counter counts to 1, the decoder receives 001, and the Y1 terminal of the decoder outputs a high level while the other output terminals output a low level.

[0036] When the counter counts to 2, the decoder receives 010, and the Y2 terminal of the decoder outputs a high level while the other output terminals output a low level.

[0037] When the counter counts to 3, the decoder receives 011, and the Y3 terminal of the decoder outputs a high level while the other output terminals output a low level.

[0038] When the counter counts to 4, the decoder receives 100, and the Y4 terminal of the decoder outputs a high level while the other output terminals output a low level.

[0039] The input of the monostable circuit 1 is connected to the Y1 terminal of the decoder, and the output is connected to the processor, sending an interrupt signal to the processor.

[0040] In this embodiment, the AND gate has five input terminals, three of which are connected to the output terminals of monostable circuits 2, 3, and 4, respectively. The fourth input terminal of the AND gate receives a power-on reset signal, and the fifth input terminal receives a command reset signal.

[0041] The output of the AND gate is connected to the processor, outputting a processor reset signal. The other output of the monostable circuit 4 is connected to the standby power module, outputting a standby power-on command to start the standby power module.

[0042] The processor hardware monitoring circuit based on watchdog devices and logic devices includes the following steps:

[0043] Step S1: Enable the watchdog device and reset the watchdog counter to zero upon power-up.

[0044] The processor sends a clear dog bite count signal, which sends a clear signal to the counter through single-temperature circuit 1, thus clearing the counter to zero.

[0045] Step S2: Determine whether the watchdog device receives the feed signal from the processor within the rated time.

[0046] If a feeding signal is received, the watchdog device waits for the next feeding signal.

[0047] If no dog-feeding signal is received, the watchdog device will send a dog-biting signal.

[0048] In addition, in this embodiment, upon receiving the watchdog enable signal, a dog-biting signal is also issued.

[0049] Step S3: After receiving the dog-biting signal, the counter starts counting and sends the count value to the decoder.

[0050] Step S4: The decoder sends the corresponding operation signal based on the received value.

[0051] When the count value is 1, an interrupt signal is sent to the processor;

[0052] When the count value is 2, a reset signal is sent to the processor;

[0053] When the count value is 3, a reset signal is sent to the processor;

[0054] When the count value is 4, a reset signal is sent to the processor; and the backup power supply is turned on.

[0055] In this embodiment, after a processor malfunctions, the processor is given three restart opportunities, and a backup unit is activated on the fourth attempt. The number of restarts can be arbitrarily set according to actual needs, simply by adding a corresponding number of monostable circuits. For some processors with special requirements, the number of restarts can also be reduced.

[0056] It should be noted that components not included in the technical solution of this invention are processors whose functions are the same as those of existing spacecraft computers, and the functions of the processors are not within the scope of protection of this invention.

[0057] The embodiments described above are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A processor hardware monitoring circuit based on a watchdog device and logic devices, characterized in that: include: Counter, watchdog device, decoder, several monostable circuits and AND gates; The watchdog device receives the feed signal from the processor. The input terminals of the decoder are connected to the output terminals of the counter, and the decoder outputs a corresponding signal based on the count value. One output of the decoder is connected to the input of the corresponding monostable circuit, and the output of the monostable circuit sends an interrupt signal to the processor. The different outputs of the AND gate are connected to the inputs of the corresponding monostable circuits, and the outputs of the monostable circuits are connected to the different inputs of the AND gates. The output terminal of the decoder, which sets the maximum count value, is connected to the other output terminal of the monostable circuit, which is then connected to the power supply module. The output of the AND gate is connected to the processor, outputting a processor reset signal.

2. The processor hardware monitoring circuit based on a watchdog device and logic devices as described in claim 1, characterized in that: It also includes monostable circuit 0; The input of the monostable circuit 0 is connected to the processor to receive the dog bite count signal; the output of the monostable circuit 0 is connected to the reset terminal of the counter to output the dog bite count signal.

3. The processor hardware monitoring circuit based on a watchdog device and logic devices as described in claim 1, characterized in that: Also includes: JK flip-flops and OR gates; One input of the OR gate is connected to the output of the watchdog device, the other output is connected to the output of the JK flip-flop, and the output is connected to the CP terminal of the counter. The JK trigger will receive the disable / enable watchdog OC instruction and output it to the OR gate.

4. The processor hardware monitoring circuit based on watchdog devices and logic devices as described in claim 1, characterized in that: There are four monostable circuits: monostable circuit 1, monostable circuit 2, monostable circuit 3, and monostable circuit 4. The decoder has four output terminals: Y1, Y2, Y3, and Y4. The input terminal of the monostable circuit 1 is connected to the Y1 terminal of the decoder, and the output terminal is connected to the processor to send an interrupt signal to the processor; The Y2, Y3, and Y4 terminals of the decoder are connected to the output terminals of monostable circuit 2, monostable circuit 3, and monostable circuit 4, respectively.

5. The processor hardware monitoring circuit based on a watchdog device and logic devices as described in claim 4, characterized in that: in, The AND gate also has two inputs that receive the power-on reset signal and the instruction reset signal, respectively.

6. A processor hardware monitoring method based on watchdog devices and logic devices, characterized in that: Includes the following steps: Step S1: Enable the watchdog device and reset the watchdog counter to zero upon power-up; Step S2: Determine whether the watchdog device receives the processor's feed signal within the rated time; If a feeding signal is received, the watchdog device waits for the next feeding signal; if no feeding signal is received, the watchdog device sends a bite signal. Step S3: After receiving the dog-biting signal, the counter starts counting and sends the count value to the decoder; Step S4: The decoder sends the corresponding operation signal according to the received value; When the count value is 1, an interrupt signal is sent to the processor; When the count reaches the set maximum value, a reset signal is sent to the processor, and the backup power supply is turned on. If the count value is any other value, a reset signal is sent to the processor.

7. The processor hardware monitoring method based on watchdog devices and logic devices as described in claim 6, characterized in that: The maximum count is 4; When the count value is 2, a reset signal is sent to the processor; When the count value is 3, a reset signal is sent to the processor; When the count value is 4, a reset signal is sent to the processor; and the backup power supply is turned on.

8. The processor hardware monitoring method based on watchdog devices and logic devices as described in claim 6, characterized in that: in, In step S2, the watchdog enable signal is received, and the bite signal is also issued.

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