A communication method capable of automatic networking

Abstract

The application relates to the technical field of communication networks, and discloses a communication method capable of automatic networking, which is applied to a network containing a host and cascaded slaves, the slaves are provided with controlled switch modules, and the communication method comprises the following steps: the host reads a historical topology snapshot matrix, and only the first slave is initially turned on; the host broadcasts a networking request signal, the turned-on slave delays and returns a response frame based on a hardware unique identifier; the host allocates a logical communication address according to a comparison result of the identifier and the matrix, and sends an authorization instruction to close the controlled switch module of the corresponding slave to turn on the next-level slave; the host and the slave monitor the network execution to perform abnormal diagnosis, and when a fault is detected, corresponding step addressing or physical disconnection operation of the controlled switch module is performed; when a convergence condition is met, the networking is ended, and the host updates the latest topology mapping relationship to the matrix. The application avoids concurrent conflicts based on a snapshot matrix and a backoff mechanism, and realizes automatic isolation of short-circuit faults by using voltage monitoring and physical disconnection.

Description

Technical Field

[0001] This invention relates to the field of communication network technology, specifically to a communication method capable of automatically forming a network. Background Technology

[0002] In applications such as battery management systems and industrial control, a bus-type communication network consisting of a master and multiple slave devices is typically used. To achieve automatic allocation of logical communication addresses for each slave node, existing technologies generally employ a hardware cascaded topology. This involves inserting a controlled switch into each slave device, enabling communication and wake-up power to be switched on sequentially according to the physical connection order. The master then uses this to assign addresses to each newly connected node in turn.

[0003] However, existing cascaded communication networking mechanisms have several limitations in practical applications. During system initialization or abnormal reset, multiple nodes on the bus may be powered on simultaneously. Due to the lack of an underlying anti-collision mechanism, concurrent responses from multiple nodes can directly lead to bus signal overlap and data conflicts, which not only reduces the efficiency of address allocation but may also cause address errors.

[0004] Meanwhile, this step-by-step networking process is highly dependent on the reliability of the internal hardware switches of the slave devices. When the controlled switch of a slave device in the link experiences physical contact sticking due to prolonged operation, the host, after connecting the upstream node, may unexpectedly wake up the faulty node as well. At this point, the host cannot effectively distinguish whether this is a regular bus conflict or a low-level hardware failure, and the regular single-step handshake procedure will not be able to continue, causing all remaining nodes after that node to be unable to connect to the network.

[0005] Furthermore, existing networks lack protective isolation strategies for localized physical lines. If a short circuit to ground or leakage fault exists in a non-conductive downstream communication harness, once the upstream slave device closes the controlled switch according to the host's command, the short circuit point will instantly lower the power supply voltage of the entire backbone network. This will not only cause a complete power outage of the communication backbone but also cause all previously normal nodes in the system to go offline, allowing a localized line fault to spread into a system-wide communication failure. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a communication method that can automatically form a network, solving the problems of bus conflicts easily generated when multiple nodes respond concurrently in existing cascaded communication networks, and the lack of isolation mechanisms that lead to overall communication interruption when underlying physical short circuits or node hardware failures occur.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a communication method capable of automatic networking, applied to a network comprising a master unit and cascaded slave units, wherein the slave units are equipped with a controlled switch module, comprising the following steps: S1, the host reads the historical topology snapshot matrix. Initially, only the first slave is turned on, and the controlled switch modules of the other slaves are turned off. S2, the host broadcasts a network request signal, and the connected slave device backs off after a delay based on the hardware unique identifier and returns a response frame containing the hardware unique identifier; S3, the host assigns a logical communication address based on the comparison result between the hardware unique identifier and the historical topology snapshot matrix, and sends an authorization command to make the corresponding slave close the controlled switch module to turn on the lower-level slave; S4, the master and slave synchronous monitoring network is used to perform anomaly diagnosis, and when a fault is detected, the corresponding step addressing or physical disconnection operation of the controlled switch module is performed accordingly; S5, when the convergence condition is met, the network formation ends and the host updates the latest topology mapping relationship to the historical topology snapshot matrix.

[0008] Through the above steps, this invention relies on controlled switch modules to maintain the physical blockage of communication links in the initial stage of network setup, achieving step-by-step network topology connectivity. The host uses a historical topology snapshot matrix as a diagnostic benchmark, combined with the unique hardware identifiers of each slave device, to perform addressing comparisons and establish a correspondence between physical spatial locations and logical communication addresses. During step-by-step addressing, the host and slave devices use current electrical parameters and historical topology data to perform state synchronization determination. By directly skipping steps to address faulty controlled switch modules, or by actively disconnecting the drive circuit to isolate downstream nodes with short-circuit faults, the communication system achieves automatic recovery and isolation of underlying hardware faults.

[0009] Preferably, in step S2, the activated slave device delays back off based on a hardware unique identifier and returns a response frame containing the hardware unique identifier, specifically including: After receiving the network request signal, the activated slave device performs a hash modulo operation on its own hardware unique identifier based on a non-zero determination base to generate the target backoff time; After the start timer reaches the target backoff time, the activated slave device continuously samples the differential voltage of the bus multiple times to perform carrier sensing; If the bus level is determined to be in an idle state, the active slave device sends a response frame to the master. This process uses the factory-defined hardware unique identifier as the calculation parameter, allocates non-overlapping backoff time slots on the time axis to multiple slave devices, and combines multiple voltage sampling and determination logic to avoid bus signal conflicts caused by concurrent node responses.

[0010] Preferably, in step S3, the host allocates a logical communication address based on the comparison result between the hardware unique identifier and the historical topology snapshot matrix, specifically including:

[0011] If the extracted hardware unique identifier exists in the historical topology snapshot matrix, the host binds the hardware unique identifier to the original logical communication address in the historical topology snapshot matrix and releases the pre-allocated address resources.

[0012] If the extracted hardware unique identifier does not exist in the historical topology snapshot matrix, the host allocates an idle logical communication address for the hardware unique identifier.

[0013] Preferably, in step S3, sending an authorization command to cause the corresponding slave device to close the controlled switch module to turn on the downstream slave device specifically includes: The host sends a unicast command carrying the unique identifier of the target hardware to the bus as an authorization command; The corresponding slave device parses the unicast instruction. When the target hardware unique identifier is consistent with the slave device's own hardware unique identifier, and the slave device detects that the real-time sampled power supply voltage is greater than the set minimum action threshold, it outputs a control level to drive its own controlled switch module to close.

[0014] Preferably, in step S4, the host monitors the network and performs jump addressing accordingly when a fault is detected, specifically including: Within the host's listening window, if the host receives multiple different hardware unique identifiers consecutively, the host extracts the hardware unique identifiers to construct a sequence and compares the sequence with the historical topology snapshot matrix. If the comparison results show that the sequence belongs to an adjacent physical cascade sequence number in the historical topology snapshot matrix, the host determines that the controlled switch module at the corresponding physical location has stuck or broken down. The host suspends the normal networking process and sequentially unicasts the corresponding logical communication address and authorization command to all hardware unique identifiers in the sequence to bypass the failed controlled switch module.

[0015] This step utilizes the historical physical cascading sequence recorded in the matrix to distinguish fault conditions such as contact sintering and physical short circuits in the controlled switch module from bus conflicts, and ensures the normal access of subsequent nodes through continuous unicast at the protocol level.

[0016] Preferably, in step S4, the slave device monitors the network and, upon detecting a fault, performs a physical disconnection operation on the controlled switch module accordingly, specifically including: After the slave device performs the operation of driving the controlled switch module to close, it starts a local timer and monitors the real-time level status of the bus. If the real-time bus level is lower than the set fault voltage threshold during the operation of the local timer, or if a valid communication frame is not parsed after the local timer overflows, the slave device determines that there is a short circuit or leakage fault in the downstream communication link. The slave device actively cancels the control level to disconnect the corresponding controlled switch module, and listens for the local bus voltage to rise after cancellation.

[0017] Preferably, after the slave device actively cancels the control level to disconnect the corresponding controlled switch module, and listens to whether the local bus voltage recovers after the cancellation, the method further includes: If the local bus voltage rises back to a safe range, the slave device sends a fault diagnosis message to the master device. After receiving the message, the master device blocks the topology path after the corresponding slave device in the historical topology snapshot matrix. If the local bus voltage does not rise back to a safe range, the slave device enters isolation mode and stops sending communication. After the heartbeat timeout, the master device actively blocks the fault path containing the area where the slave device is located.

[0018] By monitoring the voltage drop characteristics of the power supply at the moment the switch module is closed, the slave hardware execution layer actively disconnects the downstream power supply and communication circuits to prevent local short circuits from causing abnormal voltage drops in the entire network.

[0019] Preferably, in step S5, satisfying the convergence condition means satisfying at least one of the following triggering conditions: The host did not receive any new response frames within a preset series of listening windows; The number of slave devices that have been successfully assigned logical communication addresses has reached the system's set capacity limit threshold.

[0020] Preferably, in step S5, the host updates the historical topology snapshot matrix with the latest topology mapping relationship, specifically including: The host collects the system power supply voltage in real time and extracts the integrity verification identifier of the data to be written. When the integrity check passes and the system power supply voltage is greater than or equal to the safe voltage threshold that allows erase and write operations, the host writes the mapping relationship containing the latest physical concatenation sequence number, hardware unique identifier, and logical communication address into the non-volatile memory, generating a data update that overwrites the historical topology snapshot matrix.

[0021] Preferably, when reading the historical topology snapshot matrix in step S1, a data validity verification step is also included: The host performs start flag matching and cyclic redundancy check on the read data segment; If all the data read is empty bytes or the data verification fails, the host determines that the storage medium data is damaged or the system is in the initial networking state, and clears the historical topology snapshot matrix cache, directly entering the initial addressing process of the slave without an assigned address.

[0022] This invention provides a communication method capable of automatically forming a network. It has the following beneficial effects: 1. This invention introduces a hash modulo delay backoff and carrier sense mechanism based on hardware unique identifiers to allocate different response time slots to slave devices in the on state. Combined with address matching using the host's historical topology snapshot matrix, this method reduces bus data conflicts caused by concurrent responses from multiple nodes during system power-on or reset, and shortens the logical address allocation time for network nodes. 2. This invention utilizes a historical topology snapshot matrix as a mapping reference between physical locations and logical addresses. When a host receives multiple unique hardware identifiers that conform to historical adjacent ordering within the same listening window, it can determine that the controlled switch module at the corresponding location has experienced a physical short-circuit fault. The host then performs step-by-step addressing through continuous unicasting, ensuring that the failure of a single node's switch hardware will not block the subsequent networking access process of normal nodes. 3. This invention adds voltage monitoring and pullback logic after the controlled switch module is closed at the slave end. When a short circuit or leakage fault in a local communication harness causes the voltage to drop below a set threshold, the slave will actively disconnect the corresponding controlled switch module. This mechanism prevents a local physical short circuit from causing an abnormal power drop in the entire trunk network, ensuring that the main communication network upstream of the fault point can continue to operate normally. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the method flow of the present invention; Figure 2 This is a schematic diagram illustrating the process of host system initialization and topology snapshot loading in this invention; Figure 3 This is a schematic diagram illustrating the process of the host broadcasting a network request and the slave responding to the network. Figure 4 This is a schematic diagram illustrating the process of host access authorization and slave cascading connection in this invention; Figure 5 This is a schematic diagram of the network state convergence and topology snapshot fixation process of the present invention; Figure 6 A comparison curve of convergence time for large-scale node networking provided in an embodiment of the present invention; Figure 7 A bar chart comparing fault isolation time under bus short-circuit conditions provided in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Please see the appendix Figure 1 , Figure 1 This is a flowchart illustrating an automatic networking communication method according to an embodiment of the present invention. The present invention provides an automatic networking communication method applied to a master-slave communication topology including a master and multiple slave devices, wherein the multiple slave devices are cascaded in a daisy-chain manner, and each slave device is configured with a controlled switch module for controlling the connectivity status of downstream physical links, including the following steps: Step S1: After the host is powered on, it reads the historical topology snapshot matrix in the non-volatile memory to complete system initialization. In the initial state, only the loop of the first slave device directly physically connected to the host is in the conducting state, while the controlled switch modules of the subsequent cascaded slave devices are all in the disconnected state, and the downstream communication link is physically blocked.

[0026] The host reads the historical topology snapshot matrix to obtain the mapping relationship between the physical concatenation sequence number, hardware unique identifier, and corresponding logical communication address of each slave device under the historical network conditions. When the system is first networked, the historical topology snapshot matrix is ​​empty.

[0027] In step S2, the host broadcasts a network request signal to the communication link. The network request signal carries the host identifier and the pre-assigned logical communication address.

[0028] After receiving a network request signal, a slave device that is in the ON state and has not been assigned a logical communication address uses its own hardware unique identifier to perform a hash modulo operation based on a non-zero determination base to generate a deterministic backoff time.

[0029] Subsequently, the slave device, which is in the ON state and has not been assigned a logical communication address, starts an internal timer and performs a carrier sense operation to detect the bus level status after the backoff time is reached.

[0030] If the bus is determined to be idle, the slave device will send a response frame containing its own unique hardware identifier to the master device to avoid interference of underlying signals when multiple nodes respond concurrently.

[0031] Step S3: The host receives the response frame and extracts the hardware unique identifier from the response frame. The extracted hardware unique identifier is compared with the historical topology snapshot matrix obtained in step S1 to complete the logical communication address allocation.

[0032] If the extracted hardware unique identifier exists in the historical topology snapshot matrix, the host will bind the extracted hardware unique identifier to the original logical communication address in the historical topology snapshot matrix, and actively release the logical communication address pre-allocated in step S2 for subsequent nodes to use.

[0033] If the extracted hardware unique identifier does not exist in the historical topology snapshot matrix, the host will assign the logical communication address pre-allocated in step S2 to the extracted hardware unique identifier.

[0034] After address allocation is completed, the host sends a unicast authorization token instruction containing the unique identifier of the target hardware to the bus.

[0035] The slave device parses the authorization token instruction. Only when the target hardware unique identifier in the authorization token instruction matches the slave device's own hardware unique identifier, the slave device's internal controller outputs a control level to drive the controlled switch module to close, enabling the next-level slave device to connect to the power supply or communication circuit.

[0036] The steps S2 to S3 above constitute a single node addressing loop. The host continuously repeats this loop to connect the downstream links step by step until the convergence condition of step S5 is met.

[0037] In step S4, the master and slave devices synchronously trigger the abnormal diagnosis logic during the execution of steps S2 and S3.

[0038] Within the listening window of the host waiting for a response frame, if the host receives multiple different hardware unique identifiers in succession, the host extracts the multiple different hardware unique identifiers to construct a hardware unique identifier sequence, and compares the hardware unique identifier sequence with the historical topology snapshot matrix.

[0039] If the comparison results show that the hardware unique identifier sequence belongs to an adjacent physical concatenation sequence number in the historical topology snapshot matrix, or if multiple out-of-order responses with valid checksums are received consecutively when the historical topology snapshot matrix is ​​empty, the host determines that the controlled switch module at the corresponding physical location has become stuck or broken down. Subsequently, the host initiates a pass-through addressing procedure, sequentially unicasting the corresponding logical communication address and authorization token instruction to all hardware unique identifiers in the hardware unique identifier sequence to bypass the failed controlled switch module and mark the fault status in memory.

[0040] On the slave side, after the slave performs the controlled switch module closing operation in step S3, it immediately starts the local pre-listening timer and monitors the bus level status.

[0041] If the bus level is lower than the set threshold during the operation of the local listen timer, or if the communication signal amplitude is attenuated due to severe leakage after the local listen timer overflows and no valid frame can be parsed, the slave device determines that there is a short circuit or leakage fault in the downstream communication link.

[0042] At this time, the slave device initiates the path retraction procedure, actively cancels the control level to disconnect the controlled switch module, and listens to whether the local bus voltage has returned to a safe range after cancellation.

[0043] If the bus voltage recovers, the slave device sends a fault diagnosis message to the master device. After receiving the fault diagnosis message, the master device blocks the corresponding topology path after the slave device in the historical topology snapshot matrix.

[0044] If the bus voltage does not recover, it indicates that the system trunk line has failed or the fault point is located at this level. The slave device will set itself to deep isolation mode and stop communication. Since the slave device has most likely lost its communication capability due to undervoltage at this time, the system will wait for the master side to trigger a timeout due to the lack of heartbeat response, and then passively determine the timeout on the master side and actively block the fault path.

[0045] Step S5: When the host does not receive any new response frames within a preset number of consecutive listening windows, or when the number of slave devices with assigned logical communication addresses reaches the system's set capacity limit, the host determines that the networking process has ended and issues a networking end command.

[0046] The host writes the mapping relationship of physical concatenation sequence number, hardware unique identifier and logical communication address constructed in real time in steps S3 and S4 into non-volatile memory to generate the latest historical topology snapshot matrix.

[0047] The historical topology snapshot matrix serves as a comparison benchmark for subsequent system restarts, equipment replacements, and anomaly diagnosis.

[0048] Please see the appendix Figure 2 , Figure 2 This is a schematic diagram illustrating the host system initialization and topology snapshot loading process according to an embodiment of the present invention. In this embodiment, after the host is powered on, system initialization is performed to establish the basic physical environment of the communication network and load historical network data. The initialization process specifically includes the following steps: S11, the host is powered on and establishes initial physical isolation. In a master-slave communication topology containing the host and multiple slave devices, the slave devices are cascaded in a daisy-chain manner. Each slave device is equipped with a controlled switch module. This controlled switch module is connected in series in the power supply circuit or communication signal line of the downstream communication link.

[0049] As a preferred approach, the specific circuit implementation of the controlled switch module includes controllable switching devices such as electromagnetic relays, solid-state relays, or field-effect transistors.

[0050] In the initial power-on state, except for the first slave device directly physically connected to the host and connected to the communication link, the controlled switch modules of all cascaded slave devices in the system are in the off state by default. At this time, the communication links of the second slave device and all subsequent slave devices are physically blocked, forming an initial physical topology with single-node access. This physical blocking state constitutes the underlying hardware foundation for the physical sequence spatial awareness of this invention, ensuring that subsequent networking commands can only be received by the single slave device currently at the end of the electrical connection.

[0051] S12, the host reads the non-volatile memory to obtain the historical topology snapshot matrix. The host's internal control chip accesses the non-volatile memory via an internal bus or an external communication interface. As a preferred method, the specific type of non-volatile memory includes electrically erasable programmable read-only memory or serial flash memory.

[0052] For the specific hardware circuit connections and underlying communication timing of a microcontroller reading data from non-volatile memory via an integrated circuit bus or serial peripheral interface, those skilled in the art can consult the technical manuals of commonly used microcontrollers for routine configuration. The data reading and driving process is a well-known technology in this field and will not be described in detail here.

[0053] S13, the host parses the data structure of the historical topology snapshot matrix. Based on the underlying binary data extracted in the above read operation, the host needs to reconstruct the mapping relationship between physical space and logical address in random access memory. The historical topology snapshot matrix extracted by the host from non-volatile memory contains the mapping relationship between the physical concatenation sequence number, hardware unique identifier, and corresponding logical communication address of each slave device in the historical networking state.

[0054] The hardware unique identifier is a globally unique serial number permanently embedded in the microcontroller's internal registers at the factory. The logical communication address is an independent addressing number assigned by the host to the slave device in the communication protocol stack. To achieve accurate alignment and tracking of the states of multiple source nodes in the communication link, the data structure of this historical topology snapshot matrix is ​​represented as a two-dimensional array, and its mathematical expression model is as follows: ; In the formula, This is a matrix containing node state information. …, They are respectively the 1st to the 1st Working status parameters of each node; …, They are respectively the 1st to the 1st A unique identifier for each node; …, They are respectively the 1st to the 1st The logical address assigned to each node; This represents the total number of nodes recorded in the network, and its value is an integer less than or equal to 255.

[0055] To address potential matrix data out-of-bounds issues, the host synchronously checks whether the index letter 'n' exceeds the system's preset maximum capacity threshold when parsing data. If it does, truncation is performed and an overflow exception interrupt is triggered.

[0056] To ensure the logical integrity of matrix reading, if the length of data read from non-volatile memory is zero or the total number of cascaded slaves parsed is zero, the host determines that the historical topology snapshot matrix is ​​an empty set and directly jumps to the initial network initialization logic to avoid the index pointing to an unknown memory area. Through this matrix model, the host reconstructs the correspondence between historical physical topology and logical addressing in random access memory, thereby providing a spatial dimension benchmark for subsequently determining whether the controlled switch modules have physically stuck together.

[0057] S14, the host performs the initial network status determination. After reading the data from the specified address segment of the non-volatile memory, the host uses multi-dimensional logic to verify the validity of the data to avoid biased judgments caused by a single data condition. Specifically, the host synchronously checks whether the start flag of the data segment is a preset activation flag, whether the total data length matches the preset node block length, and performs cyclic redundancy check based on the entire data segment.

[0058] If all the read data is in the preset empty byte state or any of the above verifications fails, the host determines that the current system is in the initial networking state or the storage medium data has been damaged. At this time, the host clears the cache of the historical topology snapshot matrix in the random access memory, and the system enters the subsequent process of broadcasting networking requests and allocating logical communication addresses under the condition that the historical topology snapshot matrix is ​​empty.

[0059] If the multi-dimensional data verification passes, the host retains the historical topology snapshot matrix and uses it as a data benchmark for subsequent device replacement diagnosis and abnormal status comparison.

[0060] Please see the appendix Figure 3 , Figure 3 This is a schematic diagram illustrating the process of a host broadcasting a network request and a slave responding to a backoff request according to an embodiment of the present invention. In this embodiment, to address the problem of interference in the underlying communication bus signals caused by concurrent power-on of multiple nodes under specific abnormal operating conditions, the system constructs an anti-collision response mechanism based on deterministic time slot backoff and carrier sense. This anti-collision response mechanism specifically includes the following steps:

[0061] S21, the host broadcasts a network request signal to the communication link and opens a listening window. Based on the physical link established during system initialization, the host's internal communication protocol stack constructs a data frame for the network request signal. The network request signal carries a start preamble, host identifier, pre-assigned logical communication address, and data checksum.

[0062] The pre-allocated logical communication addresses are free numbers generated sequentially by the host according to its internal address pool allocation algorithm. As a preferred approach, the host, while sending the network request signal to the bus, simultaneously starts a fixed-duration listener window timer to asynchronously capture response data returned by downstream slave devices within a specified time span. The duration threshold of this listener window timer is not arbitrarily set, but is strictly determined based on the product of the maximum allowed number of cascaded nodes in the network and the complete handshake cycle of a single communication, ensuring coverage of the total global node backoff delay under worst-case conditions.

[0063] For the initialization configuration of the asynchronous transceiver and the bit-stuffing transmission logic of the underlying serial data in the master-slave communication architecture, those skilled in the art can refer to the technical specifications of the general serial bus controller for conventional programming, which will not be elaborated here.

[0064] S22, the slave device receives the network request signal and calculates the backoff time based on hardware mapping. The slave device, which is in the ON state and has not yet been assigned a logical communication address, receives the network request signal through the bus transceiver and performs multi-dimensional data integrity verification by combining the data checksum and frame header and footer features.

[0065] After extracting a valid network request command, the system introduces a hardware mapping principle based on discrete uniform distribution to avoid abrupt mathematical calculations. Specifically, the reason for choosing a hardware unique identifier as the input parameter is that it has factory-fixed global uniqueness and physical immutability, and can serve as a reliable physical source of deterministic random seeds, thereby eliminating the hash collision risk that may be caused by soft addressing.

[0066] To achieve reference alignment of multi-source data on the timeline, the slave device synchronously triggers a global reset and enable operation of the hardware timer from the moment it parses the checksum flag or enters the idle state after parsing the complete frame end of the network request signal. The mathematical expression model for calculating the backoff time is as follows: ; In the formula, Delay the backoff time for the node; A unique identifier for the node participating in the computation; This is the modulo operator; The set backoff window modulus coefficient; The unit base time slot length; This is the base delay time specified by the system. This formula utilizes the inherent discreteness of physical hardware factors to map the response actions of multiple slave devices to non-overlapping time slices, achieving static decoupling of concurrent signals in the time domain.

[0067] S23, the slave device starts its internal timer to perform a delay and then performs a carrier sense operation. The slave device writes the calculated backoff time into the overload register of the internal hardware timer and starts the countdown. When the timer overflow interrupt is triggered, the slave device does not immediately drive the transmit pin, but instead further performs a carrier sense operation in conjunction with the real-time electrical conditions of the physical link to detect the bus level status.

[0068] To avoid decision failure caused by a single extreme value due to instantaneous electromagnetic pulse interference, the system abandons the single voltage comparison mechanism and instead adopts a filtering decision logic based on continuous multi-point sampling and weighted averaging. The decision logic model for carrier sensing is as follows: ; In the formula, The logic level at the target time determines the state; (As the return value of the segmentation function) is determined to be either a logic high level or a valid state; (As the return value of the segmentation function) is determined to be either a logic low level or an invalid state; This is a sequence index for the working mode and sampling time; For the first Enable detection flag for each working mode; (As a conditional comparison constant) Enables the detection flag to be on; For the first A specific sampling time variable; In order to be in Real-time values ​​of the bus differential voltage collected at all times; The set differential voltage comparison threshold; This is a logical AND operator. The carrier sense logic compensates for the fault tolerance blind spot of a single time slot algorithm under extremely low probability conditions by introducing smooth physical sampling in the voltage dimension, thus preventing local false triggering.

[0069] S24, the slave device sends a response frame to the master device based on the listening result. If the bus state is determined to be idle based on the above carrier sensing operation, the communication controller inside the slave device takes over the control of the communication bus and sends a response frame containing its own hardware unique identifier to the master device.

[0070] Based on the above operating conditions, if the bus is determined to be occupied, the slave device will enter a random backoff suspension state and continuously monitor the bus level. To prevent indefinite deadlock of the slave device caused by extreme bus congestion, the internal controller synchronously starts a retransmission counter when entering the suspension state. When the number of retransmissions accumulates to the preset maximum retransmission threshold, the communication controller is forcibly released and a local give-up flag is generated.

[0071] Based on the aforementioned multi-dimensional underlying collaborative verification, the host can completely and clearly extract the hardware sequence of all slave devices that are in a valid conducting state on the current bus within the preset listening window.

[0072] Please see the appendix Figure 4 , Figure 4 This is a schematic diagram illustrating the host admission authorization and slave cascading connection process according to an embodiment of the present invention. In this embodiment, to completely eliminate the address drift problem caused by node reset or bus interference in traditional cascading networks, the system strips the slave from its local physical connectivity decision-making power, and the host implements reverse hardwired control through global historical state matching. This admission authorization mechanism specifically includes the following steps: S31, the host receives the response frame and extracts the hardware unique identifier for comparison and retrieval. Within its listening window, the host captures the response frame sent by the slave device via the bus transceiver. Based on the aforementioned low-level data capture operation, the host's internal communication protocol stack performs redundancy checks on the response frame and removes invalid interference data.

[0073] After confirming the integrity of the response frame data, the host extracts the hardware unique identifier from the response frame data payload. To establish the historical mapping state of the current physical node, the host uses the extracted hardware unique identifier as an index key to traverse the historical topology snapshot matrix loaded in step S1.

[0074] The reason for choosing a hardware unique identifier as the retrieval key is that it possesses factory-fixed physical immutability, enabling it to serve as an absolute topology anchor point across power supply cycles and abnormal resets. For situations where the system is first networked or the historical topology snapshot matrix has been cleared, the host first verifies the total number of rows in the matrix before performing the retrieval. If the total number of rows is zero, it directly outputs a matching failure result and skips the traversal process.

[0075] For the data retrieval and comparison process, the host employs multi-dimensional feature matching logic, simultaneously verifying the length field and checksum field of the hardware unique identifier to prevent mismatches. The mathematical expression model for this retrieval and comparison is as follows: ; In the formula, The returned value is the index number of the node that was successfully matched. The output row index number when a match is successful (its value is equal to the row index number that satisfies the condition). ); The row index variable used for traversing the matrix; It is an existential quantifier; This is the starting lower boundary constant for row index traversal; The maximum number of rows recorded in the matrix; The first in the state information matrix The row's unique identifier records the value; The unique identifier for the received target node; A data verification function that calculates the unique identifier received; This is the constant value for comparison when the data verification function passes; This is the default return value when a match fails or validation fails. For the remaining cases that do not meet the specific matching conditions mentioned above.

[0076] This model introduces strict constraints to eliminate interference from similar items caused by bus errors during matrix traversal, ensuring the uniqueness and accuracy of node identification.

[0077] S32, the host performs logical communication address allocation based on the comparison and retrieval results. Based on the matching index results calculated above, the host executes a deterministic branch allocation strategy.

[0078] If the matching index result is a non-zero positive integer, it indicates that the current responding slave is a historical node with a known location in the original network. To avoid misallocation caused by crosstalk in a single communication, after determining that the matching index result is a non-zero positive integer, the host further verifies the online activity status and error counter of the historical node. If the slave is not in a suspended state locked by other abnormal routines, the host extracts the logical communication address corresponding to the index in the historical topology snapshot matrix and rebinds the logical communication address to the current slave, maintaining the original logical communication topology unchanged. At the same time, the pre-allocated free address in step S21 is released back into the address pool to prevent system address resource leakage. If the slave is in an abnormally locked state, the host refuses to allocate a logical communication address and issues a reset command to force the node to restart.

[0079] If the matching index result is zero, it indicates that the current responding slave is a newly connected network or a replaced unknown node. The host calls the internal address allocation manager to extract an unused logical communication address from the preset free address pool and allocate it to the slave (i.e., formally adopt the pre-allocated address carried in step S21).

[0080] To prevent system capacity overflow, the host synchronously checks whether the total number of currently allocated logical communication addresses exceeds the system's maximum node threshold before allocating a new address. If it does, a network saturation alarm is triggered, the allocation process is suspended, and the network saturation alarm is triggered. If there are no available addresses in the free address pool, the host rejects the allocation operation and sends a rejection handshake frame containing a saturation status indicator to the downstream bus.

[0081] S33, the host encapsulates and sends a unicast authorization token command to the communication link. After completing the logical communication address allocation, the host needs to grant the target slave device permission to start the downstream physical link. To prevent the control command from being mishandled by other listening nodes in the link, the host uses a secure encapsulation mechanism containing a strong constraint identifier to construct the unicast command.

[0082] The host's internal protocol packaging module concatenates a specific unlock control code, the target slave's unique hardware identifier, and a dynamic checksum to generate an authorization token command. To ensure strict alignment of multi-source node operating conditions, the host additionally appends a timestamp or synchronization sequence number to the authorization token command, forcing the slave to execute actions within a specified valid time window and preventing historical command replay attacks caused by network latency.

[0083] The authorization token instruction's specific data structure includes a frame header, an opcode field, a target identity field, a time series field, and a cyclic redundancy check field at the end. The host sends the authorization token instruction to the communication link via a bus transceiver in unicast format.

[0084] S34, the slave device parses the authorization token instruction and drives the controlled switch module to close. The slave device on the communication link listens to the bus data in real time and performs local unpacking and identity verification after receiving the authorization token instruction.

[0085] The system extracts the target hardware unique identifier from the authorization token instruction from the internal controller and compares it bit-by-bit with the hardware unique identifier stored in its own non-volatile memory. The execution logic model for the control-driven action is as follows: ; In the formula, A flag used to control the triggering of actions; The return value for determining whether a control action is allowed; The return value for determining whether to prevent the triggering of control actions; This is the unique identifier of the target node parsed from the instruction frame; This is a unique identifier inherent to the local node; This is the identity matching operator; The not equals operator; The bus power supply voltage currently being sampled in real time; The minimum operating voltage threshold that the system is allowed to perform control actions; For logical AND operator; For logical OR operator.

[0086] This logical model not only ensures accurate spatial positioning through absolute identification but also introduces underlying power supply status assessment logic. Only when the target identity of the command is completely consistent with the local identity, and the slave device's own power supply voltage is sufficient to support the switching action, will the slave device's internal controller output a control level to the external drive circuit. This control level, after amplification, drives the controlled switch module to close, connecting the next-level slave device to the loop.

[0087] The anomaly diagnosis and execution logic specifically includes the following steps: S41, the host extracts multi-source response features and constructs a sequence of unique hardware identifiers within the listening window. During network detection and controlled switch module operation phases, the host and slave synchronously trigger the background anomaly diagnosis logic. Within the preset listening window where the host awaits response frames, if the host continuously receives multiple response frames containing different unique hardware identifiers, it indicates an abnormal electrical condition of cascading conduction in the current physical link.

[0088] The host's internal communication protocol stack captures and extracts the aforementioned multiple distinct hardware unique identifiers. To ensure strict alignment of multi-source node data in terms of time and operating environment, the host captures the absolute timestamp of each response frame based on an underlying timer and forcibly removes drifting data packets whose timestamp intervals exceed the maximum allowable delay deviation for a single response. Subsequently, the host sorts the extracted valid hardware unique identifiers in ascending order based on the timestamps, constructing a sequence of hardware unique identifiers representing the actual connectivity state.

[0089] S42, the host performs historical topology mapping and diagnoses physical breakdown faults in the controlled switch modules. After obtaining the above sequence, the host performs a cross-domain comparison with the historical topology snapshot matrix cached in system memory. The historical topology snapshot matrix records the stable physical space ordering of the system under normal operating conditions.

[0090] The host invokes an internal decision algorithm to check whether the nodes in the hardware unique identifier sequence have continuous physical concatenation sequence numbers in the historical record. If the historical topology snapshot matrix is ​​empty, the host records the sequence length and marks the presence of a pre-conducting node, then proceeds to the regular address allocation process; if the historical record is valid, the mathematical expression model for determining the adjacency relationship of physical concatenation sequence numbers is as follows: ; In the formula, This is a flag used to determine the continuity of node addresses. The return value is determined by whether the addresses are consecutive or the physical locations are adjacent; The return value is for determining whether the address is discontinuous or has gaps; It is a universal quantifier; It is an existential quantifier; The sorting index number of the node sequence; This is the starting lower boundary constant for the node sequence index; The total length of the node sequence involved in the decision; This is the step decrement constant used to calculate the upper boundary of the sequence index; This is the step increment constant when calculating the index of the next adjacent node; For the first in the sequence A unique identifier for each node; For the first in the sequence A unique identifier for each node; For unique identifiers The corresponding logical address allocation value; For unique identifiers The corresponding logical address allocation value; The target constant is used to determine the difference between logical addresses that are consecutive. The not equals operator; For logical OR operator; This is an identifier indicating that the address of a node is in an unassigned, vacant state.

[0091] This judgment model utilizes multi-dimensional historical space constraints to accurately isolate specific hardware fault modes, such as contact sintering and sticking or solid-state breakdown, from the complex bus conflict manifestations. If the adjacent judgment flag outputs 1, the host determines that the controlled switch module at the corresponding physical location has experienced irreversible physical sticking.

[0092] S43, the host initiates the tunneling addressing procedure to cross the failed hardware layer. After confirming the physical connection, the host immediately suspends the normal single-step networking process and starts the tunneling addressing procedure. The host uses its internal address routing table to sequentially send the corresponding logical communication address and authorization token instructions to all hardware unique identifiers in the above sequence, without waiting for retransmission in the next network broadcast cycle.

[0093] As a preferred approach, the host synchronously inserts a special penetrating addressing flag into the protocol frame header to force the receiving node to skip the regular time slot backoff process and respond directly. This mechanism utilizes the physically shorted link channel and uses continuous unicast injection of data frames to directly connect subsequent cascaded nodes to the network, compensating for hardware failures at the physical execution layer.

[0094] S44, the slave device performs a weighted judgment of local pre-listening and short-circuit / leakage faults. In coordination with the master side, the slave side synchronously deploys a self-healing mechanism for downstream electrical conditions. At the instant the slave device parses the authorization token instruction and outputs a control level to drive the switch module to close, its microcontroller synchronously starts the local pre-listening timer and enables the analog-to-digital conversion peripheral to monitor the bus level status.

[0095] The logical model for fault trigger determination is as follows: ; In the formula, This is the system fault error flag. Error return values ​​used to determine if there is a system fault; The safe return value is used to determine if the system is operating normally; It is an existential quantifier; It is a universal quantifier; It is a time variable; The zero-time constant is the starting point of the time variable interval; This is the maximum value of the preset system monitoring time window; In order to be in Real-time bus voltage values ​​collected at all times; The fault voltage threshold for power failure or undervoltage as determined by the system; For logical OR operator; For logical AND operator; Set the system ready or reset complete flag; The comparison constant is used to determine whether the system is in a pre-ready state; The comparison constant is used to determine whether the system is in a ready state; The set timeout threshold.

[0096] The technical purpose of this logic model is to eliminate false triggering caused by a single electromagnetic disturbance by introducing a dual weighted judgment of signal loss caused by voltage drop recognition and timing timeout waiting, thus ensuring that the pathfinding mechanism has both sensitivity and high fault tolerance.

[0097] S45, the slave device executes the pathfinding and reversal procedure and the master device's path blocking mechanism. If the pathfinding fault trigger flag is output as 1, it indicates a potential problem in the downstream link. To protect the hardware, the slave device's internal controller immediately initiates the pathfinding and reversal procedure, actively cancels the output control level, and cuts off the power supply circuit to the drive coil to forcibly disconnect the downstream connection.

[0098] After the control level is canceled, the slave device synchronously listens to whether the local bus voltage rises back to a safe range within the set time window.

[0099] If the bus voltage successfully recovers, it indicates that the underlying physical isolation is complete. The slave's internal communication control module encapsulates a fault diagnosis message containing its own unique hardware identifier and the underlying electrical status word and uploads it to the host. After receiving the message, the host uses pointer indexes in the historical topology snapshot matrix to forcibly block all topology paths after the corresponding faulty node.

[0100] If the bus voltage does not recover, it indicates that the physical disconnection has failed or the short circuit has spread to the upstream trunk line. At this time, the slave device will set itself to deep isolation mode and stop all communication transmission. Due to the paralysis of the power supply environment at this level, the slave device has lost its active alarm capability, and the system will rely entirely on the continuous listening mechanism on the master side. When the master does not receive a response message from the slave device within the set heartbeat cycle and triggers a timeout judgment, the master will actively block the fault path and all its extended areas locally.

[0101] Please see the appendix Figure 5 , Figure 5This is a schematic diagram illustrating the network state convergence and topology snapshot fixation process according to an embodiment of the present invention. The network state convergence and topology snapshot fixation process specifically includes the following steps:

[0102] S51, the host performs multi-dimensional convergence determination of the network state. During network addressing, the system scheduler inside the host monitors the response status of communication links and the consumption of the memory address pool in real time. At the end of each preset listening window, the system scheduler synchronously latches the idle state and address count value, and uses the logical OR operation of Boolean algebra to construct the convergence threshold boundary. The mathematical expression model of network state convergence determination is as follows: ; In the formula, Assign convergence flag bits to the bus network address; Return a value indicating that the allocation is complete and the network has converged; Return value for determining non-convergence of the network incomplete allocation; This represents the continuous cycle count value when the bus is in an idle state; The threshold for the idle wait period when no new node is added to the bus; For logical OR operator; For logical AND operator; This is a statistical value representing the number of nodes that have been successfully assigned addresses. This is the threshold for the maximum number of nodes allowed to access the system's network protocol.

[0103] This logic module prevents the system from falling into a deadlock state of infinite waiting for a response by combining the dual determination of temporal silence characteristics and spatial capacity characteristics.

[0104] S52, the host sends a network termination command to the downstream communication link. Based on the convergence result of the above judgment model outputting 1, the host actively suspends the periodic listening window timer. The protocol packetization module inside the host constructs a network termination command carrying a specific opcode and sends it to the entire network in broadcast form through the bus transceiver.

[0105] After receiving and parsing the instruction, the slave device in the ON state synchronously shuts down the underlying time slot backoff logic and officially switches from the network configuration mode to the application data interaction mode.

[0106] S53, the host performs topology snapshots using non-volatile, persistent storage. To provide a reliable topology comparison benchmark during the next system power-on or abnormal reset cycle, the host needs to write the real-time constructed mapping relationship into non-volatile memory. To avoid data block corruption caused by writing operations at the critical moment of system power failure, the host introduces a dual security control mechanism for power supply conditions and memory data integrity. The logical model of the persistent write operation is as follows: ; In the formula, The target persistent data state for non-volatile memory; This represents the current state of the cached data awaiting writing in memory. To maintain the existing data in the memory in a hold state; This is a data integrity verification flag. This is the comparison constant used to determine whether the data has passed verification. This is the comparison constant used to determine data verification failure. For logical AND operator; For logical OR operator; Provide the current system with real-time power supply voltage; The minimum safe voltage threshold that allows memory erase and write operations to be performed.

[0107] This solidified model transforms the dynamically volatile networking results into static and persistent physical state constraints, and uses hardware-level voltage constraints to shield against the risk of power failure and tampering, thus completely closing the loop of the physical topology anti-drift and self-healing architecture constructed by this invention.

[0108] To further aid in understanding the technical solution of this invention, a specific application embodiment (in conjunction with an energy storage battery management system scenario) is provided below.

[0109] Specific application examples: Automatic networking based on large-scale battery management system (BMS) 1. Application scenario setting: The automatic networking communication method of this invention is applied to an energy storage battery management system comprising one master control module (BMU) and 50 slave control modules (CMUs). The 50 slaves are cascaded sequentially in a daisy-chain configuration. Each slave uses an optocoupler relay as a controlled switch module to control the wake-up power and communication bus of its downstream slaves. The system is set to operate at a normal bus voltage of 12V and a power-down fault threshold. =8V, minimum operating voltage =9V.

[0110] 2. Network topology and fault self-healing implementation process: State initialization (S1): After the host is powered on, it reads the external non-volatile memory and loads the "Historical Topology Snapshot Matrix" M from the previous cycle. In the initial state, only slave device 1 is powered on and connected.

[0111] Sudden fault injection: Suppose that there are two hardware vulnerabilities in the system at this time: The internal controlled switch of slave device No. 15 suffered physical contact sintering and adhesion due to long-term high current. The outer sheath of the physical wiring harness between slave devices No. 30 and No. 31 is damaged, resulting in a short circuit to ground.

[0112] Network topology and sticky penetration (S2-S4): The host assigns logical communication addresses level by level. When addressing slave 14 and closing its switch, slave 15 and slave 16 are simultaneously powered on because the switch of slave 15 is stuck.

[0113] After the host broadcasts the network request, slave devices 15 and 16 calculate the backoff time based on their respective UIDs. And return response frames sequentially in different time slots.

[0114] The host receives two UIDs within the same listening window, triggering anomaly diagnosis. The matrix is ​​extracted and substituted into the address continuity determination formula to calculate... (That is, the two are physically adjacent in the historical snapshot).

[0115] The host determines that switch 15 is broken down, immediately starts the tunneling addressing procedure, skips the normal waiting of switch 15, and directly sends logical address and authorization token instructions to switches 15 and 16 continuously via unicast, successfully crossing the failed hardware layer.

[0116] Short-circuit pathfinding retreat (S4): When the network deployment progresses to slave device 30, the master sends an authorization token to it. Slave device 30 closes the controlled switch, at which point a short circuit in the downstream harness causes the bus voltage to drop instantaneously to 5V.

[0117] The analog-to-digital converter inside slave device #30 detected... Substituting into the fault determination formula yields... .

[0118] Slave unit #30 immediately initiated a pathfinding retraction, actively disconnecting the controlled switch, and the bus voltage quickly recovered to 12V. Slave unit #30 then reported a short-circuit alarm frame to the master unit.

[0119] After receiving the alarm, the host blocks paths 31 to 50 in the matrix to prevent short circuits from paralyzing the communication of the entire energy storage battery cabinet.

[0120] Convergence and Consolidation (S5): The host listening cycle ends, and the calculation is completed. The network termination command is issued. The host then checks the current voltage. The new topology matrix, stripped of short-circuit nodes, is then fixed to Flash. The system, despite its defects (30 units available), was safely started and put into operation.

[0121] II. Experimental Verification and Effect Comparison: To verify the technological advancement of this invention, a hardware testing platform containing 100 nodes was built, and comparative tests were conducted with two existing conventional methods: Control group A (traditional random MAC access): adopts a CSMA / CD collision detection and retransmission mechanism similar to the standard CAN bus, without physical topology awareness.

[0122] Control group B (traditional daisy-chain cascading): adopts pure hardware cascading, without historical topology snapshots, and without voltage monitoring and leakage prevention mechanisms.

[0123] Experimental group (method of this invention): adopts backoff addressing, snapshot comparison and bidirectional pathfinding self-healing mechanism.

[0124] 1. Experimental Test Item 1: Large-scale node networking convergence time test. Under fault-free conditions, when the number of nodes increases from 10 to 100, the time it takes for the system to complete all address allocations and enter normal communication.

[0125] Experimental Results: In control group A, the convergence time deteriorated sharply after the number of nodes exceeded 60 due to the exponential increase in bus conflicts (approximately 3.5 seconds for 100 nodes). Control group B relied on conflict-free wake-up at each level, but each level required a full handshake, resulting in a linear and slow increase in time (approximately 2.8 seconds). The method of this invention, by introducing deterministic matching based on historical snapshots M, reduces the number of handshake interactions, achieving a convergence time of only 1.1 seconds for 100 nodes, thus improving network efficiency by approximately 60%.

[0126] 2. Experimental Test Item Two: System Survivability and Recovery Time under Catastrophic Bus Short Circuit Conditions. During the network operation (at the 50th node), a hard short circuit fault to ground on the bus is artificially injected using a relay.

[0127] Experimental results: Please refer to the appendix. Figure 6 and attached Figure 7 Control group A has no isolation capability; upon a short circuit, all 100 nodes instantly lose power and become paralyzed, resulting in a 0% survival rate and an infinitely long recovery time. Control group B, lacking a pre-listening mechanism, pulls the main line low upon closure, triggering a power outage at the host computer system level, requiring manual reset and taking >120 seconds. The method of this invention relies on… The pathfinding and withdrawal mechanism allows the slave device to actively withdraw control signals to isolate the fault within 2.5 milliseconds (ms) after a short circuit occurs. The first 50 nodes remain 100% alive and communication is uninterrupted, and the system achieves millisecond-level self-healing isolation.

[0128] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A communication method for automatic network formation, applied to a network including a master unit and cascaded slave units, wherein the slave units are equipped with a controlled switch module, characterized in that, include: S1, the host reads the historical topology snapshot matrix. Initially, only the first slave is turned on, and the controlled switch modules of the other slaves are turned off. S2, the host broadcasts a network request signal, and the connected slave device backs off after a delay based on the hardware unique identifier and returns a response frame containing the hardware unique identifier; S3, the host allocates a logical communication address based on the comparison result between the hardware unique identifier and the historical topology snapshot matrix, and sends an authorization command to cause the corresponding slave to close the controlled switch module to turn on the lower-level slave; S4, the master and slave synchronous monitoring network is used to perform anomaly diagnosis, and when a fault is detected, the corresponding step addressing or physical disconnection operation of the controlled switch module is performed accordingly; S5, when the convergence condition is met, the network formation ends, and the host updates the latest topology mapping relationship to the historical topology snapshot matrix.

2. The communication method for automatic network formation according to claim 1, characterized in that, In step S2, the activated slave device delays back off based on a hardware unique identifier and returns a response frame containing the hardware unique identifier, specifically including: After receiving the network request signal, the activated slave device performs a hash modulo operation on its own hardware unique identifier based on a non-zero determination base to generate the target backoff time; After the start timer reaches the target backoff time, the activated slave device continuously samples the bus differential voltage multiple times for carrier sensing. If the bus level is determined to be in an idle state, the activated slave device sends the response frame to the master device.

3. The communication method for automatic network formation according to claim 1, characterized in that, In step S3, the host allocates a logical communication address based on the comparison result between the hardware unique identifier and the historical topology snapshot matrix, specifically including: If the extracted hardware unique identifier exists in the historical topology snapshot matrix, the host binds the hardware unique identifier to the original logical communication address in the historical topology snapshot matrix and releases the pre-allocated address resources. If the extracted hardware unique identifier does not exist in the historical topology snapshot matrix, the host allocates an idle logical communication address for the hardware unique identifier.

4. The communication method for automatic network formation according to claim 1, characterized in that, In step S3, sending the authorization command to cause the corresponding slave device to close the controlled switch module to turn on the downstream slave device specifically includes: The host sends a unicast command carrying the unique identifier of the target hardware to the bus as the authorization command; The corresponding slave device parses the unicast instruction. When the target hardware unique identifier is consistent with the slave device's own hardware unique identifier, and the slave device detects that the real-time sampled power supply voltage is greater than the set minimum action threshold, it outputs a control level to drive its own controlled switch module to close.

5. The communication method for automatic network formation according to claim 1, characterized in that, In step S4, the host monitors the network and performs jump addressing accordingly when a fault is detected, specifically including: Within the host's listening window, if the host continuously receives multiple different hardware unique identifiers, the host extracts the hardware unique identifiers to construct a sequence and compares the sequence with the historical topology snapshot matrix; If the comparison result shows that the sequence belongs to an adjacent physical cascade sequence number in the historical topology snapshot matrix, the host determines that the controlled switch module at the corresponding physical location has stuck or broken down. The host suspends the normal networking process and sequentially unicasts the corresponding logical communication address and authorization command to all hardware unique identifiers in the sequence to bypass the failed controlled switch module.

6. The communication method for automatic network formation according to claim 1, characterized in that, In step S4, the slave device monitors the network and, upon detecting a fault, performs a physical disconnection operation on the controlled switch module accordingly, specifically including: After the slave device performs the operation of driving the controlled switch module to close, it starts a local timer and monitors the real-time level status of the bus. If the real-time bus level is lower than the set fault voltage threshold during the operation of the local timer, or if a valid communication frame is not parsed after the local timer overflows, the slave device determines that there is a short circuit or leakage fault in the downstream communication link. The slave device actively cancels the control level to disconnect the corresponding controlled switch module, and listens for the local bus voltage to rise after cancellation.

7. The communication method for automatic network formation according to claim 6, characterized in that, The process of the slave device actively canceling the control level to disconnect the corresponding controlled switch module, and after listening to whether the local bus voltage has rebounded after the cancellation, further includes: If the local bus voltage rises back to a safe range, the slave device sends a fault diagnosis message to the master device. After receiving the message, the master device blocks the topology path after the corresponding slave device in the historical topology snapshot matrix. If the local bus voltage does not rise back to a safe range, the slave device enters isolation mode and stops sending communication. After the heartbeat timeout, the master device actively blocks the fault path containing the area where the slave device is located.

8. The communication method for automatic network formation according to claim 1, characterized in that, In step S5, satisfying the convergence condition means satisfying at least one of the following triggering conditions: The host did not receive any new response frames within a preset series of listening windows; The number of slave devices that have been successfully assigned logical communication addresses has reached the system's set capacity limit threshold.

9. The communication method for automatic network formation according to claim 1, characterized in that, In step S5, the host updates the historical topology snapshot matrix with the latest topology mapping relationship, specifically including: The host collects the system power supply voltage in real time and extracts the integrity verification identifier of the data to be written. When the integrity check passes and the system power supply voltage is greater than or equal to the safe voltage threshold that allows erase and write operations, the host writes the mapping relationship containing the latest physical concatenation sequence number, hardware unique identifier and logical communication address into the non-volatile memory, generating a data update that covers the historical topology snapshot matrix.

10. A communication method capable of automatic network formation according to claim 1, characterized in that, When reading the historical topology snapshot matrix in step S1, a data validity verification step is also included: The host performs start flag matching and cyclic redundancy check on the read data segment; If all the data read is empty bytes or the data verification fails, the host determines that the storage medium data is damaged or the system is in the initial networking state, and clears the historical topology snapshot matrix cache, directly entering the initial addressing process of the slave without an assigned address.

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