Active flow control device and method
By introducing an active flow control device and adopting a device address mapping and weighted round-robin scheduling mechanism, the problems of flow control lag and head-blocking in the interconnection of multiple master devices and multiple slave devices are solved, thereby improving link utilization and data transmission stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
- Filing Date
- 2026-02-25
- Publication Date
- 2026-06-16
AI Technical Summary
In scenarios involving the interconnection of multiple master and slave devices, existing flow control methods suffer from lag and head-blocking, leading to low link transmission efficiency and stagnation, especially when dealing with complex path mapping relationships and resource consumption, making effective management difficult.
An active flow control device is introduced. Through the active flow control module and the system control module, a mechanism of slave device address mapping, command queue, time slot management and weighted round-robin scheduling is adopted to dynamically distribute and schedule write commands, avoid overall transmission stagnation caused by the blockage of a single slave device and suppress head-blocking phenomenon.
It improves link utilization under multi-path concurrent transmission conditions, enhances the stability and reliability of data transmission, reduces the risk of link downtime, and realizes ordered caching and scheduling of write commands.
Smart Images
Figure CN122226697A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an active flow control device and method. Background Technology
[0002] In applications involving the interconnection of multiple master and slave devices, complex path mapping relationships often exist between them. Data flows initiated by a master device need to pass through multiple intermediate routing nodes to reach the target slave device. In a multi-level routing link structure, when any routing node becomes congested due to limited processing capacity or resource consumption, this congestion can easily propagate along the data transmission path, affecting other nodes in the link. This leads to congestion propagation along the data transmission path, resulting in reduced overall routing link transmission efficiency or even link shutdown.
[0003] In existing technologies, congestion control for the aforementioned interconnect links typically employs two main technical solutions: One is a tiered backpressure scheme, where a handshake interface is set up at the slave device end. When a slave device is unable to continue receiving data at a given time, the ready signal is invalidated, applying backpressure control to the on-chip interconnect structure, thereby limiting the master device from sending data to that slave device. The other is a master-device proactive flow control scheme based on credit token management. This involves configuring preset credit values for different slave devices at the master device end. When the credit value corresponding to a slave device is exhausted, the master device suspends data transmission to that slave device, thus limiting the traffic to different target slave devices.
[0004] However, the aforementioned existing technologies still have certain shortcomings. The step-by-step backpressure scheme is a passive flow control method. Backpressure information needs to be fed back up the data transmission path step by step. The master device has a certain lag in sensing the congestion status of downstream slave devices or intermediate routing nodes. Usually, the suppression mechanism is only triggered after congestion has already formed, which can easily lead to further accumulation of data within the link. In extreme cases, it may even cause the link to stop.
[0005] Furthermore, although the master-side active flow control scheme based on credit value has relatively simple control logic, when the credit value corresponding to a slave device within the master device is exhausted, the master device's command transmission to that slave device will be blocked. Moreover, when multiple slave devices share command transmission resources, it can easily affect the command transmission to other slave devices, preventing them from being sent in a timely manner, thus causing the head-of-line blocking (HOL blocking) problem.
[0006] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0007] This invention provides an active flow control device for dynamically splitting, scheduling, and controlling the flow of active flow control requests according to different slave devices in scenarios involving interconnection of multiple master and slave devices. This improves link utilization under multi-path concurrent transmission conditions, suppresses head-blocking phenomena, and enhances the stability and reliability of on-chip system data transmission.
[0008] The active flow control device includes: an active flow control module and a system control module; the active flow control module includes: multiple slave device command queues; The system control module is used to generate a request signal based on the received write command and send the request signal to the active flow control module; The active flow control module is used to parse the request signal based on the configuration information to determine the target slave device identifier corresponding to the request signal; transmit the request identifier in the request signal to the slave device command queue corresponding to the target slave device identifier; when any slave device command queue reaches the preset storage capacity limit, query whether the currently parsed request signal corresponds to the slave device command queue; if so, send a flow switching signal to the system control module so that the system control module performs a flow switching operation.
[0009] In some embodiments, the system control module includes: a write address channel buffer and a write data channel buffer; The system control module is also used to receive data packets sent from the device, and parse the data packets into write commands and write data; transmit the write commands to the write address channel buffer, and transmit the write data to the write data channel buffer.
[0010] In some embodiments, the configuration information includes: a slave device address mapping relationship; the system control module includes: a control status register; the active flow control module further includes: a slave device address mapping module, used to perform address range matching on the request address in the request signal according to the slave device address mapping relationship in the control status register; if the request address matches the address range of any slave device, the target slave device identifier corresponding to the request address is obtained.
[0011] In some embodiments, when any slave device command queue reaches a preset storage capacity limit, the slave device address mapping module sends an invalidation request ready signal to the request interface of the active flow control module.
[0012] In some embodiments, the active flow control module further includes: a slave device flow monitoring module, which, when the slave device flow monitoring module detects that any target slave device command queue has reached a preset storage capacity limit, queries whether the request signal currently parsed by the slave device address mapping module corresponds to the target slave device command queue that has reached the storage capacity limit; if so, sends a flow cutting signal to the system control module. After receiving the flow switching signal, the system control module reselects a write command from the write address channel buffer, generates a request signal based on the write command, and transmits the request signal to the slave device address mapping module.
[0013] In some embodiments, the active flow control module further includes: a time slot management module and a response identifier queue; when the slave device command queue is not empty and the response identifier queue has not reached the preset storage capacity limit, the time slot management module obtains the corresponding request identifier in the slave device command queue based on the weighted round-robin scheduling request signal, and transmits the request identifier to the response identifier queue.
[0014] In some embodiments, the time slot management module includes: a weighted round-robin scheduler and multiple slave device status management modules; The slave device status management module is used to determine whether each slave device command queue participates in weighted round-robin scheduling based on preset flow control conditions, and to generate the weighted round-robin scheduling request signal; The weighted round-robin scheduler is used to poll the slave device command queues participating in the weighted round-robin scheduling based on the weighted round-robin scheduling request signal and the preset weight coefficient, determine the arbitrated slave device command queue, obtain the request identifier in the arbitrated slave device command queue through the corresponding slave device status management module, and transmit the request identifier to the response identifier queue.
[0015] In some embodiments, when the response identifier queue reaches a preset storage capacity limit, a first backpressure signal is sent to the weighted round-robin scheduler.
[0016] In some embodiments, when the response ready signal is valid, the response identifier queue outputs a request identifier that allows sending and a response valid signal to the master device system control module; After receiving the request identifier and the response valid signal, the system control module retrieves the corresponding write command from the write address channel buffer based on the request identifier and sends the write command to the corresponding slave device.
[0017] In some embodiments, the system control module further includes: a synchronization trigger module, configured to receive a second reverse voltage signal from each slave device; The synchronous trigger module is used to generate a third reverse pressure signal based on the second reverse pressure signal and send it to the active flow control module; Based on the third back pressure signal, the active flow control module pauses the acquisition of the request identifier in the corresponding slave device command queue during the polling scheduling process.
[0018] This invention also provides an active flow control method that, in scenarios involving interconnection of multiple master and slave devices, dynamically distributes, schedules, and controls the flow of active flow control requests according to different slave devices. This improves link utilization under multi-path concurrent transmission conditions, suppresses head-blocking phenomena, and enhances the stability and reliability of on-chip system data transmission.
[0019] This proactive flow control method includes: The system control module generates a request signal based on the received write command and sends the request signal to the active flow control module; The active flow control module parses the request signal based on the configuration information to determine the target slave device identifier corresponding to the request signal; transmits the request identifier in the request signal to the slave device command queue corresponding to the target slave device identifier; when any slave device command queue reaches the preset storage capacity limit, it queries whether the currently parsed request signal corresponds to the slave device command queue; if so, it sends a flow-cutting signal to the system control module so that the system control module performs a flow-cutting operation.
[0020] This invention also provides a chip that includes the above-described active flow control device.
[0021] This invention also provides a board card, including the chip described above.
[0022] This invention also provides an electronic device, including the aforementioned circuit board.
[0023] The active flow control device and method provided in this invention introduce a request parsing and diversion control mechanism based on write command identifiers between the master device system control module and the active flow control module. This allows write commands to be orderly cached and scheduled according to the target slave device before entering the on-chip interconnect network (Interconnect), thereby avoiding congestion spread caused by indiscriminate entry of write commands into downstream links. When any slave device command queue reaches its capacity limit, the active flow control module can identify the correspondence between the current write command and the corresponding slave device command queue during the request parsing phase and trigger flow switching control. The system control module then switches to other write commands to continue transmission, effectively preventing the overall transmission stagnation on the master device side due to the blockage of a single slave device and significantly suppressing the head-blocking phenomenon. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the active flow control device in an embodiment of the present invention; Figure 2 This is a schematic diagram of the active flow control module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the timing control of the device flow monitoring module in an embodiment of the present invention. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.
[0026] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.
[0027] To address the challenges of complex data transmission paths, numerous routing nodes, and susceptibility to congestion and head-blocking in multi-master and multi-slave interconnection architectures, this application proposes an active flow control device. Without relying on tiered backpressure mechanisms or static credit control mechanisms, it achieves active scheduling and control of data flows from different slave devices. This active flow control device establishes a slave device address mapping module, multiple slave device command queues, a time slot management module, and an active flow control response identifier queue within the active flow control module. It then performs flow distribution and caching of write command identifiers corresponding to write commands and implements dynamic scheduling based on time slot control and a weighted round-robin scheduling mechanism.
[0028] When the command queue of a slave device reaches its capacity limit, or when a back pressure signal from a downstream link is detected, the active flow control device can trigger a flow switching control mechanism. This avoids the problem that write commands from other slave devices cannot be sent in time due to the blockage of a single slave device, thereby effectively suppressing head-blocking phenomenon, improving link utilization efficiency and scheduling flexibility in the process of concurrent transmission of multi-channel data, and reducing the risk of link stalling.
[0029] This invention provides an active flow control device, such as... Figure 1 As shown, the active flow control device includes an active flow control module (AFC) and a master system control module (mst_sys_ctrl). The active flow control module includes multiple slave command FIFOs (slv... _cmd_fifo).
[0030] The main device system control module is used to generate an active flow control request signal based on the received write command, and send the active flow control request signal to the active flow control module.
[0031] The active flow control module parses the active flow control request signal based on configuration information to determine the target slave device identifier corresponding to the active flow control request signal. It then transmits the active flow control request identifier from the active flow control request signal to the slave device command queue corresponding to the target slave device identifier. When any slave device command queue reaches its preset storage capacity limit, it checks whether the currently parsed active flow control request signal corresponds to that slave device command queue. If so, it sends a flow-switching signal to the master device system control module, causing the master device system control module to perform a flow-switching operation.
[0032] According to the above embodiments, by introducing a request parsing and diversion control mechanism based on write command identifiers between the master device system control module and the active flow control module, write commands can be orderly cached and scheduled according to the target slave device before entering the on-chip interconnect network (Interconnect), thereby avoiding congestion spread caused by indiscriminate entry of write commands into downstream links. When any slave device command queue reaches its capacity limit, the active flow control module can identify the correspondence between the current write command and the corresponding slave device command queue during the request parsing phase and trigger flow switching control, allowing the system control module to switch to other write commands to continue transmission. This effectively avoids the overall transmission stagnation on the master device side due to the blockage of a single slave device, significantly suppressing the occurrence of head-blocking phenomenon.
[0033] In this embodiment of the invention, the bus signals are typically divided into an address bus and a data bus in the bus protocol. Taking the AXI (Advanced eXtensible Interface) protocol as an example, the Write Address Channel (AW) and Read Address Channel (AR) are the address bus, and the Write Data Channel (W) and Read Data Channel (R) are the data bus. The technical solution of this invention is mainly applied to the write address channel on the master device side, used for flow control and scheduling of write command transmissions.
[0034] like Figure 1 As shown, the following embodiments illustrate the specific application of the technical solution of the present invention on the main device.
[0035] In some embodiments, the master device system control module includes: a write address channel buffer (aw_chl_buf) and a write data channel buffer (w_chl_buf).
[0036] The master device system control module is also used to receive data packets sent by the slave device and parse the data packets into write commands and write data. The write commands are transmitted to the write address channel buffer, and the write data is transmitted to the write data channel buffer.
[0037] In this embodiment of the invention, the master device receives the data packet corresponding to the write transaction through the AXI Slave Interface, and parses the data packet to obtain the write command and write data. The write command includes, but is not limited to, fields such as write command ID, write address, and write burst length.
[0038] A corresponding Active Flow Control Request ID (afc_req_id) is generated based on the write command identifier in the write command. A corresponding Active Flow Control Request Address (afc_req_addr) is generated based on the write address in the write command. A corresponding Active Flow Control Request Length (afc_req_len) is generated based on the write burst length in the write command.
[0039] The write command is stored in the write address channel buffer, and the write data is stored in the write data channel buffer. The master device system control module sends an active flow control request signal containing the active flow control request identifier, active flow control request address, and active flow control request length to the active flow control module through the Active Flow Control Request Interface (AFC Request Interface).
[0040] According to the above embodiments, by parsing the write transaction and extracting key information such as the write command identifier, write address and write burst length at the master device end, a corresponding active flow control request signal is constructed, so that the write command can participate in flow control and scheduling decisions before entering the on-chip interconnect. This achieves decoupling caching and fine-grained management of write commands and write data, and improves the controllability of the data transmission process and the stability of system operation.
[0041] In some embodiments, the master device system control module further includes a control and status register (CSR).
[0042] like Figure 2 As shown, the active flow control module also includes a slave address mapping module (slv_map), which is used to match the active flow control request address in the active flow control request signal with the address range according to the slave address mapping relationship in the control status register. If the active flow control request address matches the address range of any slave device, the target slave device identifier corresponding to the active flow control request address is obtained.
[0043] In this embodiment of the invention, the control status register is a register list used to store the configuration information required by the active flow control module. This configuration information is written to the control status register via the Advanced Peripheral Bus (APB). The slave device address mapping module reads the configuration information from the control status register through the Control Status Register Configuration Interface (CSR_cfg_if).
[0044] The configuration information includes, but is not limited to, slave device address mapping relationships. Slave device address mapping relationships are used to describe the address range corresponding to each slave device, for example... Figure 2 The address ranges shown as slv1 to slv6 each include at least a start address and an end address, and may also include a System Address Map (SAM) table for the System on-Chip (NoC) to represent the address mapping relationship under different networking modes or chip packaging modes.
[0045] For example, the slave device address mapping module matches the active flow control request address in the active flow control request signal with the address range corresponding to each slave device in the slave device address mapping relationship. When the active flow control request address matches the address range of any slave device, the target slave device identifier corresponding to the active flow control request address is determined.
[0046] According to the above embodiments, by setting a configurable control status register to centrally store slave device address mapping relationships, the active flow control module can obtain address mapping information during operation and determine the target slave device corresponding to the active flow control request accordingly. This realizes the parameterized configuration of the request parsing and flow control decision process, improving the accuracy of address parsing and the flexibility of the flow control mechanism.
[0047] In some embodiments, after the slave device address mapping module determines the corresponding target slave device identifier based on the active flow control request address in the active flow control request signal, it writes the active flow control request identifier in the active flow control request signal to the slave device command queue corresponding to the target slave device identifier, so as to store the active flow control request identifiers corresponding to different slave devices in different slave device command queues. The storage entity of the slave device command queue can be a random access memory composed of registers (Reg) or a static random access memory (SRAM), and this invention is not limited thereto.
[0048] For example, the active flow control request identifier of the target device identified as slv0 is written to slv0_cmd_fifo, the active flow control request identifier of the target device identified as slv1 is written to slv1_cmd_fifo, ..., the active flow control request identifier of the target device identified as slv6 is written to slv6_cmd_fifo.
[0049] In some embodiments, when any slave device command queue reaches a preset storage capacity limit, the slave device address mapping module sends an invalid Active Flow Control Request Ready Signal (afc_req_rdy) to the Active Flow Control Request Interface of the Active Flow Control Module.
[0050] In this embodiment of the invention, when any slave device command queue is in a full state, the slave device address mapping module sets the active flow control request ready signal to invalid (i.e., afc_req_rdy=0) through the active flow control request interface to perform a backpressure operation on the active flow control request signal receiving process of the active flow control request interface, thereby suppressing the master device system control module from continuing to send active flow control request signals to the active flow control request interface.
[0051] In some embodiments, the active flow control module further includes a slave flow monitoring module (Slave FlowMonitor, abbreviated as sf_monitor).
[0052] When the device flow monitoring module detects that any slave device command queue has reached the preset storage capacity limit, it queries whether the active flow control request signal currently parsed by the slave device address mapping module corresponds to the target slave device command queue that has reached the storage capacity limit. If so, it sends a flow-cutting signal to the master device system control module.
[0053] After receiving the flow switching signal, the master device system control module reselects a write command from the write address channel buffer, generates an active flow control request signal based on the reselected write command, and transmits the active flow control request signal to the slave device address mapping module.
[0054] In this embodiment of the invention, the device flow monitoring module monitors in real time the empty / full status of each slave device command queue and the parsing results of the active flow control request signal by the slave device address mapping module.
[0055] When the slave device traffic monitoring module detects that any slave device command queue is in a full state, the slave device traffic monitoring module queries whether the active flow control request signal currently being parsed by the slave device address mapping module corresponds to the target slave device command queue in a full state. If the active flow control request signal being parsed corresponds to the target slave device command queue in a full state, the slave device traffic monitoring module sends a flow-cutting signal to the master device system control module.
[0056] Upon receiving the flow-cutting signal, the master device system control module selects a new write command from the write address channel buffer. The target slave device identifier corresponding to the newly selected write command is different from the target slave device identifier in the full state. The master device system control module generates a new active flow control request signal based on the newly selected write command and transmits this active flow control request signal to the slave device address mapping module for parsing.
[0057] For example, when the device traffic monitoring module detects that slv0_cmd_fifo is in a full state, the device traffic monitoring module obtains the active flow control request signal currently parsed by the device address mapping module, and determines whether the target slave device identifier corresponding to the active flow control request signal is slv0.
[0058] When it is confirmed that the target slave device identifier corresponding to the currently parsed active flow control request signal is slv0, the slave device address mapping module sets the active flow control request ready signal to invalid through the active flow control request interface, even if afc_req_rdy is 0.
[0059] If at least one slave device command queue is not full, the slave device flow monitoring module sends a flow switching signal to the master device system control module.
[0060] Upon receiving the flow-cutting signal, the master device system control module reselects a write command from the write address channel buffer, for example, reselecting a write command targeting slave device identified as slv4. Based on the reselected write command, the master device system control module generates a new active flow control request signal and transmits this signal to the slave device address mapping module for parsing and processing.
[0061] After the slave device address mapping module determines that the corresponding target slave device identifier is slv4 based on the active flow control request address in the new active flow control request signal, the slave device traffic monitoring module further determines whether slv4_cmd_fifo is full. If slv4_cmd_fifo is not full, the slave device address mapping module sets the active flow control request ready signal to valid through the active flow control request interface, i.e., afc_req_rdy is 1, to allow new active flow control requests to be received. At this time, the flow switching operation is completed. If slv4_cmd_fifo is full, the above flow switching judgment and write command reselection process is repeated until the slave device command queue corresponding to the selected write command is not full.
[0062] According to the above embodiments, by introducing a slave device traffic monitoring and flow-switching coordination mechanism into the active flow control module, the active flow control device can monitor the empty / full status of each slave device's command queue in real time before the active flow control request signal enters the downstream link, and dynamically determine the target slave device corresponding to the current active flow control request signal. When any slave device's command queue is full and the current active flow control request signal points to that slave device, backpressure can be applied to the active flow control request interface in a timely manner, and the master device system control module can switch to sending write commands corresponding to other slave devices that are not full, thereby avoiding the overall request transmission stagnation at the master device end due to the blockage of a single slave device. Through the above mechanism, dynamic diversion and orderly scheduling of active flow control request signals in the direction of multiple slave devices are realized, effectively reducing the probability of head-end blocking, improving the link utilization efficiency and system throughput in multi-path concurrent data transmission scenarios, and enhancing the operational stability and robustness of the on-chip interconnect system under complex topologies and high load conditions.
[0063] In some embodiments, the active flow control module further includes a time slot management module (time_slot_mgmt) and an active flow control response ID FIFO (afc_rsp_id_fifo). When the slave device command queue is not empty and the active flow control response ID queue has not reached the preset storage capacity limit, the time slot management module obtains the corresponding active flow control request ID in the slave device command queue according to the weighted round-robin request signal (wrr_req), and transmits the active flow control request ID to the active flow control response ID queue.
[0064] According to the above embodiments, by introducing time slot management and weighted round-robin scheduling mechanisms into the active flow control module, the active flow control request identifiers of different slave devices can participate in scheduling in an orderly manner and be released gradually under the condition of satisfying queue state constraints. This avoids a single request occupying scheduling resources for a long time, realizes relatively fair scheduling and sending rhythm control of requests from multiple slave devices, and is conducive to improving the scheduling balance and overall operational stability of the active flow control device in multi-path concurrent data transmission scenarios.
[0065] In some embodiments, the time slot management module includes a weighted round-robin scheduler (WRR) and multiple slave status management modules (slv_st_mgmt).
[0066] The slave device status management module is used to determine whether each slave device command queue participates in weighted round-robin scheduling based on preset flow control conditions, and to generate a weighted round-robin scheduling request signal.
[0067] The weighted round-robin scheduler is used to poll the slave device command queues participating in the weighted round-robin scheduling based on the weighted round-robin scheduling request signal and the preset weight coefficient, determine the arbitrated slave device command queue, obtain the active flow control request identifier in the arbitrated slave device command queue through the corresponding slave device status management module, and transmit the active flow control request identifier to the active flow control response identifier queue.
[0068] In this embodiment of the invention, within a scheduling cycle, the time slot management module is used to determine the slave device command queues that are allowed to participate in weighted round-robin scheduling. That is, slave device command queues that are in a scheduling time slot are allowed to participate in weighted round-robin scheduling, while slave device command queues that are not in a scheduling time slot do not participate in weighted round-robin scheduling.
[0069] When at least one slave device command queue is not empty and the active flow control response flag queue is not full, each slave device status management module performs a status check on its corresponding slave device command queue based on preset flow control conditions. If the slave device command queue meets the participation scheduling conditions, the active flow control request flag is read from the corresponding slave device command queue, and the position corresponding to the slave device command queue is marked as valid in the weighted round-robin scheduling request signal to indicate that the slave device command queue participates in this weighted round-robin scheduling.
[0070] The weighted round-robin scheduler performs polling selection based on each valid bit in the weighted round-robin scheduling request signal and the preset weight coefficient, determines the active flow control request identifier that is allowed to be sent to the slave device, and transmits the active flow control request identifier to the active flow control response identifier queue.
[0071] For example, suppose the weighted round-robin scheduler sets the scheduling priorities for slave devices slv0 to slv6 to be 0 to 6, where 0 represents the highest priority and 6 represents the lowest priority. The preset weight coefficients for slave devices slv0 to slv6 are 2, 1, 1, 1, 1, and 1, respectively.
[0072] The bits in the weighted round-robin scheduling request signal wrr_req[6:0] correspond to slave devices slv0 to slv6, respectively, and are used to indicate whether the corresponding slave device command queue participates in weighted round-robin scheduling within the current clock signal (clk) period. A bit of 1 indicates that participation in weighted round-robin scheduling is allowed, and a bit of 0 indicates that participation is not allowed.
[0073] During the clock signal clk0 period, when the weighted round-robin scheduling request signal wrr_req[6:0] is 6'b101011, since slave device slv0 has the highest scheduling priority and the corresponding bits are valid, the weighted round-robin scheduler selects the active flow control request identifier of slave device slv0 during this scheduling period. slv0_st_mgmt reads the active flow control request identifier of slave device slv0 from slv0_cmd_fifo and transmits the active flow control request identifier of slv0 to the active flow control response identifier queue.
[0074] During the clock signal clk1 cycle, when the weighted round-robin scheduling request signal wrr_req[6:0] is still 6'b101011, given that the weight coefficient of slave device slv0 is 2, it is allowed to be selected for two consecutive scheduling cycles. Therefore, during this scheduling cycle, the weighted round-robin scheduler continues to select the active flow control request flag of slave device slv0. slv0_st_mgmt reads the active flow control request flag of slave device slv0 from slv0_cmd_fifo and transmits the active flow control request flag of slv0 to the active flow control response flag queue.
[0075] During the clock signal clk2 period, when the weighted round-robin scheduling request signal wrr_req[6:0] is still 6'b101011, since slave device slv0 has reached the number of consecutive scheduling allowed by its corresponding weight coefficient, the weighted round-robin scheduler selects the next active flow control request flag of slave device slv1 that meets the scheduling conditions according to the preset priority order and weight rules. slv1_st_mgmt reads the active flow control request flag of slave device slv1 from slv1_cmd_fifo and transmits the active flow control request flag of slv1 to the active flow control response flag queue.
[0076] According to the above embodiments, by introducing a mechanism combining scheduling slot control and weighted round-robin scheduling into the active flow control module, the slave device command queues participate in the scheduling process in an orderly manner under the premise of satisfying the queue status and preset flow control conditions, thereby achieving fine-grained scheduling management of multiple slave device requests. The participation scope of the slave device command queues is limited by scheduling slots, avoiding disorderly competition. Using a weighted round-robin scheduler combined with preset priority and weight coefficients, different slave device requests are selected fairly and controllably, ensuring that high-weight or high-priority slave devices obtain corresponding scheduling opportunities, preventing a single slave device from occupying scheduling resources for a long time. This scheme helps balance the sending rhythm of multiple requests, improves the predictability and balance of the scheduling process, and thus enhances the overall scheduling efficiency and system stability in multi-concurrent data transmission scenarios.
[0077] In some embodiments, such as Figure 1 and Figure 2 As shown, when the active flow control response flag queue reaches the preset storage capacity limit, a first backpressure signal is sent to the weighted round-robin scheduler.
[0078] In this embodiment of the invention, when the active flow control response flag queue is full, the active flow control response flag queue sends a backpressure signal to the weighted round-robin scheduler. After receiving the backpressure signal, the weighted round-robin scheduler passes the backpressure signal up level by level to the active flow control request interface, so as to implement backpressure control on the receiving process of the active flow control request signal at the interface level, thereby inhibiting the main device system control module from continuing to send active flow control request signals to the active flow control request interface.
[0079] In some embodiments, when the Active Flow Control Response Ready Signal (afc_rsp_rdy) is valid, the Active Flow Control module outputs an active flow control request identifier that is allowed to be sent and an Active Flow Control Response Valid Signal (afc_rsp_vld) to the main device system control module.
[0080] After receiving the active flow control request identifier and the active flow control response valid signal, the master device system control module retrieves the corresponding write command from the write address channel buffer based on the active flow control request identifier and sends the write command to the corresponding slave device.
[0081] In this embodiment of the invention, when the value of the active flow control response ready signal received from the master device system control module is 1, the active flow control module reads the active flow control request identifier that is allowed to be sent from the active flow control response identifier queue, and sends the active flow control request identifier as an active flow control response identifier (AFCResponse Interface, abc_rsp_id) together with the active flow control response valid signal to the master device system control module through the active flow control response interface (AFCResponse Interface, abbreviated as afc_rsp interface).
[0082] After receiving the active flow control request identifier and the active flow control response valid signal, the master device system control module obtains the corresponding write command from the write address channel buffer based on the active flow control request identifier, and sends the write command to the corresponding slave device through the AXI Master Interface (AXI_mst_if).
[0083] According to the above embodiments, by establishing a handshake mechanism based on response identifiers between the main device system control module and the active flow control module, the write commands after scheduling and arbitration can be released and sent in an orderly manner when the main device has the conditions to receive them. This ensures that the write command sending process matches the resource status on the main device side, avoids the issuance of invalid or conflicting commands, improves the controllability and reliability of the write command scheduling and sending process, and enhances the data transmission stability of the system in multi-concurrency scenarios.
[0084] In some embodiments, the master device system control module further includes a synchronization trigger module (3-stage Synchronization Flip-Flop, sync_ff3) for receiving the second backpressure signal from each slave device. The second backpressure signal is the slave backpressure signal (slv_bp[6:0]).
[0085] The synchronous trigger module is used to generate a third backpressure signal afc_slv_mst_bp[6:0] based on the second backpressure signal and send it to the active flow control module. The third backpressure signal is the Active Flow Control Slave-to-Master Backpressure Signal (afc_slv_mst_bp).
[0086] Based on the third back pressure signal, the active flow control module pauses the acquisition of the active flow control request identifier in the corresponding slave device command queue during the polling and scheduling process.
[0087] In this embodiment of the invention, the synchronous trigger module receives a slave device backpressure signal from the slave device, where each bit of the slave device backpressure signal corresponds to slave device slv0 to slave device slv6. When any bit in the slave device backpressure signal is valid, it indicates that the slave device corresponding to that bit applies backpressure to the active flow control module.
[0088] After synchronizing the backpressure signal from the slave device, the synchronous trigger module sends it to the active flow control module as the backpressure signal from the slave device to the master device. Specifically, each bit of the active flow control backpressure signal afc_slv_mst_bp[6:0] represents the backpressure state from slave device slv0 to slave device slv6.
[0089] When any bit in the active flow control back pressure signal from the slave device to the master device is valid, the active flow control module pauses acquisition and sends a new write command related to the slave device corresponding to that bit during the scheduling process.
[0090] According to the above embodiments, by synchronously processing the backpressure signals of each slave device, the active flow control device can monitor the receiving capability status of each slave device in a timely manner during the scheduling phase, and selectively suppress the scheduling and transmission of new write commands for slave devices in the backpressure state. This avoids continuing to apply load to the corresponding slave device when the downstream receiving capability is limited, effectively preventing the spread of congestion in the interconnection link, and improving the data transmission stability and overall operational reliability in multi-slave device interconnection scenarios.
[0091] In some embodiments, Figure 3 A timing control diagram from the device flow monitoring module is shown. (For example...) Figure 3 As shown, during each clock cycle from clk0 to clk6, the status signals of slv0_cmd_fifo to slv6_cmd_fifo are all at a low level, indicating that the corresponding slave device command queues are not full, meaning that no flow switching operation needs to be triggered during each clock cycle from clk0 to clk6.
[0092] During the clk7 clock cycle, the active flow control request signal sent by the master device system control module is parsed by the slave device address mapping module, which determines that the target slave device is identified as slv2. Since the slv2_cmd_fifo status signal is at a high level, indicating that slv2_cmd_fifo is in a full state, the slave device flow monitoring module triggers a flow switching operation.
[0093] Within the clk8 clock cycle, the master device system control module reselects a write command based on the flow switching signal and generates a new active flow control request signal based on this write command. After being parsed by the slave device address mapping module, the target slave device identifier is determined to be slv1. Since the slv1_cmd_fifo status signal is also at a high level, indicating that slv1_cmd_fifo is in a full state, the slave device flow monitoring module continues to trigger the flow switching operation.
[0094] Within the clk9 clock cycle, the master device system control module selects a new write command and generates an active flow control request signal based on it. After being parsed by the slave device address mapping module, the target slave device identifier is determined to be slv4. Since the slv4_cmd_fifo status signal is at a low level, indicating that slv4_cmd_fifo is not full, the slave device flow monitoring module does not need to continue performing flow switching operations, and the write command can be received.
[0095] During each clock cycle from clk11 to clk16, the slave device command queue corresponding to the parsed target slave device identifier is always full, thus continuously executing the stream switching operation during each corresponding clock cycle.
[0096] During the clk17 clock cycle, the status signal of slv1_cmd_fifo goes low, indicating that slv1_cmd_fifo has changed from a full state to a non-full state. The master device system control module does not need to continue to perform the flow switching operation, and the write command can be received normally.
[0097] As can be seen from the timing diagram above, even when slv2_cmd_fifo is in a full state from the start of clock cycle clk7, the above-mentioned flow switching mechanism does not affect the writing process of the corresponding write commands in the command queues of other slave devices, thus avoiding the head-blocking phenomenon caused by the blocking of a single slave device.
[0098] This application provides an active flow control method applied to the aforementioned active flow control device. This active flow control method and the active flow control device in one embodiment of this application are based on the same inventive concept and have similar problem-solving principles. Therefore, the implementation of the active flow control method is the same as that of the active flow control device in one embodiment of this application, and repeated details will not be described again. The terms "unit" or "module" used below can refer to a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0099] This proactive flow control method includes: The system control module generates a request signal based on the received write command and sends the request signal to the active flow control module.
[0100] The active flow control module parses the request signal based on the configuration information to determine the target slave device identifier corresponding to the request signal. The request identifier in the request signal is then transmitted to the slave device command queue corresponding to the target slave device identifier. When any slave device command queue reaches its preset storage capacity limit, the module checks whether the currently parsed request signal corresponds to that slave device command queue. If so, a flow-switching signal is sent to the system control module to cause the system control module to perform a flow-switching operation.
[0101] In some embodiments, the system control module is further configured to receive data packets sent by the device and parse the data packets into write commands and write data. The write commands are transmitted to the write address channel buffer, and the write data is transmitted to the write data channel buffer.
[0102] In some embodiments, the configuration information includes: slave device address mapping relationship. The slave device address mapping module performs address range matching on the request address in the request signal according to the slave device address mapping relationship in the control status register. If the request address matches the address range of any slave device, the target slave device identifier corresponding to the request address is obtained.
[0103] In some embodiments, when any slave device command queue reaches a preset storage capacity limit, the slave device address mapping module sends an invalidation request ready signal to the request interface of the active flow control module.
[0104] In some embodiments, when the device traffic monitoring module detects that any target slave device command queue has reached a preset storage capacity limit, the device traffic monitoring module queries whether the request signal currently parsed by the slave device address mapping module corresponds to the target slave device command queue that has reached the storage capacity limit. If so, a flow-cutting signal is sent to the system control module.
[0105] After receiving the flow switching signal, the system control module reselects a write command from the write address channel buffer, generates a request signal based on the write command, and transmits the request signal to the slave device address mapping module.
[0106] In some embodiments, when the slave device command queue is not empty and the response identifier queue has not reached the preset storage capacity limit, the time slot management module obtains the corresponding request identifier in the slave device command queue based on the weighted round-robin scheduling request signal and transmits the request identifier to the response identifier queue.
[0107] In some embodiments, the slave device status management module determines whether each slave device command queue participates in weighted round-robin scheduling based on preset flow control conditions, and generates a weighted round-robin scheduling request signal.
[0108] The weighted round-robin scheduler polls the slave device command queues participating in the weighted round-robin scheduling based on the weighted round-robin scheduling request signal and the preset weight coefficients, determines the arbitrated slave device command queue, obtains the request identifier in the arbitrated slave device command queue through the corresponding slave device status management module, and transmits the request identifier to the response identifier queue.
[0109] In some embodiments, when the response identifier queue reaches a preset storage capacity limit, a first backpressure signal is sent to the weighted round-robin scheduler.
[0110] In some embodiments, when the response ready signal is valid, the response identifier queue outputs a request identifier that allows sending and a response valid signal to the master device system control module.
[0111] After receiving the request identifier and the response valid signal, the system control module retrieves the corresponding write command from the write address channel buffer based on the request identifier and sends the write command to the corresponding slave device.
[0112] In some embodiments, the synchronization trigger module receives a second back pressure signal from each slave device. The synchronization trigger module generates a third back pressure signal based on the second back pressure signal and sends it to the active flow control module.
[0113] The active flow control module, based on the third back pressure signal, pauses the acquisition of the request identifier in the corresponding slave device command queue during the polling and scheduling process.
[0114] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0115] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0116] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0117] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0118] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0119] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An active flow control device, characterized in that, include: Active flow control module and system control module; The active flow control module includes: multiple slave device command queues; The system control module is used to generate a request signal based on the received write command and send the request signal to the active flow control module; The active flow control module is used to parse the request signal based on the configuration information to determine the target slave device identifier corresponding to the request signal; transmit the request identifier in the request signal to the slave device command queue corresponding to the target slave device identifier; when any slave device command queue reaches the preset storage capacity limit, query whether the currently parsed request signal corresponds to the slave device command queue; if so, send a flow switching signal to the system control module so that the system control module performs a flow switching operation.
2. The apparatus according to claim 1, characterized in that, The system control module includes: a write address channel buffer and a write data channel buffer; The system control module is also used to receive data packets sent from the device, and parse the data packets into write commands and write data; transmit the write commands to the write address channel buffer, and transmit the write data to the write data channel buffer.
3. The apparatus according to claim 1, characterized in that, The configuration information includes: slave device address mapping relationship; the system control module includes: control status register; the active flow control module further includes: slave device address mapping module, used to perform address range matching on the request address in the request signal according to the slave device address mapping relationship in the control status register; if the request address matches the address range of any slave device, the target slave device identifier corresponding to the request address is obtained.
4. The apparatus according to claim 3, characterized in that, When any slave device command queue reaches the preset storage capacity limit, the slave device address mapping module sends an invalidation request ready signal to the request interface of the active flow control module.
5. The apparatus according to claim 3, characterized in that, The active flow control module further includes: a slave device flow monitoring module, which, when the slave device flow monitoring module detects that any target slave device command queue has reached the preset storage capacity limit, queries whether the request signal currently parsed by the slave device address mapping module corresponds to the target slave device command queue that has reached the storage capacity limit; if so, it sends a flow switching signal to the system control module. After receiving the flow switching signal, the system control module reselects a write command from the write address channel buffer, generates a request signal based on the write command, and transmits the request signal to the slave device address mapping module.
6. The apparatus according to claim 1, characterized in that, The active flow control module further includes: a time slot management module and a response identifier queue; when the slave device command queue is not empty and the response identifier queue has not reached the preset storage capacity limit, the time slot management module obtains the corresponding request identifier in the slave device command queue based on the weighted round-robin scheduling request signal, and transmits the request identifier to the response identifier queue.
7. The apparatus according to claim 6, characterized in that, The time slot management module includes: a weighted polling scheduler and multiple slave device status management modules; The slave device status management module is used to determine whether each slave device command queue participates in weighted round-robin scheduling based on preset flow control conditions, and to generate the weighted round-robin scheduling request signal; The weighted round-robin scheduler is used to poll the slave device command queues participating in the weighted round-robin scheduling based on the weighted round-robin scheduling request signal and preset weight coefficients, determine the arbitrated slave device command queue, obtain the request identifier in the arbitrated slave device command queue through the corresponding slave device status management module, and transmit the request identifier to the response identifier queue.
8. The apparatus according to claim 7, characterized in that, When the response identifier queue reaches the preset storage capacity limit, a first backpressure signal is sent to the weighted round-robin scheduler.
9. The apparatus according to claim 6, characterized in that, When the response ready signal is valid, the response identifier queue outputs a request identifier that allows sending and a response valid signal to the system control module; After receiving the request identifier and the response valid signal, the system control module retrieves the corresponding write command from the write address channel buffer based on the request identifier and sends the write command to the corresponding slave device.
10. The apparatus according to claim 1, characterized in that, The system control module further includes: a synchronous trigger module, used to receive the second reverse voltage signal from each slave device; The synchronous trigger module is used to generate a third reverse pressure signal based on the second reverse pressure signal and send it to the active flow control module; Based on the third back pressure signal, the active flow control module pauses the acquisition of the request identifier in the corresponding slave device command queue during the polling scheduling process.
11. An active flow control method, characterized in that, include: The system control module generates a request signal based on the received write command and sends the request signal to the active flow control module; The active flow control module parses the request signal based on the configuration information to determine the target slave device identifier corresponding to the request signal; The request identifier in the request signal is transmitted to the slave device command queue corresponding to the target slave device identifier; when any slave device command queue reaches the preset storage capacity limit, it is queried whether the currently parsed request signal corresponds to the slave device command queue; if so, a flow-cutting signal is sent to the system control module so that the system control module performs a flow-cutting operation.
12. A chip, characterized in that, Includes the active flow control device according to any one of claims 1 to 10.
13. A circuit board, characterized in that, Includes the chip described in claim 12.
14. An electronic device, characterized in that, Includes the board as described in claim 13.