A communication device address allocation method, apparatus, device, and storage medium

Abstract

The application discloses a communication device address allocation method and device, equipment and a storage medium, relates to the technical field of communication, and is applied to a host device of a backboard communication system; the backboard communication system further comprises at least two slave devices connected with the host device; the host device and the slave devices are connected to differential signal lines, and the slave devices are sequentially connected in turn through a state signal line, and the host device is connected with the first slave device through the state signal line; comprising: setting the differential signal line to a level state corresponding to an address allocation mode, so that the slave device enters the address allocation mode; sending a pulse sequence representing address allocation to the first slave device through the state signal line, so that the first slave device extracts address information and sends the pulse sequence to the next slave device; obtaining the pulse sequence returned by the first slave device after extracting the address information, and ending the address allocation mode. Thus, the communication anti-interference performance can be improved, the equipment space can be saved, and the operation and maintenance workload can be reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, apparatus, device, and storage medium for address allocation of communication devices. Background Technology

[0002] Industrial environments involve the collection and processing of numerous I / O (Input / Output) data, with varying I / O requirements across different industrial settings. Backplane communication typically consists of a master unit and multiple slave units, with the master accessing the slave units via specific addresses. Traditionally, slave addresses are either preset using DIP switches (which leads to communication errors if the address is misconfigured, and requires reconfiguration every time the connection topology is changed, making it inconvenient) or automatically assigned by adding multiple address assignment lines.

[0003] Therefore, optimizing the anti-interference capability of backplane communication and reducing the workload of equipment maintenance are problems that need to be solved in this field. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a method, apparatus, device, and storage medium for allocating communication device addresses. Employing differential signal communication can significantly improve the anti-interference capability and increase communication speed. Furthermore, by using status signal lines to achieve automatic device address allocation and automatic status reporting, it can save device space, reduce costs, and alleviate the workload of device maintenance. The specific solution is as follows: In a first aspect, this application provides a communication device address allocation method, applied to a host device in a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: The differential signal lines are set to the level state corresponding to the address allocation mode, so that each slave device can enter the address allocation mode after recognizing the level state; The pulse sequence representing address allocation is sent to the first slave device via the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and send the pulse sequence representing address allocation after updating the address information to the next slave device; The system acquires the pulse sequence indicating successful reception of the representation address, which is uploaded by the first slave device and returned by the at least two slave devices after extracting address information from the pulse sequence indicating the representation address allocation is complete. After receiving the pulse sequence indicating the representation address allocation is complete forwarded by the first slave device, the system ends the address allocation mode. The pulse sequence indicating the representation address allocation is complete is a pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0005] Optionally, the preset tail device condition is that after a single slave device sends a pulse sequence representing address allocation to the status signal line, it detects whether it receives a pulse sequence representing successful address reception within a preset time to determine whether it is a tail slave device.

[0006] Optionally, any one of the at least two slave devices, excluding the tail slave device, may transmit the pulse sequence uploaded by the next slave device to the previous slave device or the master device via transparent transmission.

[0007] Secondly, this application provides a communication device address allocation method, applied to the first slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: When the differential signal line is detected to be set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered. The pulse sequence representing address allocation sent by the host device is obtained through the status signal line, and the address information is extracted. Then, the pulse sequence representing successful address reception is sent to the host device. The pulse sequence representing address allocation after updating the address information is sent to the next slave device, and the pulse sequence representing successful address reception uploaded by the next slave device is forwarded to the master device, until the pulse sequence representing address allocation is completed is forwarded to the master device, so that the master device ends the address allocation mode; the pulse sequence representing address allocation completion is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0008] Thirdly, this application provides a communication device address allocation method, applied to the tail slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein, the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: When the differential signal line is detected to be set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered. The pulse sequence representing address allocation sent by the previous slave device is obtained through the status signal line, and the address information is extracted. Then, the pulse sequence representing successful address reception is uploaded to the previous slave device through the status signal line, so that the first slave device forwards the corresponding pulse sequence representing successful address reception to the master device. After determining that it meets the preset tail device conditions, it generates a pulse sequence indicating that the address allocation is complete, and uploads the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, thereby causing the master device to end the address allocation mode.

[0009] Fourthly, this application provides a communication device address allocation apparatus applied to a host device in a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The level state setting module is used to set the differential signal line to the level state corresponding to the address allocation mode, so that each slave device can enter the address allocation mode after recognizing the level state. The first pulse sequence transmission module is used to transmit a pulse sequence representing address allocation to the first slave device through the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and transmit the pulse sequence representing address allocation after updating the address information to the next slave device; The pulse sequence acquisition module is used to acquire the pulse sequence of successful reception of the representation address returned by the at least two slave devices after extracting address information from the pulse sequence of the representation address allocation uploaded by the first slave device, and to end the address allocation mode after receiving the pulse sequence of the representation address allocation completed forwarded by the first slave device; the pulse sequence of the representation address allocation completed is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0010] Fifthly, this application provides a communication device address allocation apparatus, applied to the first slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The first level state recognition module is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The second pulse sequence transmission module is used to obtain the pulse sequence representing address allocation sent by the host device through the status signal line and extract the address information, and then send the pulse sequence representing successful address reception to the host device. The third pulse sequence sending module is used to send the pulse sequence representing address allocation after updating the address information to the next slave device, and forward the pulse sequence representing successful address reception uploaded by the next slave device to the master device, until the pulse sequence representing complete address allocation is forwarded to the master device, so that the master device ends the address allocation mode; the pulse sequence representing complete address allocation is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0011] Sixthly, this application provides a communication device address allocation apparatus, applied to the tail slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The second level state recognition module is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The first pulse sequence uploading module is used to obtain the pulse sequence representing address allocation sent by the previous slave device through the status signal line and extract the address information, and then upload the pulse sequence representing address reception success to the previous slave device through the status signal line, so that the first slave device forwards the corresponding pulse sequence representing address reception success to the host device; The second pulse sequence uploading module is used to generate a pulse sequence indicating that the address allocation is complete after determining that it meets the preset tail device conditions, and upload the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, thereby causing the master device to end the address allocation mode.

[0012] In a seventh aspect, this application provides an electronic device, comprising: Memory, used to store computer programs; A processor for executing the computer program to implement the communication device address allocation method described above.

[0013] Eighthly, this application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the communication device address allocation method described above.

[0014] Therefore, the technical solution of this application is applied to the host device of a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein, the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are connected sequentially via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; specifically, it includes: setting the differential signal lines to the level state corresponding to the address allocation mode, so that each slave device enters the address allocation mode after recognizing the level state; and transmitting the address representation via the status signal lines. The allocated pulse sequence is sent to the first slave device, so that the first slave device can extract address information from the pulse sequence representing address allocation and send the pulse sequence representing address allocation after updating the address information to the next slave device; the pulse sequence representing successful address reception returned by the at least two slave devices after extracting address information from the pulse sequence representing address allocation is obtained from the first slave device, and the address allocation mode ends after receiving the pulse sequence representing complete address allocation forwarded by the first slave device; the pulse sequence representing complete address allocation is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions. In this way, this application adopts differential signal communication, which can greatly improve the anti-interference of communication and increase the communication speed; and the automatic allocation of device addresses and automatic reporting of status are realized through status signal lines, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 This is a flowchart of a communication device address allocation method disclosed in this application; Figure 2 This is a specific communication system architecture diagram disclosed in this application; Figure 3 This is a schematic diagram of a specific voltage level state disclosed in this application; Figure 4 This application discloses a flowchart of a specific method for allocating addresses for communication devices. Figure 5 A flowchart illustrating another specific method for allocating communication device addresses disclosed in this application; Figure 6This is a schematic diagram illustrating a specific pulse sequence definition disclosed in this application; Figure 7 This is a flowchart illustrating yet another specific method for allocating communication device addresses disclosed in this application; Figure 8 This application discloses a specific address allocation method flowchart; Figure 9 This application discloses a specific method for assigning slave device addresses. Figure 10 This is a flowchart of a specific communication method disclosed in this application; Figure 11 This is a schematic diagram of the structure of a communication device address allocation device disclosed in this application; Figure 12 This is a schematic diagram of the device structure for another communication device address allocation method disclosed in this application; Figure 13 This is a schematic diagram of the device structure for another communication device address allocation method disclosed in this application; Figure 14 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] See Figure 1 As shown, this invention discloses a communication device address allocation method applied to a host device in a backplane communication system. The backplane communication system further includes at least two slave devices that establish a line connection with the host device. The host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines. The host device establishes a line connection with the first slave device via the status signal lines. The method includes: Step S11: Set the differential signal line to the level state corresponding to the address allocation mode so that each slave device can enter the address allocation mode after recognizing the level state.

[0019] Understandably, a backplane communication system includes a master device and multiple slave devices. Specifically, Figure 2This is a specific communication system architecture diagram. The master device's AB ports are each connected to a pair of differential signal lines, and the AB ports of slave devices 1 to n are also connected to differential signal lines. This allows data communication between the master device and different slave devices via differential signal lines. Furthermore, the master device's SR (Serial Right) port is connected to the SL (Serial Left) port of master device 1 (the first slave device) via a status signal line, while slave device 1's SR port is connected to the SL port of the next slave device via a status signal line, until it is connected to the last slave device n. Further, the backplane communication system first needs to assign addresses to the slave devices before entering the communication state to achieve data communication. Specifically, the master device can inform each slave device to enter address assignment mode by setting the level state of the differential signal lines. For example, in a backplane communication system, the master device can set A to a positive level and B to a negative level. After 10ms, the system enters communication mode, and the master device can interact with slave devices. Conversely, when A is negative and B is positive, after 10ms, the system can enter address allocation mode. The master device needs to maintain this address allocation mode level until all slave devices have completed address allocation. In a specific embodiment, when the backplane communication system is in communication mode and no data is being transmitted, the idle level of the bus (differential signal line) is also A positive and B negative. That is, when entering address allocation mode, the master device needs to forcibly set A to a positive level and B to a negative level for more than 10ms. When exiting address allocation mode, the bus is released, allowing it to enter idle mode (A positive and B negative). After 10ms, the bus can enter communication mode, enabling data communication between devices. Figure 3 This is a schematic diagram of a specific level state. Differential signal lines (buses) enter communication mode or address allocation mode by setting their level states.

[0020] Step S12: The pulse sequence representing address allocation is sent to the first slave device through the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and send the pulse sequence representing address allocation after updating the address information to the next slave device.

[0021] Furthermore, the master device can enter address allocation mode by setting the level state of the differential signal lines, and then send a pulse sequence representing address allocation to the first slave device through its connected signal lines. The first slave device can extract the address information from this pulse sequence and use it as its own address information; then it updates the address information, for example, by incrementing the address, and sends the updated pulse sequence to the next slave device. Understandably, with this address allocation method, the master device only needs to send the pulse sequence representing address allocation once, and each slave device can extract its own address information.

[0022] Step S13: Obtain the pulse sequence of successful reception of the representation address returned by the at least two slave devices after extracting address information from the pulse sequence of the representation address allocation uploaded by the first slave device, and end the address allocation mode after receiving the pulse sequence of the representation address allocation completed forwarded by the first slave device; the pulse sequence of the representation address allocation completed is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0023] Furthermore, after extracting the address information, the slave device can generate a pulse sequence indicating successful address reception. The first slave device can directly send this pulse sequence to the master device via the differential signal line. Other slave devices need to upload their own generated pulse sequences indicating successful address reception to the previous slave device via the status signal line, and so on, layer by layer, until the first slave device forwards the pulse sequence to the master device. It should be noted that for the last slave device, i.e., the tail slave device, after extracting the address information and generating the corresponding pulse sequence indicating successful address reception, it can continue to generate a pulse sequence indicating complete address allocation, uploading it layer by layer, until the first slave device forwards the pulse sequence to the master device. Upon receiving the pulse sequence indicating complete address allocation, the master device can end the address allocation mode; specifically, it ends the address allocation mode by switching the level state of the differential signal line.

[0024] It is understandable that a slave device can determine whether it is the last slave device by setting preset tail device conditions. In a specific embodiment, during the process of determining the preset tail device conditions, a single slave device sends a pulse sequence indicating address allocation to the status signal line, and then checks whether it receives a pulse sequence indicating successful address reception within a preset time. If it does not receive the pulse sequence, it indicates that it is the last slave device; if it does receive the pulse sequence, it indicates that it is not the last slave device, and another slave device has successfully allocated an address. Furthermore, the next slave device continues to determine whether it is the last slave device, until a slave device determines that it is the last slave device, and then sends a pulse sequence indicating that the address allocation is complete to the upper layer.

[0025] It should be noted that for each slave device, except for the tail slave device, any slave device needs to forward the pulse sequence uploaded by the next slave device to the previous slave device (the first slave device forwards it to the master device). This process can be carried out in a transparent transmission manner, that is, the pulse sequence uploaded by the next slave device is transparently transmitted to the previous slave device or the master device.

[0026] Furthermore, such as Figure 4 The diagram illustrates the flowchart of the address allocation process for the master device. First, the master notifies the slave device to enter address allocation mode by setting the differential signal line levels (A negative, B positive) and maintains this level until the system completes address allocation. The master also sets the SR port as an output, defaulting to a low level. The slave monitors the bus (differential signal line) status. When it detects A negative and B positive for a duration greater than 10ms, the slave enters address allocation mode. In address allocation mode, the slave immediately sets the SL port as an input and the SR port as an output, defaulting to a low level. The master can send an address allocation pulse sequence from the SR port to slave 1, containing address information. The slave extracts the address information from the address allocation pulse sequence, increments the address, and sends it to the next slave. The slave then sets SL as an output (pull-up mode) and SR as an input (floating mode); it then sends an address reception success pulse sequence to the next higher-level device (the first slave's parent device is the master device, and the other slave devices' parent devices are also slave devices), confirming that the device has completed address allocation. Afterward, it enters transparent transmission mode to transmit the information uploaded by the next slave. The address allocation operation described above can complete the address allocation for all slave devices. It should be noted that after completing address allocation, each slave device will perform a tail device detection. If it is the tail device, it will send an address allocation completion pulse sequence to the superior device. Understandably, the address allocation completion pulse sequence is reported layer by layer from the slave devices to the master device. Upon receiving this sequence, the master device exits the address allocation mode and enters the communication mode.

[0027] Therefore, it can be seen that the differential signal communication adopted in this application can greatly improve the anti-interference ability and communication speed; and the automatic allocation of device address and automatic reporting of status can be achieved through status signal line, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance.

[0028] See Figure 5 As shown, this embodiment of the invention discloses a communication device address allocation method, applied to the first slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein, the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: Step S21: When it is detected that the differential signal line is set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered.

[0029] In this application, as the first slave device, it needs to monitor the level state of the differential signal line. When it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the master device, it also enters the address allocation mode. It is understood that the slave device can enter the address allocation mode by acquiring and sending pulse sequences through the connected status signal line.

[0030] Step S22 obtains the pulse sequence representing address allocation sent by the host device through the status signal line and extracts the address information, and then sends the pulse sequence representing successful address reception to the host device.

[0031] Furthermore, the first slave device can acquire the pulse sequence indicating address allocation sent by the master device via the status signal line. Understandably, when a slave device enters address allocation mode, it can set the SL port connected to the status signal line as an input to acquire the pulse sequence sent by the master device, and set the SR port as an output to send the pulse sequence to the next slave device. Specifically, the first slave device can extract address information from the pulse sequence sent by the master device, then generate a pulse sequence indicating successful address reception, and send this pulse sequence to the master device so that the master device can statistically analyze the address allocation status of the slave devices.

[0032] Step S23: Send the pulse sequence representing address allocation after updating the address information to the next slave device, and forward the pulse sequence representing successful address reception uploaded by the next slave device to the master device, until the pulse sequence representing address allocation is completed is forwarded to the master device, so that the master device ends the address allocation mode; the pulse sequence representing address allocation completion is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0033] Furthermore, after the first slave device extracts the address information, it needs to update the address information in the received pulse sequence indicating address allocation (address incremented by one), and then send the updated pulse sequence to the next slave device so that the next slave device can extract the corresponding address information. Correspondingly, after allocating the address, the next slave device will upload the pulse sequence indicating successful address reception to the first slave device, which can then forward this pulse sequence to the master device.

[0034] Understandably, after the last slave device (tail slave device) uploads the pulse information indicating successful address reception, it will also upload a pulse sequence indicating that address allocation is complete, indicating that all slave devices have completed address allocation; after the first slave device forwards the pulse sequence indicating that address allocation is complete to the master device, the master device can end the address allocation mode.

[0035] In a specific embodiment, the pulse sequence is defined as follows: Figure 6As shown, it can include two parts: address information and end information. The address information consists of a 10kHz fundamental frequency, with the number of pulses representing the device address. The end information follows the address information and is a low-level signal lasting more than milliseconds. Furthermore, there are three types of pulse sequences: address allocation pulse sequence, address reception success pulse sequence, and address allocation completion pulse sequence. Specifically, the address allocation pulse sequence is the address allocation command initiated by the master device to the slave device. The address starts from 1 (one pulse). After receiving the address, the slave device increments the address and sends it to the next-level slave device until all slave devices have been allocated addresses. The address reception success pulse sequence is the signal fed back to the master device after the slave device receives the address allocated by the master device (master or master slave). This pulse sequence carrying the local address is forwarded by the master slave device through the uplink and finally fed back to the master. The address allocation completion pulse sequence is initiated by a slave device after all slave addresses have been allocated and the slave device detects that it is the last device. For example, the "address allocation completion pulse sequence" can be represented by sending ten consecutive "address reception successful pulse sequences". This signal is forwarded by the upper-level slave devices to the master device. After receiving this signal, the master device can end the address allocation mode and extract the total number of slave devices from the pulse sequence.

[0036] Therefore, it can be seen that the differential signal communication adopted in this application can greatly improve the anti-interference ability and communication speed; and the automatic allocation of device address and automatic reporting of status can be achieved through status signal line, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance.

[0037] See Figure 7 As shown, this invention discloses a communication device address allocation method, applied to the tail slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein, the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: Step S31: When it is detected that the differential signal line is set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered.

[0038] Step S32: Obtain the pulse sequence representing address allocation sent by the previous slave device through the status signal line and extract the address information. Then, upload the pulse sequence representing successful address reception to the previous slave device through the status signal line so that the first slave device can forward the corresponding pulse sequence representing successful address reception to the master device.

[0039] Step S33: After determining that it meets the preset tail device conditions, generate a pulse sequence indicating that the address allocation is complete, and upload the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, so that the master device ends the address allocation mode.

[0040] In this embodiment, after the tail slave device is assigned an address, it can initiate a pulse sequence indicating that the address assignment is complete; this sequence is then uploaded layer by layer from the upper-level slave devices to the master device; when the master device receives this pulse sequence indicating that the address assignment is complete, it indicates that all slave devices have completed the address assignment and can end the address assignment mode.

[0041] In a specific embodiment, the address allocation process is as follows: Figure 8 The diagram illustrates a scenario where a master device is connected to two slave devices (the protocol supports a maximum of 255 slave devices, but in practice, due to size limitations, the number of slave devices will be less than 255). At time t0, the master sets the differential bus to A negative and B positive, notifying the slave to enter address allocation mode. In this mode, the master sets the SR line as an output, and the slave sets the SL line as an input and SR as an output. At time t1, the master sends an "address allocation pulse sequence" with one pulse through the SR line. Slave 1 receives this signal through the SL line and sets its local address to 1. After sending, the master sets the SR to pull-up input mode. At time t2, Slave 1 sends an "address reception success pulse sequence" to the master, increments its address, and sends the "address allocation pulse sequence" to the downstream device. After sending, Slave 1 sets the SR to pull-up input mode. At time t3, Slave 2 sends an "address reception success pulse sequence" to the upstream device, which is then forwarded to the master. It also increments its address and sends the "address allocation pulse sequence" to the downstream device. After sending, Slave 2 sets the SR to pull-up input mode. At time t4, slave device 2 detects that it is the last device (the tail device) and sends an "address allocation complete pulse sequence" to the superior device. Upon receiving this message, the master device can determine that the address allocation is complete and then enter the normal working state.

[0042] Furthermore, such as Figure 8The diagram illustrates the process by which a slave device determines whether it is a tail slave device. Specifically, after receiving the address assigned by the superior device, the slave immediately sets its SL signal line to output mode, with a default low level. It then sends an "address allocation pulse sequence" via the SR signal line. Immediately after sending, it sets the SR signal line to input mode and pulls it up (pull-up means connecting the signal line to the power supply through a resistor, thus defaulting to a high level). The slave then checks the input level on the SR signal line within a 100ms time window. If the input level remains high, the device is considered a tail device. If the device under test is not a tail device, but has other slave devices below it, these lower-level slaves will immediately pull their own SL signal (the SR signal of the device under test) low upon receiving the "address allocation pulse sequence" and then send an "address reception success pulse sequence." The device under test can determine whether it is a tail device by checking whether the SR signal level remains high within a specific time window.

[0043] In a specific embodiment, such as Figure 9 The diagram shows the flowchart of address allocation for slave devices. It mainly involves receiving the address from the SL side and then allocating the new address to the lower-level device via the SR. During this process, tail device detection is also performed. If it is the tail device, an allocation completion command is sent; otherwise, the SR / SL signals are cascaded, transparently transmitting the pulse sequence reported by the lower-level device.

[0044] Furthermore, after completing the address allocation steps described above for each slave device, the backplane communication system can enter communication mode; such as Figure 10 As shown, the communication process uses the Modbus RTU protocol, and communication can be conducted in a query-response manner, with the master asking and the slave responding. The master accesses the slaves sequentially via addresses. As mentioned above, during the address allocation phase, the master allocates slave communication addresses sequentially, starting from 1, based on the physical connection order of the slaves, and the master knows the number of slaves. To improve the slave's response speed, the slave receiving side can use DMA + multiple verification methods. Firstly, DMA data reception is used; secondly, to address the slow speed of CRC verification, which can easily slow down the bus communication rate, a multiple verification method can be used. For interrupt handling, such as... Figure 11As shown, the program can employ pre-verification to check information such as frame address, frame length, and frame keyword. This part of the verification only requires simple comparison and does not require complex calculations, thus making the verification speed fast. Only data that passes the pre-verification will have its flag set (data_ready = TRUE) and be processed in the main program. Otherwise, the data is discarded, and the DMA is reset. To improve system response speed, the DMA reset operation can also be handled in the main program. CRC verification is performed in the main program. This part is relatively slow. Pre-processing has already eliminated most data anomalies, and CRC verification further ensures data accuracy based on pre-processing. The combination of these two methods allows for the rapid selection of target data, discarding data from non-local addresses and abnormal data.

[0045] Therefore, it can be seen that the differential signal communication adopted in this application can greatly improve the anti-interference ability and communication speed; and the automatic allocation of device address and automatic reporting of status can be achieved through status signal line, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance.

[0046] like Figure 11 As shown, this application discloses a communication device address allocation apparatus applied to a host device in a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein, the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The level state setting module 11 is used to set the differential signal line to the level state corresponding to the address allocation mode, so that each slave device can enter the address allocation mode after recognizing the level state. The first pulse sequence transmission module 12 is used to transmit a pulse sequence representing address allocation to the first slave device through the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and send the pulse sequence representing address allocation after updating the address information to the next slave device; The pulse sequence acquisition module 13 is used to acquire the pulse sequence of successful reception of the representation address returned by the at least two slave devices after extracting address information from the pulse sequence of the representation address allocation uploaded by the first slave device, and to end the address allocation mode after receiving the pulse sequence of the representation address allocation completed forwarded by the first slave device; the pulse sequence of the representation address allocation completed is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0047] Therefore, it can be seen that the differential signal communication between the host device and each slave device in this application can greatly improve the anti-interference capability and increase the communication speed. Furthermore, the host device and each slave device can automatically allocate device addresses and automatically report status through status signal lines, which can save device space, reduce costs, and reduce the workload of device operation and maintenance.

[0048] like Figure 12 As shown, this application discloses a communication device address allocation apparatus, applied to the first slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein, the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The first level state recognition module 21 is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The second pulse sequence transmission module 22 is used to obtain the pulse sequence representing address allocation sent by the host device through the status signal line and extract the address information, and then send the pulse sequence representing successful address reception to the host device. The third pulse sequence sending module 23 is used to send the pulse sequence representing address allocation after updating the address information to the next slave device, and forward the pulse sequence representing successful address reception uploaded by the next slave device to the master device, until the pulse sequence representing address allocation is completed is forwarded to the master device so that the master device ends the address allocation mode; the pulse sequence representing address allocation completion is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

[0049] Therefore, it can be seen that the differential signal communication adopted in this application can greatly improve the anti-interference ability and communication speed; and the automatic allocation of device address and automatic reporting of status can be achieved through status signal line, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance.

[0050] like Figure 13As shown, this application discloses a communication device address allocation apparatus, applied to the tail slave device among at least two slave devices that establish a line connection with a host device in a backplane communication system; wherein, the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are connected sequentially via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the apparatus includes: The second level state recognition module 31 is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The first pulse sequence uploading module 32 is used to obtain the pulse sequence representing address allocation sent by the previous slave device through the status signal line and extract the address information, and then upload the pulse sequence representing address reception success to the previous slave device through the status signal line, so that the first slave device forwards the corresponding pulse sequence representing address reception success to the host device; The second pulse sequence uploading module 33 is used to generate a pulse sequence indicating that the address allocation is complete after determining that it meets the preset tail device conditions, and upload the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, thereby causing the master device to end the address allocation mode.

[0051] Therefore, it can be seen that the differential signal communication adopted in this application can greatly improve the anti-interference ability and communication speed; and the automatic allocation of device address and automatic reporting of status can be achieved through status signal line, which can save equipment space, reduce costs, and reduce the workload of equipment operation and maintenance.

[0052] Furthermore, embodiments of this application also disclose an electronic device, Figure 14 This is a structural diagram of an electronic device 40 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0053] Figure 14 This is a schematic diagram of the structure of an electronic device 40 provided in an embodiment of this application. Specifically, the electronic device 40 may include: at least one processor 41, at least one memory 42, a power supply 43, a communication interface 44, an input / output interface 45, and a communication bus 46. The memory 42 stores a computer program, which is loaded and executed by the processor 41 to implement the relevant steps in the communication device address allocation method disclosed in any of the foregoing embodiments. Alternatively, the electronic device 40 in this embodiment may specifically be an electronic computer.

[0054] In this embodiment, the power supply 43 is used to provide operating voltage for each hardware device on the electronic device 40; the communication interface 44 can create a data transmission channel between the electronic device 40 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 45 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0055] In addition, the memory 42, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 421, computer program 422, etc., and the storage method can be temporary storage or permanent storage.

[0056] The operating system 421 is used to manage and control the various hardware devices on the electronic device 40 and the computer program 422, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the communication device address allocation method executed by the electronic device 40 as disclosed in any of the foregoing embodiments, the computer program 422 may further include a computer program capable of performing other specific tasks.

[0057] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned communication device address allocation method. The specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0058] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0059] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0060] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0061] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for address allocation in communication devices, characterized in that, A host device is used in a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are connected sequentially via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: The differential signal lines are set to the level state corresponding to the address allocation mode, so that each slave device can enter the address allocation mode after recognizing the level state; The pulse sequence representing address allocation is sent to the first slave device via the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and send the pulse sequence representing address allocation after updating the address information to the next slave device; The system acquires the pulse sequence indicating successful reception of the representation address, which is uploaded by the first slave device and returned by the at least two slave devices after extracting address information from the pulse sequence indicating the representation address allocation is complete. After receiving the pulse sequence indicating the representation address allocation is complete forwarded by the first slave device, the system ends the address allocation mode. The pulse sequence indicating the representation address allocation is complete is a pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

2. The communication device address allocation method according to claim 1, characterized in that, The preset tail device condition is that after a single slave device sends a pulse sequence representing address allocation to the status signal line, it detects whether it receives a pulse sequence representing successful address reception within a preset time to determine whether it is a tail slave device.

3. The communication device address allocation method according to claim 1, characterized in that, Each of the at least two slave devices, excluding the tail slave device, transmits the pulse sequence uploaded by the next slave device to the previous slave device or the master device via transparent transmission.

4. A method for allocating addresses for communication devices, characterized in that, A method for establishing a line connection between a host device and at least two slave devices in a backplane communication system, wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: When the differential signal line is detected to be set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered. The pulse sequence representing address allocation sent by the host device is obtained through the status signal line, and the address information is extracted. Then, the pulse sequence representing successful address reception is sent to the host device. The pulse sequence representing address allocation after updating the address information is sent to the next slave device, and the pulse sequence representing successful address reception uploaded by the next slave device is forwarded to the master device, until the pulse sequence representing address allocation is completed is forwarded to the master device, so that the master device ends the address allocation mode; the pulse sequence representing address allocation completion is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

5. A method for allocating addresses for communication devices, characterized in that, A tail slave device among at least two slave devices used in a backplane communication system to establish a line connection with a host device; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the method includes: When the differential signal line is detected to be set to the level state corresponding to the address allocation mode by the host device, the address allocation mode is entered. The pulse sequence representing address allocation sent by the previous slave device is obtained through the status signal line, and the address information is extracted. Then, the pulse sequence representing successful address reception is uploaded to the previous slave device through the status signal line, so that the first slave device forwards the corresponding pulse sequence representing successful address reception to the master device. After determining that it meets the preset tail device conditions, it generates a pulse sequence indicating that the address allocation is complete, and uploads the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, thereby causing the master device to end the address allocation mode.

6. A communication device address allocation apparatus, characterized in that, A host device for use in a backplane communication system; the backplane communication system further includes at least two slave devices that establish a line connection with the host device; wherein the host device and the at least two slave devices are all connected to differential signal lines for data interaction, and the at least two slave devices are connected sequentially via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the device includes: The level state setting module is used to set the differential signal line to the level state corresponding to the address allocation mode, so that each slave device can enter the address allocation mode after recognizing the level state. The first pulse sequence transmission module is used to transmit a pulse sequence representing address allocation to the first slave device through the status signal line, so that the first slave device can extract address information from the pulse sequence representing address allocation and transmit the pulse sequence representing address allocation after updating the address information to the next slave device; The pulse sequence acquisition module is used to acquire the pulse sequence of successful reception of the representation address returned by the at least two slave devices after extracting address information from the pulse sequence of the representation address allocation uploaded by the first slave device, and to end the address allocation mode after receiving the pulse sequence of the representation address allocation completed forwarded by the first slave device; the pulse sequence of the representation address allocation completed is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

7. A communication device address allocation apparatus, characterized in that, A device for establishing a line connection between a host device and at least two slave devices in a backplane communication system; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the device includes: The first level state recognition module is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The second pulse sequence transmission module is used to obtain the pulse sequence representing address allocation sent by the host device through the status signal line and extract the address information, and then send the pulse sequence representing successful address reception to the host device. The third pulse sequence sending module is used to send the pulse sequence representing address allocation after updating the address information to the next slave device, and forward the pulse sequence representing successful address reception uploaded by the next slave device to the master device, until the pulse sequence representing complete address allocation is forwarded to the master device, so that the master device ends the address allocation mode; the pulse sequence representing complete address allocation is the pulse sequence generated by the tail slave device after determining that it meets the preset tail device conditions.

8. A communication device address allocation apparatus, characterized in that, A tail slave device among at least two slave devices used in a backplane communication system to establish a line connection with a host device; wherein the host device and the at least two slave devices are both connected to differential signal lines for data interaction, and the at least two slave devices are sequentially connected via status signal lines, and the host device establishes a line connection with the first slave device via the status signal lines; the device includes: The second level state recognition module is used to enter the address allocation mode when it recognizes that the differential signal line is set to the level state corresponding to the address allocation mode by the host device; The first pulse sequence uploading module is used to obtain the pulse sequence representing address allocation sent by the previous slave device through the status signal line and extract the address information, and then upload the pulse sequence representing address reception success to the previous slave device through the status signal line, so that the first slave device forwards the corresponding pulse sequence representing address reception success to the host device; The second pulse sequence uploading module is used to generate a pulse sequence indicating that the address allocation is complete after determining that it meets the preset tail device conditions, and upload the pulse sequence indicating that the address allocation is complete to the previous slave device, so that the first slave device forwards the pulse sequence indicating that the address allocation is complete to the master device, thereby causing the master device to end the address allocation mode.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the communication device address allocation method as described in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, Used to store computer programs, which, when executed by a processor, implement the communication device address allocation method as described in any one of claims 1 to 5.

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