Circuit board layout method and apparatus, electronic device, and storage medium

Abstract

This application relates to a circuit board layout method, apparatus, electronic device, and storage medium. The method, using a trained routing continuity detection model, can quickly detect whether the devices to be laid out corresponding to the first layout data can be routed. Based on first routing feedback information and an objective function, the first layout data is adjusted to obtain second layout data. Since the actual routing effect is considered, the routing continuity rate of the devices to be laid out corresponding to the second layout data can be improved. Routing and adjusting the second layout data continues until the routing between all devices to be laid out is complete, obtaining the target layout data. This automatic adjustment of the layout data, without manual intervention, improves the efficiency of circuit board layout.

Description

Technical Field

[0001] This invention relates to the field of circuit board layout design technology, and in particular to a circuit board layout method, apparatus, electronic device, and storage medium. Background Technology

[0002] A printed circuit board (PCB) is the support structure for electronic components and the carrier for the electrical interconnection of electronic components.

[0003] Currently, circuit board layout is mainly done manually. Specifically, based on the circuit schematic, engineers use layout design software to determine the appropriate placement and rotation angle for each component within a specified layout area.

[0004] However, with the increase in circuit board integration and the size of components, the manual circuit board layout process is time-consuming and results in low circuit board layout efficiency. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a circuit board layout method, apparatus, electronic device, and storage medium, which have the advantage of improving circuit board layout efficiency.

[0006] According to a first aspect of the embodiments of this application, a circuit board layout method is provided, comprising the following steps:

[0007] Obtain the information of the circuit to be laid out; the information of the circuit to be laid out includes several devices to be laid out and device information of the devices to be laid out;

[0008] Based on the circuit information to be laid out, several devices to be laid out are laid out to obtain the first layout data;

[0009] The first layout data is input into the trained wiring continuity detection model to obtain the wiring continuity detection result;

[0010] When the routing continuity test result indicates that the routing of the device to be laid out corresponding to the first layout data is not continuous, the preset routing constraints are obtained. According to the preset routing constraints, the routing of the device to be laid out corresponding to the first layout data is performed to obtain the first routing data. The first routing data includes the first routing feedback information. The first routing feedback information includes the device information of the non-routable loop and the reserved hole position information of the non-routable loop.

[0011] Based on the device information of non-routeable loops, the reserved hole location information of non-routeable loops, and the objective function, the first layout data is adjusted to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pins and the similarity of the loop device layout positions.

[0012] Routing is performed on the devices to be laid out corresponding to the second layout data to obtain the second routing data; the second routing data includes routing information and second routing feedback information.

[0013] When the routing information indicates that the routing of the device to be laid out corresponding to the second layout data is not routing, the second layout data is adjusted according to the second routing feedback information and the objective function until the routing between the devices to be laid out is completed, and the target layout data is obtained.

[0014] Based on the target layout data, several devices to be laid out are laid out.

[0015] Obtain the information of the circuit to be laid out; the information of the circuit to be laid out includes several devices to be laid out and device information of the devices to be laid out;

[0016] Based on the circuit information to be laid out, several devices to be laid out are laid out to obtain the first layout data;

[0017] The first layout data is input into the trained wiring continuity detection model to obtain the wiring continuity detection result;

[0018] When the routing continuity test result indicates that the routing of the device to be laid out corresponding to the first layout data is not continuous, the preset routing constraints are obtained. According to the preset routing constraints, the routing of the device to be laid out corresponding to the first layout data is performed to obtain the first routing data. The first routing data includes the first routing feedback information. The first routing feedback information includes the device information of the non-routable loop and the reserved hole position information of the non-routable loop.

[0019] Based on the device information of non-routeable loops, the reserved hole location information of non-routeable loops, and the objective function, the first layout data is adjusted to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pins and the similarity of the loop device layout positions.

[0020] Routing is performed on the devices to be laid out corresponding to the second layout data to obtain the second routing data; the second routing data includes routing information and second routing feedback information.

[0021] When the routing information indicates that the routing of the device to be laid out corresponding to the second layout data is not routing, the second layout data is adjusted according to the second routing feedback information and the objective function until the routing between the devices to be laid out is completed, and the target layout data is obtained.

[0022] Based on the target layout data, several devices to be laid out are laid out.

[0023] According to a second aspect of the embodiments of this application, a circuit board layout apparatus is provided, comprising:

[0024] The circuit information acquisition module is used to acquire the circuit information to be laid out; the circuit information to be laid out includes several devices to be laid out and device information of the devices to be laid out.

[0025] The first layout data acquisition module is used to lay out several devices to be laid out according to the information of the circuit to be laid out, and to obtain the first layout data.

[0026] The wiring continuity detection result acquisition module is used to input the first layout data into the trained wiring continuity detection model to obtain the wiring continuity detection result;

[0027] The first wiring data acquisition module is used to acquire preset wiring constraints when the wiring continuity test result indicates that the wiring of the device to be laid out corresponding to the first layout data is not continuous, and to perform wiring on the device to be laid out corresponding to the first layout data according to the preset wiring constraints to obtain the first wiring data; wherein, the first wiring data includes first wiring feedback information; the first wiring feedback information includes device information of the non-continuous loop and reserved hole position information of the non-continuous loop.

[0028] The second layout data acquisition module is used to adjust the first layout data based on the device information of the non-routeable loop, the reserved hole position information of the non-routeable loop, and the objective function to obtain the second layout data; wherein, the objective function is determined based on the half perimeter of the loop pin and the similarity of the layout positions of the loop devices.

[0029] The second wiring data acquisition module is used to perform wiring on the device to be laid out corresponding to the second layout data to obtain the second wiring data; the second wiring data includes wiring information and second wiring feedback information.

[0030] The target layout data acquisition module is used to adjust the second layout data according to the second wiring feedback information and the target function when the wiring connection information indicates that the wiring of the device to be laid out corresponding to the second layout data is not connected, until the wiring between the devices to be laid out is connected, and thus obtain the target layout data.

[0031] The device placement module is used to place several devices to be placed based on the target placement data.

[0032] According to a third aspect of the embodiments of this application, an electronic device is provided, including: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed as a circuit board layout method as described above.

[0033] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the circuit board layout method as described in any of the above claims.

[0034] This application embodiment utilizes a trained routing continuity detection model to quickly determine whether the devices to be laid out corresponding to the first layout data can be routed. Based on the first routing feedback information and the objective function, the first layout data is adjusted to obtain second layout data. Since the actual routing effect is considered, the routing continuity rate of the devices to be laid out corresponding to the second layout data can be improved. Routing and adjusting the second layout data continues until the routing between all devices to be laid out is complete, obtaining the target layout data. This automatic adjustment of the layout data, without manual intervention, improves the efficiency of circuit board layout.

[0035] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application.

[0036] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0037] Figure 1 A schematic flowchart illustrating a circuit board layout method provided in one embodiment of this application;

[0038] Figure 2 This is a structural block diagram of a circuit board layout apparatus provided in one embodiment of this application;

[0039] Figure 3 This is a schematic block diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0041] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0042] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0043] In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0044] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In the process of realizing this invention, the inventors discovered that the current circuit board layout is mainly done manually. In the actual layout process, as the number of PCB modules to be laid out increases, due to the different specifications and quantities of components in each PCB module, the layout problem in irregular areas will be faced in the middle and later stages of the layout. It is necessary to lay out in the remaining space, and manual adjustment of the layout result is required multiple times to determine whether the wiring can be routed. The whole process is time-consuming and inefficient.

[0046] To address this, this application utilizes a trained routing continuity detection model to automatically detect whether a layout result is routeable. When a layout result is not routeable, routing is performed on the corresponding device to be placed, and routing feedback information is obtained. Based on this feedback information, the layout result is adjusted. Since the actual routing effect is taken into account, the routing continuity rate of the adjusted layout result can be improved. This eliminates the need for multiple manual adjustments, automatically adjusting the layout result and improving the efficiency of circuit board layout.

[0047] Please see Figure 1This is a flowchart illustrating a circuit board layout method provided in one embodiment of this application. This application provides a circuit board layout method, including the following steps:

[0048] S10: Obtain the circuit information to be laid out; the circuit information to be laid out includes several devices to be laid out and device information of the devices to be laid out;

[0049] The circuit board layout method of this application is implemented by a circuit board layout device, which includes, but is not limited to, computers, tablets, and mobile phones.

[0050] The circuit information to be laid out includes the area information of the PCB module to be laid out and the device information of the device to be laid out.

[0051] The area information of the PCB module to be laid out includes the border diagram of the PCB module to be laid out, which is used to display the boundary information of the PCB module. The area within the PCB border diagram can be used as the layout area of ​​the components. The unit specification for component layout is 1 mil, which is the smallest unit of PCB layout.

[0052] The device information for the device to be placed includes, but is not limited to, the name of the device, the size of the device, the area of ​​the device, the pin information of the device, the pad coordinates of the device, and the pad specifications of the device. The pin information includes, but is not limited to, the pin coordinates, the pin size, the pin number, and the pin net name.

[0053] The devices to be laid out include, but are limited to, resistors, inductors, capacitors, diodes, transistors, switches, and connectors.

[0054] In this context, the pin net name refers to the name of the net to which a pin in a device is connected. Two pins with the same net name are located on the same net, and pins within the same net are connected to each other. Generally, pin net names are represented by uppercase English letters A, B, C, ...

[0055] In this embodiment, the system can receive a PCB outline file and a circuit schematic corresponding to the PCB module to be laid out, input by the user. Specifically, the user can import the PCB outline file through PCB layout software. After receiving the imported PCB outline file, the system can obtain the area information of the PCB module to be laid out based on the length and width of the outline image contained in the PCB outline file. The area information includes the length, width, and area of ​​the PCB module to be laid out. Simultaneously, a coordinate graph is created using the length of the outline image as the X-axis range and the width of the outline image as the Y-axis range, serving as the available space for component placement. The user can also import the circuit schematic in JSON file format through the PCB layout software. After receiving the imported circuit schematic, the system can extract the component information of each component to be laid out in the PCB module from the circuit schematic.

[0056] S20: Based on the information of the circuit to be laid out, lay out several devices to be laid out to obtain the first layout data.

[0057] The first layout data includes the layout position and rotation angle of each device to be laid out.

[0058] In this embodiment, based on the information of the circuit to be laid out, a layout algorithm can be used to lay out several devices to be laid out, thereby obtaining the layout position and rotation angle of each device. The layout algorithm includes, but is not limited to, heuristic algorithms based on greedy strategies and algorithms based on NSGA-II.

[0059] S30: Input the first layout data into the trained wiring continuity detection model to obtain the wiring continuity detection result.

[0060] The cabling continuity test results are classified into two categories: cabling can be routed and cabling cannot be routed.

[0061] In this embodiment, a trained routing continuity detection model is used to detect whether routing between devices is possible after device placement on a circuit board. Specifically, the first placement data is input into the trained routing continuity detection model, which outputs whether routing is possible or not.

[0062] S40: When the routing continuity test result indicates that the routing of the device to be laid out corresponding to the first layout data is not continuous, obtain the preset routing constraints, and according to the preset routing constraints, perform routing on the device to be laid out corresponding to the first layout data to obtain the first routing data; wherein, the first routing data includes the first routing feedback information; the first routing feedback information includes the device information of the non-routable loop and the reserved hole position information of the non-routable loop.

[0063] The preset routing constraints include hard routing constraints and soft routing constraints. Hard routing constraints include that the traces cannot touch the pads of other components' circuits, the traces cannot touch other components' circuits, and the traces cannot touch vias. Soft routing constraints include that the traces should be close to the components, and each circuit should be routed as smoothly as possible, minimizing corners.

[0064] The first wiring data includes wiring results and first wiring feedback information. Wiring results refer to whether the wiring between devices in each device loop is continuous; device loops include routable loops and non-routable loops. The first wiring feedback information includes the wiring length and number of vias for routable loops, as well as relevant data regarding the reasons why wiring for non-routable loops could not be completed.

[0065] Specifically, the reasons why unrouteable loops cannot be routed include unreasonable device loop layout, lack of space for via routing within the device loop, and insufficient routing space within the device loop. For unreasonable device loop layout, the feedback data indicates the device information for unrouteable loops. For lack of space for via routing within the device loop, the feedback data indicates the reserved via locations for unrouteable loops. For insufficient routing space within the device loop, the feedback data indicates the routing extension area that, based on the loop's location, minimizes the local routing area to allow for routing.

[0066] In this embodiment, based on preset routing constraints, a routing algorithm is used to route the devices corresponding to the first layout data to obtain the first routing data. The routing algorithm includes the path planning A* algorithm and the path planning JPS algorithm.

[0067] S50: Based on the device information of the non-routeable loop, the reserved hole position information of the non-routeable loop, and the objective function, adjust the first layout data to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pin and the similarity of the layout positions of the loop devices.

[0068] The half-circumference of a loop pin refers to the sum of the differences between the x and y coordinates of the two farthest devices in the loop. The similarity of the loop device layout positions refers to the difference in distance between the device layout positions before and after loop adjustment.

[0069] In this embodiment, a secondary layout of devices in non-routeable loops is performed. Specifically, based on the reserved hole location information of the non-routeable loop, the constraints for the secondary layout of devices in the non-routeable loop are obtained. Under the premise of satisfying the constraints, the layout positions of devices in the non-routeable loop are adjusted. Based on the adjusted layout positions and the objective function, the objective function value is calculated. With the goal of minimizing the objective function value, the final layout positions of devices in the non-routeable loop are obtained.

[0070] S60: Routing is performed on the device to be laid out corresponding to the second layout data to obtain the second wiring data; the second wiring data includes wiring information and second wiring feedback information.

[0071] The second wiring data includes wiring continuity information and second wiring feedback information. Wiring continuity information refers to whether the wiring between the devices to be laid out in each device loop is continuous. The second wiring feedback information includes the wiring length and number of vias for continuous loops, as well as relevant data on the reasons why wiring for non-continuous loops cannot be completed.

[0072] In this embodiment of the application, a routing algorithm is used to route the devices corresponding to the second layout data to obtain the second routing data.

[0073] S70: When the routing information indicates that the routing of the device to be laid out corresponding to the second layout data is not routing, the second layout data is adjusted according to the second routing feedback information and the objective function until the routing between the devices to be laid out is completed, and the target layout data is obtained.

[0074] The target layout data includes the target layout position and target rotation angle of each device to be laid out.

[0075] In this embodiment, if the wiring of the device to be laid out is still not continuous after the second layout, the device information of the non-continuous loop and the reserved hole position information of the non-continuous loop are determined from the second wiring feedback information. Based on the device information of the non-continuous loop, the reserved hole position information of the non-continuous loop, and the objective function, the second layout data is adjusted. The adjustment process of the second layout data is the same as the adjustment process of the first layout data, and can be referred to step S50, which will not be repeated here. Steps S50 to S70 are repeated until the wiring between each device to be laid out is continuous, and the layout data at the time of continuous wiring is used as the target layout data.

[0076] S80: Based on the target layout data, lay out several devices to be laid out.

[0077] In this embodiment of the application, after determining the target layout data, each device to be laid out is placed in the corresponding target layout position, and the rotation angle of each device to be laid out is set to the corresponding target rotation angle.

[0078] By applying the embodiments of this application, a trained routing continuity detection model can quickly detect whether the devices corresponding to the first layout data can be routed. Using the first routing feedback information and the objective function, the first layout data is adjusted to obtain the second layout data. Since the actual routing effect is considered, the routing continuity rate of the devices corresponding to the second layout data can be improved. Routing and adjusting the second layout data continues until the routing between all devices to be laid out is complete, obtaining the target layout data. No manual adjustment is required; the layout data is automatically adjusted, improving the efficiency of circuit board layout.

[0079] In one embodiment, step S20 includes steps S21 to S23, as follows:

[0080] S21: Based on the device information, determine the device circuit and the device layout order of the device circuit; wherein, the device circuit includes multiple devices to be laid out with pins located on the same network, and the device layout order indicates the layout order of the devices to be laid out.

[0081] In this embodiment, the device loop to which the device to be laid out belongs can be determined based on the pin net names of the devices to be laid out. Specifically, one device is designated as the core device from among multiple devices to be laid out. The core device can be the device with the most pins or the device with the most device connections. The pin net names of the devices to be laid out other than the core device are matched with the pin net names of the core device, and devices to be laid out with the same pin net names are assigned to the same device loop. Each device to be laid out in the same device loop has multiple pins, and the pin with the same pin net name as the core device is only one of them. The pin net names of the remaining pins in the devices to be laid out are matched with the pin net names of other devices to be laid out, and devices to be laid out with the same pin net names are assigned to the same device loop.

[0082] The device placement order in a device circuit can be determined based on the capacitance values ​​of the devices to be placed. Specifically, devices with smaller capacitance values ​​and priority placement are placed first, while devices with larger capacitance values ​​and later placement are placed last.

[0083] S22: Obtain the layout constraints of the device circuits.

[0084] In the embodiments of this application, the layout constraints of the device circuits are that the devices to be laid out in the device circuits cannot overlap, the distance between the devices to be laid out must be greater than or equal to the safe distance, and the layout position of the devices to be laid out must be within the layout area of ​​the circuit board.

[0085] S23: Based on the layout constraints and the device layout order of the device loop, the device to be laid out in the loop is laid out using a preset device layout algorithm to obtain the first layout data.

[0086] The preset device placement algorithms include, but are not limited to, heuristic algorithms based on greedy strategies and algorithms based on NSGA-II.

[0087] In this embodiment of the application, a heuristic algorithm based on a greedy strategy is used to place the devices to be placed in the device loop one by one according to the device layout order until all the devices to be placed in all device loops are placed, thereby obtaining the first layout data.

[0088] The heuristic algorithm based on a greedy strategy in this embodiment lays out the devices to be laid out according to the layout constraints and the device layout order of the device circuit, which can make the circuit board layout compact and beautiful.

[0089] In one embodiment, before step S30, the following steps are included:

[0090] S31: Obtain the layout sample dataset; the layout sample dataset includes layout data of multiple circuit boards and device routing label information.

[0091] The device routing label information includes two status labels: device routing is accessible and device routing is not accessible.

[0092] In this application embodiment, when constructing the layout sample dataset, historical layout data of the circuit board, layout data solved by various layout algorithms, and layout data obtained in this application embodiment can be collected.

[0093] S32: Based on the layout data of each circuit board and the device routing label information, determine the graph structure and the graph label information of the graph structure; where the nodes of the graph structure are device pins, and the edges of the graph structure are the connection relationships between the pins of the same network devices.

[0094] A graph structure is a mathematical abstraction used to describe a set of objects (nodes) and the connections between them (edges). In circuit component placement, a graph structure can be used to represent the various components (nodes) in a circuit and the electrical connections between them (edges). The graph label information of the graph structure corresponds one-to-one with the component routing label information. Specifically, the component routing label information can be used as the graph label information of the graph structure.

[0095] In this embodiment of the application, the graph structure is composed of nodes with object features and edges representing the relationships between nodes. The object features of the nodes are pin coordinates and pin length and width, and the edges are the connection relationships between the same network pins.

[0096] S33: Based on the graph structure and the graph label information of the graph structure, train the wiring and routing detection model to obtain the trained wiring and routing detection model.

[0097] The wiring continuity detection model includes, but is not limited to, machine learning models and deep learning neural network modules.

[0098] In this embodiment of the application, the wiring continuity detection model is trained by using the graph structure as the input and the graph label information of the graph structure as the output, thereby obtaining the trained wiring continuity detection model.

[0099] This application embodiment converts the layout data of the circuit board into graph structure data, and trains the wiring continuity detection model using the graph structure data, which can improve the robustness and stability of the trained wiring continuity detection model.

[0100] In one embodiment, step S40, which involves routing the devices corresponding to the first layout data according to preset routing constraints to obtain the first routing data, includes steps S41 to S42, as follows:

[0101] S41: Based on the device information, determine the device loop and the device routing sequence of the device loop; wherein, the device loop includes multiple devices to be laid out with pins located on the same network, and the device routing sequence indicates the routing order of the devices to be laid out.

[0102] In this embodiment of the application, the process of determining the device circuit based on the device information is the same as step S21, and will not be repeated here.

[0103] The routing order of devices in a device loop can be determined based on the area of ​​the devices to be placed. Specifically, smaller devices are routed first, and larger devices are routed last.

[0104] S42: Based on the preset wiring constraints and the device wiring sequence of the device circuit, the preset wiring path planning algorithm is used to wire the devices to be laid out in the device circuit to obtain the first wiring data.

[0105] The preset routing path planning algorithms include, but are not limited to, the A* algorithm and the JPS algorithm.

[0106] In this embodiment, based on the path planning A* algorithm, the devices to be placed in the device loop are routed one by one according to the device routing order until all devices to be placed in all device loops are routed to obtain the first routing data.

[0107] This application embodiment is based on the path planning A* algorithm. It routes the devices to be laid out according to the preset routing constraints and the routing order of the device loops, and can automatically and quickly obtain the first routing data.

[0108] In one embodiment, step S50 includes steps S51 to S55, as follows:

[0109] S51: Determine decision variables based on the information of non-routeable loop devices; wherein, the decision variables include the layout position and rotation angle of the devices in the non-routeable loop.

[0110] In this embodiment, each device in the non-connectable loop is redefined as a device to be laid out, and the layout position and rotation angle of the device to be laid out are used as decision variables.

[0111] S52: Based on the reserved hole location information of the non-routeable loop, determine the first constraint condition that the decision variable needs to satisfy; the first constraint condition includes that the location of the device to be laid out does not overlap with the location of the reserved hole.

[0112] The reserved hole location information refers to the locations where holes are planned. The circuit board consists of two layers; when routing cannot be completed on one layer, holes can be drilled to allow traces to pass through them.

[0113] In this embodiment of the application, the reserved hole position of the non-connectable circuit is set as the position where the device to be laid out is prohibited.

[0114] S53: Obtain the second constraint conditions that the decision variables need to satisfy; the second constraint conditions include the no-distribution area constraint conditions, the device interference prohibition constraint conditions, and the device placement location constraint conditions.

[0115] In this embodiment, the "no-layout" constraint means that the device to be laid out cannot overlap with the no-layout area. The expression for the no-layout constraint is as follows:

[0116] lx i +hw i +gap z <=x z , z∈Z

[0117] lx i -hw i -gap z >=x z, z∈Z

[0118] ly i +hh i +gap z <=y z , z∈Z

[0119] ly i -hh i -gap z >=y z z∈Z

[0120] Among them, lx i ly represents the x-coordinate of the device i to be laid out. i The vertical coordinate of the device i to be laid out is represented by hw. i hh represents half the width of the device i to be laid out. i This represents half the height of the device i to be laid out, gap. z Let z represent the range of the forbidden region z, z represent the forbidden region z, and Z represent the total set of forbidden regions. At least one of the above four forbidden region constraints must be satisfied in the x-direction or y-direction.

[0121] The device interference prohibition constraint means that the device to be placed cannot interfere with other devices. The expression for the device interference prohibition constraint is as follows:

[0122] lx i +hw i +hw j +gap safe <=x j , i, j∈C

[0123] lx i -hw i -hw j -gap safe >=x j , i,j∈C

[0124] ly i +hh i +hh j +gap safe <=y j ,i,j∈C

[0125] ly i -hh i -hh i -gap safe >=y j , i,j∈C

[0126] Among them, hw j hh represents half the width of the device j to be laid out.j This represents half the height of the device j to be laid out, gap safe x represents the safe distance between device i and device j. j The x-coordinate of the device j to be laid out is represented by the y-coordinate. j Let J represent the ordinate of the device j to be laid out, and C represent the total set of devices to be laid out. At least one of the above four device interference prohibition constraints must be satisfied in the x or y direction.

[0127] The device placement constraint refers to the requirement that the placement range of the device to be placed is within a preset distance of the target device. The target device can be a specified subset of devices. The expression for the device placement constraint is as follows:

[0128] lx i +hw i +gap i <=x t i∈C,t∈T c

[0129] lx i -hw i -gap i >=x t , i∈C, t∈T c

[0130] ly i +hh i +gap i <=y t , i∈C, t∈T c

[0131] ly i -hh i -gap i >=y t , i∈C, t∈T c

[0132] Among them, gap i x represents the preset distance between the layout range of device i to be laid out and the target device t. t The x-coordinate of the target device t is represented by y. t T represents the ordinate of the target device t. c This represents the total set of target devices.

[0133] S54: Minimize the objective function based on the first and second constraints to obtain the objective decision variables.

[0134] In this embodiment, the objective function is a weighted sum of the half-circumference of the loop pin and the similarity of the loop devices. Specifically, the expression of the objective function is as follows:

[0135]

[0136] simility=∑ c∈l dist c_new -dist c_ori

[0137] Where α represents the first weighting coefficient, β represents the second weighting coefficient, HWPL represents the half-circumference of the loop pin, simility represents the similarity of the loop devices, and dist c_new Dist represents the distance between various components in the adjusted circuit. c_ori This indicates the distance between the various components in the circuit before adjustment.

[0138] S55: Based on the target decision variables, rearrange the devices in the non-connectable loops to update the first layout data and obtain the second layout data.

[0139] Among them, the target decision variables include the target placement position of the device in the non-circuitous loop and the target rotation angle.

[0140] In this embodiment of the application, after obtaining the target decision variables, the devices in the non-routeable loops are placed to the corresponding target layout positions, and the rotation angle of the devices in the non-routeable loops is set to the corresponding target rotation angle to obtain the second layout data.

[0141] Based on the first wiring feedback information and the objective function, the embodiments of this application rearrange the devices that cannot be routed through loops, so that the algorithm takes into account the actual wiring effect when solving the second layout data, which can improve the routing completion rate of the devices corresponding to the second layout data.

[0142] In one embodiment, the first wiring feedback information includes wiring area expansion information. Step S60 includes the following steps:

[0143] S61: Update the preset wiring constraints based on the wiring area expansion information to obtain the updated wiring constraints.

[0144] Among them, the wiring area expansion information refers to the wiring expansion area that is expanded to the minimum extent possible based on the location of the loop when there is not enough wiring space, so that the wiring can be laid out.

[0145] In this embodiment, the wiring extension area is used as the wiring available area. Preset wiring constraints limit some wiring restricted areas. If the restricted area overlaps with the wiring extension area, the overlapping part of the restricted area is updated to the wiring available area.

[0146] S62: Based on the updated routing constraints, route the devices corresponding to the second layout data to obtain the second routing data.

[0147] In this embodiment of the application, after obtaining the second layout data, when routing the device corresponding to the second layout data, the updated routing constraints are used as constraints for the routing algorithm to obtain the second routing data.

[0148] The embodiments of this application use the wiring area expansion information in the first wiring feedback information to guide the wiring algorithm to perform wiring, so that the wiring algorithm takes into account the actual wiring effect and can improve the wiring completion rate.

[0149] The following are embodiments of the apparatus described in this application, which can be used to execute the methods described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the methods described in the embodiments of this application.

[0150] Please see Figure 2 This diagram illustrates the structure of a circuit board layout apparatus provided in an embodiment of this application. The circuit board layout apparatus 9 provided in this embodiment includes:

[0151] The circuit information acquisition module 91 is used to acquire the circuit information to be laid out; the circuit information to be laid out includes several devices to be laid out and device information of the devices to be laid out.

[0152] The first layout data acquisition module 92 is used to lay out a number of devices to be laid out according to the information of the circuit to be laid out, and to obtain the first layout data.

[0153] The wiring continuity detection result acquisition module 93 is used to input the first layout data into the trained wiring continuity detection model to obtain the wiring continuity detection result;

[0154] The first wiring data acquisition module 94 is used to acquire preset wiring constraints when the wiring continuity detection result indicates that the wiring of the device to be laid out corresponding to the first layout data is not continuous, and to perform wiring on the device to be laid out corresponding to the first layout data according to the preset wiring constraints to obtain the first wiring data; wherein, the first wiring data includes first wiring feedback information; the first wiring feedback information includes device information of the non-continuous loop and reserved hole position information of the non-continuous loop.

[0155] The second layout data acquisition module 95 is used to adjust the first layout data based on the device information of the non-routeable loop, the reserved hole position information of the non-routeable loop, and the objective function to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pin and the similarity of the layout positions of the loop devices.

[0156] The second wiring data acquisition module 96 is used to perform wiring on the device to be laid out corresponding to the second layout data to obtain the second wiring data; the second wiring data includes wiring information and second wiring feedback information.

[0157] The target layout data acquisition module 97 is used to adjust the second layout data according to the second wiring feedback information and the target function when the wiring connection information indicates that the wiring of the device to be laid out corresponding to the second layout data is not connected, until the wiring between the devices to be laid out is connected, and thus obtain the target layout data.

[0158] The device placement module 98 is used to place several devices to be placed according to the target placement data.

[0159] By applying the embodiments of this application, a trained routing continuity detection model can quickly detect whether the devices to be laid out corresponding to the first layout data can be routed. Based on the first routing feedback information and the objective function, the first layout data is adjusted to obtain the second layout data. Since the actual routing effect is considered, the routing continuity rate of the devices to be laid out corresponding to the second layout data can be improved. Routing and adjusting the second layout data continues until the routing between all devices to be laid out is complete, obtaining the target layout data. No manual adjustment is required; the layout data is automatically adjusted, improving the efficiency of circuit board layout.

[0160] The following are embodiments of the device described in this application, which can be used to execute the methods described in the embodiments of this application. For details not disclosed in the embodiments of the device described in this application, please refer to the methods described in the embodiments of this application.

[0161] Please see Figure 3 This application also provides an electronic device 300, which may specifically be a computer, mobile phone, tablet computer, circuit board layout device, etc. In an exemplary embodiment of this application, the electronic device 300 is a circuit board layout device, which may include: at least one processor 301, at least one memory 302, at least one display, at least one network interface 303, user interface 304, and at least one communication bus 305.

[0162] The user interface 304 is primarily used to provide an input interface for the user and to acquire user input data. Optionally, the user interface may also include a standard wired interface or a wireless interface.

[0163] The network interface 303 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0164] The communication bus 305 is used to enable communication between these components.

[0165] The processor 301 may include one or more processing cores. The processor connects to various parts of the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory, and by calling data stored in memory. Optionally, the processor may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor.

[0166] The memory 302 may include random access memory (RAM) or read-only memory. Optionally, the memory may include a non-transitory computer-readable storage medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data involved in the various method embodiments described above, etc. The memory may also optionally be at least one storage device located remotely from the aforementioned processor. Figure 3 As shown, a memory, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and operating applications.

[0167] The processor can be used to call the application program of the circuit board layout method stored in the memory and specifically execute the method steps of the above-described embodiments. For the specific execution process, please refer to the detailed description shown in the embodiments, which will not be repeated here.

[0168] This application also provides a computer-readable storage medium storing a computer program thereon, the instructions of which are adapted to be loaded by a processor and executed by the method steps of the embodiments shown above. For details of the execution process, please refer to the specific descriptions shown in the embodiments, which will not be repeated here. The device containing the storage medium can be an electronic device such as a personal computer, laptop computer, smartphone, or tablet computer.

[0169] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative, wherein the components described as separate parts may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0170] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0171] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function selected in one or more boxes.

[0172] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function selected in one or more boxes.

[0173] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0174] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0175] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape storage, disk storage, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0176] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0177] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A circuit board layout method, characterized in that, The method includes the following steps: Obtain information about the circuit to be laid out; the information about the circuit to be laid out includes several devices to be laid out and device information of the devices to be laid out; Based on the circuit information to be laid out, a plurality of devices to be laid out are laid out to obtain first layout data; The first layout data is input into the trained wiring continuity detection model to obtain the wiring continuity detection result; When the wiring continuity test result indicates that the wiring of the device to be laid out corresponding to the first layout data is not continuous, a preset wiring constraint is obtained, and the device to be laid out corresponding to the first layout data is wired according to the preset wiring constraint to obtain the first wiring data; wherein, the first wiring data includes the first wiring feedback information; the first wiring feedback information includes the device information of the non-continuous loop and the reserved hole position information of the non-continuous loop. Based on the device information of the non-routeable loop, the reserved hole position information of the non-routeable loop, and the objective function, the first layout data is adjusted to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pin and the similarity of the loop device layout positions. Routing is performed on the device to be laid out corresponding to the second layout data to obtain second routing data; the second routing data includes routing information and second routing feedback information. When the routing information indicates that the routing of the device to be laid out corresponding to the second layout data is not routing, the second layout data is adjusted according to the second routing feedback information and the target function until the routing between the devices to be laid out is completed, and the target layout data is obtained. Based on the target layout data, a plurality of the devices to be laid out are laid out.

2. The circuit board layout method according to claim 1, characterized in that: The step of adjusting the first layout data based on the device information of the non-routeable loop, the reserved hole location information of the non-routeable loop, and the objective function to obtain the second layout data includes: Based on the information of the non-routeable loop device, decision variables are determined; wherein, the decision variables include the coordinates and rotation angles of the devices in the non-routeable loop; Based on the reserved hole location information of the non-connectable loop, determine the first constraint condition that the decision variable needs to satisfy; the first constraint condition includes that the location of the device to be laid out does not overlap with the location of the reserved hole. The decision variables need to satisfy a second constraint condition; the second constraint condition includes a no-distribution area constraint condition, a device interference prohibition constraint condition, and a device placement position constraint condition. Based on the first and second constraints, minimize the objective function to obtain the objective decision variables; Based on the target decision variables, the devices in the non-connectable loop are rearranged to update the first layout data and obtain the second layout data.

3. The circuit board layout method according to claim 1, characterized in that: The step of laying out a plurality of devices to be laid out according to the circuit information to obtain first layout data includes: Based on the device information, determine the device circuit and the device layout order of the device circuit; wherein, the device circuit includes multiple devices to be laid out with pins located in the same network, and the device layout order indicates the layout order of the devices to be laid out; Obtain the layout constraints of the device circuitry; Based on the layout constraints and the device layout order of the device circuit, the devices to be laid out in the device circuit are laid out using a preset device layout algorithm to obtain the first layout data.

4. The circuit board layout method according to claim 1, characterized in that: The step of routing the devices corresponding to the first layout data according to the preset routing constraints to obtain the first routing data includes: Based on the device information, determine the device circuit and the device routing order of the device circuit; wherein, the device circuit includes multiple devices to be laid out with pins located on the same network, and the device routing order indicates the routing sequence of the devices to be laid out; Based on the preset wiring constraints and the device wiring sequence of the device circuit, the device to be laid out in the device circuit is wired using a preset wiring path planning algorithm to obtain the first wiring data.

5. The circuit board layout method according to claim 1, characterized in that: The first wiring feedback information includes wiring area expansion information; The step of routing the devices corresponding to the second layout data to obtain the second routing data includes: Based on the wiring area expansion information, the preset wiring constraints are updated to obtain the updated wiring constraints. Based on the updated wiring constraints, the devices corresponding to the second layout data are wired to obtain the second wiring data.

6. The circuit board layout method according to any one of claims 1 to 5, characterized in that: Before the step of inputting the first layout data into the trained wiring continuity detection model to obtain the wiring continuity detection result, the following steps are included: Obtain a layout sample dataset; the layout sample dataset includes layout data of multiple circuit boards and device routing label information; Based on the layout data of each circuit board and the device wiring label information, a graph structure and graph label information of the graph structure are determined; wherein, the nodes of the graph structure are device pins, and the edges of the graph structure are the connection relationships between the pins of the same network device. Based on the graph structure and the graph label information of the graph structure, the wiring continuity detection model is trained to obtain the trained wiring continuity detection model.

7. A circuit board layout device, characterized in that, include: A circuit to be laid out information acquisition module is used to acquire circuit to be laid out information; the circuit to be laid out information includes a number of devices to be laid out and device information of the devices to be laid out. The first layout data acquisition module is used to lay out a plurality of the devices to be laid out according to the circuit information to be laid out, and to obtain the first layout data; The wiring continuity detection result acquisition module is used to input the first layout data into the trained wiring continuity detection model to obtain the wiring continuity detection result; The first wiring data acquisition module is used to acquire preset wiring constraints when the wiring continuity detection result indicates that the wiring of the device to be laid out corresponding to the first layout data is not continuous, and to perform wiring on the device corresponding to the first layout data according to the preset wiring constraints to obtain first wiring data; wherein, the first wiring data includes first wiring feedback information; the first wiring feedback information includes device information of the non-continuous loop and the reserved hole position information of the non-continuous loop. The second layout data acquisition module is used to adjust the first layout data based on the device information of the non-routeable loop, the reserved hole position information of the non-routeable loop, and the objective function to obtain the second layout data; wherein, the objective function is determined based on the half-perimeter of the loop pin and the similarity of the layout positions of the loop devices. The second wiring data acquisition module is used to perform wiring on the device to be laid out corresponding to the second layout data to obtain the second wiring data; the second wiring data includes wiring completion information and second wiring feedback information. The target layout data acquisition module is used to adjust the second layout data according to the second wiring feedback information and the target function when the wiring connection information indicates that the wiring of the device to be laid out corresponding to the second layout data is not connected, until the wiring between the devices to be laid out is connected, and thus obtain the target layout data. The device layout module is used to lay out a plurality of devices to be laid out according to the target layout data.

8. An electronic device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the circuit board layout method as described in any one of claims 1 to 6.

Images