A printed circuit board design method, device, medium and computer program product

Abstract

The invention relates to the technical field of printed circuit board design, and specifically discloses a printed circuit board design method, device, medium and computer program product. The invention comprises the following steps: according to the target wiring resources, global wiring position and key line identification conditions in the task parameters of the received layout adjustment task of the target board, the key line identification conditions at least include line utilization, and the key physical line is identified; according to the current first position of the component and the position of the key physical line, the layout adjustment calculation is performed to obtain the second position of each component, and the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located; after the component layout on the target board is adjusted according to the second position, the wiring task is re-executed, so that the component layout is automatically adjusted to alleviate the line congestion after the wiring task fails, and the overall efficiency of the printed circuit board design is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board design, and in particular to a printed circuit board design method, equipment, medium and computer program product. Background Art

[0002] Printed Circuit Board (PCB) is used to carry various electronic components, so as to realize the circuit function. The design of printed circuit board is mainly divided into three stages: schematic design, component layout, and wiring. When the wiring fails, the engineer needs to adjust the layout of the components on the board, and then re-wire, repeating this process until the wiring is successful.

[0003] Manual adjustment of component layout is often empirical, a cumbersome process that may require repeated attempts to successfully complete the wiring process, which is time-consuming and labor-intensive, and reduces the efficiency of printed circuit board design.

[0004] How to improve the design efficiency of printed circuit boards is a technical problem that technical personnel in this field need to solve. Summary of the invention

[0005] The object of the present invention is to provide a printed circuit board design method, device, medium and computer program product for improving the design efficiency of the printed circuit board.

[0006] In order to solve the above technical problems, the present invention provides a printed circuit board design method, comprising:

[0007] Receive task parameters of the layout adjustment task of the target board;

[0008] Identify the key physical circuits on the target board according to the target wiring resources, global wiring positions and key circuit identification conditions in the task parameters;

[0009] Perform layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component;

[0010] Outputting the second position, so as to adjust the component layout on the target board according to the second position and then re-execute the wiring task;

[0011] Among them, the key line identification conditions at least include line utilization; the second position satisfies that the edge of the component does not exceed the edge of the target board and there is no overlap between the components; the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located.

[0012] On the one hand, according to the target wiring resources, global wiring position and key line identification conditions in the task parameters, the key physical lines on the target board are identified, including:

[0013] According to the target wiring resources, the global wiring position and the goal of minimizing the number of wire net removals, a wire net removal optimization calculation is performed to alleviate the congestion of the physical lines of the target board, and an optimal wire net removal is obtained;

[0014] The critical physical line is determined according to the physical line through which the preferred removal network passes.

[0015] On the other hand, according to the target wiring resources, global wiring positions and key line identification conditions in the task parameters, identifying the key physical lines on the target board includes:

[0016] Perform resource addition calculation for the physical lines of the target board according to the target wiring resources, the global wiring position and the goal of maximizing the congestion relief utility value, and obtain the congestion relief utility value after adding the physical line resources to each of the physical lines;

[0017] According to the order of the congestion relief utility values ​​of the physical lines from large to small, a first preset number of the physical lines are determined as the key physical lines.

[0018] On the other hand, according to the target wiring resources, the global wiring position and the goal of maximizing the congestion relief utility value, the resource increase calculation of the physical line of the target board is performed to obtain the congestion relief utility value after the physical line resources are increased for each of the physical lines, including:

[0019] Using a pre-trained prediction model, according to the target wiring resources, the global wiring position, and the wire nets of the target board design task of the target board, a congestion relief utility value after adding physical line resources to each edge of the wiring tree of each of the wire nets is calculated;

[0020] The congestion relief utility value of the physical line is determined according to the congestion relief utility values ​​of the edges of the routing tree passing through the physical line in the global routing position.

[0021] On the other hand, a pre-trained prediction model is used to calculate the congestion relief utility value after adding physical line resources to each edge of the wiring tree of each of the wire nets according to the target wiring resources, the global wiring position, and the wire nets of the target board design task, including:

[0022] The resource increase calculation problem of each physical line is constructed as a constraint relationship graph, wherein each node in the constraint relationship graph corresponds to a dual variable, the dual variable corresponds to the congestion relief utility value of one physical line, an edge between two nodes corresponds to the number of times the two dual variables appear in the same constraint condition, and the characteristics of the node are determined according to the line utilization corresponding to the dual variable;

[0023] Generate a column vector corresponding to the dual variable according to the constraint relationship graph using a graph convolutional network;

[0024] Calculate the score corresponding to the dual variable using the query vector and the column vector corresponding to the dual variable;

[0025] The congestion relief utility value corresponding to the edge of the wiring tree is calculated based on the score of the dual variable corresponding to the edge of the wiring tree and the score of the dual variable corresponding to all the edges of the wiring tree.

[0026] On the other hand, determining the congestion relief utility value of the physical line according to the congestion relief utility value of the edge of the routing tree passing through the physical line in the global routing position includes:

[0027] If there are multiple routing lines of the wiring tree on the physical line, the smallest congestion relief utility value among them is used as the congestion relief utility value of the physical line.

[0028] On the other hand, the training step of the prediction model includes:

[0029] Constructing a dual problem sample pool, wherein the dual problem sample pool includes a plurality of dual problem samples, and the dual problem samples are maximization optimization problems with given constraints;

[0030] Solving the dual problem sample using a linear programming solver, and using the obtained solution as a label of the dual problem sample;

[0031] The prediction model is used to solve the dual problem sample, a training error is calculated according to the obtained solution result and the label corresponding to the dual problem sample, and the model parameters of the prediction model are updated using the training error.

[0032] On the other hand, the step of generating the dual problem sample includes:

[0033] Randomly sampling a second preset number of sample dual variables and a third preset number of sample constraints;

[0034] Initializing the sample constraint of the dual problem sample to be empty, and adding the sample dual variable to the sample constraint with a first probability; the first probability is sampled from a conjugate prior distribution of a binomial distribution;

[0035] Calculate the cost coefficient corresponding to each sample dual variable;

[0036] The constraint conditions are that each of the sample dual variables is greater than or equal to 0, and the sum of the sample dual variables in the sample constraint conditions is less than or equal to 1, and the optimization goal is to minimize the weighted sum of each of the sample dual variables based on the cost coefficient, which is used as the dual problem sample.

[0037] On the other hand, the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located, including:

[0038] An overlap between the second position and a virtual barrier of a preset size added at the position of the critical physical line is smaller than an overlap between the first position and the virtual barrier.

[0039] On the other hand, performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component includes:

[0040] Initializing the size of the virtual obstacle;

[0041] Performing layout adjustment calculation on the position of the key physical circuit according to the size of the virtual barrier, the position of the virtual barrier and the first position to obtain the second position of each of the components;

[0042] After adjusting the position of the component on the target board according to the second position of each component, calling the wiring model to re-calculate the wiring, if the output global wiring position does not meet the wiring requirements, increasing the size of the virtual barrier, returning to perform layout adjustment calculation of the position of the key physical circuit according to the size of the virtual barrier, the position of the virtual barrier and the first position, to obtain the second position of each component;

[0043] If the sum of the total area of ​​each virtual barrier and the total area of ​​each component reaches the maximum area allowed by the target wiring resources of the target board, it is determined that the component layout adjustment fails, and a suggestion information for reducing the number of components is output.

[0044] On the other hand, performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component includes:

[0045] Taking the value of minimizing the component layout adjustment penalty function as the layout adjustment task goal, performing layout adjustment calculation according to the first position and the position of the key physical circuit to obtain the second position;

[0046] The device layout adjustment penalty function is positively correlated with the overlap between the second position and the virtual barrier, and the device layout adjustment penalty function is positively correlated with the change value of the second position compared with the first position.

[0047] On the other hand, the component layout adjustment penalty function is the sum of the layout adjustment constraint penalty value and the component layout change total value;

[0048] The layout adjustment constraint penalty value is the sum of the component elimination penalty value, the component overlap penalty value, and the component obstacle overlap penalty value;

[0049] Among them, the more the second position exceeds the target board, the greater the component elimination penalty value; the larger the overlapping area between the components, the greater the component overlap penalty value; the larger the overlapping area between the component and the virtual obstacle, the greater the component obstacle overlap penalty value; the total value of the component layout change is the sum of the distances between each second position and the corresponding first position.

[0050] In order to solve the above technical problems, the present invention also provides a printed circuit board design device, comprising:

[0051] Memory for storing computer programs;

[0052] A processor is used to execute the computer program, and when the computer program is executed by the processor, the steps of the printed circuit board design method as described in any one of the above items are implemented.

[0053] In order to solve the above technical problems, the present invention also provides a non-volatile storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the printed circuit board design method as described in any one of the above items are implemented.

[0054] In order to solve the above technical problems, the present invention also provides a computer program product, including a computer program, which implements the steps of any one of the above-mentioned printed circuit board design methods when executed by a processor.

[0055] The printed circuit board design method provided by the present invention has the beneficial effect of identifying the key physical circuits on the target board according to the target wiring resources, global wiring positions and key line identification conditions in the task parameters of the received layout adjustment task of the target board, wherein the key line identification conditions at least include line utilization; performing layout adjustment calculation according to the current first positions of the components on the target board and the positions of the key physical circuits to obtain the second positions of the components, and the overlap between the second positions and the area where the key physical circuits are located is less than the overlap between the first positions and the area where the key physical circuits are located, outputting the second positions, and re-executing the wiring task after adjusting the component layout on the target board according to the second positions, realizing automatic adjustment of the component layout to alleviate the line congestion after the wiring task fails, and being able to perform layout adjustment after wiring failure faster and more labor-saving than manual adjustment based on experience, thereby improving the overall efficiency of printed circuit board design.

[0056] The present invention also provides a printed circuit board design device, a medium and a computer program product, which have the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A schematic diagram of component layout information;

[0059] Figure 2 A schematic diagram of a wiring resource;

[0060] Figure 3 It is a schematic diagram of the structure of a wire network;

[0061] Figure 4 A flow chart of a printed circuit board design method provided by an embodiment of the present invention;

[0062] Figure 5 A schematic diagram of the structure of a printed circuit board design system provided by an embodiment of the present invention;

[0063] Figure 6 A schematic diagram of a dual problem and its constraint relationship provided by an embodiment of the present invention;

[0064] Figure 7 A schematic diagram of adding a virtual barrier at a location where a key physical line is located provided by an embodiment of the present invention;

[0065] Figure 8 A schematic diagram of inserting a virtual barrier on the surface layer for congestion in a through hole provided by an embodiment of the present invention;

[0066] Fig. 9 A schematic structural diagram of a printed circuit board design device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] The core of the present invention is to provide a printed circuit board design method, device, medium and computer program product for improving the design efficiency of the printed circuit board.

[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] To facilitate understanding of the technical solution provided by the embodiment of the present invention, some key terms used in the embodiment of the present invention are first explained here.

[0070] Printed Circuit Board (PCB) is used to carry various electronic components, so as to realize the circuit function. The design of printed circuit board is mainly divided into three stages: schematic design, component layout, and wiring.

[0071] Layout refers to the physical placement of circuit components during the design process of a printed circuit board. In some concepts, layout is defined as the entire process including component layout and wiring. In an embodiment of the present invention, layout is used as a definition of the installation position of components on a printed circuit board in the design process of a printed circuit board.

[0072] The netlist describes the electrical connections between components and parts on a printed circuit board. Wiring is based on the schematic and netlist and is performed on a board with a well-defined component layout.

[0073] After determining the schematic diagram and component layout, engineers will route the printed circuit board. The netlist generated based on the schematic diagram can determine the connection information of all components in the circuit to ensure that the electrical connection of the circuit is correctly implemented on the printed circuit board.

[0074] Figure 1 A schematic diagram of component layout information. Figure 1The schematic diagram shows three electronic components arranged on a printed circuit board. Each component may include one or more pins. The connection relationship between the pins of different components is the content of the wiring task.

[0075] Figure 2 A schematic diagram of a wiring resource; Figure 3 A schematic diagram of the structure of a wire network.

[0076] In the embodiment of the present invention, the target wiring resource refers to a collection of hardware resources used for wiring the nets in the netlist, and may specifically include copper wires and vias (if any) on the target board.

[0077] The wiring resources on the printed circuit board can be represented as follows Figure 2 The wiring resource diagram is shown in the form of Figure 2 As shown in Figure 1, in a multilayer printed circuit board, the wiring resource diagram can be represented as a three-dimensional grid. The grid density is determined by the production process, and the edges between the grid points represent copper wires. Figure 2 Three copper layers are shown, with adjacent layers connected by vias, and a net is identified, which can be represented as Figure 3 The netlist consists of multiple nets, each of which consists of a drive point and one or more load points (such as Figure 3 The grid is composed of load points 1 and 2 as shown in the figure. Both the driving point and the load point are located on the grid. In the circuit of the printed circuit board, the driving point is the source of the signal, which is responsible for driving the signal to be transmitted to other nodes through the network; the load point is the receiver of the signal, which can be the input of other logic gates, resistors, capacitors, inductors and other components, which consume the signal energy provided by the driving point. Both the load point and the driving point are regarded as part of the line network, but they have different roles and functions. For a certain component, there may be multiple driving points or multiple load points on it, and the component that serves as a driving point may also serve as a load point in other lines.

[0078] In the wiring task of printed circuit boards, the "wiring tree" refers to the network of wires used to connect various nodes in the circuit (such as the pins of components), which is similar to a tree structure, in which each node is connected to the root node through one and only one path. In actual printed circuit board wiring, the construction of the wiring tree also needs to consider the electrical characteristics of the circuit, such as impedance matching, signal integrity, and electromagnetic compatibility. In addition, the construction of the wiring tree may also involve obstacle avoidance, that is, obstacles on the circuit board, such as other components or fixed structures of the circuit board, need to be avoided during wiring. Figure 3 The connection relationship shown forms a "wiring tree" after the printed circuit board is implemented.

[0079] In the design of printed circuit boards, "routing through" is the most basic requirement in the entire printed circuit board wiring process, that is, all lines must be successfully connected without any breakpoints or discontinuities. If the lines are not routed through, there are broken lines or flying wires are required to connect, then the printed circuit board is unqualified because it cannot work properly.

[0080] In the actual wiring process of the printed circuit board, engineers can use automatic wiring tools to generate global wiring positions based on the designed netlist and the component layout on the target board, and perform manual intervention when necessary to complete the remaining signal wiring. There are many kinds of automatic wiring tools, some of which automatically generate wiring diagrams after engineers input wiring parameters, and some directly output wiring trees corresponding to all wire nets (defined as global wiring positions in the embodiment of the present invention) through wiring calculations based on given target wiring resources, component layouts, and netlists.

[0081] A routing tool that implements the latter function can automatically route under resource constraints. Resource constraints mean that each copper wire can only be allocated to one wire net. When multiple wire nets compete for the same copper wire, congestion will occur, causing some wire nets to have to detour, thereby increasing system latency; a more serious consequence is that routing cannot be achieved, that is, some wire nets cannot obtain the required routing resources. Therefore, establishing an effective congestion avoidance mechanism is crucial for routing algorithms.

[0082] The embodiment of the present invention adopts a wiring model to perform wiring calculations. The wiring method of the wiring model adopted is to "negotiate" between the various lines during the wiring process to avoid congestion and reduce delays. The algorithm dynamically adjusts the lines by evaluating the congestion of different paths to achieve an overall optimization effect. This method makes the wiring results more stable and predictable, while also reducing congestion problems during the wiring process. In each round of iteration of automatic wiring calculations, the wiring model removes and reroutes all wire nets until there is no congestion or the predetermined number of iterations is reached. Since each edge in the wiring resources only allows one wire net to pass through, when an edge is used by multiple wire nets (in the embodiment of the invention, it can be regarded as the utilization rate of the edge being greater than 1), it indicates that there is congestion on the edge.

[0083] Whether it is automatic routing or manual routing by engineers, it is necessary to ensure that all connections can be routed smoothly. If routing cannot be achieved due to insufficient routing resources, engineers must adjust the component layout on the printed circuit board, and even modify the schematic design when necessary, and keep trying until the routing is successful. This process is not only complex and time-consuming, but also places extremely high demands on the experience and skills of engineers.

[0084] To solve this problem, a printed circuit board design method provided by an embodiment of the present invention identifies the key physical circuits on the target board according to the target wiring resources, global wiring positions and key line identification conditions in the task parameters of the received layout adjustment task of the target board, wherein the key line identification conditions at least include line utilization; performs layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component, and the overlap between the second position and the area where the key physical circuit is located is less than the overlap between the first position and the area where the key physical circuit is located, outputs the second position, and re-executes the wiring task after adjusting the component layout on the target board according to the second position, thereby achieving automatic adjustment of the component layout to alleviate line congestion after the wiring task fails, and can perform layout adjustment after wiring failure faster and more labor-saving than manual adjustment based on experience, thereby improving the overall efficiency of printed circuit board design.

[0085] Based on the above architecture, the printed circuit board design method provided by the embodiment of the present invention is described below with reference to the accompanying drawings.

[0086] Figure 4 A flow chart of a printed circuit board design method provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a printed circuit board design system provided by an embodiment of the present invention.

[0087] like Figure 4 As shown, the printed circuit board design method provided by the embodiment of the present invention includes:

[0088] S41: receiving task parameters of the layout adjustment task of the target board;

[0089] S42: Identify key physical circuits on the target board according to the target wiring resources, global wiring positions, and key circuit identification conditions in the task parameters;

[0090] S43: performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component;

[0091] S44: outputting the second position, so as to adjust the component layout on the target board according to the second position and then re-execute the wiring task;

[0092] Among them, the key line identification conditions include at least line utilization; the second position satisfies that the edge of the component does not exceed the edge of the target board and there is no overlap between components; the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located.

[0093] In a specific implementation, the printed circuit board design method provided by the embodiment of the present invention can be applied to Figure 5 The printed circuit board design system shown may include one or more computing devices 501, and the storage space for storing relevant calculation parameters of the printed circuit board design (schematic diagram, component layout information, target wiring resources of the target board, netlist, model parameters of the wiring model, etc.) may be provided by the computing device 501 or the storage device 502. All calculation parameters may be stored in the storage device 502, and the parameters required for the current calculation may be moved to the memory or cache of the computing device 501.

[0094] The target board design task may include an initial component layout position generation task, a wiring task, and a layout adjustment task. Among them, the wiring task is a task of performing wiring based on the target wiring resources, schematic diagram, component layout information, and netlist of the target board that have been determined. In an embodiment of the present invention, executing the wiring task may include: an engineer manually executing, calling a wiring tool to execute wiring steps, or calling a wiring model to perform wiring calculations to generate global wiring positions, etc.

[0095] When the global routing position (including the routing tree of each net) obtained by executing the routing task does not meet the routing requirements, the layout adjustment task in the embodiment of the present invention can be triggered. The layout adjustment task in the embodiment of the present invention is used to replace the engineer manually adjusting the component layout on the target board based on experience.

[0096] In the embodiment of the present invention, routing can be successful in that each net in the routing task can be successfully connected on the target routing resource. Specifically, the routing of each net on the target routing resource cannot cross or overlap.

[0097] For S41, in the embodiment of the present invention, the task parameters of the layout adjustment task may include:

[0098] Netlist : It is composed of several wire meshes. Each wire mesh contains a driving point , one or more load points .

[0099] Wiring Resource Diagram :in is a grid point set, where each element represents a grid point. is a set of physical lines, each element of which represents a physical line (such as Figure 2 as shown).

[0100] Original layout information : It can include the size of the target board, the size of the components, the location of the components, the location of the pins, etc.

[0101] Target board size: Width ,high .

[0102] Number of components: .

[0103] Component location: , you can use Indicates The coordinates of the lower left corner of a component on the target board can also be used to represent the coordinates of other reference points of the component on the target board.

[0104] Component dimensions: ,in Indicates The width and height of an electronic component (such as Figure 1 as shown).

[0105] Unrouted global routing locations: , where each For a wiring tree (such as Figure 3 as shown).

[0106] If a wiring model is used to perform the wiring task, the given information may also include: wiring model , communication delay ,use Represents edge communication delay.

[0107] In the embodiment of the present invention, the physical line refers to a copper wire between two grid points on the target wiring resource, and is also referred to as an "edge" in the following step description.

[0108] It is understandable that, assuming that the target wiring resources meet the wiring requirements of the target board design task, the reason for the failure of the wiring task is most likely that congestion occurs on some physical lines, while other physical lines are not fully utilized, which means that the set component layout is unreasonable. The layout adjustment task to be constructed in the embodiment of the present invention is intended to solve this unreasonableness. First, the physical lines that are congested must be determined. Therefore, in S42, the key line identification condition at least includes line utilization.

[0109] For S43, in an embodiment of the present invention, the layout adjustment task is constructed as an optimization solution task, so as to realize the calculation of automatic adjustment of component layout. It is necessary to set constraints and task objectives to construct the layout adjustment task. In order to alleviate the congestion on the local line, the layout adjustment task objective at least includes that the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located, that is, reducing the overlap between the position after the component adjustment and the area where the key physical line is located.

[0110] It should be noted that, in the embodiment of the present invention, overlap may refer to overlap between two areas, one area is based on the outline of the component at the location, and the other area is a key physical circuit and a certain range of its surrounding area is regarded as another area.

[0111] In an embodiment of the present invention, the overlap between the second position and the area where the critical physical circuit is located is smaller than the overlap between the first position and the area where the critical physical circuit is located. This may mean that the overlap between the second position of all components and the area where the critical physical circuit is located is smaller than the overlap between the first position of the component and the area where the critical physical circuit is located. This may also mean that the sum of the overlapping areas between the second positions of all components and the area where the critical physical circuit is located is smaller than the sum of the overlapping areas between the first positions of all components and the area where the critical physical circuit is located. Among them, the overlap between the second position of some components and the area where the critical physical circuit is located may be smaller than the overlap between the first position of the component and the area where the critical physical circuit is located, while the overlap between the second position of another part of the components and the area where the critical physical circuit is located is not less than the overlap between the first position of the component and the area where the critical physical circuit is located.

[0112] The layout adjustment constraint condition at least includes that the edge of the second position component does not exceed the edge of the target board and there is no overlap between components, that is, each component can be installed on the target board after the position is adjusted.

[0113] In an embodiment of the present invention, the line utilization rate may be the ratio of the number of wire nets occupying the physical line divided by 1. For example, if three wire nets occupy the same physical line in the global wiring position obtained by the wiring task, the line utilization rate of the physical line may be expressed as 300%.

[0114] In S43, based on the above task parameters, layout adjustment constraints and layout adjustment task objectives, the layout adjustment task is essentially an optimization solution task under given constraints. A known algorithm can be used for optimization solution to output component layout adjustment parameters for the target board design task.

[0115] The component layout adjustment parameters can be in the form of the adjusted positions of all components on the printed circuit board (i.e., the second position), or the components whose positions are adjusted and their adjusted positions, and then the second position of each component is determined based on the first position of each component.

[0116] After adjusting the component layout according to the information of the second position of each component, the task parameters of the wiring task are updated, and the wiring can be re-performed manually or by calling a wiring tool or a wiring model.

[0117] The printed circuit board design method provided by the embodiment of the present invention identifies the key physical circuits on the target board according to the target wiring resources, global wiring positions and key line identification conditions in the task parameters of the received layout adjustment task of the target board, wherein the key line identification conditions at least include line utilization; performs layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component, and the overlap between the second position and the area where the key physical circuit is located is less than the overlap between the first position and the area where the key physical circuit is located, outputs the second position, and re-executes the wiring task after adjusting the component layout on the target board according to the second position, thereby realizing automatic adjustment of component layout to alleviate line congestion after failure in executing the wiring task, and can perform layout adjustment after wiring failure faster and more labor-saving than manual adjustment based on experience, thereby improving the overall efficiency of printed circuit board design.

[0118] Based on the above embodiment, the embodiment of the present invention further illustrates the step of determining the key physical line.

[0119] In the above embodiment, it is introduced that the critical line identification condition includes at least line utilization, that is, the congested physical line is identified as the critical physical line. Then a simple way to determine the critical physical line is to traverse all physical lines on the target wiring resource, sort them from large to small according to line utilization, and take the first preset number of physical lines as the critical physical lines.

[0120] In the embodiment of the present invention, the line utilization rate can be determined according to the number of wires or the number of nets occupying the physical line, that is, how many nets are routed from the physical line in the global routing position obtained by executing the routing task.

[0121] However, it is understandable that the physical circuits on the printed circuit board are not isolated, that is, there are correlations between physical circuits. If the key physical circuits are determined only by line utilization without considering the correlation between the physical circuits, the determined key physical circuits may not be very effective in solving wiring problems.

[0122] Then in an embodiment of the present invention, determining the key physical lines can also be constructed as an optimization problem. In S41, determining the key physical lines on the target board according to the key line identification conditions can include: performing a network removal optimization calculation to alleviate the congestion of the physical lines of the target board according to the target wiring resources, the global wiring position and the goal of minimizing the number of network removals to obtain a preferred network removal; determining the key physical lines according to the physical lines through which the preferred network removal passes. That is to say, by taking the line utilization rate as given information and minimizing the number of network removals to alleviate the congestion of the physical lines as the task goal, the problem of determining the key physical lines is constructed as a network removal task, thereby obtaining the key physical lines of the layout adjustment task of removing as few lines as possible based on the global wiring position that could not be routed before.

[0123] Then the input and output of the key physical lines can be determined as follows:

[0124] Input: Wiring resource map , wiring tree , Netlist , the number of key physical lines ;

[0125] Output: Key physical lines .

[0126] The network dismantling task can be expressed as:

[0127] ;

[0128] in, , , . Indicates A wire network, Represents edge line utilization.

[0129] It can be understood that by constructing and solving the optimal wire removal problem for alleviating physical line congestion, the purpose of identifying key physical lines whose key line identification conditions at least include line utilization is achieved. Because for a physical line, the higher the line utilization, the more serious the congestion, then identifying the critical physical line with serious congestion and adjusting the components away from the critical physical line will help alleviate the congestion on the critical physical line, thereby alleviating the global congestion situation.

[0130] However, since the physical significance of the critical physical lines is their high utility in alleviating congestion, but the network removal task is an optimal line removal problem (minimizing the number of network removals) to alleviate congestion on all physical lines, it does not correspond to the purpose of determining the critical physical lines. Therefore, in some other optional implementations of the embodiments of the present invention, the critical physical lines can be determined by constructing the dual problem of the network removal task.

[0131] Then, determining the key physical lines on the target board according to the key line identification conditions in S41 may also include: performing resource increase calculations for the physical lines of the target board according to the target wiring resources, the global wiring position, and the goal of maximizing the congestion relief utility value, to obtain the congestion relief utility value after adding physical line resources to each physical line; and determining the first preset number of physical lines as key physical lines in descending order of the congestion relief utility values ​​of the physical lines.

[0132] That is to say, the dual problem of the optimal wire removal problem, that is, the resource increase calculation problem, is constructed to obtain the optimization solution corresponding to the goal of alleviating the congestion of the physical lines of the target board.

[0133] The physical meaning of this dual problem is that if the utility of increasing the resources on the physical line is greater, it means that the physical line is more likely to be a critical physical line.

[0134] Then the dual problem can be expressed as:

[0135] ;

[0136] in, , , , .

[0137] That is, the physical meaning of the original problem is to find an optimal network removal plan (minimizing the number of network removals) to alleviate congestion on all physical lines. Indicates line network Should it be demolished? Therefore, in the dual problem constructed in this way, the dual variable Indicates increase The utility of the surrounding resources is taken into consideration, and the task goal is converted to maximizing the congestion relief utility value of all physical lines after adding resources to the physical lines, that is, the congestion relief effect is the best.

[0138] In an embodiment of the present invention, a resource increase calculation of the physical lines of a target board is performed according to target wiring resources, a global wiring position, and a goal of maximizing congestion relief utility values, and a congestion relief utility value after adding physical line resources to each physical line is obtained, including: using a pre-trained prediction model to calculate the congestion relief utility value after adding physical line resources to each edge of a wiring tree of each wire net according to the target wiring resources, the global wiring position, and a wire net of a target board design task of the target board; and determining the congestion relief utility value of the physical line according to the congestion relief utility value of the edge of the wiring tree passing through the physical line in the global wiring position.

[0139] The above process can be expressed as: .in, represents the congestion relief utility value, represents the prediction model, represents the dual problem, Represents the global routing location, which is a routing tree A collection of .

[0140] Then return the utility value The maximum value of The edges are used as key physical lines.

[0141] Furthermore, the pre-trained prediction model is used to calculate the congestion relief utility value after adding physical line resources to each edge of the wiring tree of each wire net according to the target wiring resources, the global wiring position, and the wire net of the target board design task, which may include:

[0142] The resource increase calculation problem of each physical line is constructed as a constraint relationship graph. Each node in the constraint relationship graph corresponds to a dual variable. The dual variable corresponds to the congestion relief utility value of a physical line. The edge between two nodes corresponds to the number of times the two dual variables appear in the same constraint condition. The characteristics of the node are determined according to the line utilization corresponding to the dual variable.

[0143] Use graph convolutional networks to generate column vectors corresponding to dual variables based on constraint graphs;

[0144] The score corresponding to the dual variable is calculated using the query vector and the column vector corresponding to the dual variable;

[0145] According to the scores of the dual variables corresponding to the edges of the wiring tree and the scores of the dual variables corresponding to all the edges of the wiring tree, the congestion relief utility values ​​corresponding to the edges of the wiring tree are calculated.

[0146] In the specific implementation, for the convenience of description, it is assumed that the edge set ,in, is the number of edges.

[0147] The prediction model The input is the dual problem , the output is the utility value .

[0148] Figure 6 A schematic diagram of a dual problem and its constraint relationship provided in an embodiment of the present invention.

[0149] like Figure 6 As shown, the utility values ​​corresponding to the three physical lines can be expressed as follows:

[0150] ;

[0151] in, , , , ,in, represents the congestion relief utility value of the first physical line, represents the congestion relief utility value of the second physical line, Indicates the congestion relief utility value of the third physical line.

[0152] The process of solving the dual problem using the prediction model may include the following steps S71 to S75.

[0153] S71: Using dual problems to construct constraint diagrams as follows:

[0154] (a) Each node in Corresponding to a variable ;

[0155] (b) If the variable and appears in the same constraint condition, then at the node and Add an edge between them. In addition, the weight of the edge for and The number of times it appears in the same constraint;

[0156] (c) Node The characteristics are .

[0157] S72: Note The weighted adjacency matrix of ,in:

[0158] .

[0159] S73: Constructing column vectors : , for No. A quantity.

[0160] for , .in, is a hyperparameter representing the depth of graph convolution, is the learnable parameter matrix. ,other is a hyperparameter.

[0161] S74: For variables , ,in is the learnable query vector, Representation Matrix No. OK.

[0162] S75: Yes , for each wiring tree The edge ,calculate as follows:

[0163] .

[0164] in, Indicates Edges in the wiring tree The utility value of represents the exponential function, Indicates a fraction.

[0165] The congestion relief utility value of the physical line is determined according to the congestion relief utility value of the edge of the wiring tree passing through the physical line in the global wiring position, which may include: if there are multiple routing lines of the wiring tree on the physical line, then the smallest congestion relief utility value is used as the congestion relief utility value of the physical line. This process can be expressed as: .

[0166] Based on the above embodiment, the embodiment of the present invention further illustrates the training steps of the prediction model for solving the above dual problem.

[0167] In an embodiment of the present invention, the training steps of the prediction model include: constructing a dual problem sample pool, the dual problem sample pool includes multiple dual problem samples, and the dual problem samples are maximization optimization problems with given constraints; using a linear programming solver to solve the dual problem samples, and using the obtained solutions as labels of the dual problem samples; using the prediction model to solve the dual problem samples, calculating the training error based on the obtained solution results and the labels corresponding to the dual problem samples, and using the training error to update the model parameters of the prediction model.

[0168] Among them, the step of generating the dual problem sample may include: randomly sampling a second preset number of sample dual variables and a third preset number of sample constraints; initializing the sample constraints of the dual problem sample to be empty, and adding the sample dual variables to the sample constraints with a first probability; the first probability is sampled from the conjugate prior distribution of the binomial distribution; calculating the cost coefficient corresponding to each sample dual variable; taking the constraint that each sample dual variable is greater than or equal to 0 and the sum of the sample dual variables in the sample constraints is less than or equal to 1 as the constraint, and taking minimizing the weighted sum of each sample dual variable based on the cost coefficient as the optimization goal, as the dual problem sample.

[0169] In generating each dual problem sample When, the following steps S81~S83 may be included.

[0170] S81: Initialize the number of sample dual variables (i.e., the second preset number) and the number of sample constraints (i.e. the third preset number) .

[0171] S82: Initialize sample constraints is empty, that is right .

[0172] S83: For each sample dual variable , for each sample constraint , with the first probability Will Add sample constraints Therefore, The number of occurrences in the constraints follows a binomial distribution. , sampled from the Beta distribution, the conjugate prior distribution of the binomial distribution ,in and is a hyperparameter.

[0173] In addition, for each sample dual variable , sample the cost coefficient Generate dual problem samples as follows:

[0174] ;

[0175] in, , , , .

[0176] Then, an exact linear programming solver is used to solve each Solve and convert the obtained solution As a label, get the dual problem sample , the training steps based on this prediction model may include:

[0177] Randomly initialize the model parameters of the prediction model ;

[0178] right , sample from the generated dual problem samples Dual problem sample , the solution is obtained by using the prediction model: .

[0179] Then the gradient descent algorithm is used to update the model parameters of the prediction model: ;in, is the learning rate, The prediction model The model parameters in the training iteration, The prediction model The model parameters in the training iteration, The prediction model The solution obtained in the iterative training is The prediction model The sample dual variable of the corresponding dual problem sample in the iterative training, represents the square of the two-norm, Indicates gradient calculation.

[0180] On the basis of the above embodiments, in the printed circuit board design method provided in the embodiments of the present invention, the overlap between the second position and the area where the critical physical line is located is smaller than the overlap between the first position and the area where the critical physical line is located, which may include: the overlap between the second position and a virtual obstacle of a preset size added to the position of the critical physical line is smaller than the overlap between the first position and the virtual obstacle.

[0181] In the printed circuit board design method provided by the embodiment of the present invention, the component layout is adjusted on the target board where the virtual barrier is placed, and the components are required to not overlap with the virtual barrier as much as possible, so that the layout adjustment task avoids the key physical circuit. When solving the dual problem of the wire net removal task, the wiring resources around the key physical circuit are increased by requiring the components to not overlap with the virtual barrier as much as possible.

[0182] Figure 7 A schematic diagram of adding a virtual barrier at a location where a key physical line is located provided by an embodiment of the present invention; Figure 8 A schematic diagram of inserting a virtual barrier on a surface layer to deal with congestion in a through hole provided by an embodiment of the present invention.

[0183] like Figure 7 As shown in , after determining the key physical line, a square virtual barrier can be added with the center of the key physical line as the center. Figure 8 As shown, if congestion occurs in a via, a dummy barrier can be added on the surface of the target board.

[0184] In addition, as described in the above embodiment of the present invention, in order to improve the effectiveness of the determined key physical lines for layout adjustment, an optimal wire removal problem with the goal of minimizing the number of wire nets to be removed can be constructed when selecting key physical lines, and can also be solved by constructing it as a dual problem. Similarly, the layout adjustment task goal can also include minimizing the overlap between the second position and the area where the key physical line is located and the change in component layout.

[0185] Then, in S43, layout adjustment calculations are performed according to the current first positions of each component on the target board and the positions of key physical circuits to obtain the second positions of each component, which may include: taking the value of minimizing the component layout adjustment penalty function as the layout adjustment task target, performing layout adjustment calculations according to the first positions and the positions of key physical circuits to obtain the second positions; the component layout adjustment penalty function is positively correlated with the overlap of the second position with the virtual obstacle, and the component layout adjustment penalty function is positively correlated with the change value of the second position compared to the first position.

[0186] In some optional implementations of the embodiments of the present invention, the component layout adjustment penalty function can be the sum of the layout adjustment constraint penalty value and the total component layout change value. The layout adjustment constraint penalty value is the sum of the component elimination penalty value, the component overlap penalty value, and the component obstacle overlap penalty value. Among them, the more the second position causes the component to exceed the target board, the greater the component elimination penalty value; the larger the overlapping area between the components, the greater the component overlap penalty value; the larger the overlapping area between the component and the virtual obstacle, the greater the component obstacle overlap penalty value; the total component layout change value is the sum of the distances between each second position and the corresponding first position.

[0187] Then let the key physical circuit be The coordinates of the lower left corner of the virtual obstacle are , the size of the obstacle .

[0188] The layout adjustment constraints for constructing the layout adjustment task are as follows:

[0189] Layout adjustment constraint 1: Component exclusion constraint, which requires that all components must be located on the target board. This constraint can be expressed as:

[0190] , ;

[0191] , ;

[0192] in, Display element The horizontal coordinate of the lower left corner after adjusting the position, Indicates the width of the target board. Display element The width of Indicates the number of components, Display element The vertical coordinate of the lower left corner after adjusting the position, Indicates the height of the target board. Display element height.

[0193] Layout adjustment constraint 2: Component overlap constraint, which requires that all components cannot overlap. No other components can appear in the occupied area . This constraint can be expressed as:

[0194] ;

[0195] ;

[0196] ;

[0197] ;

[0198] ;

[0199] , ;

[0200] in, Display element The horizontal coordinate of the lower left corner after adjusting the position, Display element The horizontal coordinate of the lower left corner after adjusting the position, Display element The width of Display element The vertical coordinate of the lower left corner after adjusting the position, Display element The vertical coordinate of the lower left corner after adjusting the position, Display element Height, , , , They are indicator variables, used to indicate whether the corresponding constraints are met.

[0201] Layout Adjustment Constraint 3: Components There should be no virtual obstacles in the occupied area as much as possible . This constraint can be expressed as:

[0202] ;

[0203] ;

[0204] ;

[0205] ;

[0206] ;

[0207] ;

[0208] in, Display element The horizontal coordinate of the lower left corner after adjusting the position, Indicates virtual obstacles The horizontal axis appears in the element The penalty value within the horizontal axis range is Indicates virtual obstacles The horizontal coordinate of the lower left corner, Display element The width of Display element The vertical coordinate of the lower left corner after adjusting the position, Indicates virtual obstacles The vertical coordinate of the lower left corner, Indicates virtual obstacles The vertical coordinate appears in the element The penalty value within the vertical axis range is Display element Height, , , , They are indicator variables, used to indicate whether the corresponding constraints are met.

[0209] Layout adjustment constraint 4: virtual barriers Try to avoid components in the occupied area . This constraint can be expressed as:

[0210] ;

[0211] ;

[0212] ;

[0213] ;

[0214] ;

[0215] , ;

[0216] , ;

[0217] in, Display element The horizontal coordinate of the lower left corner after adjusting the position, Display element The horizontal axis appears in the virtual obstacle The penalty value within the horizontal axis range is Indicates virtual obstacles The horizontal coordinate of the lower left corner Display element The width of Display element The vertical coordinate of the lower left corner after adjusting the position, Indicates virtual obstacles The vertical coordinate of the lower left corner, Display element The vertical coordinate of the virtual obstacle appears within the vertical coordinate range of the penalty value, Display element Height, , , , They are indicator variables, used to indicate whether the corresponding constraints are met.

[0218] Then the layout adjustment task objective can be expressed as:

[0219] ;

[0220] in, is a hyperparameter that controls the difference from the original layout.

[0221] The above layout adjustment task is a minimization optimization problem, and can be solved by using any algorithm for solving minimization optimization problems.

[0222] On the basis of the above embodiment, in S43, the layout adjustment calculation is performed according to the current first position of each component on the target board and the position of the key physical line to obtain the second position of each component, which may include: initializing the size of the virtual barrier; performing layout adjustment calculation on the position of the key physical line according to the size of the virtual barrier, the position of the virtual barrier and the first position to obtain the second position of each component; after adjusting the position of the component on the target board according to the second position of each component, calling the wiring model to re-calculate the wiring, if the output global wiring position does not meet the wiring requirements, then increasing the size of the virtual barrier, returning to the layout adjustment calculation of the position of the key physical line according to the size of the virtual barrier, the position of the virtual barrier and the first position to obtain the second position of each component; if the sum of the total area of ​​each virtual barrier and the total area of ​​each component reaches the maximum area allowed by the target wiring resources of the target board, it is determined that the component layout adjustment has failed, and outputs a suggestion information for reducing the number of components.

[0223] In a specific implementation, solving the layout adjustment task in S43 and outputting the component layout adjustment parameters for the target board design task, so as to adjust the position of the component on the target board according to the component layout adjustment parameters and then re-execute the routing task, may include the following S91-S96.

[0224] S91: Determine the key physical circuit (see the above embodiment for details). , wiring tree and Netlist ,Sure The most critical physical line.

[0225] S92: Place a size of A rectangular virtual obstacle (such as Figure 7 , Figure 8 as shown). The initial value of is a hyperparameter. If the virtual obstacle exceeds the target board, only the part within the target board is retained as the virtual obstacle.

[0226] S93: Adjust the layout on the target board after placing the obstacle (detailed description of the above embodiment), and increase the wiring resources around the critical physical lines by requiring the components to not overlap with the virtual obstacles as much as possible.

[0227] S94: Remove virtual obstacles before routing.

[0228] S95: After adjusting the position of the component on the target board according to the component layout adjustment parameters, update the parameters of the routing task, call the routing model to execute the routing task, and if the routing is successful, return the component layout adjustment parameters and the total length of the bus under the layout. If the routing is not successful, determine whether the size of the virtual barrier can be increased (such as increasing the side length). ). If the sum of the total area of ​​the components and the total area of ​​the virtual barriers exceeds the maximum area allowed by the target wiring resources of the target board, it is not allowed to continue to increase the size of the virtual barriers, the program ends, and the user is prompted to reduce the number of components or increase the area of ​​the target board. Otherwise, for , is a hyperparameter.

[0229] S96: Jump to S92 and restart execution.

[0230] In the above embodiment, the wiring model can adopt a wiring model that implements wiring calculation by performing congestion avoidance through line negotiation. However, the congestion evaluation parameters used in the calculation process of this type of wiring model cannot well evaluate the congestion of each edge on a given wiring resource, resulting in the problem that many rounds of iterative calculations are often required and even the model cannot converge. This situation becomes more serious as the circuits on the printed circuit board become increasingly dense, resulting in the reliance on engineers to manually adjust the wiring.

[0231] To solve this problem, in an embodiment of the present invention, calling a wiring model to execute a wiring task may include: obtaining the task parameters of the target wiring task; performing iterative calculation according to the task parameters, and in the iterative calculation process, generating a first coefficient according to the target wiring resources in the task parameters and the global wiring position obtained by the previous round of iterative calculation, using the first coefficient to calculate the congestion evaluation parameter corresponding to the global wiring position obtained by the previous round of iterative calculation, calling the wiring model to perform wiring calculation according to the task parameters, the global wiring position obtained by the previous round of iterative calculation, and the corresponding congestion evaluation parameter, and outputting the global wiring position obtained by the current round of iterative calculation; if the iteration end condition is met and a global wiring position that satisfies the routing is obtained, it is output as a recommended global wiring position for the target wiring task. Among them, the first coefficient includes a historical congestion attenuation factor and / or a current round of congestion cost coefficient update coefficient; routing means that each wire net in the task parameters can be successfully connected on the target wiring resource.

[0232] In the specific implementation, the task parameters of the wiring task are obtained, that is, according to the information of the printed circuit board design system, the reading and writing positions of the wiring calculation related parameters are determined, and the computing resources and storage resources for iterative calculation are obtained, so as to carry out the transfer of the wiring calculation related parameters and call the thread that executes the calculation task.

[0233] The target board is the printed circuit board that needs to be wired. In the wiring task, the prerequisite is that the netlist and the component layout on the target board have been determined. At this time, the extraction method in the relevant field can be used to extract the wire net to be wired from the netlist.

[0234] In the embodiment of the present invention, the task parameters of the target routing task may include the target routing resources provided by the target board, the component layout on the target board, and the wire nets to be routed.

[0235] The wiring model adopted by the embodiment of the present invention is a pathfinder model commonly used in printed circuit board wiring problems. The wiring model is used for iterative calculation, and a global wiring position is output in each iterative calculation. The global wiring position includes the wiring tree corresponding to each wire net of the wiring task. Each wire net is continuously removed and re-routed in the iterative calculation until there is no congestion or the predetermined number of iterations is reached. To avoid congestion, the wiring model uses the cost of the "hotspot" edge to guide the signal to use the "non-hotspot" edge.

[0236] Specifically, in the In the round iteration, the edge The congestion cost is as follows:

[0237] ;

[0238] in, Indicates that in the current round (i.e. Round) Iterative calculation of the edge Congestion evaluation, Represents edge The communication delay on Indicates in front Round iterative calculation of edges The historical congestion cost of Indicates that in the current round (i.e. Round) Iterative calculation of the edge Real-time congestion cost.

[0239] By the front Round iterative calculation of edges Historical congestion costs and in At the end of the round of iterations, the edge Number of wire nets Sure:

[0240] .

[0241] The update formula is as follows:

[0242] ;

[0243] in, Indicates that in the current round (i.e. Round) Iterative calculation of the edge The real-time congestion cost evaluation parameter is updated every time a network is wired. Indicates that in the current round (i.e. The congestion cost coefficient of the current round in the iterative calculation of rounds, , Indicates that in the previous round (i.e. The congestion cost coefficient of the current round in the iterative calculation of rounds, It is an empirical value, usually 1.3.

[0244] Although this wiring model is widely used in practice, it has the problem that the update of congestion evaluation parameters is too rigid, which is reflected in: historical congestion cost The update is too "aggressive". Even if an edge with severe historical congestion is not congested in recent rounds, it will still have a high historical congestion cost, thus hindering the network from making reasonable use of it. The current round congestion cost coefficient Depends on experience And its adjustment lacks flexibility, and the manual setting This is usually suboptimal. In addition, all edges share the same monotonically increasing congestion cost coefficient, which will make it impossible to deal with the specific conditions of different edges and the real-time congestion cost evaluation parameters in the current round of iterative calculations. over-adjustment.

[0245] To this end, an embodiment of the present invention improves the calculation method of the congestion evaluation parameters of the wiring model, and adds a first coefficient, which can be a historical congestion attenuation factor and / or a current round of congestion cost coefficient update coefficient. As the name implies, the historical congestion attenuation factor, that is, the update process of the historical congestion cost, is not only determined by the continuous accumulation of the number of wire nets that have used the edge in the historical iterative calculation, but also adaptively attenuates the congestion situation in the historical iterative calculation through the historical congestion attenuation factor, thereby diluting the impact of historical congestion that is a long time apart. The current round of congestion cost coefficient update coefficient is calculated by changing the fixed coefficient that depends on the experience value into the form of the first coefficient to obtain the current round of congestion cost coefficient used to calculate the real-time congestion cost, thereby increasing the flexibility of increasing or decreasing the current round of congestion cost coefficient.

[0246] It can be understood that the added first coefficient can be one or both of the historical congestion attenuation factor and the current round congestion cost coefficient update coefficient, both of which can achieve the effect of more flexible calculation of congestion evaluation parameters compared with the current wiring model.

[0247] In some optional implementations of the embodiments of the present invention, the congestion evaluation parameters corresponding to the global routing position obtained by the previous round of iterative calculation are calculated using the historical congestion attenuation factor, which may include: for each edge of the target routing resource, the historical congestion cost corresponding to the edge in the current round is calculated based on the historical congestion attenuation factor corresponding to the edge in the current round, the historical congestion cost of the edge input in the previous round of iterative calculation, and the number of wire nets occupying the edge in the global routing position obtained by the previous round of iterative calculation; the congestion cost of the edge in the current round of iterative calculation is calculated based on the historical congestion cost corresponding to the edge in the current round, the current round congestion cost of the edge, and the communication delay of the edge; the congestion cost of each edge in the current round of iterative calculation is used as the congestion evaluation parameter corresponding to the global routing position obtained by the previous round of iterative calculation. Wherein, the edge is a copper wire between two grid points. The historical congestion cost in the above steps can be calculated by the following formula:

[0248] ;

[0249] in, Indicates in front Round iterative calculation of edges The historical congestion cost of Indicates in front Round iterative calculation of edges The historical congestion cost of Indicated in At the end of the round of iterations, the edge The number of wire nets, Indicates the corresponding Round iterative calculation of edges The historical congestion attenuation factor of the historical congestion cost can be .

[0250] Calculating the congestion evaluation parameter corresponding to the global routing position obtained by the previous round of iterative calculation using the current round congestion cost coefficient update coefficient may include: for each edge of the target routing resource, calculating the current round congestion cost coefficient of the edge based on the current round congestion cost coefficient update coefficient corresponding to the edge in the current round and the current round congestion cost coefficient of the edge input in the previous round of iterative calculation; calculating the current round congestion cost of the edge based on the current round congestion cost coefficient of the edge and the real-time congestion cost evaluation parameter of the edge; calculating the congestion cost of the edge in the current iterative calculation based on the current round congestion cost coefficient of the edge, the historical congestion cost corresponding to the edge in the current round and the communication delay of the edge; using the congestion cost of each edge in the current round of iterative calculation as the congestion evaluation parameter corresponding to the global routing position obtained by the previous round of iterative calculation. Wherein, the edge is the copper wire between two grid points. The current round congestion cost coefficient in the above steps can be calculated by the following formula:

[0251] ;

[0252] in, Indicates that in the current round (i.e. Round) Iterative calculation of the edge The current round congestion cost coefficient, Indicates that in the previous round (i.e. Round) Iterative calculation of the edge The current round congestion cost coefficient, Indicates the current round (i.e. Round) Iterative calculation of the edge The current round congestion cost coefficient update coefficient.

[0253] It can be understood that if the two first coefficients, the historical congestion attenuation factor and the current round congestion cost coefficient update coefficient, are added to the calculation of the congestion evaluation parameter, the historical congestion cost and the real-time congestion cost are calculated according to the above two formulas respectively, and then substituted into Calculate the current round (i.e. Round) Iterative calculation of the edge The congestion evaluation of each edge in the current round of iterative calculation is used as the congestion evaluation parameter corresponding to the global wiring position obtained by the previous round of iterative calculation, and then the congestion evaluation parameter and the delay evaluation parameter corresponding to the global wiring position obtained by the previous round of iterative calculation are used as the current round (i.e. The input of the wiring model in the iterative calculation of round (round).

[0254] It should be noted that the specific formulas for the subsequent calculations of the two first coefficients, the historical congestion attenuation factor and the current round congestion cost coefficient update coefficient, recorded in the above implementation are only an enumeration of a preferred implementation method, and are not the only formula form protected by the embodiments of the present invention. That is, the formula for calculating the congestion evaluation parameter based on the first coefficient can also adopt other calculation methods, which all fall within the protection scope of the embodiments of the present invention.

[0255] It should be noted that in the above process of calculating the congestion evaluation parameters of the current round of iterative calculation, the current round is recorded as The corner mark used for the real-time congestion cost is , the superscript used for the historical congestion cost is , indicating that the historical congestion cost comes from the previous The historical congestion cost accumulated in the round of iterative calculations, but it is different from the superscript The real-time congestion costs are used to calculate the congestion evaluation parameters required to be input into the wiring model in the current round of iterative calculation. is the historical congestion attenuation factor corresponding to the edge in the current round, called is the historical congestion cost corresponding to the edge in the current round.

[0256] In each round of iterative calculation, a first coefficient is generated according to the target routing resources and the global routing position obtained by the previous round of iterative calculation, and the congestion evaluation parameter corresponding to the global routing position obtained by the previous round of iterative calculation is calculated using the first coefficient. The method for calculating the delay evaluation parameter corresponding to the global routing position obtained by the previous round of iterative calculation can refer to the calculation scheme of the traditional routing model, and the congestion evaluation parameter and the delay evaluation parameter are used as the routing evaluation parameters. The task parameters, the global routing position obtained by the previous round of iterative calculation, and the corresponding routing evaluation parameters are input into the routing model for routing calculation, and the global routing position obtained by the current round of iterative calculation is output.

[0257] The input of the wiring model in the first round of iterative calculation may be target wiring resources and initialization parameters, and the initialization parameters include an initialized global wiring position and corresponding wiring evaluation parameters.

[0258] In various embodiments of the present invention, the intermediate parameter used to calculate the wiring evaluation parameter in combination with the first coefficient is defined as the wiring control parameter. For example, the wiring control parameter may include the historical congestion cost 、Current round congestion cost coefficient , real-time congestion cost , Use Edge Number of wire nets One or more of .

[0259] In various embodiments of the present invention, the congestion evaluation parameter in the wiring evaluation parameter may adopt the congestion cost introduced in the above steps. , the delay evaluation parameter in the wiring evaluation parameter can use the margin ratio. The margin ratio means that for each load point, the remaining margin ratio is the ratio of the delay from the driving point to the load point to the system delay.

[0260] It should be noted that, in each embodiment of the present invention, , , , etc. wiring control parameters and the first coefficient , All are high-dimensional parameters , , , , , the subscript indicates the edge set corresponding to the target routing resource All edges in , for aspect description, omitting the superscript, for example Abbreviated as or .

[0261] Before starting the routing task, determine the maximum number of iterations.

[0262] In addition to routing, the task objectives of the routing model may also include minimizing system delay. In the embodiment of the present invention, "net delay" may be defined as the maximum delay from the driving point in the network to all load points after routing using the global routing position, and "system delay" may be defined as the maximum delay of all network delays after routing using the global routing position. It is understandable that the system delay may also be calculated using other methods, such as the average value, median value, etc. of all network delays.

[0263] The iteration end condition may be obtaining a global routing position that is routed through, or reaching a maximum number of iteration calculation rounds.

[0264] In some optional implementations of the embodiments of the present invention, S33 may include: before the maximum number of iterative calculation rounds is exceeded, if a global routing position that satisfies routing is obtained, it is output as a recommended global routing position for the routing task and the iterative calculation is terminated.

[0265] In some other optional implementations of the embodiments of the present invention, in order to obtain a better global routing position, S33 may also include: if a global routing position has been obtained before the maximum number of iterative calculation rounds is reached, then the iterative calculation is continued on the basis of keeping the global routing position routed to optimize the system delay until the maximum number of iterative calculation rounds is reached, and the corresponding global routing position is output as the recommended global routing position output for the routing task and the iterative calculation is terminated.

[0266] It should be noted that the recommended global routing position is the global routing position with the best routing evaluation parameters in each round of iterative calculation, and is not necessarily the global routing position output by the last round of iterative calculation.

[0267] The printed circuit board design method provided by the embodiment of the present invention uses a first coefficient including a historical congestion attenuation factor and / or a current round of congestion cost coefficient update coefficient to update the congestion evaluation parameter used in the iterative calculation of the wiring model in the process of obtaining a global wiring position by performing wiring calculation according to the wiring parameters of the wiring task and the congestion evaluation parameter using a wiring model to avoid congestion and reduce delay. The first coefficient is generated according to the target wiring resources and the global wiring position obtained by the previous round of iterative calculation, thereby solving the problem that the congestion situation of the global wiring position evaluated by the wiring model is relatively rigid, and can accelerate the convergence rate of the model calculation, thereby improving the efficiency of generating the recommended global wiring position.

[0268] It should be noted that in the embodiments of the printed circuit board design method of the present invention, some of the steps or features can be ignored or not executed. The hardware or software functional modules divided for the convenience of explanation are not the only implementation form of the printed circuit board design method provided by the embodiment of the present invention.

[0269] The above describes in detail various embodiments corresponding to the printed circuit board design method. On this basis, the present invention also discloses a printed circuit board design device, equipment, non-volatile storage medium and computer program product corresponding to the above method.

[0270] The printed circuit board design device provided by the embodiment of the present invention may include:

[0271] A receiving unit, used for receiving task parameters of a layout adjustment task of a target board;

[0272] An identification unit, used to identify key physical circuits on a target board according to target wiring resources, global wiring positions, and key circuit identification conditions in task parameters;

[0273] A calculation unit, used for performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component;

[0274] An output unit, used for outputting the second position, so as to adjust the component layout on the target board according to the second position and then re-execute the wiring task;

[0275] Among them, the key line identification conditions include at least line utilization; the second position satisfies that the edge of the component does not exceed the edge of the target board and there is no overlap between components; the overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located.

[0276] It should be noted that in each implementation of the printed circuit board design device provided by the embodiment of the present invention, the division of units is only a logical functional division, and other division methods can be used. The connection method between different units can be electrical, mechanical or other connection methods. The separated units can be located in the same physical location or distributed on multiple network nodes. Each unit can be implemented in the form of hardware or in the form of a software functional unit. That is, according to actual needs, part or all of the units provided in the embodiment of the present invention can be selected and the corresponding connection method or integration method can be adopted to achieve the purpose of the embodiment of the present invention.

[0277] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0278] Fig. 9 A schematic structural diagram of a printed circuit board design device provided by an embodiment of the present invention.

[0279] like Fig. 9 As shown, the printed circuit board design device provided in an embodiment of the present invention includes: a memory 910, used to store a computer program 911; a processor 920, used to execute the computer program 911, and when the computer program 911 is executed by the processor 920, the steps of the printed circuit board design method provided in any one of the above embodiments are implemented.

[0280] Among them, the processor 920 may include one or more processing cores, such as a 3-core processor, an 8-core processor, etc. The processor 920 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 920 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 920 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 920 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0281] The memory 910 may include one or more non-volatile storage media, which may be non-transitory. The memory 910 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 910 is at least used to store the following computer program 911, wherein the computer program 911, after being loaded and executed by the processor 920, can implement the relevant steps in the printed circuit board design method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 910 may also include an operating system 912 and data 913, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 912 may be Windows or other types of operating systems. Data 913 may include, but is not limited to, the data involved in the above method.

[0282] In some embodiments, the printed circuit board design device may further include a display screen 930 , a power supply 940 , a communication interface 950 , an input / output interface 960 , a sensor 970 , and a communication bus 980 .

[0283] Those skilled in the art will understand that Fig. 9 The structure shown in the figure does not constitute a limitation of the printed circuit board design device, and may include more or fewer components than shown.

[0284] The printed circuit board design device provided in the embodiment of the present invention includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the steps of the printed circuit board design method provided in the above embodiment, and the effect is the same as above.

[0285] An embodiment of the present invention provides a non-volatile storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the printed circuit board design method provided in any one of the above embodiments can be implemented.

[0286] The non-volatile storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0287] For the introduction of the non-volatile storage medium provided in the embodiment of the present invention, please refer to the above method embodiment, and the effect thereof is the same as the printed circuit board design method provided in the embodiment of the present invention, and the present invention will not elaborate on it here.

[0288] An embodiment of the present invention provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the printed circuit board design method provided in any one of the above embodiments are implemented.

[0289] For an introduction to the computer program product provided by the embodiment of the present invention, please refer to the above method embodiment, and the effect thereof is the same as the printed circuit board design method provided by the embodiment of the present invention, and the present invention will not elaborate on it here.

[0290] The above is a detailed introduction to a printed circuit board design method, device, medium and computer program product provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the devices, equipment, non-volatile storage media and computer program products disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0291] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A printed circuit board design method, characterized in that: include: Receive task parameters of the layout adjustment task of the target board; Identify the key physical circuits on the target board according to the target wiring resources, global wiring positions and key circuit identification conditions in the task parameters; Perform layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component; Outputting the second position, so as to adjust the component layout on the target board according to the second position and then re-execute the wiring task; The critical line identification condition at least includes line utilization, so as to identify the congested physical line as the critical physical line; the second position satisfies that the edge of the component does not exceed the edge of the target board and there is no overlap between the components; The overlap between the second position and the region where the key physical line is located is smaller than the overlap between the first position and the region where the key physical line is located.

2. The printed circuit board design method according to claim 1, characterized in that: According to the target wiring resources, global wiring positions and key line identification conditions in the task parameters, the key physical lines on the target board are identified, including: According to the target wiring resources, the global wiring position and the goal of minimizing the number of wire net removals, a wire net removal optimization calculation is performed to alleviate the congestion of the physical lines of the target board, and an optimal wire net removal is obtained; The critical physical line is determined according to the physical line through which the preferred removal network passes.

3. The printed circuit board design method according to claim 1, characterized in that: According to the target wiring resources, global wiring positions and key line identification conditions in the task parameters, the key physical lines on the target board are identified, including: Perform resource addition calculation for the physical lines of the target board according to the target wiring resources, the global wiring position and the goal of maximizing the congestion relief utility value, and obtain the congestion relief utility value after adding the physical line resources to each of the physical lines; According to the order of the congestion relief utility values ​​of the physical lines from large to small, a first preset number of the physical lines are determined as the key physical lines.

4. The printed circuit board design method according to claim 3, characterized in that: The resource increase calculation of the physical line of the target board is performed according to the target wiring resources, the global wiring position and the goal of maximizing the congestion relief utility value, and the congestion relief utility value after the physical line resources are added to each of the physical lines is obtained, including: Using a pre-trained prediction model, according to the target wiring resources, the global wiring position, and the wire nets of the target board design task of the target board, a congestion relief utility value after adding physical line resources to each edge of the wiring tree of each of the wire nets is calculated; The congestion relief utility value of the physical line is determined according to the congestion relief utility values ​​of the edges of the routing tree passing through the physical line in the global routing position.

5. The printed circuit board design method according to claim 4, characterized in that: The pre-trained prediction model is used to calculate the congestion relief utility value after adding physical line resources to each edge of the wiring tree of each of the wire nets according to the target wiring resources, the global wiring position, and the wire nets of the target board design task, including: The resource increase calculation problem of each physical line is constructed as a constraint relationship graph, wherein each node in the constraint relationship graph corresponds to a dual variable, the dual variable corresponds to the congestion relief utility value of one physical line, an edge between two nodes corresponds to the number of times the two dual variables appear in the same constraint condition, and the characteristics of the node are determined according to the line utilization corresponding to the dual variable; Generate a column vector corresponding to the dual variable according to the constraint relationship graph using a graph convolutional network; Calculate the score corresponding to the dual variable using the query vector and the column vector corresponding to the dual variable; The congestion relief utility value corresponding to the edge of the wiring tree is calculated based on the score of the dual variable corresponding to the edge of the wiring tree and the score of the dual variable corresponding to all the edges of the wiring tree.

6. The printed circuit board design method according to claim 4, characterized in that: Determining the congestion relief utility value of the physical line according to the congestion relief utility value of the edge of the routing tree passing through the physical line in the global routing position includes: If there are multiple routing lines of the wiring tree on the physical line, the smallest congestion relief utility value among them is used as the congestion relief utility value of the physical line.

7. The printed circuit board design method according to claim 4, characterized in that: The training steps of the prediction model include: Constructing a dual problem sample pool, wherein the dual problem sample pool includes a plurality of dual problem samples, and the dual problem samples are maximization optimization problems with given constraints; Solving the dual problem sample using a linear programming solver, and using the obtained solution as a label of the dual problem sample; The prediction model is used to solve the dual problem sample, a training error is calculated according to the obtained solution result and the label corresponding to the dual problem sample, and the model parameters of the prediction model are updated using the training error.

8. The printed circuit board design method according to claim 7, characterized in that: The steps of generating the dual problem sample include: Randomly sampling a second preset number of sample dual variables and a third preset number of sample constraints; Initializing the sample constraint of the dual problem sample to be empty, and adding the sample dual variable to the sample constraint with a first probability; the first probability is sampled from a conjugate prior distribution of a binomial distribution; Calculate the cost coefficient corresponding to each sample dual variable; The constraint conditions are that each of the sample dual variables is greater than or equal to 0, and the sum of the sample dual variables in the sample constraint conditions is less than or equal to 1, and the optimization goal is to minimize the weighted sum of each of the sample dual variables based on the cost coefficient, which is used as the dual problem sample.

9. The printed circuit board design method according to claim 1, characterized in that: The overlap between the second position and the area where the key physical line is located is less than the overlap between the first position and the area where the key physical line is located, including: An overlap between the second position and a virtual barrier of a preset size added at the position of the critical physical line is smaller than an overlap between the first position and the virtual barrier.

10. The printed circuit board design method according to claim 9, characterized in that: Performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component includes: Initializing the size of the virtual obstacle; Performing layout adjustment calculation according to the size of the virtual barrier, the position of the virtual barrier, the first position, and the position of the key physical circuit to obtain the second position of each of the components; After adjusting the position of the component on the target board according to the second position of each component, calling the wiring model to re-calculate the wiring, if the output global wiring position does not meet the wiring requirements, increasing the size of the virtual barrier, returning to perform layout adjustment calculation according to the size of the virtual barrier, the position of the virtual barrier, the first position and the position of the key physical line, to obtain the second position of each component; If the sum of the total area of ​​each virtual barrier and the total area of ​​each component reaches the maximum area allowed by the target wiring resources of the target board, it is determined that the component layout adjustment fails, and a suggestion information for reducing the number of components is output.

11. The printed circuit board design method according to claim 9, characterized in that: Performing layout adjustment calculation according to the current first position of each component on the target board and the position of the key physical circuit to obtain the second position of each component includes: Taking the value of minimizing the component layout adjustment penalty function as the layout adjustment task goal, performing layout adjustment calculation according to the first position and the position of the key physical circuit to obtain the second position; The device layout adjustment penalty function is positively correlated with the overlap between the second position and the virtual barrier, and the device layout adjustment penalty function is positively correlated with the change value of the second position compared with the first position.

12. The printed circuit board design method according to claim 11, characterized in that: The component layout adjustment penalty function is the sum of the layout adjustment constraint penalty value and the component layout change total value; The layout adjustment constraint penalty value is the sum of the component elimination penalty value, the component overlap penalty value, and the component obstacle overlap penalty value; Among them, the more the second position exceeds the target board, the greater the component elimination penalty value; the larger the overlapping area between the components, the greater the component overlap penalty value; the larger the overlapping area between the component and the virtual obstacle, the greater the component obstacle overlap penalty value; the total value of the component layout change is the sum of the distances between each second position and the corresponding first position.

13. A printed circuit board design device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program, and when the computer program is executed by the processor, the steps of the printed circuit board design method as claimed in any one of claims 1 to 12 are implemented.

14. A non-volatile storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the printed circuit board design method according to any one of claims 1 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the printed circuit board design method according to any one of claims 1 to 12 are implemented.

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