Overcurrent protection circuit, chip, gate drive circuit and display device

Abstract

This application discloses an overcurrent protection circuit, a chip, a gate driving circuit, and a display device, belonging to the field of integrated circuit design technology. The overcurrent protection circuit is used in a gate driving circuit, which includes multiple cascaded driving units. The overcurrent protection circuit includes a detection unit connected to the driving units. Each driving unit includes a first switch and a second switch. The first switch can carry a charging current through a load capacitor in a conducting state; the second switch can carry a discharging current through a load capacitor in a conducting state. A first detection circuit in the detection unit can detect whether an overcurrent has occurred in the first switch within a first time window, which begins before the first switch turns off and covers the instant the switch turns off. A second detection circuit in the detection unit can detect whether an overcurrent has occurred in the second switch within a second time window, which begins before the second switch turns off and covers the instant the switch turns off. This improves the reliability of overcurrent protection.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an overcurrent protection circuit, a chip, a gate driving circuit, and a display device. Background Technology

[0002] A gate-driven array (GOA) is a circuit structure integrated onto the substrate of a display panel. A GOA has multiple row drive stages (i.e., GOA units) corresponding to the pixel rows of the display panel. In other words, each drive stage can select a row of pixels, enabling that row to receive data signals. Thus, all drive stages operate sequentially, achieving line-by-line scanning from the first row of pixels to the last row.

[0003] GOA's driver stage may encounter various overcurrent situations in operating scenarios, requiring overcurrent detection and protection to prevent component burnout due to prolonged overcurrent. Overcurrent protection mechanisms in related technologies rely on fixed-length blanking or deglitch time windows. Therefore, excessively long or short time windows can limit or even destroy the effectiveness of the overcurrent protection mechanism, leading to serious consequences such as circuit component burnout and equipment damage. Summary of the Invention

[0004] This application provides an overcurrent protection circuit, a chip, a gate driving circuit, and a display device to solve at least some of the problems in the related art. The technical solution is as follows: In a first aspect, this application provides an overcurrent protection circuit for a gate drive circuit, the gate drive circuit including multiple cascaded drive units, characterized in that the overcurrent protection circuit includes a detection unit connected to the drive units; the drive units include a first switch and a second switch; the first switch is configured to allow charging current to flow through a load capacitor in a conducting state; the second switch is configured to allow discharging current to flow through the load capacitor in a conducting state; the detection unit includes a first detection circuit connected to the first switch and a second detection circuit connected to the second switch; wherein: the first detection circuit is configured to detect whether an overcurrent has occurred in the first switch within a first time window, the first time window beginning before the first switch is turned off and covering the instant when the first switch is turned off; the second detection circuit is configured to detect whether an overcurrent has occurred in the second switch within a second time window, the second time window beginning before the second switch is turned off and covering the instant when the second switch is turned off.

[0005] In some possible implementations, the first switch is connected between the gate turn-on voltage terminal and the load capacitor; the first detection circuit includes: a first sampling resistor configured to be connected in series between the gate turn-on voltage terminal and the first switch; a first comparator configured to be coupled to a first node through a first input terminal, receive a reference voltage through a second input terminal, and output a first detection result through a first output terminal after comparing the voltage at the first node with the reference voltage; wherein, the first node is the node between the first sampling resistor and the first switch, and the first detection result characterizes whether the circuit where the first switch is located is overcurrent.

[0006] In some possible implementations, the second switch is connected between the load capacitor and the gate turn-off voltage terminal; the second detection circuit includes: a second sampling resistor configured to be connected in series between the second switch and the gate turn-off voltage terminal; a second comparator configured to be coupled to a second node via a third input terminal, receive a reference voltage via a fourth input terminal, and output a second detection result via a second output terminal after comparing the voltage at the second node with the reference voltage; wherein, the second node is the node between the second sampling resistor and the second switch, and the second detection result characterizes whether the circuit containing the second switch is overcurrent.

[0007] In some possible implementations, the overcurrent protection circuit further includes a transfer circuit connected to at least one of the first detection circuit and the second detection circuit. The transfer circuit includes a first branch comprising a control unit, a signal processing unit, and an output node. The control unit is configured to receive a current detection result and generate a control signal based on the current detection result. The current detection result is either a first detection result output by the first detection circuit or a second detection result output by the second detection circuit. The signal processing unit is configured to provide a corresponding bias current to the output node based on the control signal, causing the output node to output a detection signal matching the current detection result.

[0008] In some possible implementations, in the domain transition circuit connected to the first detection circuit, the control unit includes a first power transistor connected between the gate turn-on voltage terminal and the output node; the signal processing unit includes a second power transistor and a third power transistor, the second power transistor and the third power transistor being cascaded in sequence and connected between the first power transistor and the voltage source; the output node is the node between the third power transistor and the voltage source; the signal processing unit further includes a fourth power transistor connected between the voltage source and the output node.

[0009] In some possible implementations, the first power transistor is configured to be in an ON state when the current detection result indicates that no overcurrent has occurred, so as to allow current to flow from the gate-on voltage terminal to the signal processing unit; the second power transistor is configured to switch to an ON state when the first power transistor is in an ON state, so as to provide a first bias current from the output node to the third power transistor, the first bias current being used to clamp the output node to a low level.

[0010] In some possible implementations, the first power transistor is configured to be placed in a cutoff state when the current detection result indicates an overcurrent, thereby cutting off the current from the gate-on voltage terminal to the signal processing unit; the second power transistor is configured to switch to a cutoff state when the first power transistor is in the cutoff state; the third power transistor is configured to switch to a cutoff state when the first power transistor is in the cutoff state; and the fourth power transistor is configured to switch to an on state when the first power transistor is in the cutoff state, thereby providing a second bias current from the voltage source to the output node, the second bias current being used to clamp the output node to a high level.

[0011] In some possible implementations, in the domain transition circuit connected to the second detection circuit, the control unit includes a fifth power transistor connected between the gate shutdown voltage terminal and the signal processing unit; the signal processing unit includes a sixth power transistor and a seventh power transistor, which are cascaded in sequence and then connected between the voltage source and the fifth power transistor. The output node is the node between the seventh power transistor and the reference ground; the signal processing unit also includes an eighth power transistor connected between the output node and the reference ground.

[0012] In some possible implementations, the fifth power transistor is configured to be placed in a cutoff state when the current detection result indicates that no overcurrent has occurred, so as to cut off the current from the signal processing unit to the gate shutdown voltage terminal; the sixth power transistor is configured to switch to a cutoff state when the fifth power transistor is in the cutoff state; the seventh power transistor is configured to switch to a cutoff state when the fifth power transistor is in the cutoff state; and the eighth power transistor is configured to switch to an on state when the fifth power transistor is in the cutoff state, so as to provide a third bias current between the output node and the reference ground, the third bias current being used to clamp the output node to a low level.

[0013] In some possible implementations, the fifth power transistor is configured to be turned on when the current detection result indicates an overcurrent, so as to flow current from the signal processing unit to the gate shutdown voltage terminal; the sixth power transistor is configured to switch to the on state when the fifth power transistor is turned on, so as to provide a fourth bias current from the seventh power transistor to the output node, the fourth bias current being used to clamp the output node to a high level.

[0014] In some possible implementations, the domain-switching circuit further includes a second branch whose circuit structure is symmetrical to that of the first branch, and the first branch and the second branch form a differential common-mode structure.

[0015] Secondly, a power management chip is provided, wherein the power management chip includes any of the overcurrent protection circuits described above.

[0016] Thirdly, a gate driving circuit is provided, wherein the gate driving circuit includes any of the overcurrent protection circuits described above.

[0017] Fourthly, a display device is provided, the display device including any of the power management chips or any of the gate driving circuits described above.

[0018] Fifthly, an overcurrent detection method is provided, which is applied to the overcurrent protection circuit in the first aspect and any implementation thereof. The method includes: conducting a charging current to a load capacitor by turning on a first switch; detecting whether an overcurrent occurs in the first switch via a first detection circuit within a first time window, the first time window beginning before the first switch turns off and covering the instant of the first switch turning off; conducting a discharging current to the load capacitor by turning on a second switch; and detecting whether an overcurrent occurs in the second switch via a second detection circuit within a second time window, the second time window beginning before the second switch turns off and covering the instant of the second switch turning off.

[0019] In one possible implementation, a first switch is connected between the gate turn-on voltage VGH and the load capacitor; in the first detection circuit, a first sampling resistor is connected in series between the VGH terminal and the first switch, the first input terminal of the first comparator is coupled to a first node, and the second input terminal is used to receive a reference voltage; in a first time window, the first detection circuit detects whether the first switch has an overcurrent, including: receiving the reference voltage and the voltage at the first node through the first comparator, the first node being the node between the first sampling resistor and the first switch; after comparing the voltage at the first node with the reference voltage, a first detection result is output, wherein the first detection result characterizes whether the circuit where the first switch is located has an overcurrent.

[0020] In one possible implementation, the second switch is connected between the load capacitor and the gate turn-off voltage VGL; in the second detection circuit, the second sampling resistor is connected in series between the second switch and VGL, the third input terminal of the second comparator is coupled to the second node, and the fourth input terminal is used to receive the reference voltage; in the second time window, the second detection circuit detects whether the second switch has an overcurrent, including: receiving the reference voltage and the voltage at the second node through the second comparator, the second node being the node between the second sampling resistor and the second switch; after comparing the voltage at the second node with the reference voltage, the second detection result is output, wherein the second detection result characterizes whether the circuit where the second switch is located has an overcurrent.

[0021] In one possible implementation, the detection unit further includes a domain transfer circuit connected to the first detection circuit or the second detection circuit. The domain transfer circuit includes a first branch, which includes a control unit, a signal processing unit, and an output node. The method further includes: receiving the current detection result through the control unit, and generating a control signal based on the current detection result; the current detection result is either the first detection result or the second detection result; and providing a corresponding bias current to the output node based on the control signal through the signal processing unit, so that the output node outputs a detection signal that matches the current detection result.

[0022] The technical solution provided in this application brings at least the following beneficial effects: In this application, the overcurrent protection circuit, targeting the charging and discharging process of the load capacitor by the gate drive circuit, avoids the instantaneous large current generated at the moment the first / second switch is turned on by using a time window (before the switch is turned off and covering the instant of turn-off), thus preventing false overcurrent detection. Furthermore, since the load capacitor theoretically completes its charging and discharging process before the first and second switches are turned off, the current in the branches containing the first and second switches is theoretically close to zero. Under normal operating conditions (i.e., without short circuits or other abnormalities), no overcurrent signal will appear in the branches containing the first and second switches. Therefore, if a short circuit occurs during the charging and discharging process, regardless of the short circuit duration (i.e., in high refresh rate applications), the residual charge caused by the short circuit pulse can be detected by the detection unit within the time window, and can then be directly determined as a fault overcurrent, triggering the protection action. This eliminates the limitation of blanking time, avoids the dilemma of balancing "avoiding false detection" and "ensuring protection sensitivity," and effectively solves the protection failure problem in high refresh rate applications, achieving accurate overcurrent capture, high overcurrent protection capability, and high reliability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a GOA driver level; Figure 2 This is a short-circuit diagram of a GOA driver stage; Figure 3 This is a schematic diagram of overcurrent protection for a GOA driver level; Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 5 This is a schematic diagram of an overcurrent protection circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of an overcurrent protection circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the sampling process of an overcurrent protection circuit provided in an embodiment of this application; Figure 8 This is a schematic diagram of a short circuit phenomenon in an overcurrent protection circuit provided in an embodiment of this application; Figure 9 This is a circuit diagram illustrating an overcurrent protection circuit provided in an embodiment of this application. Figure 10 This is a schematic diagram of a domain transfer circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of a domain transfer circuit provided in an embodiment of this application; Figure 12 This is a schematic diagram of a domain transfer circuit provided in an embodiment of this application; Figure 13 This is a flowchart illustrating an overcurrent detection method provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0026] With the advancement of display technology, display panels are showing a trend towards high integration and low cost. For example, by using GOA technology to integrate all the horizontal drive signals onto the substrate of the display panel, the gate drive chip is eliminated, thus saving a lot of costs and making the bezels of the display panel narrower, which better meets people's aesthetic needs.

[0027] The driver stage of a GOA mainly includes high-voltage P-channel power transistors (P-channel MOS, PMOS) and high-voltage N-channel power transistors (N-channel MOS, NMOS). For example... Figure 1 As shown in (a), when the PMOS transistor is on and the NMOS transistor is off, the load capacitor C is charged to the gate high voltage (VGH); Figure 1 As shown in (b), when the PMOS transistor is off and the NMOS transistor is on, the load capacitor C discharges to the gate low voltage (VGL). Furthermore, the driving voltage period is matched to the size of the load capacitor C to ensure that the power transistor is on long enough to fully charge / discharge the load capacitor C.

[0028] However, in practical applications, various situations may arise that could lead to an abnormal short circuit between the VGH and VGL terminals. For example: Scenario 1, such as Figure 2 As shown in (a), when the PMOS transistor is turned on, the output is short-circuited to VGL, resulting in an overcurrent situation; Scenario 2, such as Figure 2 As shown in (b), when the NMOS transistor is turned on, the output is short-circuited to VGH, resulting in an overcurrent situation; Scenario 3, such as Figure 2 As shown in (c), the output is directly short-circuited to ground (GND), and at this time, there will be overcurrent regardless of whether the PMOS transistor or the NMOS transistor is turned on; Scenario 4, such as Figure 2 As shown in (d), if there is a short circuit between adjacent channels, for example, if the output of clock channel CLK1 is short-circuited with the output of clock channel CLK4, then when the PMOS transistor of CLK1 is turned on and the NMOS transistor of CLK4 is turned on, VGH and VGL will be connected in series, resulting in a large current.

[0029] Therefore, overcurrent detection and protection are crucial. Overcurrent protection means that once an overcurrent condition is detected, the system will shut down all PMOS and NMOS transistors in the GOA to prevent continuous overcurrent heating from burning out the device.

[0030] Figure 3 Figure (a) shows a schematic diagram of the on / off state of the power transistor (PMOS / NMOS) in the GOA. Figure 3As shown in (a), Pdriver refers to the voltage Vsg of the PMOS transistor (i.e., the voltage between the gate (G) and source (S)). When Pdriver is high, the PMOS transistor is turned on; when Pdriver is low, the PMOS transistor is turned off. Ndriver refers to the voltage Vgs of the NMOS transistor (i.e., the voltage between the gate (G) and source (S)). When Ndriver is high, the NMOS transistor is turned on; when Ndriver is low, the NMOS transistor is turned off. Ipmos refers to the current flowing through the PMOS transistor, and Inmos refers to the current flowing through the NMOS transistor.

[0031] Continue to refer to Figure 3 As shown in (a), under normal operating conditions, when the power transistor is first turned on, it needs to charge / discharge the load capacitor C. Therefore, there is often a relatively large current when the power transistor is turned on. This transient current is large, usually exceeding the overcurrent protection threshold current. However, this is a normal phenomenon and not an overcurrent. Therefore, one overcurrent protection mechanism is to detect the overcurrent when the power transistor (PMOS / NMOS) is turned on, and a blanking time needs to be set to disable the overcurrent protection mechanism during this period to prevent false detection of overcurrent. That is, the overcurrent protection should detect the actual overcurrent in the circuit and should not mistakenly detect the transient current when the power transistor is turned on as an overcurrent. However, in practical applications, the load capacitor C may be large or small, that is, the duration of the transient current may be short or long, while the blanking time is a relatively fixed value. The length of the blanking time is constrained by the load weight and the driving voltage cycle, and cannot be too long or too short. This is due to the following two reasons.

[0032] Reason 1: When the blanking time is short, if the load capacitance C is large and the charging time is long, an overcurrent may be falsely detected after the blanking time. For example... Figure 3 As shown in (b), during over-current protection (ocp), transient currents may still exceed the ocp threshold, leading to false detections. While this can be mitigated by increasing the over-current detection threshold, an excessively high threshold may prevent overcurrent detection when a true short circuit occurs, as shown in (b). Figure 3 As shown in (c), because the OCP threshold is too high, when an overcurrent actually occurs during OCP detection, the short-circuit current is less than the OCP threshold, so it cannot be identified as an overcurrent, i.e., the overcurrent detection fails.

[0033] Reason 2: When the blanking time is long, in cases where the drive voltage cycle is short (such as high refresh rate screens), the entire period during which the power transistor is turned on may be covered by the blanking time, thus losing the overcurrent detection function. Figure 3 As shown in (d), the actual circuit is still in an overcurrent state (the current magnitude is greater than the OCP threshold) after the transient large current transmission ends. However, due to the excessively long blanking time, the overcurrent protection signal cannot be triggered, and the overcurrent detection fails.

[0034] In summary, this overcurrent detection mechanism can only detect and protect against overcurrent relatively accurately when the load capacitance and drive voltage cycle of the GOA are both suitable, which has significant limitations. If the time window is too short, the load capacitance cannot complete the full charge and discharge setup process, and the instantaneous peak current in the initial stage of the circuit will be misjudged as a fault overcurrent, triggering unnecessary protection actions and causing frequent system shutdowns. If the time window is too long, in high refresh rate applications, the duration of the short-circuit pulse is often much shorter than the set blanking time, and the overcurrent protection mechanism will not be able to capture the fault signal in time, causing the protection function to fail, which in turn leads to serious consequences such as burnt-out circuit components and equipment damage.

[0035] This application provides an overcurrent detection circuit. The overcurrent detection circuit mainly involves configuring a corresponding detection circuit for the charging and discharging switch of the load capacitor. The detection circuit can perform overcurrent detection within a time window before the charging and discharging switch is turned off, and this time window covers the instantaneous moment when the charging and discharging switch is turned off. This avoids false judgments caused by detecting the instantaneous large current when the charging and discharging switch is turned on, and can also capture overcurrents caused by short circuits when the charging and discharging switch is turned off. It breaks the dependence on blanking time, resulting in higher reliability.

[0036] To facilitate understanding of the technical solution of this application, a display device provided in this application will be described below.

[0037] Figure 4 This illustration shows a schematic diagram of a display device according to an embodiment of this application. The display device may include a timing controller (TCON), a gate drive circuit (GOA), a source drive chip (SDIC), and a display panel. The display device may also include a power management integrated circuit (PMIC) for providing power to the various chips, the display panel, and related modules / circuits.

[0038] For example, the timing controller TCON is used to control the timing of the display panel and generate scan / data drive signals. For instance, the control signals output by TCON to SDIC via the interface may include a horizontal start signal (STH), a horizontal clock pulse signal (CPH), a data transmission control signal, or a data polarity inversion signal. For example, the control signals output by TCON to the gate drive circuit may include a frame start signal (STV) representing the start of a frame scan, a scan clock pulse signal (CPV), and an enable signal.

[0039] For example, each driver level of GOA is used to control the opening and closing of a row of pixels in the display panel according to the signals transmitted by TCON. For instance, for a display panel with a resolution of 1024×768, GOA needs to sequentially select 768 rows of pixels to enter a data-receiving state (i.e., the on state), with each row's on time being approximately 21.7 microseconds. During this period, SDIC completes the data writing for all pixels in that row.

[0040] For example, SDICs are used to provide image data voltage signals (i.e., grayscale voltages) to selected row pixels. There can be multiple SDICs, the number of which is related to the physical resolution of the display panel. Each SDIC can drive one display area in the display panel for image display. For example, a display panel may require tens to hundreds of SDICs.

[0041] Those skilled in the art will understand that Figure 4 The structure shown does not constitute a limitation on the display device. The display device may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0042] Next, we will introduce an overcurrent protection circuit provided in an embodiment of this application.

[0043] For example, Figure 5 The diagram shown is a structural schematic of an overcurrent protection circuit provided in an embodiment of this application. The overcurrent protection circuit provided in this embodiment can be applied to a gate drive circuit, which can be implemented as follows: Figure 4 The GOA shown, but not limited to.

[0044] like Figure 5 As shown, the gate drive circuit may include multiple cascaded drive units, and the overcurrent protection circuit provided in this application embodiment may include a detection unit connected to the drive unit.

[0045] In this embodiment, the driving unit includes a first switch and a second switch. The first switch is configured to allow charging current to flow through the load capacitor in the on state; for example, and not as a limitation, such as... Figure 6 In an example of a drive unit shown, the first switch PM1 can be a power transistor, such as a PMOS transistor, and is connected between VGH and the load capacitor C1, so that when the first switch PM1 is on (the second switch NM1 is off), the load capacitor C1 is charged to VGH.

[0046] The second switch is configured to allow the discharge current of the load capacitor to flow in the on state; for example, and not as a limitation. Figure 6 As shown, the second switch NM1 can be a power transistor, such as an NMOS transistor, and is connected between VGL and the load capacitor C1. Thus, when the second switch NM1 is turned on (the first switch is turned off), the load capacitor C1 is discharged to VGL.

[0047] Refer again Figure 5 The detection unit may include a first detection circuit connected to the first switch and a second detection circuit connected to the second switch. Wherein: The first detection circuit is configured to detect whether an overcurrent occurs in the circuit where the first switch is located within a first time window, the first time window starting before the first switch is turned off and covering the instant when the first switch is turned off. The second detection circuit is configured to detect whether an overcurrent occurs in the circuit where the second switch is located within a second time window, the second time window starting before the second switch is turned off and covering the instant when the second switch is turned off.

[0048] In this embodiment, at the instant the first / second switch is turned on, the gate drive circuit needs to support the current for charging and discharging the load capacitor. Due to the physical characteristic that the load capacitor voltage cannot change abruptly, a large instantaneous inrush current will be generated in the initial stage of these switches being turned on, forming a "false overcurrent" state. This current is not a real fault overcurrent, but an inherent physical phenomenon in the charging and discharging process of the load capacitor. Before the first and second switches are turned off, the load capacitor has theoretically completed the charging and discharging process. At this time, the current in the branch where the first and second switches are located is theoretically close to zero. That is to say, under normal operating conditions (i.e., without short circuits or other abnormalities, the same below), no overcurrent signal will appear in the branch where the first and second switches are located. Conversely, if a current signal is detected when the first and second switches are turned off, it indicates that a short circuit pulse occurred before this. This current signal is the residual charge caused by the short circuit pulse, that is, an overcurrent has occurred.

[0049] Therefore, this embodiment sets corresponding time windows, namely a first time window and a second time window. The first time window begins before the first switch is turned off and covers the instant the first switch is turned off, and the second time window begins before the second switch is turned off and covers the instant the second switch is turned off. Furthermore, in this overcurrent protection circuit, if the gate drive circuit is in normal working condition and the load capacitor has completed charging and discharging at the instant the first and second switches are turned off (i.e., within the time window), the branch containing the first and second switches will not be detected by the first and second detection circuits for current. If the first and second detection circuits detect a current signal within their respective time windows, they can directly determine it as a fault overcurrent and trigger the protection action. Since the instant the first and second switches are turned on is not within the detection time window, the instantaneous large current will be naturally filtered out, fundamentally avoiding misjudgment.

[0050] In this way, the limitation of blanking time is eliminated, and there is no need to make a difficult balance between "avoiding misjudgment" and "ensuring protection sensitivity". It also effectively solves the protection failure problem in high refresh rate application scenarios. In other words, no matter how short the short circuit pulse time is, the excess charge generated by the short circuit pulse will remain at the moment the switch is turned off (i.e. the set charging and discharging end time) and be accurately captured by the overcurrent protection circuit of this embodiment, so as to achieve efficient and accurate overcurrent protection capability and high reliability.

[0051] It should be noted that, in this embodiment, in combination with Figure 6 As shown, the driving cycle (i.e., charging and discharging duration) of the first switch PM1 and the second switch NM1 is matched to the weight of the capacitive load C1. When the first switch PM1 is turned off, the load capacitor C1 has been fully charged after a long charging period. Therefore, theoretically, no current flows through the branch where the first switch PM1 was turned off. Figure 7 As shown. Figure 7 In the diagram, Pdriver refers to the voltage Vsg of the first switch PM1. When Pdriver is high, the first switch PM1 is open; when Pdriver is low, the first switch PM1 is closed. Ndriver refers to the voltage Vgs of the second switch NM1. When Ndriver is high, the second switch NM1 is open; when Ndriver is low, the second switch NM1 is closed. Ipmos refers to the current flowing through the first switch PM1, and Inmos refers to the current flowing through the second switch NM1. The interval between the two dashed lines represents the time window.

[0052] If a short circuit occurs in the gate drive circuit during the charging process of the load capacitor C1, resulting in a large series current, it can be detected within the first time window. Figure 8The Ipmos current shown is similarly monitored after discharge, and the OCP detection follows the same principle. If the load capacitor C1 is heavy, or the drive voltage cycle is short, and the load capacitor C1 is not fully charged before the first switch PM1 is turned off, and current flows through the branch containing the first switch PM1, then... Figure 9 As shown, based on the detected current Ipmos within the first time window and the fact that the load capacitance C1 before the first switch PM1 turns off has not reached the expected voltage VGH, it can be determined that the current load is too heavy, meaning that the driving voltage cycle of the first switch PM1 is mismatched with the current load capacitance. Therefore, the overcurrent protection circuit of this embodiment can effectively detect such... Figure 8 , 9 The situations shown are highly reliable.

[0053] The overcurrent protection circuit of this application avoids the drawback of the fixed blanking time, which makes it unable to adapt to different light and heavy loads and different driving voltage cycles. The overcurrent protection circuit of this application enables adaptive detection of overcurrent under different loads and different driving voltage cycles (i.e. different refresh rates), which has higher versatility and can meet the requirements of high refresh rate screens.

[0054] The OCP principle of the overcurrent protection circuit provided in the embodiments of this application will be described in detail below.

[0055] Please refer to this again. Figure 6 As shown, the first detection circuit may include: The first sampling resistor R1 is configured to be connected in series between VGH and the first switch PM1; The first comparator D1 is configured to be coupled to the first node S1 through the first input terminal, receive the reference voltage ref through the second input terminal, and after comparing the voltage at the first node S1 with the reference voltage ref, output the first detection result (i.e., OCP signal 1) through the first output terminal. The first node S1 is the node between the first sampling resistor R1 and the first switch PM1, and the first detection result indicates whether the circuit where the first switch PM1 is located is overcurrent.

[0056] In this example, the first sampling resistor R1 converts the current flowing through the first switch PM1 into a detectable voltage signal. Specifically, when current flows through the first sampling resistor R1, a voltage drop proportional to the current magnitude is generated across it. Thus, the first comparator D1 indirectly obtains current information by monitoring the voltage at the first node S1. For example, under normal operating conditions, within the first time window, the current at the first node S1 is small, and the voltage across the first sampling resistor R1 is lower than the reference voltage ref. The first comparator D1 outputs a low-level OCP signal 1 to indicate that there is no overcurrent. As an example, a low level can be represented by the logic value "0".

[0057] Conversely, when a short circuit occurs during the operation of the first switch PM1, the current rises sharply. Regardless of the short-circuit pulse duration, residual charge remains even when the charging of the load capacitor C1 ends, resulting in a voltage drop across the first sampling resistor R1 within the first time window. Consequently, the voltage at the first node S1 exceeds the reference voltage ref of the first comparator D1, causing the first comparator D1 to immediately flip its output, displaying a high-level OCP signal 1 to indicate an overcurrent. This triggers a protection mechanism (such as shutting down the switches in the drive stage) to prevent damage to the gate drive circuit and its downstream circuits. Thus, the detection unit of this overcurrent protection circuit exhibits extremely fast response speed and high accuracy to the drive stage of the gate drive circuit, enabling OCP detection to be completed shortly before the switch is turned off.

[0058] As an example, when the OCP signal 1 is high, the high level can be represented by the logic value "1".

[0059] For example, the first sampling resistor R1 can be in the milliohm (mΩ) range, such as 500 mΩ, to reduce power loss and impact on system efficiency, and to ensure sufficient voltage signal amplitude for more accurate overcurrent detection later.

[0060] For example, the reference voltage ref can be a set value. To ensure detection sensitivity and reduce false detection rate, the reference voltage ref can be tens or hundreds of millivolts (mV), such as 100mV.

[0061] Similar to the first detection circuit, continue to refer to Figure 6 The second detection circuit may include: The second sampling resistor R2 is configured to be connected in series between the second switch NM1 and VGL; The second comparator D2 is configured to be coupled to the second node S2 through the third input terminal, receive the reference voltage ref through the fourth input terminal, and after comparing the voltage at the second node S2 with the reference voltage ref, output the second detection result (i.e., OCP signal 2) through the second output terminal. The second node S2 is the node between the second sampling resistor R2 and the second switch NM1, and the second detection result indicates whether the circuit where the second switch NM1 is located is overcurrent.

[0062] In this example, the detection principle of the second detection circuit is similar to that of the first detection circuit, and will not be described again.

[0063] In this embodiment, both the first comparator D1 and the second comparator D2 are in the low-voltage domain, which reduces power consumption. For example, the first comparator D1 is in the voltage domain from VGH to VGHm5 (i.e., 5 volts (V) lower than VGH), so the generated OCP signal 1 is also in the voltage domain from VGH to VGHm5; similarly, the second comparator D2 is in the voltage domain from VGLp5 (5V higher than VGL) to VGL, so the generated OCP signal 2 is also in the voltage domain from VGLp5 to VGL.

[0064] To save space as much as possible and facilitate the transmission of OCP signal 1 and OCP signal 2 to subsequent circuits, these OCP signals need to be uniformly transferred to a common voltage domain (e.g., 0 to voltage source VDDA). For this reason, in some possible implementations, the overcurrent protection circuit may also include a domain transfer circuit, such as a first domain transfer circuit connected to the first detection circuit and a second domain transfer circuit connected to the second detection circuit.

[0065] For example, the first domain switching circuit may include a first branch, which includes a control unit, a signal processing unit, and an output node, wherein: The control unit is configured to receive the current detection result and generate a control signal based on the current detection result; the current detection result is either the first detection result output by the first detection circuit or the second detection result output by the second detection circuit. The signal processing unit is configured to provide a corresponding bias current to the output node based on the control signal, so that the output node outputs a detection signal that matches the current detection result.

[0066] In one possible example, such as Figure 10 As shown, the control unit may include a first power transistor (such as a PMOS transistor) PM2, which is connected between VGH and the output node S3. The signal processing unit may include a second power transistor (such as an NMOS transistor) NM2 and a third power transistor (such as an NMOS transistor) NM3. The second power transistor NM2 and the third power transistor NM3 are cascaded in order and then connected between the first power transistor PNM1 and the voltage source vdda. For example, the gate and drain of the second power transistor NM2 are shorted and then connected to the gate of the third power transistor NM3. The drain of the third power transistor NM3 is connected to vdda. The sources of both the second power transistor NM2 and the third power transistor NM3 can be connected to reference ground (gnda, not in the reference ground). Figure 11 (As indicated by the Chinese symbol). Output node S3 is the node between the third power transistor NM3 and vdda. A fourth power transistor (such as a PMOS transistor) PM3 is connected between vdda and output node S3.

[0067] Therefore, continue to refer to Figure 10Taking the first transition circuit connected to the first detection circuit as an example, when the first detection circuit determines that no overcurrent has occurred, the low-level OCP signal 1 output by the first comparator D1 is an analog signal, and the voltage of this OCP signal 1 is close to VGHm5 (i.e., located in the voltage domain of the first comparator D1). At this time, the first power transistor PM2 is turned on, allowing current to flow from VGH to the signal processing unit, and the second power transistor NM2 is turned on, causing a potential to be generated near the third power transistor NM3, thereby providing a pull-down current (i.e., the first bias current) from the output node S3 to the third power transistor NM3, pulling the output node S3 down to a low level, so that the detection signal (i.e., OCP signal A) output by the output node S3 is low (voltage domain in the range of 0 to Vdda), indicating that no overcurrent has occurred. This completes the level mapping of the current-voltage transition.

[0068] When the first detection circuit determines that an overcurrent has occurred, the voltage of the high-level OCP signal 1 output by the first comparator D1 is close to VGH (located in the voltage domain of the first comparator D1). At this time, the first power transistor PM2 is cut off, and no current flows to the signal processing unit through VGH. The second power transistors NM2 and NM3 are cut off, and the fourth power transistor PM3 is turned on, thereby providing Vdda as the pull-up current (i.e., the second bias current) to the output node S3, pulling the output node S3 to a high level. The detection signal (i.e., OCP signal B) output by the output node S3 is high, indicating that an overcurrent has occurred. The voltage domain of the OCP signal B is between 0 and Vdda. This completes the level mapping of the current-to-voltage domain.

[0069] Optionally, because the power transistor is constantly in a state of frequent on / off switching, there will be large transient current changes in VGH and VGL. Combined with the effect of parasitic inductance, this will cause significant jitter in VGH and VGL. Therefore, in this embodiment, the first switching circuit adopts a fully differential circuit structure, thus having better power supply noise suppression capability. This ensures that even when VGH and VGL experience severe jitter, the internal output signal of the circuit remains normal and is unaffected by the power supply voltage. Specifically, as... Figure 11As shown, the first domain conversion circuit also includes a second branch symmetrical to the first branch, forming a fully differential common-mode structure. The second branch includes power transistors PM4, PM6, NM4, and NM6. The deployment of power transistors PM4, PM6, NM4, and NM6 can be referenced from the connection relationship of PM2, PM3, NM2, and NM3 in the first branch, and will not be elaborated further. In other words, any change in current or voltage generated in the first branch will be synchronously reflected in the second branch. When power supply jitter occurs (for example, causing jitter in the input signal of the first branch of the domain conversion circuit), it will have the same effect on both the first and second branches. Through the mutual cancellation of the current mirror ratio, common-mode interference in the first domain conversion circuit is eliminated, improving the signal's anti-interference capability. Simultaneously, it ensures the signal accuracy and stability of the output node, making the pull-up and pull-down current levels more precise, thus meeting the overcurrent protection requirements of increasingly popular high refresh rate screens.

[0070] It should be noted that the aforementioned power transistors PM2, PM3, NM2, NM3, PM4, PM6, NM4, and NM6 can perform the current-to-voltage domain conversion within their respective operating voltage ranges. For example, PM2 and PM4 are high-voltage power transistors, and their operating voltage range can be set according to circuit requirements, such as around 30V; PM3, NM2, NM3, PM6, NM4, and NM6 are low-voltage power transistors, and their operating voltage range can be 0-5V, but is not limited to this.

[0071] It is understandable that the second transfer circuit connected to the second detection circuit is similar to the first transfer circuit connected to the first detection circuit. For example, the circuit structure of the second transfer circuit can be referenced. Figure 12 As shown, in the second switching circuit, the control unit includes a fifth power transistor (such as an NMOS transistor) NM7, which is connected between VGL and the signal processing unit. The signal processing unit includes a sixth power transistor (such as a PMOS transistor) PM7 and a seventh power transistor (such as a PMOS transistor) PM8. The sixth power transistor PM7 and the seventh power transistor PM8 are cascaded in order and connected between vdda and the fifth power transistor NM7. For example, the source of the sixth power transistor PM7 and the source of the seventh power transistor PM8 are both connected to vdda. The gate-drain of the sixth power transistor PM7 is shorted and connected to the gate of the seventh power transistor PM8. The drain of the sixth power transistor PM7 is connected to the fifth power transistor NM7, and the drain of the seventh power transistor PM8 is connected to the reference ground gnda. The output node S4 is the node between the seventh power transistor PM8 and the reference ground gnda. The signal processing unit also includes an eighth power transistor NM8 connected between the output node S4 and gnda.

[0072] Therefore, when the second detection circuit determines that no overcurrent has occurred, the low-level OCP signal 2 output by the second comparator D2 is close to VGH (i.e., within the voltage domain of the second comparator D2). At this time, the fifth power transistor NM7 is cut off, preventing current from the signal processing unit to VGH. The sixth power transistor PM7 and the seventh power transistor PM8 are cut off, and the eighth power transistor NM8 is turned on to provide a pull-down current (i.e., the third bias current) from the output node S4 to the eighth power transistor NM8, pulling the output node S4 down to a low level. This makes the detection signal (i.e., OCP signal B) output by the output node S4 low (voltage domain between 0 and Vdda), indicating that no overcurrent has occurred.

[0073] When the second detection circuit determines that an overcurrent has occurred, the high-level OCP signal 2 output by the second comparator D2 approaches VGHp5 (i.e., it is located in the voltage domain of the second comparator D2). At this time, the fifth power transistor NM7 is turned on to allow current to flow from the signal processing unit to VGL, and the sixth power transistor PM7 is turned on to generate a potential near the seventh power transistor PM8, thereby providing a pull-up current from the seventh power transistor PM8 to the output node S4, i.e., the fourth bias current. The fourth bias current can clamp the output node S4 to a high level, so that the detection signal (i.e., OCP signal B) output by the output node S4 is high (voltage domain in the range of 0 to Vdda), indicating that an overcurrent has occurred.

[0074] Similarly, such as Figure 12 The second switching circuit can be constructed as a fully differential common-mode structure, that is, the branch formed by power transistors PM7, PM8, NM7, and NM8 is symmetrical with the branch formed by power transistors PM9, PM10, NM9, and NM10, in order to eliminate common-mode interference in the second switching circuit, improve the anti-interference capability of the signal, and at the same time ensure the signal accuracy and stability of the output node, making the pull-up and pull-down current levels more accurate, which can meet the overcurrent protection requirements of the increasingly popular high refresh rate screens.

[0075] It should be noted that the aforementioned power transistors PM7, PM8, NM7, NM8, PM9, PM10, NM9, and NM10 can perform the current-to-voltage domain conversion within their respective operating voltage ranges. For example, NM7 and NM9 are high-voltage power transistors, and their operating voltage range can be set according to circuit requirements, such as around 30V; PM7, PM8, NM8, PM9, PM10, and NM10 are low-voltage power transistors, and their operating voltage range can be 0-5V, but is not limited to this.

[0076] This application provides an overcurrent detection method, which is applied to an overcurrent protection circuit. The overcurrent protection circuit is connected to a gate drive circuit, and the overcurrent protection circuit is, for example, a... Figure 5 The overcurrent protection circuit shown, the gate drive circuit is, for example, Figure 5The gate drive circuit shown is not limited to this. For example... Figure 13 The process shown may include steps S121 to S124.

[0077] S121, by turning on the first switch, allows the charging current to flow to the load capacitor; S122, in the first time window, the first detection circuit detects whether the first switch has an overcurrent. The first time window begins before the first switch is turned off and covers the instant when the first switch is turned off. S123, by turning on the second switch, allows the discharge current of the load capacitor to flow; S124, in the second time window, the second detection circuit detects whether the second switch has an overcurrent. The second time window begins before the second switch is turned off and covers the instant when the second switch is turned off.

[0078] In one possible implementation, the first switch is connected between the gate turn-on voltage VGH and the load capacitor; in the first detection circuit, the first sampling resistor is connected in series between the VGH terminal and the first switch, the first input terminal of the first comparator is coupled to the first node, and the second input terminal is used to receive the reference voltage; S122 may include: The reference voltage and the voltage at the first node are received by the first comparator. The first node is the node between the first sampling resistor and the first switch. After comparing the voltage at the first node with the reference voltage, the first detection result is output, wherein the first detection result indicates whether the circuit where the first switch is located is overcurrent.

[0079] In one possible implementation, the second switch is connected between the load capacitor and the gate turn-off voltage VGL; in the second detection circuit, the second sampling resistor is connected in series between the second switch and VGL, the third input of the second comparator is coupled to the second node, and the fourth input is used to receive the reference voltage; S124 may include: The reference voltage and the voltage at the second node are received by the second comparator. The second node is the node between the second sampling resistor and the second switch. After comparing the voltage at the second node with the reference voltage, a second detection result is output, which indicates whether the circuit containing the second switch is overcurrent.

[0080] In one possible implementation, the overcurrent protection circuit further includes a switching circuit, which is connected to at least one of the first detection circuit and the second detection circuit. The switching circuit includes a first branch, which includes a control unit, a signal processing unit, and an output node. The method further includes: The control unit receives the current detection result and generates a control signal based on the current detection result; the current detection result is either the first detection result or the second detection result. The signal processing unit provides a corresponding bias current to the output node based on the control signal, so that the output node outputs a detection signal that matches the current detection result.

[0081] It should be noted that the method provided in the above embodiments and the gate drive circuit embodiments belong to the same concept, and the specific implementation process is detailed in the current protection circuit embodiments, which will not be repeated here.

[0082] In an exemplary embodiment, a power management chip is also provided, which may include the overcurrent protection circuit provided in the above embodiments. As an example, the power management chip can be connected to a gate drive circuit to provide multi-channel (connecting each drive stage) overcurrent protection, voltage domain switching, and other functions, which will not be described in detail here.

[0083] In an exemplary embodiment, a gate driving circuit is also provided, which may include the overcurrent protection circuit provided in the above embodiments, for example, implemented as follows: Figure 5 The gate drive circuit structure shown will not be described in detail again.

[0084] In an exemplary embodiment, a display device is also provided, which may include the power management chip or the gate driving circuit provided in the above embodiments, for example, implemented as follows: Figure 4 The display devices shown will not be described in detail.

[0085] In an exemplary embodiment, a computer device is also provided, comprising a processor and a memory, wherein at least one computer program is stored in the memory. The at least one computer program is loaded and executed by one or more processors to enable the computer device to implement any of the overcurrent detection methods described above.

[0086] In an exemplary embodiment, a computer-readable storage medium is also provided, storing at least one computer program. This computer program is loaded and executed by a processor of a computer device to enable the computer to implement any of the overcurrent detection methods described above. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0087] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the overcurrent detection methods described above.

[0088] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0089] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. An overcurrent protection circuit for a gate drive circuit, the gate drive circuit comprising multiple cascaded drive units, characterized in that, The overcurrent protection circuit includes a detection unit connected to the drive unit; the drive unit includes a first switch and a second switch; the first switch is configured to allow charging current to flow through the load capacitor in the on state; the second switch is configured to allow discharging current to flow through the load capacitor in the on state. The detection unit includes a first detection circuit connected to the first switch and a second detection circuit connected to the second switch; wherein: The first detection circuit is configured to detect whether the first switch has an overcurrent in a first time window, the first time window starting before the first switch is turned off and covering the instant when the first switch is turned off. The second detection circuit is configured to detect whether an overcurrent occurs in the second switch within a second time window, the second time window beginning before the second switch is turned off and covering the instant the second switch is turned off.

2. The overcurrent protection circuit according to claim 1, characterized in that, The first switch is connected between the gate turn-on voltage terminal and the load capacitor; The first detection circuit includes: The first sampling resistor is configured to be connected in series between the gate turn-on voltage terminal and the first switch; A first comparator is configured to be coupled to a first node via a first input terminal, receive a reference voltage via a second input terminal, and output a first detection result via a first output terminal after comparing the voltage at the first node with the reference voltage; wherein, the first node is the node between the first sampling resistor and the first switch, and the first detection result characterizes whether the circuit where the first switch is located is overcurrent.

3. The overcurrent protection circuit according to claim 1 or 2, characterized in that, The second switch is connected between the load capacitor and the gate turn-off voltage terminal; The second detection circuit includes: The second sampling resistor is configured to be connected in series between the second switch and the gate turn-off voltage terminal; The second comparator is configured to be coupled to the second node via the third input terminal, receive a reference voltage via the fourth input terminal, and output a second detection result via the second output terminal after comparing the voltage at the second node with the reference voltage; wherein the second node is the node between the second sampling resistor and the second switch, and the second detection result characterizes whether the circuit where the second switch is located is overcurrent.

4. The overcurrent protection circuit according to claim 1, characterized in that, The overcurrent protection circuit further includes a transfer circuit, which is connected to at least one of the first detection circuit and the second detection circuit. The transfer circuit includes a first branch, which includes a control unit, a signal processing unit, and an output node, wherein: The control unit is configured to receive the current detection result and generate a control signal based on the current detection result; the current detection result is either a first detection result output by the first detection circuit or a second detection result output by the second detection circuit. The signal processing unit is configured to provide a corresponding bias current to the output node based on the control signal, so that the output node outputs a detection signal that matches the current detection result.

5. The overcurrent protection circuit according to claim 4, characterized in that, In the domain switching circuit connected to the first detection circuit, the control unit includes a first power transistor, which is connected between the gate turn-on voltage terminal and the output node. The signal processing unit includes a second power transistor and a third power transistor, wherein the second power transistor and the third power transistor are cascaded in order and connected between the first power transistor and the voltage source; The output node is the node between the third power transistor and the voltage source; The signal processing unit also includes a fourth power transistor connected between the voltage source and the output node.

6. The overcurrent protection circuit according to claim 5, characterized in that, The first power transistor is configured to be in the ON state when the current detection result indicates that no overcurrent has occurred, so as to allow current to flow from the gate turn-on voltage terminal to the signal processing unit; The second power transistor is configured to switch to the on state when the first power transistor is in the on state, so as to provide a first bias current from the output node to the third power transistor, the first bias current being used to clamp the output node to a low level.

7. The overcurrent protection circuit according to claim 5 or 6, characterized in that, The first power transistor is configured to be placed in a cutoff state when the current detection result indicates that an overcurrent has occurred, so as to cut off the current from the gate turn-on voltage terminal to the signal processing unit; The second power transistor is configured to switch to the cutoff state when the first power transistor is in the cutoff state; The third power transistor is configured to switch to the cutoff state when the first power transistor is in the cutoff state; The fourth power transistor is configured to switch to the on state when the first power transistor is in the off state, so as to provide a second bias current from the voltage source to the output node, the second bias current being used to clamp the output node to a high level.

8. The overcurrent protection circuit according to claim 4, characterized in that, In the domain switching circuit connected to the second detection circuit, the control unit includes a fifth power transistor, which is connected between the gate shutdown voltage terminal and the signal processing unit; The signal processing unit includes a sixth power transistor and a seventh power transistor. The sixth power transistor and the seventh power transistor are cascaded in order and then connected between the voltage source and the fifth power transistor. The output node is the node between the seventh power transistor and the reference ground; The signal processing unit also includes an eighth power transistor connected between the output node and the reference ground.

9. The overcurrent protection circuit according to claim 8, characterized in that, The fifth power transistor is configured to be placed in a cutoff state when the current detection result indicates that no overcurrent has occurred, so as to cut off the current from the signal processing unit to the gate shutdown voltage terminal; The sixth power transistor is configured to switch to the cut-off state when the fifth power transistor is in the cut-off state; The seventh power transistor is configured to switch to the cutoff state when the fifth power transistor is in the cutoff state; The eighth power transistor is configured to switch to the on state when the fifth power transistor is in the off state, so as to provide a third bias current between the output node and the reference ground, the third bias current being used to clamp the output node to a low level.

10. The overcurrent protection circuit according to claim 8 or 9, characterized in that, The fifth power transistor is configured to be turned on when the current detection result indicates that an overcurrent has occurred, so as to allow current to flow from the signal processing unit to the gate turn-off voltage terminal. The sixth power transistor is configured to switch to the on state when the fifth power transistor is in the on state, so as to provide a fourth bias current from the seventh power transistor to the output node, the fourth bias current being used to clamp the output node to a high level.

11. The overcurrent protection circuit according to any one of claims 4-10, characterized in that, The domain-switching circuit also includes a second branch, the circuit structure of which is symmetrical to that of the first branch, and the first branch and the second branch form a differential common-mode structure.

12. A power management chip, characterized in that, The power management chip includes the overcurrent protection circuit as described in any one of claims 1 to 11.

13. A gate driving circuit, characterized in that, The gate drive circuit includes the overcurrent protection circuit as described in any one of claims 1 to 11.

14. A display device, characterized in that, The display device includes the power management chip of claim 12 or the gate driving circuit of claim 13.

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