oscillator

Abstract

This disclosure relates to an oscillator. A first reference current source and a second reference current source generate currents with opposite temperature characteristics and output summed reference currents. The ring oscillator outputs an output signal having an oscillation frequency corresponding to the reference current. The first reference current source has a first diode connected in series, and a first n-type transistor, a second n-type transistor, and a twelfth n-type transistor. The gate of the second n-type transistor is connected to a node, and the gate of the first n-type transistor is connected to ground. The second reference current source has a third n-type transistor and a second diode connected in series, a fourth n-type transistor, a fifth p-type transistor, and a first resistor connected in series, and a sixth p-type transistor forming a current mirror with the fifth p-type transistor. The gates of the third n-type transistor and the fourth n-type transistor are connected to the anode of the second diode. The second n-type transistor is connected to another node.

Description

Cross-reference to related applications

[0001] The disclosure (including the specification, drawings and abstract) of Japanese Patent Application No. 2024-221807, filed on December 18, 2024, is incorporated herein by reference in its entirety. Background Technology

[0002] This disclosure relates to an oscillator, and for example, to an oscillator for use under conditions of changing surrounding environment.

[0003] Oscillators are widely used to provide a clock signal for a circuit. Such oscillators need to output a signal with a fixed oscillation frequency, unaffected by the operating environment.

[0004] The following is a technique disclosed.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2004-48690

[0006] Patent Document 1 discloses an oscillator capable of preventing a decrease in oscillation frequency as temperature rises. When the power supply voltage is 1.8V, the oscillator in Patent Document 1 has an oscillation frequency of 2.8MHz at -40°C and an oscillation frequency of 3.6MHz at 150°C. Furthermore, when the power supply voltage is 2.5V, the oscillator in Patent Document 1 has an oscillation frequency of 2.1MHz at -40°C and an oscillation frequency of 2.7MHz at 150°C. Summary of the Invention

[0007] However, when the oscillator in Patent Document 1 is used to generate the clock to be supplied to a flip-flop included in a digital circuit, the oscillation frequency may vary too much. The flip-flop needs to preferably ensure setup and hold times. Setup time is the shortest time before the data input of the flip-flop should stabilize before the clock edge rises. Hold time is the shortest time after the clock edge rises for the data input of the flip-flop to stabilize.

[0008] When the oscillation frequency of the oscillator that generates the clock changes with temperature, the timing of the clock's rise and fall also changes. Therefore, the time periods used for setup and hold become shorter. Consequently, sufficient setup and hold times cannot be guaranteed. Therefore, an oscillator capable of suppressing the frequency variation with temperature is needed.

[0009] Other objects and novel features will become clear from the description in this specification and the accompanying drawings.

[0010] According to one embodiment, an oscillator includes a first current source, a second current source, and a ring oscillator. The first current source generates a first current with a positive temperature characteristic based on a power supply voltage output from a power source. The second current source generates a second current with a negative temperature characteristic based on the power supply voltage and outputs a reference current obtained by adding the first and second currents. The ring oscillator outputs an output signal with an oscillation frequency based on the reference current. The oscillator also includes multiple inverters, in which transistors of a first conductivity type and transistors of a second conductivity type are complementaryly connected. The first current source includes a first diode and a first transistor of a first conductivity type connected in series between the power source and ground, and a second transistor of a first conductivity type and a second resistor connected in series between the second current source and ground. The control terminal of the second transistor is connected to a node between the first diode and the first transistor. The control terminal of the first transistor is connected to ground. The second current source includes a third transistor of a first conductivity type and a second diode connected in series between the power source and ground, a fifth transistor of a second conductivity type, a fourth transistor of a second conductivity type and a first resistor connected in series between the power source and ground, and a sixth transistor of a second conductivity type. The sixth transistor has one end connected between the power source and the ring oscillator and forms a current mirror with the fifth transistor. The control terminals of each of the third and fourth transistors are connected to the anode of the second diode. The second transistor is connected between the node between the fourth and fifth transistors and the second resistor.

[0011] According to one embodiment, an oscillator capable of maintaining an oscillation frequency regardless of temperature can be provided. Attached Figure Description

[0012] Figure 1 This is a graph showing the relationship between the drain-source current and the gate-source voltage of a MOS transistor;

[0013] Figure 2 This is a circuit diagram showing the configuration of a typical ring oscillator;

[0014] Figure 3 This is a diagram schematically illustrating the relationship between the temperature characteristics of a MOS transistor and the temperature characteristics of the oscillation frequency of a ring oscillator;

[0015] Figure 4 This is a circuit diagram showing the configuration of the oscillator according to the first embodiment;

[0016] Figure 5 This is a diagram illustrating the current flow in the oscillator according to the first embodiment;

[0017] Figure 6 Each figure depicts simulation results showing the current in the oscillator according to the first embodiment;

[0018] Figure 7 This is a table indicating the simulation results of the oscillation frequency in the oscillator according to the first embodiment;

[0019] Figure 8 This is a circuit diagram showing the configuration of the oscillator according to the second embodiment;

[0020] Figure 9 It is a table showing the relationship between the on / off state of the indicator switch and the reference current value;

[0021] Figure 10 This is a circuit diagram showing the configuration of the oscillator according to the third embodiment;

[0022] Figure 11 The eye diagrams of the output signals of each oscillator are depicted when noise is superimposed on the supply voltage; and

[0023] Figure 12 This is a circuit diagram showing the configuration of the oscillator according to the fourth embodiment. Detailed Implementation

[0024] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings. In each drawing, components having the same function are indicated by the same reference numerals, and repeated descriptions thereof will be omitted as necessary.

[0025] As a prerequisite for understanding the oscillator described in the following embodiments, the relationship between the metal-oxide-semiconductor (MOS) transistors constituting the oscillator and the oscillation frequency will be described.

[0026] The threshold voltage V of a MOS transistor is typically used. t And the gain factor β, the drain-source current I of the MOS transistor ds With gate-source voltage V gs The relationship between them is represented by the following expression. [Equation 1] [1]

[0027] Using the mobility μ of a MOS transistor and the gate oxide capacitor C ox The channel width W and channel length L, and the gain coefficient β are represented by the following expressions. [Equation 2] [2]

[0028] Based on the above expression, the drain-source current I will be described. ds With gate-source voltage V gs The relationship between them. Figure 1This shows the drain-source current I of the MOS transistor. ds With gate-source voltage V gs A graph showing the relationship between the gain coefficient β and the threshold voltage V of a MOS transistor. t Both exhibit negative temperature characteristics, with drain-source current I... ds With gate-source voltage V gs The relationship between them varies with temperature. Specifically, as the temperature increases, β in expression [1] decreases, and therefore the drain-source current I... ds The rate of change decreases. Therefore, in Figure 1 In the process, as the temperature increases, the drain-source current I is indicated. ds The slope of the curve decreases. Furthermore, as the temperature increases, V in expression [1]... t The smaller the value, the more the drain-source current I is indicated. ds The curve shifts to the left. Therefore, as... Figure 1 As shown, the drain-source current I ds With gate-source voltage V gs The relationship between them is divided into two regions. Region 1 is the drain-source current I. ds The region where the drain-source current I increases at high temperatures compared to low temperatures. Region 2 is the drain-source current I. ds The region that becomes larger at low temperatures than at high temperatures.

[0029] Next, a typical ring oscillator will be described. Figure 2 This is a circuit diagram illustrating a typical configuration of a ring oscillator 10. The ring oscillator 10 is configured such that complementary metal-oxide-semiconductor (CMOS) inverters INV1 to INVm are connected in parallel between the power supply VCC and ground. In each inverter, a p-type transistor MP and an n-type transistor MN are connected in series. However, note that m is an integer equal to or greater than 2. Note that in the following description, the p-type transistor MP is also referred to as the tenth transistor, and the n-type transistor MN is also referred to as the eleventh transistor. Furthermore, in the following description, the power supply voltage output from the power supply VCC is referred to as the power supply voltage VCC.

[0030] The input of CMOS inverter INV1 and the output of CMOS inverter INVm are connected to the output terminal OUT. The outputs of CMOS inverters INV1 to INVm-1 are connected to the corresponding inputs of CMOS inverters INV2 to INVm. In other words, when k is an integer equal to or greater than 1 and equal to or less than m-1, the output of CMOS inverter INVk is connected to the input of its adjacent CMOS inverter INVk+1.

[0031] When the rise and fall delay times of the output voltage of each inverter stage are both expressed as td At that time, the oscillation frequency f of the ring oscillator 10 OSC It is represented by the following expression. [Equation 3] [3]

[0032] As is generally known, with the drain-source current I of a MOS transistor... ds Increase the delay time t of each inverter stage d It becomes smaller. Therefore, due to the temperature characteristics of the MOS transistor, based on the delay time t... d The determined oscillation frequency f OSC Temperature characteristics are also generated in the middle.

[0033] Figure 3 This schematically illustrates the temperature characteristics of the MOS transistor and the oscillation frequency f of the ring oscillator 10. OSC A graph showing the relationship between temperature characteristics. Figure 1 In region 1, when the transistors included in the ring oscillator 10 are operating, the drain-source current I increases as the ambient temperature rises. ds It increases, and therefore, according to expression [3], the oscillation frequency f OSC It increases. In this case, the oscillation frequency f OSC It has positive temperature characteristics.

[0034] On the contrary, Figure 1 In region 2, when the transistors included in the ring oscillator 10 are operating, the drain-source current I increases as the ambient temperature rises. ds It becomes smaller, and therefore, according to expression [3], the oscillation frequency f OSC It decreases. In this case, the oscillation frequency f OSC It has negative temperature characteristics.

[0035] Given the recent demand for low power consumption, ring oscillators are also needed to reduce power consumption P. OSC To achieve this, the power supply voltage VCC to the ring oscillator and the current consumption I of the ring oscillator need to be reduced. OSC The power consumption P of the ring oscillator is considered valid. OSC It is represented by the following expression. [Equation 4] [4]

[0036] Current consumption I of the ring oscillator OSC The gate charging / discharging current I of the MOS transistor charge and direct current I pene The sum is represented by . [Equation 5] [5]

[0037] Gate charge / discharge current I charge This can be expressed by the following expression. However, note that C is the total gate capacitance of the MOS transistors that constitute the ring oscillator 10. [Equation 6] [6]

[0038] Direct current I pene Represented by the following expression. [Equation 7] [7]

[0039] As described above, in order to reduce the power consumption P of the ring oscillator 10 OSC Lowering the power supply voltage VCC is effective.

[0040] In the case of being simply referred to as a transistor below, it means a MOS transistor. As for transistor, it is also abbreviated as Tr. One of the source and drain terminals of a MOS transistor is called one terminal, and the other is also called the other terminal, and its gate is also called the control terminal.

[0041] like Figure 1 As shown, the oscillator according to Patent Document 1 prevents the oscillator frequency from decreasing as the temperature increases. However, since the oscillator frequency changes significantly with increasing temperature, it is difficult to use the oscillator for clock generation in digital circuits, as described above. First Embodiment

[0042] Oscillator 100 is a circuit that oscillates due to the power supply voltage supplied from the power source. In the following description, the power supply voltage output from the power source VCC is also referred to as the power supply voltage VCC. Figure 4 This is a circuit diagram showing an oscillator 100 according to a first embodiment. The oscillator 100 according to the first embodiment includes a reference current source 1, a reference current source 2, and a ring oscillator 3. The reference current sources 1 and 2 are referred to as the first current source and the second current source, respectively.

[0043] In the oscillator 100, the current I is obtained by adding the current I1 from the reference current source 1 with positive temperature characteristics and the current I2 from the reference current source 2 with negative temperature characteristics. REF It is supplied to the ring oscillator 3. Therefore, the oscillator 100 cancels the current I caused by temperature change. REF The change in temperature suppresses the oscillation frequency of the ring oscillator 3.

[0044] Reference current source 1 is configured as a current source with positive temperature characteristics. Reference current source 1 has a diode D1 and n-type transistors M1, M2, and M90. In the first embodiment, n-type transistors M1, M2, and M90 are depletion-type MOS transistors.

[0045] Diode D1 and n-type transistor M1 are connected in series between power supply VCC and ground GND. The anode of diode D1 is connected to power supply VCC. The cathode of diode D1 is connected to the drain of n-type transistor M1. The source and gate of n-type transistor M1 are connected to ground GND.

[0046] n-type transistors M2 and M90 are connected in series between reference current source 2 and ground GND. The drain of n-type transistor M2 is connected to the node between the drain of p-type transistor M5 and the drain of n-type transistor M4 of reference current source 2, as described below. The source of n-type transistor M2 is connected to the drain of n-type transistor M90. The gate of n-type transistor M2 is connected to node N between the cathode of diode D1 and the drain of n-type transistor M1. B The source and gate of the n-type transistor M90 are connected to ground (GND).

[0047] The n-type transistor M90 is provided as a resistor in the reference current source 2 and can be replaced by a typical resistor element. In the following description, the n-type transistor M9 is also referred to as the second resistor.

[0048] As described above, reference current source 1 is configured using a depletion-type MOS transistor and is therefore used as a normally-on current source.

[0049] In the following description, n-type transistors M1 and M2 are also referred to as the first transistor and the second transistor, respectively. n-type transistor M90 is also referred to as the twelfth transistor. Diode D1 is also referred to as the first diode.

[0050] Reference current source 2 is configured as a current source with negative temperature characteristics. Reference current source 2 includes a diode D2, a resistor R1, n-type transistors M3 and M4, and p-type transistors M5 and M6. In the first embodiment, n-type transistor M3 is a depletion-mode MOS transistor. n-type transistor M4 and p-type transistors M5 and M6 are enhancement-mode MOS transistors.

[0051] An n-type transistor M3 and a diode D2 are connected in series between the power supply VCC and ground GND. The drain of the n-type transistor M3 is connected to the power supply VCC. The source of the n-type transistor M3 is connected to the gate of the n-type transistor M3 and the anode of the diode D2. The cathode of the diode D2 is connected to ground GND.

[0052] P-type transistor M5, n-type transistor M4, and resistor R are connected in series between power supply VCC and ground GND. The source of p-type transistor M5 is connected to power supply VCC. The drain of p-type transistor M5 is connected to the gate of p-type transistor M5, the drain of n-type transistor M4, and the drain of n-type transistor M2. Resistor R1 is connected between the source of n-type transistor M4 and ground GND. The gate of n-type transistor M4 is connected to node N between the source of n-type transistor M3 and the anode of diode D2. A .

[0053] p-type transistors M5 and M6 form a current mirror circuit. The source of p-type transistor M6 is connected to the power supply VCC. The drain of p-type transistor M6 is connected to the ring oscillator 3. The gate of p-type transistor M6 is connected to the gate of p-type transistor M5.

[0054] As described above, reference current source 2 is configured using a depletion-type MOS transistor and is therefore used as a normally-on current source.

[0055] In the following description, n-type transistors M3 and M4 are also referred to as the third and fourth transistors, respectively. P-type transistors M5 and M6 are also referred to as the fifth and sixth transistors, respectively. Diode D2 is also referred to as the second diode, and resistor R1 is referred to as the first resistor.

[0056] Ring oscillator 3 has the same characteristics as Figure 2 The ring oscillator 3 has the same configuration as the ring oscillator 10. The ring oscillator 3 is supplied with a reference current I from the drain of the p-type transistor M6 of the reference current source 2. REF Other configurations of the ring oscillator 3 are the same as those of the ring oscillator 3. Figure 2 The configuration of the ring oscillator 10 is the same, and therefore its redundant description will be omitted.

[0057] Next, the operation of oscillator 100 will be described. First, the temperature characteristics of the current flowing in reference current source 2 will be investigated. Figure 5 This is a diagram illustrating the current flow in the oscillator 100 according to the first embodiment. The forward voltage of diode D2 is set to V. F [D2], and the temperature is set to T. The reverse voltage V of diode D2... F When the temperature characteristic of [D2] is negative, the following expression is satisfied. [Equation 8] [8]

[0058] Therefore, the node N between the source of n-type transistor M3 and the anode of diode D2 A voltage V A The temperature characteristic is negative, as shown in the following expression. [Equation 9] [9]

[0059] Here, assuming the temperature characteristic of resistor R1 is approximately 0, the temperature characteristic of the current I2 flowing through n-type transistor M4 and resistor R1 is also negative, as shown in the following expression. Note that the description of the temperature characteristic of resistor R1 being approximately 0 indicates that the temperature characteristic of resistor R1 is equal to or close to 0. To provide resistor R1 with a temperature characteristic equal to or close to 0, for example, resistor R1 can be configured as a polysilicon resistor. [Equation 10]

[10]

[0060] Next, the temperature characteristics of the current flowing in reference current source 1 will be investigated. The forward voltage of diode D1 is set to V. F [D1]. The forward voltage V of diode D1 F When the temperature characteristic of [D1] is negative, the following expression is satisfied. [Equation 11]

[11]

[0061] Therefore, node N between the cathode of diode D1 and the drain of n-type transistor M1 B Voltage V at point B The temperature characteristic is negative, as shown in the following expression. [Equation 12]

[12]

[0062] The drain-source voltage V of the n-type transistor M90 DS When the temperature characteristics between [M90] are positive, the following expression is satisfied. [Equation 13]

[13]

[0063] In this case, the temperature characteristics of the current I1 flowing in the n-type transistors M2 and M90 are also positive, as shown in the following expression. [Equation 14]

[14]

[0064] As described above, the current flowing in the p-type transistor M5 of reference current source 2 is the sum of currents I1 and I2. Therefore, the reference current I flowing in the p-type transistor M6, which forms a current mirror circuit with p-type transistor M5, is... REF It is also the sum of currents I1 and I2. [Equation 15]

[15]

[0065] As shown in expression

[15] , the reference current I REF The currents I1 and I2 included in the oscillator have opposite temperature characteristics. Therefore, it is found that temperature-dependent changes in current I1 and current I2 cancel each other out. Thus, in the oscillator 100, the reference current I can be suppressed. REF Temperature changes.

[0066] Figure 6 A graph depicts the simulation results for each oscillator 100 according to the first embodiment. (See figure.) Figure 6 As shown, currents I1 and I2 have opposite temperature characteristics. Conversely, as a result of the cancellation of the temperature characteristics of currents I1 and I2, a reference current I, which is the sum of currents I1 and I2, is... REF It exhibits moderately positive temperature characteristics. Overall, the transistors included in the oscillator 100... Figure 1 When the power supply voltage VCC is equal to or greater than 1.9V in region 2, the reference current I can be preferably suppressed. REF The changes.

[0067] Figure 7 This is a table indicating the simulation results of the oscillation frequency in the oscillator 100 according to the first embodiment. For example... Figure 7 As shown, it was found that compared to the case of supplying current I1 or I2 to the ring oscillator 3, the supply current I REF This further reduces the range of oscillation frequency variation.

[0068] As described above, according to this configuration, by adding the currents with opposite temperature characteristics generated in the two reference current sources and supplying the resulting summed current to the ring oscillator, temperature variations in the current supplied to the ring oscillator can be suppressed. Consequently, temperature variations in the oscillation frequency of the oscillator can be suppressed. Second Embodiment

[0069] In the first embodiment, an oscillator capable of reducing temperature variations in oscillation frequency has been described. However, due to variations in manufacturing processes, the oscillation frequency of the oscillator may exhibit individual differences. Therefore, in this embodiment, an oscillator will be described that can be finely adjusted using a reference current I. REF To adjust the oscillation frequency of the ring oscillator 3.

[0070] Figure 8This is a circuit diagram illustrating the configuration of an oscillator according to the second embodiment. The oscillator 200 is configured such that the reference current source 2 of the oscillator 100 is replaced by a reference current source 4. The reference current source 4 has a configuration in which the p-type transistor M6 of the reference current source 2 is replaced by p-type transistors M61 to M64. Furthermore, compared to the reference current source 2, switches SW1 to SW4 are added to the reference current source 4.

[0071] The sources of p-type transistors M61 to M64 are connected to the power supply VCC. Switches SW1 to SW4 are positioned between the corresponding drains of p-type transistors M61 to M64 and the ring oscillator 3. The gates of p-type transistors M61 to M64 are connected to the gate of p-type transistor M5.

[0072] In this configuration, p-type transistors M61 and M64 are transistors with different dimensions from each other. For example, p-type transistor M61 is the same size as p-type transistor M5. P-type transistor M62 is twice the size of p-type transistor M5. P-type transistor M63 is four times the size of p-type transistor M5. P-type transistor M64 is eight times the size of p-type transistor M5.

[0073] Therefore, by switching SW1 to SW4 on / off, the oscillator 200 can adjust the reference current I. REF The value of . Figure 9 It indicates the on / off state of switches SW1 to SW4 and the reference current I. REF A table showing the relationships between the values. Figure 9 An example is shown where a value of 1 μA is obtained by adding the currents I1 and I2 flowing in the p-type transistor M5. For example... Figure 9 As shown, by appropriately selecting any one of the switches SW1 to SW4, the reference current I can be adjusted in 15 stages. REF The value of .

[0074] The control unit (not shown) can provide a switching signal to any of the switches SW1 to SW4 to achieve on / off control of the switches SW1 to SW4.

[0075] Therefore, the oscillator 200 can fine-tune the reference current I. REF This is to suppress the change in the oscillation frequency of the ring oscillator 3 caused by process variations. Third Embodiment

[0076] In the oscillator according to the above embodiment, when noise is superimposed on the power supply voltage VCC, the noise propagates into the ring oscillator 3. As a result, jitter can appear on the output signal OUT, which is used as a clock signal.

[0077] For example, we will examine the case where the oscillator according to the above embodiments is installed in an integrated circuit (IC) in an automobile. For instance, the noise immunity of automotive ICs has attracted attention in the automotive industry regarding the International Electrotechnical Commission (IEC) standards. In the IEC standards, IEC 62132-4 (Direct Power Injection (DPI) method) is standardized as an immunity test for electromagnetic compatibility (EMC). In the DPI method, radio frequency (RF) signals, typically in the range of 150 kHz to 1 GHz, are injected into local pins (pins connected to components in the electronic control unit (ECU), including other ICs, but not to external components outside the ECU), resulting in ±600 mV (based on 50 Ω) of noise superimposed on the power supply terminals. As a result, even with noise superimposed on the power supply terminals of the IC, the IC is required to remain fault-free.

[0078] When noise is superimposed on the power supply voltage, it can also be superimposed on the output signal of the oscillator mounted in the IC. Therefore, an oscillator with excellent noise immunity is required. In view of this, this embodiment will describe an oscillator capable of suppressing the effects of noise superimposed on the power supply voltage VCC.

[0079] Figure 10 This is a circuit diagram illustrating the configuration of the oscillator 300 according to the third embodiment. The oscillator 300 is configured such that the reference current source 2 of the oscillator 100 according to the first embodiment is replaced by a reference current source 5. Furthermore, a capacitor C2 is added to the oscillator 300 compared to the oscillator 100.

[0080] Reference current source 5 is configured to have a capacitor C1 added to reference current source 2. Capacitor C1 is connected to the power supply VCC and the node between the gates of p-type transistor M5 and p-type transistor M6. The path through which noise superimposed on the power supply voltage is introduced via capacitor C1 is also referred to as the first bypass path. Furthermore, capacitor C1 is also referred to as the first capacitor.

[0081] Capacitor C2 is connected between the drain of p-type transistor M6 and ground GND. The path through which noise superimposed on the power supply voltage is introduced via capacitor C2 is also called the second bypass path. In the following description, capacitor C2 is also referred to as the second capacitor.

[0082] Next, the noise reduction caused by capacitors C1 and C2 will be described. In the reference current source 5, providing capacitor C1 reduces the impact of noise superimposed on the p-type transistor M5. In this case, capacitor C1 can be designed such that its impedance is less than the impedance of the p-type transistor M5.

[0083] Here, the transconductance of the p-type transistor M5 is denoted as gm[M5]. The frequency of the noise applied to the power supply VCC is denoted as f. In this case, to make the impedance of capacitor C1 less than the impedance of the p-type transistor M5, the following expression must be satisfied. [Equation 16]

[16]

[0084] Therefore, capacitor C1 is represented by the following expression. [Equation 17]

[17]

[0085] Furthermore, providing a capacitor C2 in the oscillator 300 reduces the impact of noise superimposed on the p-type transistor M6 on the ring oscillator 3. In this case, the capacitor C2 can be designed such that its impedance to noise is less than the impedance of the p-type transistor M6, as shown in the following expression. Here, the voltage change between the drain and source of the p-type transistor M6 when noise of frequency f is applied is expressed as ΔV. DS [M6]. Furthermore, the current change between the drain and source of the p-type transistor M6 is expressed as ΔI. DS [M6] [Equation 18]

[18]

[0086] Therefore, capacitor C2 is represented by the following expression. [Equation 19]

[19]

[0087] As described above, capacitors C1 and C2 are designed to satisfy expressions

[17] and

[19] , thereby effectively reducing the impact of noise superimposed on the power supply voltage VCC on the ring oscillator 3.

[0088] Figure 11 Eye diagrams of the output signal of each oscillator are depicted when noise is superimposed on the power supply voltage VCC. Figure 11 In this case, ±600mV of noise is superimposed on the power supply voltage VCC. The eye diagrams of oscillator 100 and oscillator 300 are compared. In the eye diagram of oscillator 100, the output signal OUT is expanding, and the eye diagram is noticeably narrower. Conversely, in the eye diagram of oscillator 300, the expansion of the output signal OUT is significantly suppressed, and the eye is clearly visible. Therefore, in oscillator 300, providing a bypass path for noise effectively suppresses the degradation of output signal quality due to noise.

[0089] As described above, according to the oscillator 300, a bypass path is provided for power supply noise propagating into the ring oscillator 3 so that the effect of noise on the ring oscillator 3 can be suppressed. Fourth embodiment

[0090] In the above embodiments, it has been described that the n-type transistors M1 to M3 and M90 are depletion-type MOS transistor oscillators. However, some of the n-type transistors M1 to M3 and M90 can be replaced with enhancement-type MOS transistors.

[0091] Figure 12 This is a circuit diagram illustrating the configuration of an oscillator 400 according to a fourth embodiment. The oscillator 400 has a configuration in which reference current sources 1 and 2 of the oscillator 100 are replaced with reference current sources 11 and 12, respectively. Furthermore, compared to the oscillator 100, the oscillator 400 has a bias circuit 21 added thereto.

[0092] Reference current source 11 has a configuration where the depletion-type n-type transistor M1 of reference current source 1 is replaced with an enhancement-type n-type transistor M11. Reference current source 12 has a configuration where the depletion-type n-type transistor M3 of reference current source 2 is replaced with a resistor R2.

[0093] The bias circuit 21 has enhancement-type n-type transistors M21 and M22, a p-type transistor M23, and a current source CS. The n-type transistors M21 and M22, and the p-type transistor M23 are enhancement-type MOS transistors. In the following description, the n-type transistors M21 and M22, and the p-type transistor M23, are also referred to as the seventh to ninth transistors, respectively.

[0094] The current source CS and the n-type transistor M21 are connected in series between the power supply VCC and ground GND. The current source CS is connected between the power supply VCC and the drain of the n-type transistor M21. The source of the n-type transistor M21 is connected to ground GND. The gate of the n-type transistor M21 is connected to the drain of the n-type transistor M21, the gate of the n-type transistor M22, and the gate of the n-type transistor M11.

[0095] P-type transistor M23 and n-type transistor M22 are connected in series between power supply VCC and ground GND. The source of p-type transistor M23 is connected to power supply VCC. The drain of p-type transistor M23 is connected to the gate of p-type transistor M23, the gate of n-type transistor M13, and the drain of n-type transistor M22. The source of n-type transistor M22 is connected to ground GND. As described above, the gate of n-type transistor M22 is connected to the gate of n-type transistor M21 and the gate of n-type transistor M11.

[0096] Therefore, n-type transistors M11, M21, and M22 constitute a current mirror circuit. n-type transistors M13 and M23 also constitute a current mirror circuit. Therefore, the bias voltage generated by the bias circuit 21 is applied to the gates of n-type transistors M11 and M13.

[0097] According to this configuration, oscillator 400 can perform the same operation as oscillator 100 according to the first embodiment. Therefore, even if some depletion-type transistors included in the oscillator are replaced with enhancement-type transistors, an oscillator capable of performing the same operation can be obtained. Other embodiments

[0098] While this disclosure has been described above with reference to embodiments, it is not limited to the embodiments described above. Various modifications to the configurations and details of this disclosure, as will be understood by those skilled in the art, can be made within the scope and spirit of this disclosure. Furthermore, embodiments can be appropriately combined with each other.

[0099] As described in the above embodiments, it is assumed that both reference current source 1 and reference current source 11 have an n-type transistor M90 disposed therein, but the n-type transistor M90 can be replaced with a resistor. In this case, in order to suppress temperature characteristics, the resistor can preferably be configured as a polysilicon resistor.

[0100] Each accompanying drawing is merely an example illustrating one or more embodiments. Each of the drawings is not associated with only one specific embodiment, but may be associated with one or more other embodiments. As those skilled in the art will understand, various features or steps described with reference to any of the drawings may be combined with features or steps shown in one or more other drawings to produce embodiments, such as those not explicitly shown in the drawings or described in the specification. Not all features or steps shown in any drawing used to describe exemplary embodiments are essential, and some features or steps may be omitted. The order of steps in any drawing may be changed as needed.

Claims

1. An oscillator, comprising: The first current source generates a first current with positive temperature characteristics based on the power supply voltage output from the power supply. The second current source generates a second current with negative temperature characteristics based on the power supply voltage, and outputs a reference current obtained by adding the first current and the second current. as well as A ring oscillator outputs an output signal with an oscillation frequency based on the reference current, and includes multiple inverters in which transistors of a first conductivity type and transistors of a second conductivity type are complementaryly connected. The first current source includes: A first diode and a first transistor of the first conductivity type are connected in series between the power supply and ground, and A second transistor of the first conductivity type and a second resistor are connected in series between the second current source and ground. The control terminal of the second transistor is connected to the node between the first diode and the first transistor. The control terminal of the first transistor is connected to ground. The second current source includes: A third transistor of the first conductivity type and a second diode are connected in series between the power supply and ground. A fifth transistor of the second conductivity type, a fourth transistor of the second conductivity type, and a first resistor are connected in series between the power supply and ground. The sixth transistor of the second conductivity type has one end connected between the power supply and the ring oscillator, and forms a current mirror with the fifth transistor. The control terminal of each of the third and fourth transistors is connected to the anode of the second diode, and The second transistor is connected between the node between the fourth transistor and the fifth transistor and the second resistor.

2. The oscillator according to claim 1, Wherein the first to the third transistors are depletion-type metal-oxide-semiconductor (MOS) transistors, and The fourth to sixth transistors are enhancement-mode MOS transistors.

3. The oscillator according to claim 1, further comprising: The bias circuit supplies a bias voltage to the first current source. The bias circuit includes: A current source and a seventh transistor of the first conductivity type are connected in series between the power supply and ground, and A ninth transistor of the first conductivity type and an eighth transistor of the second conductivity type are connected in series between the power supply and ground. The first transistor, the seventh transistor, and the eighth transistor constitute a current mirror. The third transistor and the ninth transistor constitute a current mirror. Wherein the first transistor and the third to ninth transistors are enhancement-mode metal-oxide-semiconductor (MOS) transistors, and The second transistor is a depletion-type MOS transistor.

4. The oscillator according to claim 2, When the gate-source voltage is greater than a predetermined value, the MOS transistor has a drain-source current with negative temperature characteristics, and The power supply voltage is set such that the gate-source voltage of the first transistor through the sixth transistor and the transistor of the ring oscillator is greater than the predetermined value.

5. The oscillator according to claim 1, The sixth transistor includes: Multiple transistors, connected in parallel and having different sizes from each other, and Multiple switches, each inserted between each of the multiple transistors and the ring oscillator, and The value of the reference current can be switched by switching each of the plurality of switches.

6. The oscillator according to claim 1, The second current source includes a first bypass path connecting the power supply, the control terminal of the fifth transistor, and the control terminal of the sixth transistor. The first bypass path is configured such that the impedance of the noise superimposed on the power supply voltage supplied to the fifth transistor is lower than that of the fifth transistor.

7. The oscillator according to claim 6, The second current source further includes a first capacitor connected between the power supply and the control terminal of the fifth transistor and the control terminal of the sixth transistor.

8. The oscillator according to claim 1, comprising: A second bypass path connects the second current source and ground; the ring oscillator is not inserted between the second current source and ground. The second bypass path is configured such that the impedance of the noise superimposed on the reference current supplied to the ring oscillator is lower than that of the ring oscillator.

9. The oscillator according to claim 1, further comprising: The second capacitor is connected between the node between the second current source and the ring oscillator and ground.

10. The oscillator according to claim 1, The first resistor is configured such that the temperature characteristic of its resistance value is equal to or close to 0.

11. The oscillator according to claim 10, The first resistor is configured as a polysilicon resistor.

12. The oscillator according to claim 1, Each of the plurality of inverters in the ring oscillator includes a tenth transistor of the first conductivity type, one end of which is supplied with the reference current, and an eleventh transistor of the second conductivity type, one end of which is connected to the tenth transistor and the other end of which is connected to ground. The gates of the tenth and eleventh transistors are connected to each other as the input of the inverter, and the node between the tenth and eleventh transistors is configured as the output. The input of the inverter in the first stage is connected to the output of the inverter in the last stage, and the inverter in the second stage is connected to the inverter in the stage immediately preceding the last stage, with the output of the inverter in the previous stage connected to the input of the inverter in the next stage.

13. The oscillator according to claim 1, The second resistor is the twelfth transistor of the first conductivity type, which is connected between the second transistor and ground and has a control terminal connected to ground.

14. The oscillator according to claim 1, The first conductivity type is n-type, and the second conductivity type is p-type.

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