Oscillator

Abstract

A low power oscillator maintains its oscillation frequency regardless of environmental conditions. The oscillator comprises a reference current source, a voltage source and a ring oscillator. The reference current source outputs a reference current dependent on the first supply voltage, and the voltage source outputs a second supply voltage dependent on the reference current. The oscillation frequency of the ring oscillator depends on the second supply voltage.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2024-135327, filed on August 14, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to oscillators, particularly oscillators used under conditions of changing ambient environment. Background Technology

[0004] Oscillators are widely used to supply operating clocks to circuits. These oscillators need to output a signal with a constant oscillation frequency, unaffected by the operating environment.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2001-68976

[0007] Patent Document 1 discloses an oscillator that outputs a signal with a constant oscillation frequency regardless of temperature. In this oscillator, when the oscillation frequency of the ring oscillator has a negative temperature characteristic, the power supply voltage supplied to the ring oscillator has a positive temperature characteristic, thereby maintaining the constant oscillation frequency of the ring oscillator.

[0008] Furthermore, the oscillator in Patent Document 1 can reduce the variation in oscillation frequency caused by changes in the transistor threshold voltage due to manufacturing variations. In an oscillator, if the threshold voltage of a MOS (metal-oxide-semiconductor) transistor varies due to manufacturing errors, the oscillation frequency decreases when the threshold voltage is high and increases when the threshold voltage is low. Patent Document 1 proposes a method to counteract the variation in oscillation frequency by generating a power supply voltage using a MOS transistor with a threshold voltage variation similar to that of a ring oscillator. Summary of the Invention

[0009] As will be described later, it is known that, depending on the gate-source voltage, a MOS transistor exhibits an operating state in which the drain-source current has a positive temperature characteristic and an operating state in which the drain-source current has a negative temperature characteristic.

[0010] When a ring oscillator composed of MOS transistors is used to configure the oscillator, the oscillation frequency exhibits a negative temperature characteristic under operating conditions where the drain-source current has a negative temperature characteristic. In this case, the oscillator configuration proposed in Patent Document 1 can maintain a constant oscillation frequency.

[0011] However, in recent years, there has also been a demand for reducing oscillator power consumption. When the power supply voltage to the oscillator is reduced to decrease power consumption, the gate-source voltage of the MOS transistor decreases, resulting in a smaller drain-source current. In this case, the drain-source current of the MOS transistor will have a positive temperature characteristic, and as a result, the oscillation frequency of the ring oscillator will also exhibit a positive temperature characteristic. Therefore, the oscillator in Patent Document 1 cannot maintain a constant oscillation frequency while achieving low power consumption.

[0012] Other issues and novel features will become apparent from the description in this specification and the accompanying drawings.

[0013] According to one embodiment, the oscillator includes: a current source configured to output a reference current dependent on a first power supply voltage from a power source; a voltage source configured to output a second power supply voltage dependent on the reference current; and a ring oscillator having a plurality of inverters and configured to output an output signal having an oscillation frequency based on the second power supply voltage, each inverter including a first conductivity type transistor and a second conductivity type transistor connected complementary to each other. The current source includes a first transistor of the first conductivity type, a fourth transistor of the second conductivity type, a fifth transistor of the first conductivity type, and a sixth transistor of the second conductivity type. The first, fourth, fifth, and sixth transistors are connected in series between the power source and ground in this order. The current source also includes a second transistor of the first conductivity type, a seventh transistor of the second conductivity type, and a resistor. The second and seventh transistors and the resistor are connected in series between the power source and ground in this order. The current source further includes a third transistor of the first conductivity type, which is coupled between the power source, the voltage source, and the ring oscillator, and is configured to output the reference current to the voltage source and the ring oscillator. A first, second, and third transistor form a first current mirror that replicates the current flowing through the second transistor. A fourth and seventh transistor form a second current mirror that replicates the current flowing through the fourth transistor. The control terminals of the fifth and sixth transistors are coupled to the node between the fifth and sixth transistors. The voltage source includes an eighth transistor having a first conductivity type and a ninth transistor having a second conductivity type. The eighth and ninth transistors are coupled in series between the power supply and ground. The terminals of the eighth and ninth transistors are coupled to the node between the eighth and ninth transistors.

[0014] According to one embodiment, a low-power oscillator can be provided that is able to maintain an oscillation frequency regardless of environmental conditions. Attached Figure Description

[0015] Figure 1This is a graph showing the relationship between the drain-source current and the gate-source voltage of a MOS transistor.

[0016] Figure 2 This is a circuit diagram showing the configuration of a typical ring oscillator.

[0017] Figure 3 This is a graph schematically illustrating the relationship between the temperature characteristics of a MOS transistor and the temperature characteristics of the oscillation frequency of a ring oscillator.

[0018] Figure 4 This is a circuit diagram showing the configuration of the oscillator according to the first embodiment.

[0019] Figure 5 This is a circuit diagram showing the configuration of the oscillator according to the second embodiment.

[0020] Figure 6 This is a circuit diagram showing the configuration of the oscillator according to the third embodiment.

[0021] Figure 7 This is a diagram illustrating noise propagation in an oscillator according to a third embodiment. Detailed Implementation

[0022] Embodiments of the present invention will now be described with reference to the accompanying drawings. In each drawing, the same elements are indicated by the same reference numerals, and repeated descriptions are omitted where necessary.

[0023] First embodiment. As a prerequisite for understanding the oscillator according to the first embodiment, the relationship between the MOS (metal-oxide-semiconductor) transistor constituting the oscillator and the oscillation frequency will be described.

[0024] Using the threshold voltage Vt and gain coefficient β of a MOS transistor, the relationship between the drain-source current Ids and the gate-source voltage Vgs of a MOS transistor is generally expressed by the following equation.

[0025] [Equation 1]

[0026] I ds =0.5β·(V gs -V t ) 2 [1]

[0027] Using the mobility μ, gate oxide capacitance Cox, channel width W, and channel length L of a MOS transistor, the gain coefficient β is expressed by the following equation.

[0028] [Equation 2]

[0029]

[0030] Based on the above equation, the relationship between drain-source current Ids and gate-source voltage Vgs will be described. Figure 1 This is a graph showing the relationship between the drain-source current Ids and the gate-source voltage Vgs of a MOS transistor. Since both the gain coefficient β and the threshold voltage Vt of a MOS transistor have negative temperature characteristics, the relationship between the drain-source current Ids and the gate-source voltage Vgs changes with temperature. Specifically, as the temperature increases, β in equation [1] decreases, thus the rate of change of the drain-source current Ids decreases. Therefore, in… Figure 1 In the equation [1], the slope of the curve indicating the drain-source current Ids decreases with increasing temperature. Furthermore, as temperature increases, Vt in equation [1] decreases, thus shifting the curve indicating the drain-source current Ids to the left. Therefore, as... Figure 1 As shown, the relationship between drain-source current Ids and gate-source voltage Vgs is divided into region 1 and region 2. In region 1, drain-source current Ids is larger at higher temperatures than at lower temperatures. In region 2, drain-source current Ids is larger at lower temperatures than at higher temperatures.

[0031] Next, a general ring oscillator will be described. Figure 2 This is a circuit diagram illustrating the configuration of a typical ring oscillator 10. The ring oscillator 10 is configured by coupling CMOS (Complementary Metal-Oxide-Semiconductor) inverters INV1 to INVm, where a p-type transistor MP and an n-type transistor MN are coupled in series and connected in parallel between the power supply VDD and ground. Here, m is an integer of 2 or greater. In the following text, the p-type transistor MP is also referred to as the tenth transistor, and the n-type transistor MN is also referred to as the eleventh transistor. Furthermore, in the following text, the power supply voltage output from the power supply VDD is represented as the power supply voltage VDD.

[0032] The input of CMOS inverter INV1 and the output of CMOS inverter INVm are coupled to the output terminal OUT. The outputs of CMOS inverters INV1 to INVm-1 are coupled to the inputs of CMOS inverters INV2 to INVm, respectively. In other words, if k is an integer of 1 or greater and m-1 or less, the output of CMOS inverter INVk is coupled to the input of the adjacent CMOS inverter INVk+1.

[0033] The oscillation frequency fOSC of the ring oscillator 10 is expressed by the following equation, where td is the rise and fall delay time of the output voltage of each inverter stage.

[0034] [Equation 3]

[0035]

[0036] Generally, it is known that as the drain-source current Ids of a MOS transistor increases, the delay time td of each inverter stage becomes smaller. Therefore, due to the temperature characteristics of the MOS transistor, the oscillation frequency fOSC determined by the delay time td also exhibits temperature characteristics.

[0037] Figure 3 This is a graph schematically illustrating the relationship between the temperature characteristics of a MOS transistor and the temperature characteristics of the oscillation frequency fOSC of a ring oscillator 10. When the transistor of the ring oscillator 10 is at... Figure 1 When operating in region 1, the drain-source current Ids increases with increasing ambient temperature, resulting in a higher oscillation frequency fOSC according to equation [3]. In this case, the oscillation frequency fOSC exhibits a positive temperature characteristic.

[0038] On the other hand, when the transistor constituting the ring oscillator 10 is in Figure 1 When operating in region 2, the drain-source current Ids decreases as the ambient temperature increases, resulting in a lower oscillation frequency fOSC according to equation [3]. In this case, the oscillation frequency fOSC exhibits a negative temperature characteristic.

[0039] The aforementioned Patent Document 1 only considers the case where the oscillation frequency of the ring oscillator has a negative temperature characteristic in region 2, and does not consider the case where the oscillation frequency of the ring oscillator has a positive temperature characteristic in region 1. In other words, Patent Document 1 can only solve the operation of the MOS transistor in region 2.

[0040] Given the recent demand for low power consumption, it is also necessary to reduce the power consumption POSC of the ring oscillator. This can be effectively achieved by reducing the ring oscillator's supply voltage VDD and its current consumption IOSC. The power consumption POSC of the ring oscillator is expressed by the following equation.

[0041] [Equation 4]

[0042] P OSC =I OSC VDD [4]

[0043] The current consumption IOSC of the ring oscillator is expressed as the sum of the gate charging / discharging current Icharge and the current flow Ipene of the MOS transistor.

[0044] [Equation 5]

[0045] I OSC =I charge +I pene [5]

[0046] The gate charge / discharge current Icharge is expressed by the following equation, where C is the total gate capacitance of the MOS transistor constituting the ring oscillator 10.

[0047] [Equation 6]

[0048] I charge =f OSC ·C·VDD [6]

[0049] The current Ipene is expressed by the following equation.

[0050] [Equation 7]

[0051] I pene ∝f OSC ·(VDD-V t ) 2 [7]

[0052] As can be seen from the above, reducing the power supply voltage VDD is effective in reducing the power consumption POSC of the ring oscillator 10. However, reducing the power supply voltage VDD causes a decrease in the drain-source current Ids of the MOS transistor, thus leading to... Figure 1 The operation of the MOS transistor in region 1. In this case, as described above, the method of Patent Document 1 may not be applicable, and it is impossible to suppress fluctuations in the oscillation frequency due to temperature changes.

[0053] Therefore, in this embodiment, an oscillator is described that maintains the oscillation frequency by reducing the power supply voltage of the ring oscillator while reducing current consumption.

[0054] In the following text, when referring to a transistor, it is assumed to mean a MOS transistor. The term "Tr" is also used as an abbreviation for transistor. Furthermore, one of the conductivity types of a MOS transistor, p-type or n-type, is referred to as the first conductivity type, while the other is referred to as the second conductivity type. One of the source and drain terminals of a MOS transistor is referred to as one terminal, and the other as the other terminal, while the gate is also referred to as the control terminal.

[0055] According to this embodiment, the oscillator is configured such that by reducing the power supply voltage of the ring oscillator, the MOS transistor constituting the ring oscillator... Figure 1 Operate in region 1. As mentioned above, in Figure 1 In region 1, the drain-source current Ids of the MOS transistors in the ring oscillator increases with increasing temperature. As a result, the delay time td of each inverter stage decreases, causing the oscillation frequency fOSC to increase.

[0056] Therefore, in order to maintain the oscillation frequency fOSC regardless of temperature, it is sufficient to suppress the increase of the drain-source current Ids of the MOS transistor in the ring oscillator due to temperature rise. To achieve this, it is necessary to provide a negative temperature characteristic to the power supply voltage of the ring oscillator. Therefore, according to this embodiment, the oscillator is configured to provide a negative temperature characteristic to the power supply voltage of the ring oscillator.

[0057] Figure 4 This is a circuit diagram showing the configuration of an oscillator 100 according to a first embodiment. The oscillator 100 according to the first embodiment includes a ring oscillator 1, a voltage source 2, and a reference current source 3.

[0058] Ring oscillator 1 has the same characteristics as Figure 2 The ring oscillator 10 in this circuit has the same configuration. Therefore, redundant explanations are omitted. In the following text, the output voltage of the voltage source 2 supplied to the ring oscillator 1 is referred to as the power supply voltage VDD2.

[0059] Voltage source 2 outputs a power supply voltage VDD2 based on the reference current Ids (MP3) output from reference current source 3. Voltage source 2 is configured by series coupling of p-type transistor MP0 and n-type transistor MN0. The source of p-type transistor MP0 is coupled to the reference current source 3 and the high-potential side of ring oscillator 1, i.e., the source of p-type transistor MP in the inverter from INV1 to INVm. The drain of p-type transistor MP0 is connected to the drain of n-type transistor MN0. The source of n-type transistor MN0 is coupled to ground and the low-potential side of ring oscillator 1, i.e., the source of n-type transistor MN in the inverter from INV1 to INVm. The gates of p-type transistor MP0 and n-type transistor MN0 are coupled to the node between the drains of p-type transistor MP0 and n-type transistor MN0. In the following text, n-type transistor MN0 is also referred to as the eighth transistor, and p-type transistor MP0 is referred to as the ninth transistor.

[0060] The reference current source 3 outputs a reference current Ids (MP3) that depends on the power supply voltage output from power supply VDD1. Reference current source 3 comprises p-type transistors MP1 to MP4, n-type transistors MN1 to MN3, and resistor R1. In the following text, the power supply voltage output from power supply VDD1 is referred to as power supply voltage VDD1.

[0061] In the following text, p-type transistors MP1 to MP3 are also referred to as the first to third transistors, respectively. n-type transistor MN1 is also referred to as the fourth transistor. p-type transistor MP4 is also referred to as the fifth transistor. n-type transistor MN3 is also referred to as the sixth transistor. n-type transistor MN2 is also referred to as the seventh transistor.

[0062] P-type transistor MP1, n-type transistor MN1, p-type transistor MP4, and n-type transistor MN3 are connected in series between power supply VDD1 and ground in this order. That is, the source of p-type transistor MP1 is coupled to power supply VDD1. The drain of p-type transistor MP1 is coupled to the drain of n-type transistor MN1. The source of n-type transistor MN1 is coupled to the source of p-type transistor MP4. The drain of p-type transistor MP4 is coupled to the drain of n-type transistor MN3. The source of n-type transistor MN3 is coupled to ground. The gates of p-type transistor MP4 and n-type transistor MN3 are coupled to the node between the drains of p-type transistor MP4 and n-type transistor MN3.

[0063] The p-type transistor MP2, the n-type transistor MN2, and the resistor R1 are connected in series between the power supply VDD1 and ground in this order. That is, the source of the p-type transistor MP2 is coupled to the power supply VDD1. The drain of the p-type transistor MP2 is coupled to the drain of the n-type transistor MN2. The resistor R1 is inserted between the source of the n-type transistor MN2 and ground.

[0064] The p-type transistor MP3 is coupled between the power supply VDD1 and the high-potential side of the ring oscillator 1 and voltage source 2 (i.e., the node of the power supply voltage VDD2). In other words, the source of the p-type transistor MP3 is coupled to the power supply VDD1, and the drain is coupled to the high-potential side of the ring oscillator 1 and voltage source 2. The p-type transistor MP3 outputs a drain-source current Ids(MP3) as a reference current.

[0065] The gates of p-type transistors MP1 to MP3 are coupled to each other, and the gate and drain of p-type transistor MP2 are coupled. Therefore, p-type transistors MP1 to MP3 form a current mirror that replicates the current flowing through p-type transistor MP2.

[0066] The gate of n-type transistor MN1 is coupled to the drain of n-type transistor MN1 and the gate of n-type transistor MN2. As a result, n-type transistors MN1 and MN2 form a current mirror that replicates the current flowing through n-type transistor MN1.

[0067] Next, the operation of oscillator 100 will be described. The power supply voltage VDD2 output by voltage source 2 is determined by the sum of the gate-source voltage Vgs(MP0) of p-type transistor MP0 and the gate-source voltage Vgs(MN0) of n-type transistor MN0.

[0068] [Equation 8]

[0069]

[0070] In the above equations, Ids(MP0) is the drain-source current of the p-type transistor MP0. Ids(MN0) is the drain-source current of the n-type transistor MN0. B(MP0) is the gain coefficient of the p-type transistor MP0. B(MN0) is the gain coefficient of the n-type transistor MN0. Vt(MP0) is the threshold voltage of the p-type transistor MP0. Vt(MN0) is the threshold voltage of the n-type transistor MN0.

[0071] Since the same current flows through p-type transistor MP0 and n-type transistor MN0, the following equation holds true.

[0072] [Equation 9]

[0073] I ds (MP0)=I ds (MN0)=I ds (MP3)-I OSC [9]

[0074] Next, the drain-source current of the p-type transistor MP3, i.e. the reference current Ids(MP3), will be described. When the W / L of the p-type transistors MP1 and MP2 that constitute the current mirror are the same, the gate-source voltage Vgs(MP1) of the p-type transistor MP1 and the gate-source voltage Vgs(MP2) of the p-type transistor MP2 become equal.

[0075] [Equation 10]

[0076] V gs (MP1)=V gs (MP2)

[10]

[0077] Therefore, the drain-source current Ids(MP1) of p-type transistor MP1 and the drain-source current Ids(MP2) of p-type transistor MP2 also become equal.

[0078] [Equation 11]

[0079] I ds (MP1)=I ds (MP2)

[11]

[0080] Furthermore, when the W / L ratios of the n-type transistors MN1 and MN2 constituting the current mirror are the same, the gate-source voltage Vgs(MN1) of the n-type transistor MN1 and the gate-source voltage Vgs(MN2) of the n-type transistor MN2 become equal.

[0081] [Equation 12]

[0082] V gs (MN1)=V gs (MN2)

[12]

[0083] Therefore, the sum of the gate-source voltage Vgs(MP4) of the p-type transistor MP4 and the gate-source voltage Vgs(MN3) of the n-type transistor MN3 is equal to the product of the drain-source voltage Ids(MP2) of the p-type transistor MP2. This product indicates the potential difference between resistors R1 and R2, as shown in the following equation.

[0084] [Equation 13]

[0085]

[0086] In this configuration, the resistance value of resistor R1 is set such that, under the condition that the gate-source voltage Vgs(MP4) of p-type transistor MP4 and the gate-source voltage Vgs(MN3) of n-type transistor MN3 operate within region 1 when a power supply voltage VDD1, set to reduce power consumption, is supplied. Furthermore, resistor R1 is designed to have a positive temperature characteristic. This can be achieved, for example, by constructing resistor R1 using a diffused resistor or a polysilicon resistor. In the following text, it is assumed that T indicates temperature.

[0087] [Equation 14]

[0088] ΔR1≥ΔT

[14]

[0089] Therefore, the following holds true.

[0090] [Equation 15]

[0091]

[0092] [Equation 16]

[0093]

[0094] Furthermore, since p-type transistors MP2 and MP3 form a current mirror, the following equation holds. In the following equation, WMP2 and WMP3 are the channel widths of p-type transistors MP2 and MP3, respectively. LMP2 and LMP3 are the channel lengths of p-type transistors MP2 and MP3, respectively.

[0095] [Equation 17]

[0096]

[0097] Therefore, according to equation

[16] , the following holds true.

[0098] [Equation 18]

[0099]

[0100] Therefore, in this case, the reference current Ids(MP3) output by the reference current source 3 has a negative temperature characteristic.

[0101] When the temperature rises while the power supply voltage VDD2 remains constant, Figure 1 In region 1, the drain-source voltage of each transistor operating increases. However, since the reference current Ids(MP3) output from reference current source 3 has a negative temperature characteristic, the supply voltage VDD2 output from voltage source 2 decreases as the temperature increases. As a result, the increase in the drain-source voltage of the transistor is offset by the decrease in the supply voltage VDD2, maintaining a constant drain-source voltage of the transistor. Therefore, the oscillation frequency fOSC of ring oscillator 1 is maintained constant regardless of temperature.

[0102] As described above, based on this configuration, it is possible to implement an oscillator that maintains a constant oscillation frequency of the output signal regardless of temperature, while operating the MOS transistors in region 1 with a reduced power supply voltage for low-power operation.

[0103] Second Embodiment

[0104] As a prerequisite for understanding the oscillator according to the second embodiment, first consider the behavior when the power supply VDD1 is activated in the oscillator 100. When the power supply VDD1 in the oscillator 100 is activated, the gate potential of the p-type transistor MP2 starts from VDD1 due to the gate-source capacitance of the p-type transistor MP2 of the reference current source 3. Therefore, the p-type transistor MP2 remains off until the gate-source capacitance of the p-type transistor MP2 is charged by leakage current, etc. Generally, if the temperature is 25 degrees Celsius, the p-type transistor MP2 remains off for about 10 milliseconds to 100 seconds from the activation of the power supply VDD1.

[0105] When p-type transistor MP2 is turned off, reference current source 3 is not operating, so no reference current is output from p-type transistor MP3 to ring oscillator 1. Therefore, ring oscillator 1 does not start.

[0106] In other words, even if the power supply VDD1 is activated, the start-up of the oscillator 100 is delayed by about 10 milliseconds to 100 seconds until the p-type transistor MP2 in the reference current source 3 transitions from the off state to the on state.

[0107] Therefore, in this embodiment, an oscillator that starts operating immediately after being powered on is described.

[0108] Figure 5This is a circuit diagram illustrating the configuration of an oscillator 200 according to a second embodiment. The oscillator 200 has a configuration in which a startup circuit 4 is further provided to the oscillator 100 according to a first embodiment. The startup circuit 4 includes a p-type transistor MP5 and n-type transistors MN4 and MN5. Hereinafter, the p-type transistor MP5 is also referred to as the twelfth transistor. The n-type transistors MN4 and MN5 are also referred to as the thirteenth and fourteenth transistors, respectively.

[0109] The p-type transistor MP5 and the n-type transistor MN4 are connected in series between the power supply VDD1 and ground in this order. That is, the source of the p-type transistor MP5 is coupled to the power supply VDD1. The drain of the p-type transistor MP5 is coupled to the drain of the n-type transistor MN4. The source of the n-type transistor MN4 is coupled to ground. The gates of the p-type transistor MP5 and the n-type transistor MN4 are coupled to the node between the drain of the n-type transistor MN2 and the resistor R1.

[0110] The drain of n-type transistor MN5 is coupled to the gates of p-type transistors MP1 to MP3, and the source is coupled to ground. The gate of n-type transistor MN5 is coupled to the node between the drain of p-type transistor MP5 and the drain of n-type transistor MN4.

[0111] Next, the operation of oscillator 200 will be described. In oscillator 200, before power supply VDD1 is activated, the gate potential of p-type transistor MP5 in startup circuit 4 is pulled down to ground potential by resistor R1 of reference current source 3. When power supply VDD1 is activated in this state, p-type transistor MP5 immediately turns on.

[0112] Therefore, the gate potential of the n-type transistor MN5 becomes the power supply voltage VDD1, and the n-type transistor MN5 turns on. As a result, the gate potential of the p-type transistor MP2 is pulled down to ground. Therefore, the p-type transistor MP2 turns on, the reference current source 3 is activated, and the reference current Ids (MP3) is supplied from the p-type transistor MP3 to the ring oscillator 1.

[0113] In this configuration, the current supply from the p-type transistor MP3 to the ring oscillator 1 typically begins approximately 10 microseconds after the power supply VDD1 is activated, regardless of temperature. Therefore, by providing the startup circuit 4, the oscillator 200 can start up much faster than the oscillator 100.

[0114] After reference current source 3 is activated, the node between n-type transistor MN2 and resistor R1 rises from ground potential, and n-type transistor MN4 turns on. As a result, the node between p-type transistor MP5 and n-type transistor MN4 decreases potential, and n-type transistor MN5 turns off. This automatically stops the operation of startup circuit 4 in pulling the gate of p-type transistor MP2 to ground potential. Therefore, startup circuit 4 automatically stops operating without affecting the operation of oscillator 200.

[0115] As described above, based on the oscillator 200, it can be understood that by providing the startup circuit 4, the reference current source 3 can be quickly activated after the power supply VDD1 is activated.

[0116] Third Embodiment

[0117] In the oscillator according to the above embodiment, if noise is superimposed on the power supply voltage VDD1, the noise can be input to the ring oscillator 1, and the jitter can be superimposed on the output signal OUT used as a clock signal.

[0118] For example, consider the case where the oscillator according to the above embodiment is mounted on an IC (integrated circuit) assembled in an automobile. Regarding the noise immunity of ICs used in automotive applications, for example, IEC 62132-4 (DPI method: Direct Power Injection method), an IEC standard of concern in the automotive industry, is standardized as an EMC (electromagnetic compatibility) immunity test. In the DPI method, the IC is required not to malfunction even when noise of 3.3V ± 600mV (50Ω equivalent) is superimposed on local pins (pins not connected externally to the ECU (Electronic Control Unit) but coupled to components including other ICs within the ECU) typically in the 150kHz to 1GHz range.

[0119] When noise is superimposed on the power supply voltage, it can also be superimposed on the output clock of the oscillator mounted on the IC, thus requiring an oscillator with excellent noise immunity. Therefore, in this embodiment, an oscillator capable of suppressing the effects of noise superimposed on the power supply voltage VDD1 is described.

[0120] Figure 6 This is a circuit diagram illustrating the configuration of an oscillator 300 according to a third embodiment. The oscillator 300 has a configuration in which the reference current source 3 of the oscillator 200 according to the second embodiment is replaced by a reference current source 5, and a capacitor C1 is also provided.

[0121] Reference current source 5 is configured to have an n-type transistor MN6 added to reference current source 3. The n-type transistor MN6 is also referred to as the fifteenth transistor. The n-type transistor MN6 is inserted between the ring oscillator 1 and ground. That is, the drain of the n-type transistor MN6 is connected to the source of the inverters INV1 to INVm of the ring oscillator 1, and the source of the n-type transistor MN6 is connected to ground. The gate of the n-type transistor MN6 is connected to the gate and drain of the p-type transistor MP4 and the n-type transistor MN3.

[0122] Capacitor C1 is inserted between the source of the p-type transistor MP3 of the reference current source 3 and the source of the n-type transistor MN6.

[0123] Next, the operation of oscillator 300 when noise is superimposed on the power supply voltage VDD1 will be described. Figure 7 This is a diagram illustrating noise propagation in the oscillator 300 according to the third embodiment. When noise N is superimposed on the power supply voltage VDD1, noise N propagates to the source of the p-type transistor MP3. Subsequently, noise N branches into a first path P1 and a second path P2, the first path propagating to ground via capacitor C1, and the second path propagating to ground via p-type transistor MP3, p-type transistor MP, N-type transistor MN, and N-type transistor MN6.

[0124] At this point, the impedance Z1 of the first path P1 is expressed by the following equation.

[0125] [Equation 19]

[0126]

[0127] In the above equation, f is the frequency of the noise.

[0128] Furthermore, the impedance Z2 of the second path P2 is expressed by the following equation.

[0129] [Equation 20]

[0130]

[0131] In the above equations, line (MP3) and line (MN6) are the output resistances of p-type transistor MP3 and n-type transistor MN6, respectively. gm(MP0) and gm(MN0) are the transconductances of p-type transistor MP0 and n-type transistor MN0, respectively.

[0132] Generally speaking, the output resistance of a MOS transistor is much greater than the reciprocal of its transconductance. Therefore, the contribution of the reciprocal of the transconductance in equation

[20] can be ignored, thus allowing equation

[20] to be transformed into the following equation

[21] .

[0133] [Equation 21]

[0134] Z2 = r out (MP3)+r out (MN6)

[21]

[0135] Here, if equations

[19] and

[21] are equal, then the following equation holds true.

[0136] [Equation 22]

[0137]

[0138] In this case, the noise at frequency f determined by equation

[22] propagates equally through the first path P1 and the second path P2.

[0139] However, by designing the capacitance value of capacitor C1 such that the impedance Z1 of the first path P1 is less than the impedance Z2 of the second path P2, the noise propagating through the first path P1 can be made larger, for example, ten times larger than the noise propagating through the second path P2. This allows for the effective reduction of noise input to voltage source 2 via the second path P2 by appropriately designing the capacitance value of capacitor C1.

[0140] Next, a specific example of noise reduction via capacitor C1 will be described. In this example, the noise frequency f is set to 150 kHz, and the capacitance value of capacitor C1 is set to 100 pF. At this time, according to equation

[19] , the impedance Z1 of the first path P1 becomes 106 kΩ.

[0141] [Equation 23]

[0142]

[0143] Next, the impedance Z2 of the second path P2 will be examined. The output resistance path of a MOS transistor is generally expressed by the following equation.

[0144] [Equation 24]

[0145]

[0146] In the above equation, λ is the channel length modulation parameter, which is approximately 0.1 / L regardless of whether the MOS transistor is p-type or n-type.

[0147] If the channel length L of the p-type transistor MP0 and the n-type transistor MN0 is 5 μm, then λ becomes 0.02. If the drain-source current Ids(MP0) of the p-type transistor MP0 and the drain-source current Ids(MN0) of the n-type transistor MN0 are 100 μA, then the impedance Z2 of the second path P2 becomes 1000 kΩ.

[0148] [Equation 25]

[0149] Z2 = 2·0.02·100·10 -6 =1000kΩ

[25]

[0150] Therefore, from this specific example, it can be understood that the noise propagating through the first path P1 can be ten times larger than the noise propagating through the second path P2.

[0151] As described above, according to the oscillator 300, by providing a first path P1 (which is a bypass path for power supply noise propagating to the ring oscillator 1 and the voltage source 2), the effect of noise on the output voltage VDD2 of the voltage source 2 can be suppressed.

[0152] Other embodiments have been described above. This disclosure has been explained with reference to embodiments, but it is not limited to the embodiments described above. As will be understood by those skilled in the art, various changes to the configuration and details of this disclosure can be made within the scope of this disclosure. Each embodiment can be appropriately combined with other embodiments.

[0153] The oscillator 300 according to the third embodiment described above has been described as a modified example of the oscillator 200 according to the second embodiment, but this is merely an example. The oscillator 100 according to the first embodiment can provide a noise bypass path by adding a capacitor C1 and an n-type transistor MN6.

[0154] It should be noted that the operation of the oscillator according to the above embodiment has been described with respect to the case where the MOS transistor operates in region 1. However, even when the MOS transistor operates in region 2, the oscillation frequency of the output signal OUT can be kept constant regardless of the temperature.

[0155] Each accompanying drawing is merely illustrative and is used to explain one or more embodiments. Each drawing is not necessarily associated with only one specific embodiment, but may be associated with one or more other embodiments. As those skilled in the art will understand, various features or steps described with reference to any drawing may be combined with features or steps shown in one or more other drawings to create embodiments that are not explicitly illustrated or described. Not all features or steps shown in any drawing are necessary, and some features or steps may be omitted. The order of steps described in any drawing may be changed appropriately.

Claims

1. An oscillator, comprising: A current source is configured to output a reference current that depends on a first supply voltage from the power source; A voltage source is configured to output a second supply voltage that depends on the reference current, and A ring oscillator having multiple inverters and configured to output an output signal having an oscillation frequency based on a second supply voltage, each inverter comprising a first conductivity type transistor and a second conductivity type transistor connected complementary to each other. The current source mentioned above includes: A first transistor having the first conductivity type, a fourth transistor having the second conductivity type, a fifth transistor having the first conductivity type, and a sixth transistor having the second conductivity type are connected in series between the power supply and ground in this order; A second transistor having the first conductivity type, a seventh transistor having the second conductivity type, and a resistor are coupled in series between the power supply and the ground in this order. A third transistor having the first conductivity type is coupled between the power supply, the voltage source, and the ring oscillator, and is configured to output the reference current to the voltage source and the ring oscillator. The first transistor, the second transistor, and the third transistor constitute a first current mirror, which replicates the current flowing through the second transistor. The fourth transistor and the seventh transistor constitute a second current mirror, which replicates the current flowing through the fourth transistor. The control terminals of the fifth transistor and the sixth transistor are coupled to a node between the fifth transistor and the sixth transistor. The voltage source includes an eighth transistor having the first conductivity type and a ninth transistor having the second conductivity type. The eighth transistor and the ninth transistor are coupled in series between the power supply and the ground. The terminals of the eighth transistor and the ninth transistor are coupled to a node between the eighth transistor and the ninth transistor.

2. The oscillator according to claim 1, Each of the first transistor, the second transistor, and the third transistor includes a source and a drain that are supplied with the first power supply voltage, and the control terminals of the first transistor, the second transistor, and the third transistor are coupled to each other. The second transistor includes another of a source and a drain, the other of which is coupled to the control terminal of the second transistor and to one of the source and drain of the seventh transistor. The fourth transistor includes one of a source and a drain, and the other of the source and the drain, wherein one of the source and the drain is coupled to the other of the source and the drain of the first transistor, as well as to the control terminal of the fourth transistor and the control terminal of the seventh transistor, and the other of the source and the drain is coupled to one of the source and the drain of the fifth transistor. The fifth transistor includes another of a source and a drain, which is coupled to a control terminal of the fifth transistor and a control terminal of the sixth transistor, as well as to one of the source and drain of the sixth transistor. The sixth transistor includes another of a source and a drain, which is coupled to ground. The resistor includes one end coupled to the other of the source and drain of the seventh transistor, and the other end coupled to ground. The eighth transistor includes one of a source and a drain, and the other of the source and the drain. One of the source and the drain is coupled to the other of the source and the drain of the third transistor and to the high-potential side of the ring oscillator. The other of the source and the drain is coupled to the control terminal of the eighth transistor and to one of the source and the drain of the ninth transistor and the control terminal of the ninth transistor. The ninth transistor includes another of a source and a drain, which is coupled to the ground and the low-potential side of the ring oscillator.

3. The oscillator according to claim 1, The first power supply voltage is set such that the current flowing through the first transistor to the ninth transistor and the ring oscillator has a negative temperature characteristic, thereby the oscillation frequency of the output signal has a positive temperature characteristic.

4. The oscillator according to claim 1, When the first power supply voltage is supplied, the value of the resistor has a positive temperature characteristic.

5. The oscillator according to claim 1, Each of the transistors in the first to ninth transistors and the ring oscillator comprises a metal-oxide-semiconductor (MOS) transistor, wherein the drain-source current of the MOS transistor has a positive temperature characteristic when the gate-source voltage of the MOS transistor is lower than the predetermined voltage. The first power supply voltage is set such that the gate-to-source voltage of each of the first transistor through the ninth transistor and the transistor of the ring oscillator is lower than the predetermined voltage.

6. The oscillator according to claim 1, Each of the plurality of inverters in the ring oscillator includes a tenth transistor having the first conductivity type and an eleventh transistor having the second conductivity type. The tenth and eleventh transistors are coupled in series between the voltage source and the ground. The source of the tenth transistor is supplied with the second power supply voltage. The gate terminals of both the tenth and eleventh transistors are coupled to each other as inverter inputs. The connection node between the tenth and eleventh transistors is the inverter output. The plurality of inverters are coupled in such a manner that the inverter output of the preceding inverter is coupled to the inverter input of the following inverter, and the inverter output of the last inverter is coupled to the first inverter as its inverter input.

7. The oscillator according to claim 1, further comprising: The startup circuit includes a twelfth transistor having the first conductivity type, a thirteenth transistor and a fourteenth transistor having the second conductivity type, and is configured to activate the current source. The first power supply voltage is supplied to one of the source and drain terminals of the twelfth transistor. One of the source and drain of the thirteenth transistor is coupled to the other of the source and drain of the twelfth transistor, and the other of the source and drain is coupled to ground. The gates of the twelfth and thirteenth transistors are coupled to each other and to the connection node between the seventh transistor and the resistor. The fourteenth transistor is coupled between the control terminal of the first transistor and the ground, and includes a gate coupled to the connection node between the twelfth and thirteenth transistors.

8. The oscillator according to claim 7, further comprising: A bypass path, between the power supply and the ground, without passing through the third transistor and the current source. The bypass path is configured to have an impedance lower than that of noise superimposed on the first power supply voltage, propagating to ground through the third transistor and the voltage source.

9. The oscillator according to claim 8, The bypass path includes a capacitor and a fifteenth transistor, the capacitor being coupled between the high-potential side of the third transistor and ground, and the fifteenth transistor having the second conductivity type being coupled between the low-potential side of the eleventh transistor and ground. The fifteenth transistor includes a control terminal that is coupled to the control terminal of the fifth transistor, and In response to the noise, the capacitor value is set to have an impedance lower than that of the ring oscillator.

10. The oscillator according to claim 1, The first conductivity type is P-type, and the second conductivity type is N-type.

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