Timestamp parallel access method, system and device based on fttr gateway and medium

Abstract

This application discloses a time-stamped parallel access method, system, device, and medium based on an FTTR gateway. When a terminal device sends a delay-sensitive service data frame, a timestamp is injected into the PHY layer encoded stream at the MAC-PHY interface and mapped to preset bits of the Ethernet preamble. The user-side PHY layer of the FTTR gateway extracts the timestamp and generates a frame attribute marker signal during the preamble reception phase. The user-side MAC layer distributes the data frame to different service queues according to the marker signal. The network-side PON module schedules transmission from the corresponding queue according to the uplink time slot type allocated by the OLT and the marker signal. This application utilizes preamble bit flipping to establish PHY layer bypass signaling, completes service determination before buffering, does not modify the frame format, does not occupy the CPU, supports mixed deployment of new and old terminals, and achieves low-latency, zero-overhead parallel access.

Description

Technical Field

[0001] This application relates to the field of FTTR network technology, specifically to a time-stamped parallel access method, system, device, and medium based on an FTTR gateway. Background Technology

[0002] In the actual operation of FTTR networks, there is an increasing number of application scenarios where a single physical port simultaneously carries edge cloud services and internet services. Edge cloud services exhibit latency sensitivity during transmission, requiring end-to-end transmission latency to be kept at a low level; internet services have relatively relaxed latency requirements but have greater bandwidth demands.

[0003] Existing FTTR gateway architectures and various traffic splitting schemes exhibit the following objective phenomena when enabling a single physical port to simultaneously carry both types of services: MAC layer and above solutions (including VLAN, MPLS, policy routing, 802.1ad, etc.) only make traffic splitting decisions after the Ethernet frame is fully received and enters the MAC layer buffer. Due to the uncertainty of queuing time introduced by the MAC layer buffer, the length of time a data frame stays in the buffer fluctuates randomly, causing the differentiated allocation of upstream PON (Passive Optical Network) time slots to be ineffective—the frame loses its temporal correlation with its service type while in the buffer. Pure physical layer rhythm schemes rely on inter-frame intervals or transmission rhythms as classification criteria, but after a frame traverses the MAC layer buffer, the original physical layer rhythm is completely erased by the buffering behavior, making it impossible to reliably couple with the PON time slots.

[0004] In existing technologies, one approach is to differentiate different services using VLAN tags, which requires inserting VLAN tags into the frame header and modifying the standard Ethernet frame format. Another approach is to make traffic splitting decisions at the MAC or network layer using policy routing, but the decision-making time is after the frame has been completely received and entered the buffer. Yet another approach is to classify services based on the physical layer transmission rhythm, but the caching behavior will destroy the original rhythm information.

[0005] The above phenomena indicate that existing systems, without modifying the Ethernet frame format, cannot complete the splitting and marking before the frame traverses the MAC layer buffer. This results in extremely low utilization of PON uplink differentiated time slot resources, and the low-latency requirements of edge cloud services cannot be effectively guaranteed. This highlights the problem of balancing accurate identification of long-term storage service types with the time uncertainty introduced by caching in traditional technologies.

[0006] This problem remains unresolved. Summary of the Invention

[0007] This application aims to solve the technical problems of marking service types without modifying the Ethernet frame format, completing service determination before MAC layer caching, and using physical layer marking to achieve PON uplink time slot adaptive scheduling. It provides a timestamp-based parallel access method, system, device, and medium based on FTTR gateway, which can achieve unmodified frame structure, low latency determination, and differentiated uplink scheduling.

[0008] To achieve the above objectives, this application provides a timestamp-based parallel access method based on an FTTR gateway, applied to an FTTR network. The FTTR network includes terminal equipment and an FTTR gateway. The terminal equipment includes a MAC layer and a PHY layer, and the FTTR gateway includes a user-side MAC layer, a user-side PHY layer, and a network-side PON module. The method includes: when the terminal equipment sends a data frame for a delay-sensitive service, it injects timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer, and maps the timestamp information to preset bits of an Ethernet preamble; the user-side PHY layer extracts the timestamp information during the preamble reception stage and generates a corresponding frame attribute marker signal; the user-side MAC layer receives the frame attribute marker signal and distributes the data frame to different service queues according to the frame attribute marker signal; the network-side PON module schedules the transmission of data frames from the corresponding service queues according to the uplink time slot type allocated by the OLT and the frame attribute marker signal.

[0009] Optionally, the terminal device injects timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer, including: the driver of the terminal device inserts a timestamp pulse through the interface between the MAC layer and the PHY layer during the interframe interval; the PHY layer captures the timestamp pulse and flips a preset bit of the Ethernet preamble.

[0010] Optionally, the user-side PHY layer extracts the timestamp information during the preamble reception stage, including: when the user-side PHY layer detects the preamble sequence, it monitors the level state of a preset bit of the preamble; if the preset bit is high, it generates a frame attribute marker signal representing the delay-sensitive service; if the preset bit is low, it generates a frame attribute marker signal representing a non-delay-sensitive service.

[0011] Optionally, the user-side MAC layer receiving the frame attribute marker signal includes: the user-side PHY layer transmitting the frame attribute marker signal synchronously to the user-side MAC layer along with the received data stream through the interface between the MAC layer and the PHY layer.

[0012] Optionally, the network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marking signal, further including: the service queue includes a delay-sensitive queue and a non-delay-sensitive queue; when the uplink time slot type is a low-delay time slot, the scheduler is configured to take frames from the delay-sensitive queue for transmission; when the uplink time slot type is a standard time slot, the scheduler is configured to take frames from the non-delay-sensitive queue for transmission.

[0013] Preferably, after the network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal, the method further includes a backward compatibility mechanism, specifically including: the user-side PHY layer counting the number of frames for which the timestamp information has not been detected consecutively; when the number of frames reaches a preset range threshold, entering a compatibility mode and stopping the differential parsing of the preamble; and when the timestamp information is detected again, resuming the monitoring mode.

[0014] This application also provides a timestamp-based parallel access system based on an FTTR gateway, used to implement any of the methods described above. The system includes: a terminal device, comprising a MAC layer and a PHY layer, configured to inject timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer when sending data frames for time-sensitive services, and to map the timestamp information to preset bits of an Ethernet preamble; an FTTR gateway, comprising a user-side PHY layer, a user-side MAC layer, and a network-side PON module; the user-side PHY layer is configured to extract the timestamp information during the preamble reception stage and generate a corresponding frame attribute marker signal; the user-side MAC layer is configured to receive the frame attribute marker signal and distribute data frames to different service queues according to the frame attribute marker signal; and the network-side PON module is configured to schedule the transmission of data frames from the corresponding service queues according to the uplink time slot type allocated by the OLT and the frame attribute marker signal.

[0015] Optionally, the FTTR gateway is further configured to: the user-side PHY layer counts the number of consecutive frames for which the timestamp information is not detected; when the number of frames reaches a preset threshold, it enters a compatibility mode and stops differential parsing of the preamble; when the timestamp information is detected again, it resumes monitoring mode.

[0016] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements any of the methods described above.

[0017] This application also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements any of the methods described above.

[0018] The timestamp-based parallel access method, system, device, and medium provided in this application have the following beneficial effects: 1. By injecting a timestamp into the Ethernet preamble, the Ethernet frame format can be modified without changing the timestamp. The timestamp is located before the frame delimiter, so neither the MAC layer of the terminal device nor the user-side MAC layer of the gateway can detect the existence of the timestamp, thus achieving zero-frame format modification. 2. By extracting the timestamp during the preamble reception stage at the user-side PHY layer, the traffic splitting decision is completed before buffering, and the attribution determination is synchronized with frame reception, thus avoiding the buffering from corrupting the service's time attributes; 3. Timestamp injection and extraction are completed through the hardware circuits of the PHY layer of the terminal device and the user-side PHY layer of the FTTR gateway, respectively. The CPU does not intervene in the traffic splitting decision, and zero instruction cycle consumption is achieved, realizing zero CPU overhead and deterministic latency. 4. Through a traffic splitting mechanism based on preamble marking, new and old terminals can be deployed together under the same LAN port without affecting each other, achieving plug-and-play backward compatibility. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the time-stamped parallel access system based on an FTTR gateway according to this application.

[0021] Figure 2 This is a timing diagram of the timestamp-based parallel access method based on an FTTR gateway according to this application.

[0022] Figure 3 This is a schematic diagram of the signal flow in Example 1.

[0023] Figure 4 This is a schematic diagram of the signal flow in Example 2.

[0024] Figure 5 This is a schematic diagram of the signal flow in Example 3. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0027] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0028] 1. Latency-sensitive services: These are applications with strict requirements for end-to-end transmission latency, including edge cloud services, VR services, cloud gaming services, industrial control services, etc., whose latency requirements are usually ≤5ms.

[0029] 2. Preset bit position: refers to the specific bit position in the Ethernet preamble used to carry timestamp information.

[0030] 3. Frame attribute marker signal: This refers to the electrical signal generated by the user-side PHY layer to identify the service type of the data frame, which can be represented as a logic high level or a logic low level.

[0031] 4. Preset range threshold: This refers to the range of frames used to trigger compatibility mode switching. The lower limit of this range is used to avoid frequent false switching, while the upper limit is used to ensure response speed.

[0032] This application utilizes the level inversion of preset bits in the Ethernet preamble to establish a bypass signaling channel for the PHY layer. The transmitting end inserts a timestamp pulse during the frame interval, and the PHY layer performs level inversion on the preset bits of the preamble, without affecting the preamble synchronization function; the standard MAC layer is unaware of this. The receiving end's user-side PHY layer monitors the level value of this preset bit in real time. Since the standard preamble bit pattern is fixed, level changes deviating from the fixed pattern can be instantaneously captured by the analog circuit, without waiting for the complete frame to enter the buffer. The PHY layer generates a frame attribute marker signal based on the level state (high level corresponds to delay-sensitive, low level corresponds to non-delay-sensitive), and transmits it synchronously to the user-side MAC layer via the MAC-PHY interface. The user-side MAC layer distributes data frames to either the delay-sensitive queue or the non-delay-sensitive queue based on the marker signal. The network-side PON module receives the uplink time slot type (low-delay time slot or standard time slot) allocated by the OLT. The scheduler, combining the time slot type and the marker signal, makes a decision: low-delay time slots only retrieve frames from the delay-sensitive queue, and standard time slots only retrieve frames from the non-delay-sensitive queue. In this entire mechanism, service marking and determination are completed at the PHY layer, without modifying the frame content, triggering the CPU, or being transparent to the upper-layer protocol stack. Preset bits in the standard preamble sent by traditional terminals remain at their default levels, and the receiving end identifies them as non-latency-sensitive services. This allows for the mixed deployment of new and old terminals.

[0033] like Figure 2 As shown in the figure, this application provides a timestamp-based parallel access method based on an FTTR gateway, applied to an FTTR network. The FTTR network includes terminal devices and an FTTR gateway. The terminal devices include a MAC layer and a PHY layer, and the FTTR gateway includes a user-side MAC layer, a user-side PHY layer, and a network-side PON module. The method specifically includes timestamp injection and mapping, timestamp extraction and frame attribute tag generation, frame attribute tag signal transmission and queue distribution, and adaptive scheduling based on PON uplink time slots. Each part is described below.

[0034] Timestamp Injection and Mapping: When sending data frames for time-sensitive services, the terminal device injects timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer, and maps the timestamp information to preset bits of the Ethernet preamble. By carrying the timestamp in the preset bits of the Ethernet preamble, there is no need to modify the payload or frame header structure of the Ethernet frame. The timestamp is located before the frame delimiter, and neither the MAC layer of the terminal device nor the user-side MAC layer of the gateway can detect the existence of the timestamp, achieving zero frame format modification and ensuring full compatibility with the standard Ethernet protocol stack.

[0035] Timestamp Extraction and Frame Attribute Marker Generation: The user-side PHY layer extracts the timestamp information during the preamble reception stage and generates the corresponding frame attribute marker signal. Completing timestamp extraction and service type determination during the preamble reception stage, before the data frame enters the MAC layer buffer, avoids the buffer queue from damaging the time attributes of latency-sensitive services, allowing traffic splitting decisions to be implemented earlier during frame reception synchronization.

[0036] Frame attribute marking signal transmission and queue distribution: The user-side MAC layer receives the frame attribute marking signal and distributes data frames to different service queues according to the frame attribute marking signal. Through the frame attribute marking signal, the user-side MAC layer can send latency-sensitive services and non-latency-sensitive services into different service queues respectively, so as to complete subsequent uplink differentiated scheduling and avoid head-blocking problems caused by mixed queuing.

[0037] Adaptive scheduling based on PON uplink time slots: The network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal. The network-side PON module can adaptively retrieve frames from the corresponding service queue for transmission, achieving precise matching between uplink time slots and service types, and significantly reducing the transmission waiting time of latency-sensitive services.

[0038] This application provides a timestamp-based parallel access method for FTTR gateways. This method involves four sequentially coordinated steps: timestamp injection and mapping, timestamp extraction and frame attribute tag generation, frame attribute tag signal transmission and queue distribution, and adaptive scheduling based on PON uplink time slots. This forms a complete closed loop from terminal device timestamp injection, gateway physical layer tag extraction, MAC layer queue distribution to PON module adaptive scheduling. The entire process requires no modification to the Ethernet frame format, eliminates waiting time for MAC layer buffering to complete service determination, and completely excludes CPU involvement in traffic splitting decisions. Parallel access is achieved without modifying the frame format, without consuming CPU instruction cycles, and supports mixed deployment of new and old terminals.

[0039] In a further embodiment of timestamp injection and mapping, the terminal device injects timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer. Specifically, this includes: the terminal device's driver inserting a timestamp pulse through the interface between the MAC layer and the PHY layer during the frame gap; the PHY layer capturing the timestamp pulse and flipping a preset bit of the Ethernet preamble. Inserting the timestamp pulse during the idle period of the frame gap does not occupy the normal data frame transmission bandwidth; the PHY layer flips the preset bit of the preamble through hardware circuitry, a process that does not consume CPU instruction cycles, and the timestamp marking delay is a fixed value (determined by the hardware gate delay).

[0040] In a further embodiment of timestamp extraction and frame attribute tag generation, the user-side PHY layer extracts the timestamp information during the preamble reception stage, including: when the user-side PHY layer detects the preamble sequence, it monitors the level state of a preset bit in the preamble; if the preset bit is high, it generates a frame attribute tag signal representing a delay-sensitive service; if the preset bit is low, it generates a frame attribute tag signal representing a non-delay-sensitive service. Service types are distinguished through pure hardware level comparison, without involving software table lookups or protocol stack parsing, determining latency to be on the order of nanoseconds, and not affecting the timing of subsequent MAC layer processing.

[0041] In a further embodiment of frame attribute tagging signal transmission and queue distribution, the user-side MAC layer receives the frame attribute tagging signal by: the user-side PHY layer synchronously transmitting the frame attribute tagging signal to the user-side MAC layer along with the received data stream through the interface between the MAC layer and the PHY layer. The tagging signal is transmitted synchronously with the data stream, and the tag and the corresponding data frame are strictly aligned in timing to avoid tag misalignment or frame loss. This transmission path reuses the existing MAC-PHY interface, eliminating the need for additional signal lines.

[0042] In a further embodiment of adaptive scheduling based on PON uplink time slots, the network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal. This includes: the service queues comprising latency-sensitive queues and non-latency-sensitive queues; when the uplink time slot type is a low-latency time slot, the scheduler is configured to retrieve frames from the latency-sensitive queue for transmission; when the uplink time slot type is a standard time slot, the scheduler is configured to retrieve frames from the non-latency-sensitive queue for transmission. By distinguishing between low-latency time slots and standard time slots, corresponding to latency-sensitive and non-latency-sensitive queues respectively, the uplink bandwidth resources allocated by the OLT are matched with service requirements. Latency-sensitive services are transmitted only in low-latency time slots, avoiding queuing in standard time slots; non-latency-sensitive services use standard time slots and do not preempt low-latency resources.

[0043] This application provides a timestamp-based parallel access method based on an FTTR gateway. Following adaptive scheduling based on PON uplink time slots, it further includes: the user-side PHY layer counting the number of consecutive frames without detected timestamp information; when the number of frames reaches a preset threshold, entering compatibility mode and stopping differential parsing of the preamble; and resuming monitoring mode when the timestamp information is detected again. By detecting the number of consecutive frames without timestamps, traditional terminals (which do not support timestamp injection) are automatically identified. After entering compatibility mode, the gateway stops parsing the preamble bits, and all data frames are processed in normal mode, avoiding erroneous discarding or marking of data frames from traditional devices. Monitoring mode is automatically resumed after a timestamp is detected. This mechanism allows new and old terminals to coexist on the same LAN port without manual configuration or upgrading of old equipment.

[0044] like Figure 1 As shown, this application also provides a timestamp-based parallel access system based on an FTTR gateway, used to implement the method described in any of the above method embodiments. The system includes a terminal device and an FTTR gateway; the terminal device includes a MAC layer and a PHY layer, configured to inject timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer when sending data frames for time-sensitive services, and to map the timestamp information to preset bits of the Ethernet preamble; the FTTR gateway includes a user-side PHY layer, a user-side MAC layer, and a network-side PON module. Wherein: The user-side PHY layer is configured to extract the timestamp information during the preamble reception stage and generate a corresponding frame attribute marker signal. The user-side MAC layer is configured to receive the frame attribute marking signal and distribute data frames to different service queues according to the frame attribute marking signal. The network-side PON module is configured to schedule and send data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal.

[0045] In the timestamp-based parallel access system based on an FTTR gateway in this embodiment, the terminal device and each module of the FTTR gateway work together according to the above process to complete the entire parallel access from timestamp injection, extraction, tag transmission to uplink scheduling. The tag signal transmission from the user-side PHY layer to the user-side MAC layer uses a standard interface multiplexed, and the network-side PON module independently schedules based on OLT time slot allocation and user-side PHY layer tags. The overall solution does not change the Ethernet frame format, does not trigger CPU interrupts or protocol stack processing, and supports mixed deployment of new and old terminals.

[0046] In a preferred embodiment of the system described in this application, the FTTR gateway is further configured to: count the number of consecutive frames for which the timestamp information is not detected at the user-side PHY layer; when the number of frames reaches a preset threshold, enter compatibility mode and stop differential parsing of the preamble; when the timestamp information is detected again, resume monitoring mode. The system can automatically detect traditional terminals and switch operating modes without user intervention, supporting mixed access of new and old terminals under the same PON port.

[0047] Specific embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the method described in any one of the embodiments of this application, achieving the technical effects of the above methods. Specific embodiments of this application also provide a computer-readable storage medium storing a computer program thereon. When the program is executed by a processor, it implements the method described in any one of the embodiments of this application, achieving the technical effects of the above methods. By embedding the above methods in a device or storage medium as a processor-executable program, it can be used for software upgrades of existing FTTR gateways or terminal devices, reducing hardware modification costs.

[0048] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. In actual deployment, the appropriate solution can be selected according to the network topology. The described embodiments are only a part of the embodiments of this application, and not all of them. In the following specific embodiments of this application, the latency-sensitive service is an edge cloud service, and the non-latency-sensitive service is an Internet service.

[0049] Example 1: As Figure 3 As shown, this is applied to a home FTTR network. Terminal devices include new terminals with virtual network adapter drivers installed (such as VR devices) and traditional terminals without drivers installed (such as ordinary PCs). The FTTR gateway connects to the terminals via a LAN port, and the network-side PON module connects to the OLT. The OLT allocates two types of uplink time slots: low-latency time slots (e.g., 100μs, 1kHz) for edge cloud services (e.g., latency requirement ≤5ms), and standard time slots (e.g., 1ms, 100Hz) for internet services (e.g., latency requirement ≤20ms).

[0050] Step 1: Timestamp Injection and Mapping. When a terminal device sends edge cloud service data frames, the virtual network interface card driver inserts a timestamp pulse into the frame gap between the MAC layer and the PHY layer. The PHY layer's preamble generation logic captures this pulse and flips a preset bit in the preamble from its default low level to a high level, while other bits remain unchanged. When sending Internet service frames or frames sent by traditional terminals, no pulse is inserted, and the preamble remains at its default level. Timestamp injection occurs during the frame gap and does not affect normal data frame transmission. The flipping operation is performed by the PHY layer hardware, does not consume CPU instruction cycles, and the timestamp marking delay is a fixed hardware delay. Since the preamble is located before the frame delimiter, the original frame content sent by the MAC layer is not modified and is completely transparent to the upper-layer protocol stack.

[0051] Step 2: Timestamp Extraction and Frame Attribute Marking. During the preamble reception phase, the user-side PHY layer of the FTTR gateway monitors the level of preset bits in real time. If the level is high, a frame attribute marker signal (logic high) is generated to indicate delay-sensitive services; if the level is low, a marker signal (logic low) is generated to indicate non-delay-sensitive services. This determination is completed before the frame payload (destination MAC address, etc.) begins transmission, before the data frame enters the MAC layer buffer. Service type differentiation is achieved through pure hardware level comparison, without involving software table lookups or protocol stack parsing, resulting in a determination delay in the nanosecond range. Traffic splitting decisions are made before buffering, avoiding the disruption of time attributes for delay-sensitive services by the buffer queue.

[0052] Step 3: Marking Signal Transmission and Queue Distribution. The user-side PHY layer synchronously transmits the frame attribute marking signal along with the received data stream to the user-side MAC layer via the MAC-PHY interface. The user-side MAC layer latches the mark at the start of frame reception. After frame reception is complete, the driver delivers the frame to the corresponding service queue based on the mark: a latency-sensitive queue (edge ​​cloud services) or a non-latency-sensitive queue (internet services). The marking signal and data stream are strictly aligned to avoid mark misalignment. This transmission reuses existing interface signal lines, requiring no additional hardware. Queue distribution is entirely based on physical layer marking; the MAC layer does not need to re-parse the frame header.

[0053] Step 4: Adaptive Uplink Time Slot Scheduling. The network-side PON module maintains two uplink queues: a latency-sensitive queue and a non-latency-sensitive queue. The OLT periodically allocates uplink time slots (each 10ms period contains 10 low-latency time slots and 1 standard time slot). When a low-latency time slot arrives, the scheduler retrieves a frame from the latency-sensitive queue and sends it; when a standard time slot arrives, it retrieves a frame from the non-latency-sensitive queue and sends it. If the corresponding queue is empty, a frame is retrieved from the other queue to fill it. The OLT time slot type is precisely matched with the service queue, ensuring that all low-latency time slots are used to transmit latency-sensitive services, avoiding head-of-queue congestion. The scheduler does not need to classify in real time, only selects queues, reducing scheduling latency.

[0054] Step 5: Backward Compatibility Mechanism. The user-side PHY layer maintains a counter, checking preset bits for each received frame. When the number of consecutive frames without a high level detected reaches a preset threshold (e.g., 100 frames), it enters compatibility mode: differential parsing of the preamble stops, all frames are marked as low (non-latency sensitive), and all frames use the Internet path. Once a high level is detected, the counter is reset to zero, and monitoring mode resumes. It automatically identifies traditional terminals (whose frames lack timestamps) to avoid misjudgments. New and old terminals can be deployed together on the same LAN port without manual configuration or upgrading of older equipment.

[0055] The above steps form a complete closed loop from terminal timestamp injection, gateway physical layer extraction, MAC layer queue distribution to PON uplink scheduling. The entire solution does not modify the Ethernet frame format, does not trigger CPU interrupts, supports the coexistence of new and old terminals, and achieves the end-to-end latency target for edge cloud services.

[0056] Example 2: Figure 4 As shown, this embodiment is applied to an enterprise office FTTR network, and the terminal devices include cloud desktop terminals, video conferencing terminals, and ordinary office PCs. The network has high requirements for service isolation. Below, we will only describe the differences between this embodiment and Embodiment 1: the implementation methods of timestamp injection and extraction, and the backward compatibility mechanism.

[0057] Step 1 in this example: Timestamp Injection and Mapping. This embodiment does not use existing sideband signals to transmit timestamp pulses. Instead, a dedicated GPIO pin is added between the MAC layer and the PHY layer of the terminal device. The virtual network card driver sends a timestamp trigger signal to the PHY layer through this GPIO pin. After detecting this signal, the preamble generation logic in the PHY layer flips the preamble preset bits from the default level to the opposite level. This method requires modification of the PHY layer hardware, adding a GPIO input pin, but it avoids timing conflicts that may be caused by reusing existing sideband signals.

[0058] Step 2 in this example: Timestamp Extraction and Frame Attribute Marking. This embodiment does not use existing sideband signals to transmit frame attribute marking signals. Instead, a dedicated GPIO pin is added between the user-side PHY layer and the user-side MAC layer of the FTTR gateway. After the user-side PHY layer extracts the timestamp, it sends the frame attribute marking signal to the user-side MAC layer through this GPIO pin. The user-side MAC layer's receiving logic latches the mark through this pin and passes the mark to the driver when frame reception is complete. This method requires modification to the user-side MAC layer hardware, adding a GPIO input pin, thus avoiding the timing constraints of existing sideband signals.

[0059] Step 5 in this example: Backward compatibility mechanism. This embodiment uses a statistical window mechanism instead of a counter mechanism. The user-side PHY layer maintains a statistical window (e.g., 1000 frames in size) and calculates the proportion of frames with detected timestamps within the window. If the proportion is lower than a first preset value (e.g., 5%), it is determined to be a device without a timestamp and enters compatibility mode (stopping preamble differentiation parsing). If the proportion is higher than a second preset value (e.g., 10%), monitoring mode is restored. Compared to the counter method in Embodiment 1, this mechanism has a stronger tolerance for occasional false detections and avoids frequent mode switching.

[0060] Dedicated GPIO pins eliminate the timing dependency associated with multiplexing sideband signals from existing interfaces, making them suitable for high-load or more real-time-critical scenarios. The statistical window mechanism, based on proportional judgment, avoids mode switching triggered by error detection in a single or small number of frames, resulting in higher stability in hybrid deployment scenarios. Both alternatives retain core features: hardware-based marking at the PHY layer, no modification to the frame format, no CPU usage, and support for coexistence of new and old terminals.

[0061] Example 3: Figure 5 As shown, this embodiment is applied to a small home FTTR network, which includes an FTTR gateway and a small number of terminal devices. This scenario is cost-sensitive, and basic timestamp marking and traffic splitting functions are implemented with the lowest hardware cost, so step 3 is omitted.

[0062] Step 1: Timestamp Injection and Mapping. Instead of using a virtual network interface card (NIC) driver, the timestamp injection function is directly added to the terminal device's NIC driver. The driver determines the service type based on the destination IP address or port number: for edge cloud services, a timestamp pulse is inserted into the inter-frame gap of the MAC-PHY interface; for internet services, no pulse is inserted. This method eliminates the need for a virtual NIC, reducing software complexity, but requires configuring service identification rules.

[0063] Step 2: Timestamp Extraction and Frame Attribute Marking. The mechanism for extracting timestamps at the user-side PHY layer is the same as in Example 1. However, the user-side MAC layer no longer receives frame attribute marks via sideband signals. Instead, after frame reception, it determines the service type based on the source MAC address or destination IP address of the frame and directly distributes it to the corresponding receiving queue. This method avoids modifying interface signal lines and reduces hardware complexity, but requires configuring identification rules.

[0064] Step 4: Uplink Time Slot Adaptive Scheduling. The network-side PON module maintains two queues (edge ​​cloud queue and internet queue), using fixed bandwidth allocation, with the edge cloud queue accounting for 30% and the internet queue accounting for 70%. The scheduler does not recognize OLT time slot types, simplifying the scheduling logic.

[0065] Step 5: Backward compatibility mechanism. Automatic compatibility is not implemented; all terminals must have a driver that supports timestamp injection installed. If legacy terminals exist, the gateway must be manually configured to enter compatibility mode.

[0066] This embodiment retains the core features of hardware marking and pre-buffered traffic splitting at the PHY layer, but reduces hardware and software costs by simplifying software (no virtual network card), simplifying mark transmission (based on MAC address / IP address for judgment), simplifying scheduling (fixed ratio), and simplifying compatibility (manual configuration). It is suitable for home scenarios with a small number of terminals and simple service types, and can still achieve basic traffic splitting between edge cloud services and Internet services.

[0067] The timestamp-based parallel access method, system, device, and storage medium provided in this application have at least the following technical advantages: 1) Zero-frame format modification: The timestamp information is mapped to the preset bits of the Ethernet preamble, without changing the data frame payload, frame header or trailer, and is completely transparent to the upper-layer protocol stack (such as IP, TCP, application layer, etc.); the frames captured by standard packet capture tools are no different from ordinary Ethernet frames, and no protocol adaptation or network upgrade is required. 2) Pre-buffered traffic splitting: The user-side PHY layer completes the service type determination and generates a frame attribute marker signal during the preamble reception stage. At this time, the data frame has not yet entered the MAC layer buffer. Compared with the traditional solution (which can only be identified after the complete frame is stored in the buffer), this avoids the time attribute destruction of latency-sensitive services by the buffer queue. The traffic splitting decision is completed synchronously with the frame reception. 3) Zero CPU overhead: The injection (bit flipping at the terminal PHY layer) and extraction (level comparison at the gateway user-side PHY layer) of timestamps are both completed by hardware circuits. The CPU does not participate in any traffic splitting decision process, does not consume instruction cycles, and does not perform table lookup or interrupt handling; the system has high determinism and is not affected by CPU load. 4) PON uplink time slot adaptive scheduling: The network-side PON module retrieves frames from the corresponding service queue (delay-sensitive queue or non-delay-sensitive queue) and sends them according to the time slot type (low-latency time slot or standard time slot) allocated by the OLT and the frame attribute marking signal generated by the PHY layer; the low-latency time slot is only used to transmit delay-sensitive services to avoid head-of-queue congestion and improve bandwidth utilization. 5) Backward compatibility and hybrid deployment: By counting the number of consecutive frames without detected timestamps or the proportion of timestamps within a statistical window, the gateway can automatically identify traditional terminals (which do not support timestamp injection) and switch to compatibility mode (stop preamble differential parsing); it supports the mixed operation of new and old terminals on the same physical port without the need for manual configuration or upgrading of old devices; 6) Implementation flexibility: It provides multiple specific implementation paths: standard solution (reuses existing MAC-PHY interface sideband signals, counter compatible), enterprise solution (dedicated GPIO pins, statistical window compatible), and home simplified solution (based on IP / port identification, fixed bandwidth scheduling); it can balance hardware cost, software complexity, and functional integrity in different scenarios; 7) Low latency guarantee: This application can significantly reduce the end-to-end latency of latency-sensitive services, meet the requirements of low latency services; effectively improve the utilization rate of PON uplink time slots; timestamp identification has high accuracy; and the number of compatibility mode switching times under hybrid deployment is significantly reduced.

[0068] The various technical features in this application work in close collaboration: the terminal device inserts timestamp pulses into the frame gaps via a driver, and the PHY layer hardware flips the preamble preset bits. This marking method does not modify the frame format and is transparent to the upper layers. The user-side PHY layer of the FTTR gateway detects the level status in real time during the preamble reception stage and generates a frame attribute marking signal without waiting for buffering, thus completing the service determination before the data frame enters the MAC layer buffer. This marking signal is transmitted to the user-side MAC layer through the MAC-PHY interface and is directly used for queue distribution, avoiding the parsing overhead of the upper-layer protocol stack. The network-side PON module uses the time slot type allocated by the OLT and the physical layer marking signal as the scheduling basis, so that low-latency time slots only take frames from the latency-sensitive queue, and standard time slots take frames from the non-latency-sensitive queue, achieving accurate matching between uplink time slots and service types. At the same time, by counting the number or proportion of frames for which no timestamps are detected, the gateway automatically switches to compatibility mode to ensure that traditional terminals and new terminals are deployed in a mixed manner without affecting each other. The aforementioned features, from tag injection, fast determination, delivery and distribution, adaptive scheduling to backward compatibility, form a closed loop, which together achieves the overall technical effect of not modifying the frame format, not relying on CPU intervention, pre-buffering splitting, time slot matching, and hybrid deployment.

[0069] The above descriptions are merely embodiments of this application. Commonly known technical solutions or characteristics are not described in detail here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical solution of this application. These modifications and improvements should also be considered within the scope of protection of this application, and will not affect the effectiveness of the application or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A timestamp-based parallel access method based on an FTTR gateway, characterized in that, The method is applied to an FTTR network, which includes terminal equipment and an FTTR gateway. The terminal equipment includes a MAC layer and a PHY layer, and the FTTR gateway includes a user-side MAC layer, a user-side PHY layer, and a network-side PON module. When the terminal device sends a data frame for a time-sensitive service, it injects timestamp information into the encoding stream of the PHY layer at the interface between the MAC layer and the PHY layer, and maps the timestamp information to preset bits of the Ethernet preamble. The user-side PHY layer extracts the timestamp information during the preamble reception stage and generates a corresponding frame attribute marker signal. The user-side MAC layer receives the frame attribute marking signal and distributes the data frame to different service queues according to the frame attribute marking signal; The network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal.

2. The method according to claim 1, characterized in that, The terminal device injects timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer, including: The driver for the terminal device inserts timestamp pulses through the interface between the MAC layer and the PHY layer during the frame interval; The PHY layer captures the timestamp pulse and flips the preset bits of the Ethernet preamble.

3. The method according to claim 1, characterized in that, The user-side PHY layer extracts the timestamp information during the preamble reception stage, including: When the user-side PHY layer detects the preamble sequence, it monitors the level state of a preset bit of the preamble. If the preset bit is high, a frame attribute marker signal representing the delay-sensitive service is generated; If the preset bit is low, a frame attribute marker signal representing a non-delay-sensitive service is generated.

4. The method according to claim 1, characterized in that, The user-side MAC layer receives the frame attribute tag signal, including: The user-side PHY layer transmits the frame attribute marker signal synchronously to the user-side MAC layer along with the received data stream through the interface between the MAC layer and the PHY layer.

5. The method according to claim 1, characterized in that, The network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal, further including: The service queue includes latency-sensitive queues and non-latency-sensitive queues; When the uplink time slot type is a low-latency time slot, the scheduler is configured to retrieve frames from the latency-sensitive queue for transmission; When the uplink timeslot type is a standard timeslot, the scheduler is configured to retrieve frames from the non-delay-sensitive queue for transmission.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes, after the network-side PON module schedules and sends data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal: The user-side PHY layer counts the number of consecutive frames for which the timestamp information is not detected. When the number of frames reaches a preset range threshold, the system enters compatibility mode and stops differential parsing of the preamble. When the timestamp information is detected again, the monitoring mode is restored.

7. A timestamp-based parallel access system based on an FTTR gateway, characterized in that, The system for implementing the method as described in any one of claims 1 to 6 comprises: The terminal device, including a MAC layer and a PHY layer, is configured to inject timestamp information into the encoded stream of the PHY layer at the interface between the MAC layer and the PHY layer when sending data frames of time-sensitive services, and to map the timestamp information to preset bits of the Ethernet preamble; The FTTR gateway includes a user-side PHY layer, a user-side MAC layer, and a network-side PON module. The user-side PHY layer is configured to extract the timestamp information during the preamble reception stage and generate a corresponding frame attribute marker signal. The user-side MAC layer is configured to receive the frame attribute marker signal and distribute data frames to different service queues according to the frame attribute marker signal. The network-side PON module is configured to schedule and send data frames from the corresponding service queue according to the uplink time slot type allocated by the OLT and the frame attribute marker signal.

8. The system according to claim 7, characterized in that, The FTTR gateway is also configured to: The user-side PHY layer counts the number of consecutive frames for which the timestamp information is not detected. When the number of frames reaches a preset range threshold, the system enters compatibility mode and stops differential parsing of the preamble. When the timestamp information is detected again, the monitoring mode is restored.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 6.

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