Semiconductor memory device and electronic system including the same

Abstract

A semiconductor memory device includes: a cell structure including a cell wiring structure and a cell bonding pad; and a peripheral circuit structure including: a peripheral circuit substrate including a first surface and a second surface; a plurality of peripheral circuit elements disposed on the first surface of the peripheral circuit substrate; a peripheral wiring structure electrically connected to the plurality of peripheral circuit elements; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad, wherein the plurality of peripheral circuit elements includes a plurality of first peripheral circuit elements disposed in a first region of the peripheral circuit substrate and a plurality of second peripheral circuit elements disposed in a second region of the peripheral circuit substrate, the thickness of the second region of the peripheral circuit substrate is greater than the thickness of the first region in a first direction, the first surface of the peripheral circuit substrate extends in a second direction, and the first direction intersects the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices and electronic systems including semiconductor memory devices. Background Technology

[0002] In electronic systems requiring data storage, semiconductor memory devices capable of storing large amounts of data are needed. Therefore, research is underway to improve the data storage capacity of semiconductor memory devices. For example, as one method for increasing the data storage capacity of semiconductor memory devices, a semiconductor memory device has been proposed that includes three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the Invention

[0003] To address one or more problems (e.g., the problems described above and / or other problems not explicitly described herein), this disclosure provides a semiconductor memory device with improved electrical properties and an electronic system including the semiconductor memory device.

[0004] To address one or more problems (e.g., the problems described above and / or other problems not explicitly described herein), this disclosure provides a semiconductor memory device with increased integration density and an electronic system including the semiconductor memory device.

[0005] According to some embodiments, a semiconductor memory device may include: a cell structure including a cell wiring structure and a cell bonding pad electrically connected to the cell wiring structure; and a peripheral circuit structure including: a peripheral circuit substrate including a first surface and a second surface facing the first surface; a plurality of peripheral circuit elements disposed on the first surface of the peripheral circuit substrate; a peripheral wiring structure electrically connected to the plurality of peripheral circuit elements; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad, wherein the plurality of peripheral circuit elements may include a plurality of first peripheral circuit elements disposed in a first region of the peripheral circuit substrate and a plurality of second peripheral circuit elements disposed in a second region of the peripheral circuit substrate, wherein the thickness of the second region of the peripheral circuit substrate may be greater than the thickness of the first region of the peripheral circuit substrate in a first direction, and the first surface of the peripheral circuit substrate extends in a second direction, and the first direction intersects the second direction.

[0006] According to some embodiments, a semiconductor memory device may include: a cell structure including a cell wiring structure and a cell bonding pad electrically connected to the cell wiring structure; and a peripheral circuit structure stacked on the upper surface of the cell structure in a first direction, wherein the peripheral circuit structure may include: a peripheral circuit substrate having a first surface and a second surface opposite to the first surface, the peripheral circuit substrate including a first region and a second region disposed along a second direction intersecting the first direction; a first peripheral circuit element disposed on the first region and a second peripheral circuit element disposed on the second region; a peripheral wiring structure electrically connected to the first peripheral circuit element and the second peripheral circuit element; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad, wherein the first surface of the first region and the first surface of the second region may be coplanar with each other, and the second surface of the second region may be located at a height higher than the second surface of the first region in the first direction.

[0007] According to some embodiments, an electronic system may include: a main substrate; a semiconductor memory device stacked on the main substrate; and a controller electrically connected to the semiconductor memory device on the main substrate, wherein the semiconductor memory device may include: a cell structure including a cell wiring structure and a cell bonding pad electrically connected to the cell wiring structure; and a peripheral circuit structure including: a peripheral circuit substrate including a first surface and a second surface facing the first surface; a plurality of peripheral circuit elements disposed on the first surface of the peripheral circuit substrate; a peripheral wiring structure electrically connected to the plurality of peripheral circuit elements; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad, wherein the plurality of peripheral circuit elements may include a plurality of first peripheral circuit elements having a first voltage applied and a plurality of second peripheral circuit elements having a second voltage applied higher than the first voltage, the peripheral circuit substrate may include a first region disposed of the plurality of first peripheral circuit elements and a second region disposed of the plurality of second peripheral circuit elements, the thickness of the second region of the peripheral circuit substrate being greater than the thickness of the first region of the peripheral circuit substrate in a first direction, the first surface of the peripheral circuit substrate extending in a second direction, and the first direction intersecting the second direction.

[0008] According to some embodiments of this disclosure, semiconductor memory devices can have improved electrical performance and higher integration density because the volume thickness of the transistors to which relatively low voltages are applied is reduced. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a plan view used to illustrate a semiconductor memory device according to some embodiments;

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken by line X-X';

[0012] Figure 3 yes Figure 2 A magnified view of the boxed area A;

[0013] Figure 4 These are diagrams used to illustrate semiconductor memory devices according to some embodiments;

[0014] Figure 5 yes Figure 4 A magnified view of the boxed area B;

[0015] Figure 6 These are diagrams used to illustrate semiconductor memory devices according to some embodiments;

[0016] Figure 7 yes Figure 6 A magnified view of the boxed area C;

[0017] Figure 8 These are diagrams used to illustrate semiconductor memory devices according to some embodiments;

[0018] Figure 9 These are diagrams used to illustrate semiconductor memory devices according to some embodiments;

[0019] Figures 10 to 12 This is a diagram illustrating a method of manufacturing a semiconductor memory device according to some embodiments;

[0020] Figures 13 to 15 This is a diagram illustrating a method of manufacturing a semiconductor memory device according to some embodiments;

[0021] Figure 16 These are example block diagrams used to illustrate electronic systems according to some embodiments;

[0022] Figure 17 This is an example perspective view illustrating an electronic system including a semiconductor memory device according to some embodiments; and

[0023] Figure 18 It is along Figure 17 A schematic cross-sectional view of the line V-V'. Detailed Implementation

[0024] In the following, semiconductor memory devices and electronic systems according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise requires. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0026] When referring to orientation, layout, location, shape, size, composition, quantity or other measure, terms such as “same” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, composition, quantity or other measure, but are intended to include, for example, orientation, layout, location, shape, size, composition, quantity or other measure that are substantially the same within typical variations that may occur due to conventional manufacturing processes.

[0027] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or “on” another element, the element may be directly connected or coupled to that other element or directly on that other element, or may be an intermediate element. Conversely, when an element is referred to as “in contact with another element” or “in contact with another element” (or any form of using the word “in contact”), there is no intermediate element at the point of contact.

[0028] As used herein, components described as “electrical connections” are configured such that electrical signals can be transmitted from one component to another (although the strength of such electrical signals may be attenuated and may be selectively transmitted during transmission).

[0029] Ordinal numbers such as "first," "second," and "third" can be simply used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be referenced elsewhere without the ordinal number or using a different ordinal number (e.g., "second" in the specification or another claim).

[0030] As can be seen in the accompanying figures, multiple items may be described in the singular form herein. Therefore, unless the context otherwise indicates, a description of a single item provided in the plural form should be understood to apply to the remaining multiple items.

[0031] For ease of description, this document may use spatial relative terms such as “below,” “down,” “up,” “front,” “rear,” “right,” and “left” to describe positional relationships, as shown in the accompanying figures. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms also include different orientations of the equipment.

[0032] As used herein, the terms “overlap” or “cover” are intended to indicate that an element is on top of another element. These elements may or may not be in contact. An element that “covers” another element does not need to cover the entire element to be considered a “cover.” These terms are intended to encompass an element “covering” all or any part of the element below it. As used herein, the word “around” is intended to indicate that an element is outside another element. These elements may or may not be in contact. An element that surrounds another element may or may not completely surround an inner element.

[0033] Figure 1 This is a plan view used to illustrate a semiconductor memory device according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken by line X-X'. Figure 3 yes Figure 2 A magnified view of the boxed area A.

[0034] Semiconductor memory devices can be semiconductor chips (i.e., semiconductor devices derived from wafer dicing (e.g., cutting)).

[0035] Semiconductor memory devices according to some embodiments may have a chip-to-chip (C2C) structure, wherein peripheral circuit structures (PERIs) and cell structures (CELLs) are interconnected. For example, a semiconductor memory device may include a structure that interconnects a first chip including cell structures (CELLs) on a first wafer and a second chip including upper peripheral circuit structures (PERIs) on a second wafer via a bonding method. For example, the bonding method may be a hybrid bonding method.

[0036] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor memory device may include a peripheral circuit structure PERI and a cell structure CELL.

[0037] The cell structure may include a cell substrate 100, source structures 102 and 104, a molded structure MS, a channel structure CH, a bit line BL, a word line contact 160, a contact spacer 170, a cell wiring structure 180, a cell bonding pad 185, etc.

[0038] The cell substrate 100 may include a cell array region CAR, an extension region EXT, and a through region THR.

[0039] A memory cell array comprising multiple memory cells can be formed on a cell array region (CAR). Channel structures (CH), molding structures (MS), bit lines (BL), etc., can be disposed on the cell array region (CAR). In this disclosure, the description of configuration B being formed or disposed on configuration A is not limited to configuration B being formed or disposed in contact with configuration A. For example, it may also include embodiments where another configuration C is located between configuration B and configuration A. Furthermore, in this disclosure, the description of configuration B being formed or placed on configuration A is not limited to configuration B being disposed above configuration A in the drawings. For example, it may also include embodiments where configuration B is disposed below, to the right, or to the left of configuration A in the drawings.

[0040] The extension area EXT can be disposed around the cell array area CA. For example, the extension area EXT can surround the cell array area CAR. Word line contacts 160, contact spacers 170, dummy channel structures 150, etc., can be disposed on the extension area EXT.

[0041] The through-region THR can be located outside the extension region EXT. For example, the through-region THR can be located on one side of the extension region EXT, but the embodiment is not limited to this. The source contact 184, input and output contacts, etc., can be located in the through-region THR.

[0042] For example, the unit substrate 100 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, the unit substrate 100 may include polycrystalline silicon (polycrystalline Si).

[0043] The unit substrate 100 may include a first surface 100_A and a second surface 100_B opposite to the first surface 100_A. The first surface 100_A of the unit substrate 100 may refer to the surface on which the molding structure MS and the channel structure CH are disposed. The first surface 100_A of the unit substrate 100 may be referred to as the front side of the unit substrate 100. The second surface 100_B of the unit substrate 100 may be referred to as the rear side of the unit substrate 100.

[0044] Source structures 102 and 104 can be formed on the cell substrate 100. Source structures 102 and 104 can be disposed between the cell substrate 100 and the molded structure MS. For example, source structures 102 and 104 can extend along the upper surface of the cell substrate 100. Source structures 102 and 104 can be formed as semiconductor patterns connected to the channel structure CH. For example, a second source layer 104 in source structures 102 and 104 can be formed using an information storage film and contact the semiconductor pattern. Source structures 102 and 104 can be configured as a common source line of the semiconductor device (e.g., ...). Figure 16(CSL in the example). For example, source structures 102 and 104 may include polysilicon or metal doped with impurities, but the embodiments are not limited thereto.

[0045] In some embodiments, the channel structure CH may be formed to pass through the source structures 102 and 104. For example, the lower portion of the channel structure CH may be formed to pass through the source structures 102 and 104 and disposed in the cell substrate 100.

[0046] In some embodiments, source structures 102 and 104 may include multiple films. For example, source structures 102 and 104 may include a first source layer 102 and a second source layer 104 sequentially stacked on a unit substrate 100. Each of the first source layer 102 and the second source layer 104 may include impurity-doped polysilicon or undoped polysilicon, but embodiments are not limited thereto. The first source layer 102 may be in contact with a semiconductor pattern and may be provided as a common source line of a semiconductor device (e.g., Figure 16 The second source layer 104 can be used as a support layer to prevent the molded stack (e.g., molded structure MS) from collapsing or falling off during the replacement process for forming the first source layer 102.

[0047] Although not shown, a substrate insulating film may be inserted between the unit substrate 100 and the source structures 102 and 104. For example, the substrate insulating film may include, but is not limited to, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0048] A molded structure MS can be disposed on source structures 102 and 104. The molded structure MS can be disposed on the cell array region CAR and the extended region EXT of the cell substrate 100. The molded structure MS may include a plurality of molded insulating layers 110 and a plurality of gate electrodes 120 alternately stacked along a first direction D1. Each of the molded insulating layers 110 and each of the plurality of gate electrodes 120 may have a layered structure extending parallel to the first surface 100_A of the cell substrate 100. The gate electrodes 120 may be spaced apart from each other by the molded insulating layers 110 and sequentially stacked on source structures 102 and 104.

[0049] The molded insulating layer 110 may include an insulating material. For example, the molded insulating layer 110 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride, but the embodiments are not limited thereto.

[0050] The gate electrode 120 may include a conductive material. For example, the gate electrode 120 may include a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon, but the embodiments are not limited thereto.

[0051] Interlayer insulating film 125 may be formed on a first surface 100_A of unit substrate 100. Interlayer insulating film 125 may be disposed on molded structure MS to cover molded structure MS. For example, interlayer insulating film 125 may include at least one of silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than silicon oxide, but the embodiments are not limited thereto.

[0052] A channel structure CH can be disposed on the cell array region CAR of the cell substrate 100. The channel structure CH can extend in a first direction D1 that intersects with a second direction D2 of the first surface 100_A of the cell substrate 100. For example, the first direction D1 can be perpendicular to the second direction D2. The channel structure CH can be formed to pass through the molding structure MS. For example, the channel structure CH can be formed to pass through each of the plurality of gate electrodes 120 and intersect with each of the plurality of gate electrodes 120. The channel structure CH can have a cylindrical shape (e.g., a cylinder) extending in the first direction D1. In some embodiments, the cross-section of the channel structure CH can have inclined side surfaces such that its width gradually narrows toward the cell substrate 100. However, the embodiments are not limited to the above.

[0053] In some embodiments, the channel structure CH may include a filling insulating layer, a channel layer, and an information storage film.

[0054] The channel layer may extend in the first direction D1 and be formed through the molded structure MS. The channel layer may have various shapes, such as cylindrical, rectangular cylindrical, and filled cylindrical. The channel layer may include, for example, semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and / or carbon nanostructures, but the embodiments are not limited thereto.

[0055] An information storage film may be inserted between the channel layer and each gate electrode 120. For example, the information storage film may extend along the outer surface of the channel layer. For example, the information storage film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material with a dielectric constant higher than silicon oxide. For example, the high-k material may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or combinations thereof.

[0056] In some embodiments, the channel structure CH can be arranged in a zigzag pattern. For example, as... Figure 1 As shown, the channel structure CH can be arranged to alternate with each other on the second direction D2 and the third direction D3. A zigzag pattern of channel structure CH can further improve the integration density of semiconductor memory devices. In some embodiments, the channel structure CH can be arranged in a honeycomb pattern.

[0057] In some embodiments, the information storage film may include multiple films. The information storage film may include a tunnel insulating film, a charge storage film, and a barrier insulating film, which may be sequentially stacked on the outer surface of the channel layer.

[0058] Tunnel insulating films may, for example, comprise silicon oxide or high-k materials with a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). Charge storage films may, for example, comprise silicon nitride. Barrier insulating films may, for example, comprise silicon oxide or high-k materials with a dielectric constant higher than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0059] In some embodiments, the channel structure CH may further include a filling insulating layer. The filling insulating layer may be formed to fill the interior of the cup-shaped channel layer. For example, the filling insulating layer may include an insulating material such as silicon oxide, but the embodiments are not limited thereto.

[0060] In some embodiments, the channel pad 132 may be disposed on the channel structure CH. The channel pad 132 may be formed to connect to the channel layer. For example, the channel pad 132 may be disposed in the interlayer insulating film 125 and connected to one end of the channel layer. For example, the channel pad 132 may comprise polysilicon doped with impurities, but the embodiments are not limited thereto.

[0061] The molded structure MS can be divided by word line cut regions (WCF) to form memory cell blocks (e.g., Figure 1 (BLK). For example, the word line cut area WCF may include at least one of insulating material, silicon oxide, silicon nitride, or silicon oxynitride, but the embodiments are not limited thereto.

[0062] Bit lines BL can be formed on the molded structure MS. Bit lines BL can intersect with word line cut areas WCF. For example, each bit line BL can extend in a third direction D3. Bit lines BL can be positioned along a second direction D2, while being spaced apart from each other.

[0063] Bit line BL can be connected to channel structure CH arranged along the second direction D2. Bit line contact 136 can be formed in unit interlayer insulating film 125. Bit line BL can be electrically connected to channel structure CH through bit line contact 136 and channel pad 132.

[0064] Word line contacts 160 may be disposed on the extension region EXT of the cell substrate 100. Word line contacts 160 may extend in the first direction D1 and connect to the gate electrode 120. For example, word line contacts 160 may be formed as a portion passing through the molded structure MS and connected to the corresponding gate electrode 120. Although Figure 2The illustration shows a word line contact 160 formed through at least one of the plurality of gate electrodes 120 and connected to a corresponding gate electrode 120, but the embodiment is not limited thereto. In another example, the word line contact 160 may be disposed on an extension region EXT of the cell substrate 100 and connected to a corresponding gate electrode 120 of the plurality of gate electrodes 120 in a stepped structure.

[0065] Contact spacer 170 may be disposed on the side surface of word line contact portion 160. Contact spacer 170 may extend along the side surface of word line contact portion 160 in a first direction D1. Contact spacer 170 may surround word line contact portion 160. Contact spacer 170 may include an insulating material. For example, contact spacer 170 may include a silicon oxide-based insulating material.

[0066] A word line via can be provided on the word line contact 160. The word line via can be provided in the interlayer insulating film 125. The word line contact 160 can be electrically connected to the unit wiring structure 180 through the word line via.

[0067] A dummy channel structure 150 may be disposed on the extension region EXT of the cell substrate 100. The dummy channel structure 150 may be disposed around the word line contact 160. The dummy channel structure 150 may include an insulating material. For example, the dummy channel structure 150 may include a silicon oxide-based insulating material. However, embodiments are not limited to the above. As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists only as a pattern in a device.

[0068] The cell wiring structure 180 can be formed on the molded structure MS. For example, a cell wiring insulating film 182 can be formed on the cell interlayer insulating film 125, and the cell wiring structure 180 is formed in the cell wiring insulating film 182. The cell wiring structure 180 can be electrically connected to the bit line BL and the word line contact 160. Therefore, the cell wiring structure 180 can be electrically connected to the channel structure CH and the gate electrode 120. The number of layers and arrangement of the cell wiring structure 180 shown herein are merely illustrative, and the embodiments are not limited thereto.

[0069] In some embodiments, the cell structure (CELL) may be stacked with the peripheral circuit structure (PERI). The PERI may be positioned at a height higher than the cell structure (CELL) in a first direction. For example, the PERI may be stacked on the upper surface of the cell structure (CELL). In some embodiments, the cell structure (CELL) may be stacked on the upper surface of the PERI.

[0070] The peripheral circuit structure PERI may include a peripheral circuit substrate 200, a plurality of peripheral circuit elements 260 disposed on the peripheral circuit substrate 200, an interlayer insulating film 240 stacked on the peripheral circuit substrate 200, and a peripheral wiring structure 280 disposed in the interlayer insulating film 240. The peripheral wiring structure 280 may include a plurality of wiring layers and connection vias disposed in the interlayer insulating film 240.

[0071] The peripheral circuit substrate 200 may include a semiconductor substrate. For example, the peripheral circuit substrate 200 may be a single-crystal silicon (Si(100)) substrate, but the embodiments are not limited thereto. In some embodiments, the peripheral circuit substrate 200 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0072] The peripheral circuit substrate 200 may have a first surface 201 and a second surface 202. The first surface 201 and the second surface 202 may be surfaces facing each other. The second surface 202 may be a surface facing the first surface 201. A peripheral circuit element 260 may be disposed on the first surface 201. The surface on which the peripheral circuit element 260 is disposed may be referred to as the front side of the peripheral circuit substrate 200. For example, the first surface 201 of the peripheral circuit substrate 200 may be referred to as the front side, and the second surface 202 of the peripheral circuit substrate 200 may be referred to as the rear side.

[0073] The first surface 201 of the peripheral circuit substrate 200 can be configured to face the cell structure. The front side of the peripheral circuit substrate 200 can be configured to face the cell structure.

[0074] The peripheral circuit substrate 200 may include a first region R1 and a second region R2. The first surface 201 of the peripheral circuit substrate 200 may include the first surface 201_R1 of the first region R1 and the first surface 201_R2 of the second region R2, and the second surface 202 of the peripheral circuit substrate 200 may include the second surface 202_R1 of the first region R1 and the second surface 202_R2 of the second region R2.

[0075] The first region R1 can be a region to which a first voltage is applied. The second region R2 can be a region to which a second voltage is applied, the second voltage being a voltage higher than the first voltage. The first region R1 and the second region R2 can overlap each other in the second direction D2. The first region R1 and the second region R2 can be adjacent to each other in the second direction D2.

[0076] The thickness of the second region R2 of the peripheral circuit substrate 200 in the first direction D1 can be greater than the thickness of the first region R1 of the peripheral circuit substrate 200. The first surface 201_R1 of the first region R1 and the first surface 201_R2 of the second region R2 can be coplanar with each other. The second surface 202_R2 of the second region R2 can be located at a height higher than the second surface 202_R1 of the first region R1 in the first direction.

[0077] Peripheral circuit elements 260 may be disposed on a first surface 201 of the peripheral circuit substrate 200. Each of the plurality of peripheral circuit elements 260 may form peripheral circuitry for controlling the operation of a semiconductor memory device. For example, each of the plurality of peripheral circuit elements 260 may include Figure 16 The logic circuits include 1130, page buffer 1120, decoder 1110, etc.

[0078] Each of the plurality of peripheral circuit elements 260 may include, for example, a transistor, but is not limited thereto. For example, the peripheral circuit elements 260 may include not only various active elements such as transistors, but also various passive elements such as capacitors, registers and / or inductors.

[0079] The plurality of peripheral circuit elements 260 may include a first peripheral circuit element 261 disposed on a first region R1 and a second peripheral circuit element 262 disposed on a second region R2. The first peripheral circuit element 261 may be disposed on a first surface 201_R1 of the first region R1 of the peripheral circuit substrate 200, and the second peripheral circuit element 262 may be disposed on a first surface 201_R2 of the second region R2 of the peripheral circuit substrate 200.

[0080] A first voltage can be applied to a first peripheral circuit element 261, and a second voltage can be applied to a second peripheral circuit element 262. For example, the voltage applied to the second peripheral circuit element 262 can be greater than the voltage applied to the first peripheral circuit element 261.

[0081] A first element isolation film 211 defining the active region of the first peripheral circuit element 261 may be disposed on one side of the first peripheral circuit element 261. Additionally, a second element isolation film 212 defining the active region of the second peripheral circuit element 262 may be disposed on one side of the second peripheral circuit element 262.

[0082] The first element isolation film 211 can be formed to pass through a first region R1 of the peripheral circuit substrate 200 in the first direction D1. The first element isolation film 211 can be formed to pass through both a first surface 201_R1 and a second surface 202_R1 of the first region R1. For example, the first element isolation film 211 can divide adjacent first peripheral circuit elements 261 among a plurality of first peripheral circuit elements 261.

[0083] The second element isolation film 212 can be formed as a second region R2 that extends through the peripheral circuit substrate 200 in the first direction D1. The second element isolation film 212 can be defined as a region that overlaps with the second region R2 of the peripheral circuit substrate 200 in the second direction D2. The second element isolation film 212 can be formed as extending through both the first surface 201_R2 and the second surface 202_R2 of the second region R2. For example, the second element isolation film 212 can divide adjacent second peripheral circuit elements 262 among a plurality of second peripheral circuit elements 262.

[0084] The lower surface of the first element isolation film 211 may be located at the same height as the first surface 201_R1 of the first region R1 in the first direction. The upper surface of the first element isolation film 211 may be located at the same height as the second surface 202_R1 of the first region R1 in the first direction. The lower surface of the second element isolation film 212 may be located at the same height as the first surface 201_R2 of the second region R2 in the first direction, and the upper surface of the second element isolation film 212 may be located at the same height as the second surface 202_R2 of the second region R2 in the first direction.

[0085] The length of the second element isolation film 212 in the first direction D1 may be longer than the length of the first element isolation film 211 in the first direction D1. In some embodiments, the width of the second element isolation film 212 in the second direction D2 may be greater than the width of the first element isolation film 211 in the second direction D2.

[0086] The width of the first element isolation film 211 can decrease in the second direction D2 as it moves along the first direction D1 toward the second surface 202_R1 of the first region R1. The first element isolation film 211 can have a contour that appears as the first surface 201_R1 of the first region R1 is etched. The width of the second element isolation film 212 in the second direction D2 can decrease as it moves along the first direction D1 toward the second surface 202_R2 of the second region R2. The second element isolation film 212 can have a contour that appears as the first surface 201_R2 of the second region R2 is etched.

[0087] Each of the first element isolation membrane 211 and the second element isolation membrane 212 may, for example, include an oxide membrane, a nitride membrane, or a combination thereof.

[0088] A peripheral insulating layer 250 may be disposed on the second surface 202 of the peripheral circuit substrate 200. The peripheral insulating layer 250 may include a first peripheral insulating layer 251 disposed on a first region R1 of the peripheral circuit substrate 200 and a second peripheral insulating layer 252 disposed on a second region R2 of the peripheral circuit substrate 200. The first peripheral insulating layer 251 may contact the first element isolation film 211, and the second peripheral insulating layer 252 may contact the second element isolation film 212. The thickness of the first peripheral insulating layer 251 in the first direction D1 may be greater than the thickness of the second peripheral insulating layer 252 in the first direction D1.

[0089] Each of the first peripheral insulating layer 251 and the second peripheral insulating layer 252 may, for example, comprise an oxide film, a nitride film, or a combination thereof. In some embodiments, the second peripheral insulating layer 252 may not be distinguished from the second element isolation film 212. The second element isolation film 212 may be a portion of the peripheral circuit substrate 200 located at a height corresponding to the second region R2 in the first direction. Alternatively, the second peripheral insulating layer 252 may be a portion located at a height higher than the second element isolation film 212 in the first direction.

[0090] Multiple body contacts 270 may be disposed on the second surface 202 of the peripheral circuit substrate 200. The multiple body contacts 270 may include a first body contact 271 disposed on a first region R1 of the peripheral circuit substrate 200 and a second body contact 272 disposed on a second region R2 of the peripheral circuit substrate 200. The body contacts 270 may apply an electrical signal (e.g., body voltage) to the active region of the peripheral circuit element 260 to adjust the threshold voltage. Specifically, the first body contact 271 may apply a body voltage to the active region of the first peripheral circuit element 261, and the second body contact 272 may apply a body voltage to the active region of the second peripheral circuit element 262.

[0091] The first contact portion 271 can contact the second surface 202_R1 of the first region R1, and the second contact portion 272 can contact the second surface 202_R2 of the second region R2. The length of the first contact portion 271 in the first direction D1 can be greater than the length of the second contact portion 272 in the first direction D1. For example, the upper surface of the first contact portion 271 and the upper surface of the second contact portion 272 can be at the same height in the first direction, and the lower surface of the first contact portion 271 can be at a lower height in the first direction than the lower surface of the second contact portion 272.

[0092] Peripheral wiring structures 280 electrically connected to other peripheral wiring structures 280 may be provided on multiple peripheral circuit elements 260. The peripheral wiring structures 280 may be formed on the peripheral circuit elements 260, and may be disposed, for example, in an interlayer insulating film 240 formed on the front side of the peripheral circuit substrate 200. The peripheral wiring structures 280 may be electrically connected to the peripheral circuit elements 260. Figure 2 The number of layers and arrangement of the peripheral wiring structure 280 shown are illustrative only, and the embodiments are not limited thereto.

[0093] In some embodiments, the peripheral circuit structure PERI and the cell structure CELL can be connected to each other by a bonding method. The peripheral circuit structure PERI and the cell structure CELL can be connected to each other by cell bonding pads 185 formed in the cell structure CELL and peripheral bonding pads 285 formed in the peripheral circuit structure PERI. In some embodiments, the cell bonding pads 185 and the peripheral bonding pads 285 can comprise copper (Cu), but embodiments are not limited thereto, and the cell bonding pads 185 and the peripheral bonding pads 285 can comprise various other metals such as aluminum (Al) or tungsten (W). Because the cell bonding pads 185 and the peripheral bonding pads 285 are in contact with or bonded to each other, the cell wiring structure 180 can be electrically connected to the peripheral wiring structure 280. Therefore, the bit line BL and / or each gate electrode 120 can be electrically connected to the peripheral circuit element 260.

[0094] refer to Figure 3 The first peripheral circuit element 261 may include a first gate electrode 261a and a first gate insulating film 261b. The second peripheral circuit element 262 may include a second gate electrode 262a and a second gate insulating film 262b. Since the second voltage applied to the second peripheral circuit element 262 is greater than the first voltage applied to the first peripheral circuit element 261, the width of the second gate electrode 262a may be greater than the width of the first gate electrode 261a. In the second direction D2, the lengths of the second gate electrode 262a and the second gate insulating film 262b may be longer than the lengths of the first gate electrode 261a and the first gate insulating film 261b, respectively.

[0095] The first element isolation film 211 may include a first base surface 211a that is coplanar with the first surface 201_R1 of the first region R1. The second element isolation film 212 may include a second base surface 212a that is coplanar with the first surface 201_R2 of the second region R2. In the second direction D2, the width of the second base surface 212a may be greater than the width of the first base surface 211a.

[0096] In an embodiment, the first peripheral insulating layer 251 may include two opposing side surfaces. The two side surfaces of the first peripheral insulating layer 251 may include corresponding inclined portions to be dispersed from each other in a first direction D1. The width of the first peripheral insulating layer 251 in the second direction D2 may increase with increasing distance from the second surface 202_R1 of the first region R1 along the first direction D1. For example, the angle α between the second surface 202_R1 of the first region R1 and the side surfaces of the first peripheral insulating layer 251 may be an obtuse angle.

[0097] In the following description, other embodiments different from the above embodiments will be described. Elements that are the same as those described above may be given the same reference numerals, and their detailed descriptions may be omitted.

[0098] Figure 4 This is a diagram used to illustrate a semiconductor memory device according to some embodiments. Figure 5 yes Figure 4 A magnified view of the boxed area B. For reference. Figure 4 It can correspond to along Figure 1 A cross-sectional view taken by line X-X'.

[0099] refer to Figure 4 According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI). The PERI may be disposed on the cell structure (CELL). A description of the cell structure (CELL) can be found in the reference above. Figures 1 to 3 The content described is the same.

[0100] The plurality of peripheral circuit elements 260 may include a first peripheral circuit element 261 disposed on a first region R1 and a second peripheral circuit element 262 disposed on a second region R2. The first peripheral circuit element 261 may be disposed on a first surface 201_R1 of the first region R1 of the peripheral circuit substrate 200, and the second peripheral circuit element 262 may be disposed on a first surface 201_R2 of the second region R2 of the peripheral circuit substrate 200.

[0101] The peripheral circuit structure PERI may include: a first element isolation film 211, which divides adjacent first peripheral circuit elements 261; and a second element isolation film 212A, which divides adjacent second peripheral circuit elements 262.

[0102] The width of the first element isolation film 211 can decrease in the second direction D2 as it moves towards the second surface 202_R1 of the first region R1 along the first direction D1. The first element isolation film 211 can have a profile that appears as the first surface 201_R1 of the first region R1 is etched.

[0103] The length of the second element isolation film 212A in the first direction D1 may be longer than the length of the first element isolation film 211 in the first direction D1. In some embodiments, the width of the second element isolation film 212A in the second direction D2 may be greater than the width of the first element isolation film 211 in the second direction D2.

[0104] The second element, the isolation membrane 212A, may include a first part 212A_1 and a second part 212A_2.

[0105] The first portion 212A_1 may overlap with the first element isolation film 211 in the second direction D2. The width of the first portion 212A_1 may decrease in the second direction D2 as the distance from the first surface 201_R2 of the second region R2 along the first direction D1 increases. The length of the first portion 212A_1 in the first direction D1 may be the same as the length of the first element isolation film 211 in the first direction D1. The first portion 212A_1 may have a contour that appears as the first surface 201_R2 of the second region R2 is etched.

[0106] The second portion 212A_2 may contact the first portion 212A_1. The second portion 212A_2 may be aligned with the first portion 212A_1 in the first direction D1. The width of the second portion 212A_2 may increase in the second direction D2 as it moves along the second surface 202_R2 towards the second region R2 in the first direction D1. The width of the second portion 212A_2 in the second direction D2 may be greater than the width of the first portion 212A_1 in the second direction D2. In some embodiments, the surfaces in contact with the second portion 212A_2 and the first portion 212A_1 may have the same width in the second direction D2. The second portion 212A_2 may have a contour that appears as the second surface 202_R2 of the second region R2 is etched.

[0107] refer to Figure 5 The first portion 212A_1 and the second portion 212A_2 can have the same etch profile. For example, each of the first portion 212A_1 and the second portion 212A_2 can be formed by dry etching.

[0108] The first portion 212A_1 of the second element isolation film 212A may include a second base surface 212a that is coplanar with the first surface 201_R2 of the second region R2. The second portion 212A_2 of the second element isolation film 212A may include a third base surface 212b that is coplanar with the second surface 202_R2 of the second region R2.

[0109] The side surface of the first portion 212A_1 of the second element isolation film 212A may have an angle θ1 with the second base surface 212a. The side surface of the second portion 212A_2 of the second element isolation film 212A may have an angle θ2 with the third base surface 212b.

[0110] The angle θ1 between the side surface of the first part 212A_1 and the second base surface 212a can be the same as the angle θ2 between the side surface of the second part 212A_2 and the third base surface 212b. Since the first part 212A_1 and the second part 212A_2 are each formed by a dry etching process, the side surfaces of the first part 212A_1 and the second part 212A_2 can each have the same tilt.

[0111] Figure 6 This is a diagram used to illustrate a semiconductor memory device according to some embodiments. Figure 7 yes Figure 6 A magnified view of the boxed area C. For reference. Figure 6 It can correspond to along Figure 1 A cross-sectional view taken by line X-X'.

[0112] refer to Figure 6 According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI). The PERI may be disposed on the cell structure (CELL). A description of the cell structure (CELL) can be found in the reference above. Figures 1 to 3 The content described is the same.

[0113] The plurality of peripheral circuit elements 260 may include a first peripheral circuit element 261 disposed on a first region R1 and a second peripheral circuit element 262 disposed on a second region R2. The first peripheral circuit element 261 may be disposed on a first surface 201_R1 of the first region R1 of the peripheral circuit substrate 200, and the second peripheral circuit element 262 may be disposed on a first surface 201_R2 of the second region R2 of the peripheral circuit substrate 200.

[0114] The peripheral circuit structure PERI may include: a first element isolation film 211 that separates adjacent first peripheral circuit elements 261 from each other; and a second element isolation film 212B that separates adjacent second peripheral circuit elements 262 from each other.

[0115] The width of the first element isolation film 211 can decrease in the second direction D2 as it moves towards the second surface 202_R1 of the first region R1 along the first direction D1. The first element isolation film 211 can have a profile that appears as the first surface 201_R1 of the first region R1 is etched.

[0116] The length of the second element isolation film 212B in the first direction D1 may be longer than the length of the first element isolation film 211 in the first direction D1. In some embodiments, the width of the second element isolation film 212B in the second direction D2 may be greater than the width of the first element isolation film 211 in the second direction D2.

[0117] The second element, the isolation membrane 212A, may include a first part 212B_1 and a second part 212B_2.

[0118] The first portion 212B_1 may overlap with the first element isolation film 211 in the second direction D2. The width of the first portion 212B_1 may decrease in the second direction D2 as the distance from the first surface 201_R2 of the second region R2 along the first direction D1 increases. The length of the first portion 212B_1 in the first direction D1 may be the same as the length of the first element isolation film 211 in the first direction D1. The first portion 212B_1 may have a contour that appears as the first surface 201_R2 of the second region R2 is etched.

[0119] The second portion 212B_2 can contact the first portion 212B_1. The second portion 212B_2 can be aligned with the first portion 212B_1 in the first direction D1. The width of the second portion 212B_2 can increase in the second direction D2 as it moves along the second surface 202_R2 towards the second region R2 from the first direction D1. The rate at which the width of the second portion 212B_2 of the second element isolation film 212B increases in the second direction D2 can be greater than [missing information]. Figure 5 The width of the second portion 212A_2 of the second element isolation membrane 212A shown increases at the rate of increase in the second direction D2.

[0120] The width of the second portion 212B_2 in the second direction D2 may be greater than the width of the first portion 212B_1 in the second direction D2. In some embodiments, the surfaces in contact with the second portion 212B_2 and the first portion 212B_1 may have the same width in the second direction D2. The second portion 212B_2 may have a contour that appears as the second surface 202_R2 of the second region R2 is etched. For example, the second portion 212B_2 may be formed by wet etching.

[0121] refer to Figure 7 The first part 212B_1 and the second part 212B_2 can have different etching profiles. For example, the first part 212B_1 can be formed by dry etching, and the second part 212B_2 can be formed by wet etching.

[0122] The first portion 212B_1 of the second element isolation film 212B may include a second base surface 212a that is coplanar with the first surface 201_R2 of the second region R2. The second portion 212B_2 of the second element isolation film 212B may include a third base surface 212b that is coplanar with the second surface 202_R2 of the second region R2.

[0123] An angle θ1 may exist between the side surface of the first portion 212B_1 of the second element isolation film 212B and the second base surface 212a. An angle β1 may exist between the side surface of the second portion 212B_2 of the second element isolation film 212B and the third base surface 212b. The angle β1 between the side surface of the second portion 212B_2 and the third base surface 212b may be smaller than the angle θ1 between the side surface of the first portion 212B_1 and the second base surface 212a. For example, the angle β1 between the side surface of the second portion 212B_2 and the third base surface 212b may be determined based on the crystal orientation of the peripheral circuit substrate 200. For example, if the peripheral circuit substrate 200 comprises or has a (100) crystal orientation of single-crystal silicon, the angle β1 between the side surface of the second portion 212B_2 and the third base surface 212b may be approximately 54.7 degrees. As described above, since the first part 212B_1 and the second part 212B_2 are formed by different etching processes, the side surfaces of the first part 212A_1 and the second part 212A_2 can have different inclinations.

[0124] An angle β2 may exist between the side surface of the first peripheral insulating layer 251 and the second surface 202_R1 of the first region R1. The two side surfaces of the first peripheral insulating layer 251 may be inclined to be dispersed from each other along the first direction D1. The width of the first peripheral insulating layer 251 in the second direction D2 may increase with increasing distance from the second surface 202_R1 of the first region R1 along the first direction D1. For example, the angle β2 between the second surface 202_R1 of the first region R1 and the side surface of the first peripheral insulating layer 251 may be an obtuse angle. The angle β2 between the second surface 202_R1 of the first region R1 and the side surface of the first peripheral insulating layer 251 may be greater than... Figure 3 The angle α between the second surface 202_R1 of the first region R1 and the side surface of the first peripheral insulating layer 251.

[0125] The angle β1 between the side surface of the second portion 212B_2 of the second element isolation film 212B and the third base plane 212b, and the angle β2 between the side surface of the first peripheral insulating layer 251 and the second surface 202_R1 of the first region R1, can be complementary angles. For example, the sum of the angle β1 between the side surface of the second portion 212B_2 of the second element isolation film 212B and the third base plane 212b and the angle β2 between the side surface of the first peripheral insulating layer 251 and the second surface 202_R1 of the first region R1 can be 180 degrees. The angle β2 between the side surface of the first peripheral insulating layer 251 and the second surface 202_R1 of the first region R1 can also be determined according to the crystal orientation of the peripheral circuit substrate 200.

[0126] Figure 8 This is a diagram used to illustrate a semiconductor memory device according to some embodiments.

[0127] refer to Figure 8 According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI). The PERI may be disposed on the cell structure (CELL). A description of the cell structure (CELL) can be found in the reference above. Figures 1 to 3 The content described is the same.

[0128] Multiple peripheral circuit elements 260 may be disposed on the peripheral circuit substrate 200. Specifically, the multiple peripheral circuit elements 260 may be disposed on the first surface 201 of the peripheral circuit substrate 200. The peripheral circuit substrate 200 may include or be monocrystalline silicon. For example, the peripheral circuit substrate 200 may include or be monocrystalline silicon having a (100) crystal orientation.

[0129] The peripheral circuit substrate 200 may include a first region R1 and second regions R2 disposed on both sides of the first region R1. The first region R1 and the second region R2 may be adjacent to each other in the second direction D2. The first region R1 may be disposed between the second regions R2.

[0130] The plurality of peripheral circuit elements 260 may include a first peripheral circuit element 261 disposed on a first region R1 and a second peripheral circuit element 262 disposed on a second region R2. The first peripheral circuit element 261 may be disposed on a first surface 201_R1 of the first region R1 of the peripheral circuit substrate 200, and the second peripheral circuit element 262 may be disposed on a first surface 201_R2 of the second region R2 of the peripheral circuit substrate 200.

[0131] The peripheral circuit structure PERI may include a third element isolation film 213 that separates the first peripheral circuit element 261 and the second peripheral circuit element 262. For example, the third element isolation film 213 may be located on the boundary between the first region R1 and the second region R2.

[0132] The third element, the isolation membrane 213, may include a first part 213_1 and a second part 213_2.

[0133] The width of the first portion 213_1 can decrease in the second direction D2 as the distance from the first surface 201 along the first direction D1 increases. The first portion 213_1 can have a contour that appears as the first surface 201 is etched. The width of the second portion 213_2 can decrease in the second direction D2 as the distance from the second surface 202 along the first direction D1 increases. The second portion 213_2 can have a contour that appears as the second surface 202 is etched. For example, the first portion 213_1 can be formed by dry etching, and the second portion 213_2 can be formed by wet etching.

[0134] The second part 213_2 of the third element isolation film 213 can be etched along the crystal orientation by wet etching.

[0135] The second surface 202_R1 of the first region R1 of the peripheral circuit substrate 200 may include a first inclined surface 202a_R1 and a second inclined surface 202b_R1. The first inclined surface 202a_R1 and the second inclined surface 202b_R1 may have contours formed by wet etching. The first region R1 of the peripheral circuit substrate 200 may have an approximately triangular shape. For example, if the peripheral circuit substrate 200 is a single-crystal silicon with a (100) crystal orientation, the angle γ between the first inclined surface 202a_R1 or the second inclined surface 202b_R1 and the first surface 201_R1 of the first region R1 may be about 53 degrees to about 56 degrees, or 53.5 degrees to 55.5 degrees, or 54 degrees to 55 degrees. Specifically, the angle γ between the first inclined surface 202a_R1 or the second inclined surface 202b_R1 and the first surface 201_R1 of the first region R1 may be about 54.7 degrees. In some embodiments, the first inclined surface 202a_R1 and the second inclined surface 202b_R1 may be symmetrical to each other.

[0136] The second surface 202_R2 of the second region R2 of the peripheral circuit substrate 200 may include an inclined surface 202a_R2 and a horizontal surface 202b_R2. The smaller of the angles between the inclined surface 202a_R2 and the horizontal surface 202b_R2 may be equal to the angle γ between the first inclined surface 202a_R1 or the second inclined surface 202b_R1 and the first surface 201_R1 of the first region R1. In some embodiments, the second surface 202_R2 of the second region R2 of the peripheral circuit substrate 200 may include different inclined surfaces, excluding the horizontal surface 202b_R2. Specifically, if the first region R1 is disposed on both sides of the second region R2, the second surface 202_R2 of the second region R2 of the peripheral circuit substrate 200 may include two inclined surfaces.

[0137] The thickness of the second region R2 of the peripheral circuit substrate 200 can be greater than the thickness of the first region R1. For example, the thickness of the horizontal surface 202b_R2 from the first surface 201 to the second region R2 can be greater than the thickness from the first surface 201 to the first region R1. The thickness of the first region R1 can be defined as the distance from the first surface 201 to the point where the first inclined surface 202a_R1 and the second inclined surface 202b_R1 intersect.

[0138] Because the first inclined surface 202a_R1 and the second inclined surface 202b_R1 have contours formed by wet etching, the second portions 213_2 of adjacent third element isolation films 213 can be connected to each other. If the length of the first region R1 in the first direction D1 is insufficient, the second portions 213_2 of adjacent third element isolation films 213 can be connected to each other. In some embodiments, if the length of the first region R1 in the first direction D1 is sufficient, the second portions 213_2 of adjacent third element isolation films 213 can be separated from each other.

[0139] The first contact portion 271 can be disposed on the second surface 202_R1 of the first region R1, and the second contact portion 272 can be disposed on the second surface 202_R2 of the second region R2. The upper surfaces of the first contact portion 271 and the second contact portion 272 can be located at the same height in a first direction. The lower surface of the first contact portion 271 can contact the portion where the first inclined surface 202a_R1 and the second inclined surface 202b_R1 intersect. The lower surface of the second contact portion 272 can be disposed on the inclined surface 202a_R2 of the second region R2.

[0140] The lengths of the first contact portion 271 and the second contact portion 272 in the first direction D1 can be the same. However, this is merely an example, and the shapes of the first contact portion 271 and the second contact portion 272 are not limited to the shapes described above. In some embodiments, the lengths of the first contact portion 271 and the second contact portion 272 in the first direction D1 can be different from each other.

[0141] Figure 9 This is a diagram used to illustrate a semiconductor memory device according to some embodiments.

[0142] refer to Figure 9 According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI). The cell structure (CELL) may be stacked on the peripheral circuit structure (PERI). Specifically, the peripheral circuit structure (PERI) may be disposed at a lower height than the cell structure (CELL) in a first direction. The peripheral circuit structure (PERI) may be disposed on the lower surface of the cell structure (CELL).

[0143] The cell structure can include a cell substrate 100, a common source plate 105, a molded structure MS, a channel structure CH, a bit line BL, a word line contact 160, a contact spacer 170, a cell wiring structure 180, etc.

[0144] A common source plate 105 can be disposed on the first surface 100_A of the unit substrate 100. The common source plate 105 can be disposed on... Figure 1 The common source plate 105 can be connected to the channel structure CH. For example, the common source plate 105 can be electrically connected to the channel layer of the channel structure CH. The common source plate 105 can be connected to the source contact 184 in the through region THR. The common source plate 105 can be configured as the common source line of the semiconductor memory device (e.g., Figure 16 (CSL). For example, the common source plate 105 may include polysilicon or metal doped with impurities, but the embodiments are not limited thereto.

[0145] A molded structure MS can be disposed on a common source plate 105. The molded structure MS can be disposed on the cell array region CAR and the extension region EXT of the cell substrate 100. The molded structure MS may include a plurality of molded insulating layers 110 and a plurality of gate electrodes 120 alternately stacked along a first direction D1. Each molded insulating layer 110 and each gate electrode 120 may have a structure stacked on top of each other, extending parallel to the first surface 100_A of the cell substrate 100. The gate electrodes 120 may be sequentially stacked on the common source plate 105 and spaced apart from each other by the molded insulating layers 110.

[0146] In some embodiments, some of the gate electrodes 120 may be configured as ground select lines (GSL) of a semiconductor memory device. Other gate electrodes 120 may be configured as serial select lines (SSL) of a semiconductor memory device. For example, among the gate electrodes 120, the gate electrode 120 adjacent to the common source plate 105 may be configured as a ground select line (GSL). Among the gate electrodes 120, the gate electrode 120 adjacent to the bit line BL may be configured as a serial select line (SSL). However, the embodiments are not limited to the above. The arrangement and number of ground select lines (GSL) and serial select lines (SSL) may vary.

[0147] The description of the PERI peripheral circuit structure can be found in the above reference. Figures 1 to 8 The content described is the same. For example, Figure 9 The PERI peripheral circuit structure is merely an example, and the PERI peripheral circuit structure according to the various embodiments described above can be applied.

[0148] The cell structure (CELL) can be bonded to the peripheral circuit structure (PERI). The structure can be provided by forming a first chip including the PERI on a first wafer and a second chip including the cell structure (CELL) on a second wafer, and then connecting the first and second chips to each other using a bonding method.

[0149] Figures 10 to 12 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0150] The wafer or chip on which the peripheral circuit structure is to be formed can have been previously bonded to the wafer or chip that has a cell structure formed thereon. For example, the bonding method can be hybrid bonding.

[0151] refer to Figure 10 The first element isolation film 211, the second element isolation film 212 and a plurality of peripheral circuit elements 260 may be formed on the first surface 201 or the front side of the peripheral circuit substrate 200.

[0152] Etching can begin at the first surface 201 of the peripheral circuit substrate 200. For example, the etching process can be performed by dry etching. A portion of the peripheral circuit substrate 200 can be selectively removed from the first surface 201 by a dry etching process to form a trench.

[0153] In the first region R1, a trench can be formed from the first surface 201 to a predetermined position in the peripheral circuit substrate 200. In the second region R2, a trench can be formed from the first surface 201 to the rear side of the peripheral circuit substrate 200. For example, the depth of the trench formed in the second region R2 can be greater than the depth of the trench formed in the first region R1.

[0154] Silicon oxide, silicon nitride, or a combination thereof may fill the interior of the trench. A first element isolation film 211 and a second element isolation film 212 may be formed within the trench. The first element isolation film 211 may be formed to extend through a portion of the first region R1, and the second element isolation film 212 may extend completely through the second region R2.

[0155] A first peripheral circuit element 261 can be formed between adjacent first element isolation films 211. A second peripheral circuit element 262 can be formed on the peripheral circuit substrate 200 between adjacent second element isolation films 212. For example, a first gate insulating film 261b and a first gate electrode 261a can be formed on the peripheral circuit substrate 200 separated by the first element isolation films 211, and a second gate insulating film 262b and a second gate electrode 262a can be formed on the peripheral circuit substrate 200 separated by the second element isolation films 212. An interlayer insulating film 240, a peripheral wiring structure 280, a peripheral bonding pad 285, etc., can be formed.

[0156] A planarization process can be performed on the back side of the peripheral circuit substrate 200. For example, the planarization process can be performed by a chemical physical polishing (CMP) process. Planarization can be performed up to the location where the isolation film 212 of the second element can be exposed. The second surface 202_R2 of the second region R2 can be formed by the planarization process.

[0157] The first region R1 and the second region R2 of the peripheral circuit substrate 200 can have the same thickness. The second peripheral circuit element 262 can be completely separated from each other by the second element isolation film 212. For example, the second element isolation film 212 can be exposed by a planarization process, and the first element isolation film 211 can be left unexposed.

[0158] refer to Figure 11 An etch-back process can be selectively performed on the back side of the peripheral circuit substrate 200. An etching mask can be disposed on the second region R2 of the peripheral circuit substrate 200, and an etch-back process can be performed on the first region R1. The etch-back can proceed to a location where the first element isolation film 211 can be exposed. The second surface 202_R1 of the first region R1 can be formed by the etch-back process.

[0159] In some embodiments, an inclined surface forming a predetermined angle with the second surface 202_R1 may be formed in a first region R1 of the peripheral circuit substrate 200. This may be an etch profile formed by an etch-back process.

[0160] The first region R1 and the second region R2 of the peripheral circuit substrate 200 can have different thicknesses. Specifically, the thickness of the second region R2 of the peripheral circuit substrate 200 can be greater than the thickness of the first region R1 of the peripheral circuit substrate 200.

[0161] The peripheral insulating layer 250 may be formed on the second surface of the peripheral circuit substrate 200. The peripheral insulating layer 250 may be formed in both the first region R1 and the second region R2. The peripheral insulating layer 250 may include a first peripheral insulating layer 251 disposed on the second surface 202_R1 of the first region R1, and a second peripheral insulating layer 252 disposed on the second surface 202_R2 of the second region R2 and the second element isolation film 212.

[0162] A silicon oxide layer of sufficient thickness can be formed on the upper surface of the first peripheral insulating layer 251, positioned at the same height as or higher than the upper surface of the second peripheral insulating layer 252 in the first direction. A planarization process can be performed on the upper surfaces of the first and second peripheral insulating layers 251. The upper surfaces of the first and second peripheral insulating layers 252 can be located at the same height. For example, the upper surfaces of the first and second peripheral insulating layers 251 can be coplanar.

[0163] refer to Figure 12 Each of the first peripheral insulating layer 251 and the second peripheral insulating layer 252 can be selectively etched and filled with a conductive material. The first peripheral insulating layer 251 can be removed to the location where the second surface 202_R1 of the first region R1 can be exposed, and the second peripheral insulating layer 252 can be removed to the location where the second surface 202_R2 of the second region R2 can be exposed.

[0164] Body contact portion 270 may be formed in the portion where the first peripheral insulating layer 251 and the second peripheral insulating layer 252 have been removed. The portion where the first peripheral insulating layer 251 and the second peripheral insulating layer 252 have been removed may be filled with conductive material. The first body contact portion 271 may be formed within the first peripheral insulating layer 251, and the second body contact portion 272 may be formed within the second peripheral insulating layer 252.

[0165] The lower surface of the first body contact 271 can contact the first region R1 of the peripheral circuit substrate 200, and the lower surface of the second body contact 272 can contact the second region R2 of the peripheral circuit substrate 200. The upper surfaces of the first body contact 271 and the second body contact 272 can be coplanar with the upper surfaces of the first peripheral insulating layer 251 and the second peripheral insulating layer 252. The first body contact 271 and the second body contact 272 can be formed with upper wiring, through which a body voltage can be applied.

[0166] Figures 13 to 15 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. In the following text, for ease of description, [the following will be omitted / referred to as "symbols"]. Figures 10 to 12 The same operation or component as the embodiment is described in detail.

[0167] refer to Figure 13 The first element isolation film 211, the first portion 212A_1 of the second element isolation film, and a plurality of peripheral circuit elements 260 may be formed on the first surface 201 or the front side of the peripheral circuit substrate 200.

[0168] Etching can begin at the first surface 201 of the peripheral circuit substrate 200. For example, the etching process can be performed by dry etching. A portion of the peripheral circuit substrate 200 can be selectively removed from the first surface 201 by a dry etching process to form a trench.

[0169] Trenches can be formed in the first region R1 and the second region R2, extending from the first surface 201 to predetermined locations in the peripheral circuit substrate 200. For example, the depth of the trench formed in the first region R1 can be the same as the depth of the trench formed in the second region R2. Silicon oxide, silicon nitride, or a combination thereof can fill the interior of the trenches.

[0170] The first portion 212A_1 of the second element isolation membrane and the first element isolation membrane 211 can be formed within the trench. The first portion 212A_1 of the second element isolation membrane and the first element isolation membrane 211 can be formed as a portion passing through the first region R1. The length of the first element isolation membrane 211 and the length of the first portion 212A_1 of the second element isolation membrane can be the same as each other.

[0171] A first peripheral circuit element 261 can be formed between adjacent first element isolation films 211. A second peripheral circuit element 262 can be formed on the peripheral circuit substrate 200 between adjacent first portions 212A_1 of second element isolation films. For example, a first gate insulating film 261b and a first gate electrode 261a can be formed on the peripheral circuit substrate 200 between adjacent first element isolation films 211, and a second gate insulating film 262b and a second gate electrode 262a can be formed on the peripheral circuit substrate 200 between adjacent first portions 212A_1 of second element isolation films. An interlayer insulating film 240, a peripheral wiring structure 280, a peripheral bonding pad 285, etc., can be formed.

[0172] A planarization process can be performed on the back side of the peripheral circuit substrate 200 and carried out to a predetermined position. For example, the planarization process can be performed by a chemical physical polishing (CMP) process. The second surface 202_R2 of the second region R2 can be formed by the planarization process. The first region R1 and the second region R2 of the peripheral circuit substrate 200 can have the same thickness.

[0173] refer to Figure 14 and Figure 15 An etch-back process can be selectively performed on the back side of the peripheral circuit substrate 200. An etch-back process can be performed on the first region R1. The etch-back can proceed to a location where the first element isolation film 211 can be exposed. The second surface 202_R1 of the first region R1 can be formed by the etch-back process. A pattern mask PM can be disposed on the second region R2 of the peripheral circuit substrate 200. The portion of the second region R2 exposed by the pattern mask PM can be selectively removed. A trench TR can be formed on the second region R2 by an etching process. Both the etch-back process performed on the first region R1 and the etching process performed on the second region R2 can be dry etching. In some embodiments, the etch-back process performed on the first region R1 and the etching process performed on the second region R2 can be performed simultaneously.

[0174] In some embodiments, an inclined surface forming a predetermined angle with the second surface 202_R1 may be formed in a first region R1 of the peripheral circuit substrate 200. This may be an etch profile formed by an etch-back process.

[0175] The first region R1 and the second region R2 of the peripheral circuit substrate 200 can have different thicknesses. Specifically, the thickness of the second region R2 of the peripheral circuit substrate 200 can be greater than the thickness of the first region R1 of the peripheral circuit substrate 200.

[0176] Silicon oxide, silicon nitride, or a combination thereof may be filled inside the trench TR formed in the second region R2 of the peripheral circuit substrate 200. The silicon oxide, silicon nitride, or a combination thereof filled in the trench TR may form the second portion 212A_2 of the second element isolation film.

[0177] The peripheral insulating layer 250 may be formed on the second surface of the peripheral circuit substrate 200. The peripheral insulating layer 250 may be formed in both the first region R1 and the second region R2. The peripheral insulating layer 250 may include a first peripheral insulating layer 251 disposed on the second surface 202_R1 of the first region R1, and a second peripheral insulating layer 252 disposed on the second surface 202_R2 of the second region R2 and the second portion 212A_2 of the second element isolation film.

[0178] A silicon oxide layer of sufficient thickness can be formed on the upper surface of the first peripheral insulating layer 251, positioned at the same height as or higher than the upper surface of the second peripheral insulating layer 252 in the first direction. A planarization process can be performed on the upper surfaces of both the first and second peripheral insulating layers 251. The upper surfaces of the first and second peripheral insulating layers 252 can be at the same height in the first direction. For example, the upper surfaces of the first and second peripheral insulating layers 251 can be coplanar.

[0179] Each of the first peripheral insulating layer 251 and the second peripheral insulating layer 252 can be selectively etched and filled with a conductive material. The first peripheral insulating layer 251 can be removed to the location where the second surface 202_R1 of the first region R1 can be exposed, and the second peripheral insulating layer 252 can be removed to the location where the second surface 202_R2 of the second region R2 can be exposed.

[0180] Body contact portion 270 may be formed in the portion where the first peripheral insulating layer 251 and the second peripheral insulating layer 252 have been removed. The portion where the first peripheral insulating layer 251 and the second peripheral insulating layer 252 have been removed may be filled with conductive material. The first body contact portion 271 may be formed within the first peripheral insulating layer 251, and the second body contact portion 272 may be formed within the second peripheral insulating layer 252.

[0181] The lower surface of the first body contact 271 can contact the first region R1 of the peripheral circuit substrate 200, and the lower surface of the second body contact 272 can contact the second region R2 of the peripheral circuit substrate 200. The upper surfaces of the first body contact 271 and the second body contact 272 can be coplanar with the upper surfaces of the first peripheral insulating layer 251 and the second peripheral insulating layer 252. The first body contact 271 and the second body contact 272 can be formed with upper wiring, through which a body voltage can be applied.

[0182] Figure 16 These are block diagrams provided as examples to illustrate electronic systems according to some embodiments.

[0183] refer to Figure 16 Electronic system 1000 may include reference Figure 1 and Figure 9 The semiconductor device 1100 and the controller 1200 electrically connected to the semiconductor device 1100 are described. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0184] Semiconductor device 1100 can be, for example, the one referenced above. Figure 1 and Figure 9 The described NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may be a peripheral circuit structure including a decoding circuit 1110, a page buffer 1120, and logic circuit 1130. The first structure 1100F may include peripheral circuit structures (e.g., Figure 2 (PERI). For example, the first structure 1100F may include multiple peripheral circuit structures stacked by a bonding method. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0185] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary according to the example embodiment.

[0186] In some embodiments, each of the upper transistors UT1 and UT2 may include a string select transistor, and each of the lower transistors LT1 and LT2 may include a ground select transistor. Each of the lower gate lines LL1 and LL2 may be the gate electrode of the lower transistors LT1 and LT2. Each of the word lines WL may be the gate electrode of the memory cell transistor MCT, and each of the upper gate lines UL1 and UL2 may be the gate electrode of the upper transistors UT1 and UT2, respectively.

[0187] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can each be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from within the first structure 1100F to the second structure 1100S.

[0188] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from inside the first structure 1100F to the second structure 1100S.

[0189] A controller can be a processor (i.e., hardware circuitry), such as a microprocessor, CPU (Central Processing Unit), GPU (Graphics Processing Unit), digital signal processor (DSP), field-programmable gate array (FPGA), etc., and can be part of a computer. Such a controller can be formed by several interconnected controllers and can be configured by software.

[0190] For example, controller 1200 may include processor 1210, NAND controller 1220, and host interface 1230. According to some embodiments, electronic system 1000 may include multiple semiconductor devices 1100, and in this case, controller 1200 may control multiple semiconductor devices 1100.

[0191] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent through NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When receiving control commands from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0192] Figure 17 This is an example perspective view illustrating an electronic system including semiconductor memory devices according to some embodiments. Figure 18 It is along Figure 17 A schematic cross-sectional view of the line V-V'.

[0193] refer to Figure 17 The electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0194] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host via an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), and / or M-Phy for Universal Flash Storage (UFS). In some embodiments, the electronic system 2000 may be operated by power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0195] The controller 2002 can record data in or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0196] DRAM 2004 can serve as a buffer memory to mitigate speed differences between the external host and semiconductor package 2003 and as a data storage space. The DRAM 2004 included in the electronic system 2000 can also function as a cache and provide space for temporary data storage during control operations on the semiconductor package 2003. If the electronic system 2000 includes DRAM 2004, then in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0197] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0198] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each of the plurality of semiconductor chips 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 16 Input / output pads 1101. Each semiconductor chip 2200 may include metal lines 3210 and channel structures 3220. Each semiconductor chip 2200 may include the above-referenced... Figure 1 and Figure 9 The semiconductor device described.

[0199] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a bonding wire method and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) rather than a bonding wire type connection structure 2400.

[0200] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected by wiring formed on the interposer substrate.

[0201] In some embodiments, the packaging substrate 2100 may be a printed circuit board. The packaging substrate 2100 may include a packaging substrate body portion 2120, an upper packaging pad 2130 disposed on an upper surface of the packaging substrate body portion 2120, a lower packaging pad 2125 disposed on or exposed through a lower surface of the packaging substrate body portion 2120, and internal wiring 2135 within the packaging substrate body portion 2120 electrically connecting the upper pad 2130 and the lower pad 2125. The upper pad 2130 may be electrically connected to a connection structure 2400. The lower pad 2125 may be connected to a conductive connection 2800. Figure 17 Wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 shown.

[0202] In an electronic system according to some embodiments, each semiconductor chip 2200 may include the above-mentioned... Figure 1 and Figure 9The semiconductor device described. For example, at least some semiconductor chips 2200 may include peripheral circuit structures (PERIs) disposed on the cell structure (CELL). In another example, at least some semiconductor chips 2200 may include cell structures (CELLs) disposed on the peripheral circuit structure (PERI). For example, the peripheral circuit structure (PERI) may include the above-referenced... Figure 1 and Figure 9 The peripheral circuit substrate 200 and peripheral wiring structure 280 are described. Additionally, for example, the cell structure (CELL) may include the features described above. Figures 1 to 9 The cell substrate 100, molded structure MS, channel structure CH, bit line BL, word line contact 160, and contact spacer 170 are described. The peripheral circuit structure PERI and the cell structure CELL can contact or bond to each other through cell bonding pad 185 and peripheral bonding pad 285.

[0203] Although the present disclosure has been described above with reference to certain embodiments and accompanying drawings, the invention is not limited thereto, and those skilled in the art can make various changes and modifications within the scope of the technical concept of the present disclosure and the equivalents of the following claims.

Claims

1. A semiconductor memory device, comprising: The unit structure includes a unit wiring structure and a unit bonding pad electrically connected to the unit wiring structure. as well as A peripheral circuit structure includes: a peripheral circuit substrate, including a first surface and a second surface facing the first surface; a plurality of peripheral circuit elements disposed on the first surface of the peripheral circuit substrate; a peripheral wiring structure electrically connected to the plurality of peripheral circuit elements; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad. The plurality of peripheral circuit elements includes a plurality of first peripheral circuit elements disposed in a first region of the peripheral circuit substrate and a plurality of second peripheral circuit elements disposed in a second region of the peripheral circuit substrate. The thickness of the second region of the peripheral circuit substrate in the first direction is greater than the thickness of the first region of the peripheral circuit substrate in the first direction. The first surface of the peripheral circuit substrate extends in the second direction, and The first direction intersects with the second direction.

2. The semiconductor memory device according to claim 1, wherein, A first voltage is applied to the plurality of first peripheral circuit elements, and A second voltage, higher than the first voltage, is applied to the plurality of second peripheral circuit elements.

3. The semiconductor memory device according to claim 1, wherein, Each of the plurality of first peripheral circuit elements includes a first gate insulating film and a first gate electrode. Each of the plurality of second peripheral circuit elements includes a second gate insulating film and a second gate electrode. In the second direction, the length of the second gate insulating film is longer than the length of the first gate insulating film, and In the second direction, the length of the second gate electrode is longer than the length of the first gate electrode.

4. The semiconductor memory device according to claim 1, wherein, The peripheral circuit structure includes: A first element isolation film is disposed in the first region of the peripheral circuit substrate in the first direction, and separates adjacent first peripheral circuit elements among the plurality of first peripheral circuit elements; and A second element isolation film is located in the second region of the peripheral circuit substrate in the first direction, and separates adjacent second peripheral circuit elements among the plurality of second peripheral circuit elements. The length of the second element isolation membrane in the first direction is longer than the length of the first element isolation membrane in the first direction.

5. The semiconductor memory device according to claim 4, wherein, The first element isolation film includes a first base surface that is coplanar with the first surface of the first region. The second element isolation film includes a second base surface coplanar with the first surface of the second region, and In the second direction, the width of the second base surface is greater than the width of the first base surface.

6. The semiconductor memory device according to claim 5, wherein, The width of the second element isolation film in the second direction decreases as it approaches the second surface of the second region along the first direction.

7. The semiconductor memory device according to claim 5, wherein, The width of the first element isolation film in the second direction decreases as the second surface moves along the first direction toward the first region, and The second element, the insulating membrane, includes: The first portion overlaps with the first element isolation film in the second direction, and the width of the first portion in the second direction decreases as the distance from the first surface of the second region in the first direction increases; and The second portion contacts the first portion, and the width of the second portion in the second direction increases with the second surface along the first direction toward the second region.

8. The semiconductor memory device according to claim 7, wherein, The second portion includes a third base surface that is coplanar with the second surface of the second region, and The angle between the side surface of the second part and the third base surface is smaller than the angle between the side surface of the first part and the second base surface.

9. The semiconductor memory device according to claim 1, wherein, The second surface of the first region includes a first inclined surface and a second inclined surface, the first inclined surface and the second inclined surface being inclined such that the width of the first region in the second direction decreases as the second surface of the first region moves toward the second region along the first direction.

10. The semiconductor memory device according to claim 9, wherein, The angle between the first inclined surface or the second inclined surface and the first surface of the first region is 53 to 56 degrees.

11. The semiconductor memory device according to claim 4, wherein, The peripheral circuit structure further includes a first peripheral insulating layer disposed on a first region of the peripheral circuit substrate and in contact with the isolation film of the first element. The first peripheral insulating layer has two opposing side surfaces, and The two opposing side surfaces of the first peripheral insulating layer include corresponding inclined portions to be dispersed from each other as they face the second surface of the peripheral circuit substrate along the first direction.

12. The semiconductor memory device according to claim 11, wherein, The peripheral circuit structure further includes a second peripheral insulating layer disposed on the second region of the peripheral circuit substrate and in contact with the isolation film of the second element, and The thickness of the first peripheral insulating layer in the first direction is greater than the thickness of the second peripheral insulating layer in the first direction.

13. The semiconductor memory device according to claim 1, wherein, The peripheral circuit structure also includes a first body contact portion that contacts the second surface of the first region and a second body contact portion that contacts the second surface of the second region.

14. A semiconductor memory device, comprising: The unit structure includes a unit wiring structure and a unit bonding pad electrically connected to the unit wiring structure. as well as The peripheral circuit structure is stacked on the upper surface of the unit structure in the first direction. The peripheral circuit structure includes: A peripheral circuit substrate has a first surface and a second surface opposite to the first surface, the peripheral circuit substrate including a first region and a second region disposed along a second direction intersecting the first direction; A first peripheral circuit element is provided in the first region and a second peripheral circuit element is provided in the second region; The peripheral wiring structure is electrically connected to the first peripheral circuit element and the second peripheral circuit element; and The peripheral bonding pads are electrically connected to the peripheral wiring structure and contact the cell bonding pads. The first surface of the first region and the first surface of the second region are coplanar, and the second surface of the second region is located at a higher height than the second surface of the first region in the first direction.

15. The semiconductor memory device according to claim 14, wherein, The peripheral circuit structure also includes: A first element isolation film, in the first region of the peripheral circuit substrate in the first direction; and The second element is an isolation film, located in the second region of the peripheral circuit substrate in the first direction, and The length of the second element isolation membrane in the first direction is greater than the length of the first element isolation membrane in the first direction.

16. The semiconductor memory device according to claim 15, wherein, The lower surface of the first element isolation film is located at the same height as the first surface of the first region in the first direction, and the upper surface of the first element isolation film is located at the same height as the second surface of the first region in the first direction. The lower surface of the second element isolation film is located at the same height as the first surface of the second region in the first direction, and the upper surface of the second element isolation film is located at the same height as the second surface of the second region in the first direction.

17. The semiconductor memory device according to claim 15, wherein, The second element, the insulating membrane, includes: The first portion overlaps with the first element's insulating film in the second direction; and The second part contacts the first part and is located at a higher height than the first part in the first direction. The width of the second part in the second direction is greater than the width of the first part in the second direction.

18. The semiconductor memory device according to claim 15, wherein, The peripheral circuit structure further includes a first body contact portion that contacts the second surface of the first region and a second body contact portion that contacts the second surface of the second region. The length of the first body contact portion in the first direction is greater than the length of the second body contact portion in the first direction.

19. The semiconductor memory device according to claim 15, wherein, The peripheral circuit structure also includes: A first peripheral insulating layer is disposed on a first region of the peripheral circuit substrate and in contact with the first element isolation film; and A second peripheral insulating layer is disposed on a second region of the peripheral circuit substrate and in contact with the isolation film of the second element. The upper surface of the first peripheral insulating layer is located at the same height as the upper surface of the second peripheral insulating layer in the first direction, and the lower surface of the first peripheral insulating layer is located at a lower height than the lower surface of the second peripheral insulating layer in the first direction.

20. An electronic system comprising: Main substrate; Semiconductor memory devices are stacked on the main substrate; as well as A controller, located on the main substrate, is electrically connected to the semiconductor memory device. The semiconductor memory device includes: The cell structure includes a cell wiring structure and cell bonding pads electrically connected to the cell wiring structure; and A peripheral circuit structure includes: a peripheral circuit substrate having a first surface and a second surface facing the first surface; a plurality of peripheral circuit elements disposed on the first surface of the peripheral circuit substrate; a peripheral wiring structure electrically connected to the plurality of peripheral circuit elements; and a peripheral bonding pad electrically connected to the peripheral wiring structure and in contact with the cell bonding pad. The plurality of peripheral circuit elements includes a plurality of first peripheral circuit elements to which a first voltage is applied and a plurality of second peripheral circuit elements to which a second voltage higher than the first voltage is applied. The peripheral circuit substrate includes a first region disposed of the plurality of first peripheral circuit elements and a second region disposed of the plurality of second peripheral circuit elements. The thickness of the second region of the peripheral circuit substrate in the first direction is greater than the thickness of the first region of the peripheral circuit substrate, and the first surface of the peripheral circuit substrate extends in the second direction. The first direction intersects with the second direction.

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