Semiconductor memory device

Abstract

A semiconductor memory device can include a peripheral circuit structure including a peripheral circuit integrated on a semiconductor substrate in a first region and a first key region disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and stacked vertically; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a through-plug spaced apart from the stack and provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuit of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a through-structure provided to penetrate the molding structure and vertically overlap the first key region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a highly integrated three-dimensional semiconductor memory device. BACKGROUND

[0002] There is a need for higher integration of semiconductor devices to meet the demands of consumers for superior performance and low prices. In the case of semiconductor devices, since their integration is an important factor in determining the price of products, there is a particular need for increased integration. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, the integration is greatly affected by the level of fine patterning technology. However, in order to obtain the finest pattern, extremely expensive processing equipment is required to increase the fineness of the pattern, and there is a practical limit to increasing the integration of two-dimensional or planar semiconductor devices. To overcome this limitation, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed. SUMMARY

[0003] One or more embodiments of the present disclosure provide a highly integrated semiconductor memory device.

[0004] According to an exemplary embodiment, a semiconductor memory device includes a peripheral circuit structure including a peripheral circuit integrated on a semiconductor substrate in a first region and a first key region provided in a second region; and a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and vertically stacked in a third direction perpendicular to the first direction; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a through plug spaced apart from the stack and provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuit of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a through structure provided to penetrate the molding structure and vertically overlap the first key region.

[0005] According to an example embodiment, a semiconductor memory device includes: a peripheral circuit structure including a peripheral circuit integrated on a semiconductor substrate in a first region and a first key region disposed in a second region surrounding the first region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and vertically stacked in a third direction perpendicular to the first direction; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a through-plug provided on the first region of the peripheral circuit structure and spaced apart from the stack; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a through structure provided to penetrate the molding structure and vertically overlap the first key region, wherein an end portion of a lowermost one of the plurality of first conductive lines is spaced apart from the through structure and is closer to the through structure than an end portion of an uppermost one of the plurality of first conductive lines.

[0006] According to an example embodiment, a semiconductor memory device includes: a peripheral circuit structure including a peripheral circuit integrated on a semiconductor substrate in a first region and a first key region disposed in a second region surrounding the first region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and vertically stacked in a third direction perpendicular to the first direction; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer, the interconnection layer including a plurality of interconnection insulating layers and a plurality of vias and a plurality of interconnection lines surrounded by the plurality of interconnection insulating layers; a through-plug provided on the first region of the peripheral circuit structure and spaced apart from the stack; a contact provided on the plurality of first conductive lines of the stack and penetrating the upper insulating layer to connect the plurality of first conductive lines to the plurality of vias; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; a separation structure interposed between the molding structure and the upper insulating layer, the separation structure including an insulating pattern and an insulating pad surrounding the insulating pattern; and a through structure penetrating the molding structure and vertically overlapping the first key region, wherein an end portion of a lowermost one of the plurality of first conductive lines is spaced apart from the through structure in the first direction and is closer to the through structure than an end portion of an uppermost one of the plurality of first conductive lines. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan view illustrating a semiconductor memory device according to an embodiment.

[0009] Figure 2 is a plan view illustrating a semiconductor memory device according to an embodiment.Figure 1 A magnified perspective view of region A.

[0010] Figure 3A It is based on one implementation method along Figure 2 The cross-sectional view taken from line I-I'.

[0011] Figure 3B It is based on one implementation method along Figure 2 The cross-sectional view taken from line II-II'.

[0012] Figure 4 This illustrates an embodiment. Figure 3A Enlarged cross-sectional view of region C.

[0013] Figure 5 This illustrates an embodiment. Figure 2 A magnified plan view of region B.

[0014] Figures 6 to 13 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to one embodiment.

[0015] Figure 14 This illustrates the following according to one embodiment: Figure 2 A cross-sectional view of a semiconductor memory device taken by line I-I'. Detailed Implementation

[0016] It will be understood that when an element or layer is referred to as "above," "on top of," "above," "below," "under," "connected to," or "attached to" another element or layer, it can be directly above, above, above, below, under, connected to, or attached to the other element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as "directly above," "directly above," "directly on," "directly below," "directly under," "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers present. Throughout the text, the same reference numerals denote the same elements.

[0017] For the sake of brevity, conventional elements of semiconductor memory devices may or may not be described in detail herein. However, even if an element is described or shown in the semiconductor device of this disclosure, that element may not be included in the claimed semiconductor memory device unless the element is stated to be included in the claimed semiconductor device.

[0018] Figure 1This is a plan view showing a semiconductor memory device according to one embodiment. Figure 2 This illustrates an embodiment. Figure 1 A magnified perspective view of region A. Figure 3A It is based on one implementation method along Figure 2 The cross-sectional view taken from line I-I'. Figure 3B It is based on one implementation method along Figure 2 The cross-sectional view taken from line II-II'. Figure 4 This illustrates an embodiment. Figure 3A Enlarged cross-sectional view of region C.

[0019] refer to Figure 1 , Figure 2 , Figure 3A and Figure 3B The peripheral circuit structure 100 may include a first region R1 and a second region R2. The peripheral circuit structure 100 may include a semiconductor substrate 10, a peripheral insulating layer 20, a peripheral circuit PTR, a peripheral path 22, a peripheral line 24, and a first bond region 40.

[0020] The first region R1 can be the central region of the semiconductor device, and the second region R2 can be the edge region of the semiconductor device. The second region R2 can surround the first region R1. The first region R1 can be the region in which a peripheral circuit PTR is disposed. The peripheral circuit PTR may not be disposed in the second region R2. As an example, the first region R1 and the second region R2 can be separated from each other by a separation structure 255.

[0021] The semiconductor substrate 10 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The semiconductor substrate 10 may have an active region defined by the device isolation pattern 15.

[0022] A peripheral circuit PTR can be provided on the semiconductor substrate 10. The peripheral circuit PTR can be disposed on a first region R1, but not on a second region R2. Each peripheral circuit PTR may include a peripheral source / drain region 25, a peripheral gate spacer 26, a peripheral gate insulating layer 27, a peripheral gate electrode 28, and a peripheral cover pattern 29. The peripheral gate insulating layer 27 can be provided between the peripheral gate electrode 28 and the semiconductor substrate 10. The peripheral cover pattern 29 can be provided on the peripheral gate electrode 28. The peripheral gate spacer 26 can cover the side surfaces of the peripheral gate electrode 28, the peripheral gate insulating layer 27, and the peripheral cover pattern 29. The peripheral source / drain region 25 can be provided in the portion of the semiconductor substrate 10 adjacent to both sides of the peripheral gate electrode 28. A peripheral line 24 can be electrically connected to the peripheral circuit PTR via a peripheral path 22. Each of the peripheral line 24 and the peripheral path 22 can be formed of or include at least one of conductive materials. For example, the conductive pad 50 may be formed of or include at least one of aluminum, copper, tungsten, and / or cobalt. The peripheral circuit PTR on the semiconductor substrate 10 may be, for example, an NMOS transistor, a PMOS transistor, or a gate-all-around transistor.

[0023] A conductive pad 50 may be provided on a first region R1 of the peripheral circuit structure 100. More specifically, the conductive pad 50 may be disposed between the through-hole plug 250 and the peripheral passage 22. The conductive pad 50 may be formed of or include at least one of conductive materials. For example, the conductive pad 50 may be formed of or include at least one of aluminum, copper, tungsten, and / or cobalt. The conductive pad 50 may be connected to the peripheral circuit PTR via the peripheral passage 22. The conductive pad 50 may be used to define the location where the through-hole plug 250 will be provided. The conductive pad 50 will be described in more detail below.

[0024] A peripheral insulating layer 20 may be provided on the semiconductor substrate 10. The peripheral insulating layer 20 may cover the peripheral circuit PTR, peripheral pathway 22, and peripheral line 24 on the semiconductor substrate 10. The peripheral insulating layer 20 may be formed of or include at least one of silicon oxide, silicon nitride, silicon nitride, and / or a low-k dielectric material. The peripheral insulating layer 20 may have a multilayer structure in which multiple insulating layers are stacked. For example, the peripheral insulating layer 20 may include a first peripheral insulating layer 21 and a second peripheral insulating layer 23. The second peripheral insulating layer 23 may be stacked on the first peripheral insulating layer 21. The first peripheral insulating layer 21 may cover the peripheral circuit PTR, but may expose the top surface of the peripheral overlay pattern 29 of the peripheral circuit PTR. The second peripheral insulating layer 23 may be provided to cover the top surface of the first peripheral insulating layer 21 and the exposed top surface of the peripheral overlay pattern 29. The second peripheral insulating layer 23 may be provided to surround the peripheral line 24 and the peripheral pathway 22.

[0025] The first bonding region 40 can be provided on the semiconductor substrate 10. More specifically, the first bonding region 40 can be provided on the second peripheral insulating layer 23 and in the second region R2 of the peripheral circuit structure 100. The top surface of the first bonding region 40 can be exposed from the second peripheral insulating layer 23. The first bonding region 40 can be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, and / or cobalt). The first bonding region 40 can overlap perpendicularly with the through-structure 280. That is, the first bonding region 40 can overlap with the through-structure 280 in a third direction D3.

[0026] The peripheral circuit structure 100 may further include a second lower key region 30. The second lower key region 30 may be provided on the second region R2 of the peripheral circuit structure 100. The second lower key region 30 may be horizontally spaced from the first key region 40. For example, the second lower key region 30 may be interposed between the first key region 40 and the conductive pad 50. The second lower key region 30 may be provided on the second peripheral insulating layer 23. More specifically, the side and bottom surfaces of the second lower key region 30 may be covered by the second peripheral insulating layer 23. Furthermore, the top surface of the second lower key region 30 may be exposed from the second peripheral insulating layer 23. The top surface of the second lower key region 30 may be coplanar with the top surface of the second peripheral insulating layer 23. The second lower key region 30 may vertically overlap with the second upper key region 270. That is, the second lower key region 30 may overlap with the second upper key region 270 in the third direction D3. The second lower bond region 30 may be formed of or include at least one of the following metallic materials (e.g., aluminum, copper, tungsten and / or cobalt).

[0027] A buffer layer may be provided on the top surface of the peripheral circuit structure 100. The buffer layer may include a first buffer layer 110 and a second buffer layer 210. The first buffer layer 110 may be provided on the top surface of the peripheral circuit structure 100. More specifically, the first buffer layer 110 may cover the top surface of the second peripheral insulating layer 23, the top surface of the peripheral line 24, the top surface of the conductive pad 50, the top surface of the second lower bonding region 30, and the top surface of the first bonding region 40. The first buffer layer 110 may be formed of or include at least one of insulating materials. For example, the first buffer layer 110 may be formed of or include at least one of silicon nitride, silicon oxide, silicon oxynitride, and / or carbon-containing silicon nitride.

[0028] A second buffer layer 210 may be provided on the top surface of the first buffer layer 110. The second buffer layer 210 may have a bottom surface in contact with the top surface of the first buffer layer 110. The second buffer layer 210 may cover the top surface of the first buffer layer 110 and may also cover the bottom surface of the stack 220, the bottom surface of the upper insulating layer 230, the bottom surface of the separation structure 255, the bottom surface of the molding structure 260, the bottom surface of the second upper bond region 270, and the bottom surface of the penetration structure 280. The second buffer layer 210 may be formed of or comprise the same material as the first buffer layer 110. In this case, there may be no observable interface between the second buffer layer 210 and the first buffer layer 110, unlike what is shown in the figures.

[0029] refer to Figure 2 , Figure 3A and Figure 3B The unit cell structure SS can be provided on the top surface of the second buffer layer 210. The unit cell structure SS can be provided on the first region R1 of the peripheral circuit structure 100. The unit cell structure SS can be perpendicularly spaced from the peripheral circuit structure 100 by the first buffer layer 110 and the second buffer layer 210 interposed therebetween. Each unit cell structure SS may include a stack 220, a semiconductor pattern SP, an insulating layer IL, a data storage element DS, a second conductive line 225, and a third conductive line 227, wherein the semiconductor pattern SP and the insulating layer IL can be alternately stacked on the second buffer layer 210.

[0030] A unit cell structure SS may include a cell region CAR and a contact region CTR. The cell region CAR may be a region in which a semiconductor pattern SP is provided, and the contact region CTR may be a region in which a semiconductor pattern SP is not provided.

[0031] Semiconductor patterns SP that are vertically stacked (i.e., stacked on a third direction D3) can be perpendicularly spaced apart from each other by an insulating layer IL. The insulating layer IL can be interposed between each pair of semiconductor patterns SP that are perpendicularly adjacent to each other. The insulating layer IL may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, and / or a carbon-containing silicon oxide nitride layer.

[0032] Each semiconductor pattern SP can be a linear, strip, or columnar pattern extending in the second direction D2. The semiconductor pattern SP can be formed or include at least one of, for example, silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). Each semiconductor pattern SP can include a first impurity region, a second impurity region, and a channel region. The channel region can be disposed between the first and second impurity regions. The first and second impurity regions can be of a first conductivity type (e.g., n-type). The channel region can be undoped or can be of a second conductivity type different from the first conductivity type (e.g., p-type).

[0033] Semiconductor patterns SP can be arranged in the first column R1 to the fourth column R4. Each of the first column R1 to the fourth column R4 may include semiconductor patterns SP that are vertically stacked and overlap each other vertically. For example, as shown in the figure, the number of semiconductor patterns SP in each of the first column R1 to the fourth column R4 may be six, but one or more embodiments are not limited to this. The first column R1 to the fourth column R4 may be arranged to be spaced apart from each other in the first direction D1. The first direction D1 and the second direction D2 may be parallel to the top surface of the semiconductor substrate 10, but may not be parallel to each other. The third direction D3 may be a direction perpendicular to both the first direction D1 and the second direction D2.

[0034] Each unit cell structure SS may include a stack 220. The stack 220 may include alternating stacked first interlayer insulating layers 221 and first conductive lines 223. The vertically stacked first conductive lines 223 may be perpendicularly spaced apart from each other by the first interlayer insulating layers 221. The first interlayer insulating layers 221 may be interposed between each pair of perpendicularly adjacent first conductive lines 223.

[0035] The first conductive line 223 can be a linear or strip pattern extending in the first direction Dl. The first conductive line 223 can extend from the unit region CAR of the unit cell structure SS to the contact region CTR.

[0036] Each first conductive line 223 may be in direct contact with the semiconductor pattern SP. As an example, each first conductive line 223 may be located at substantially the same level as a corresponding one in the semiconductor pattern SP. Each first conductive line 223 may be connected to a first impurity region of the semiconductor pattern SP. The semiconductor patterns SP in the first column R1 to the fourth column R4 may extend from a corresponding one of the first conductive lines 223 in the second direction D2, while maintaining the same level as the corresponding one of the first conductive lines 223.

[0037] Reference Figure 2 Each stack 220 may have a stepped structure on the contact area CTR of the unit cell structure SS. For example, a pair of adjacent first conductive lines 223 may have the same length in the first direction D1, but the length of the topmost pair of first conductive lines 223 may be shorter than the length of the bottommost pair of first conductive lines 223. Therefore, the ends of the bottommost pair of first conductive lines 223 may be closer to the second region R2 of the peripheral circuit structure 100 than the ends of the topmost pair of first conductive lines 223.

[0038] As another example, the length of the first conductive lines 223 stacked on the contact area CTR in the first direction D1 can decrease as the distance from the top surface of the second buffer layer 210 increases. For example, the length of the lowest first conductive line 223 can be longer than the length of the remaining first conductive lines 223. The length of the highest first conductive line 223 can be shorter than the length of the remaining first conductive lines 223.

[0039] The first conductive line 223 may be formed of or comprise at least one of conductive materials. For example, the conductive material may include doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The first interlayer insulating layer 221 may be formed of or comprise at least one of insulating materials. The insulating material may include, for example, silicon oxide, silicon nitride, and / or silicon oxide nitride.

[0040] Reference Figure 3A and Figure 3B Each unit cell structure SS may also include vertically stacked data storage elements DS. The vertically stacked data storage elements DS may be perpendicularly spaced from each other by an insulating layer IL. Each data storage element DS may extend from a corresponding one in the semiconductor pattern SP in a second direction D2.

[0041] Each data storage element DS can be in direct contact with a corresponding one in the semiconductor pattern SP. As an example, each data storage element DS can be located at approximately the same height as a corresponding one in the semiconductor pattern SP. Each data storage element DS can be connected to a second impurity region of a corresponding one in the semiconductor pattern SP.

[0042] The second conductive line 225 can be provided in the cell region CAR of each unit cell structure SS to penetrate the unit cell structure SS. Each second conductive line 225 can be a cylindrical or strip pattern extending in a third direction D3 perpendicular to the top surface of the peripheral circuit structure 100. The second conductive line 225 can be arranged in a first direction D1. The second conductive line 225 can be configured to be adjacent to the first column R1 to the fourth column R4 of the semiconductor pattern SP, respectively.

[0043] As an example, the first of the second conductive lines 225 penetrating the unit cell structure SS may be adjacent to the side surface of the semiconductor pattern SP constituting the first column R1. The first conductive line 225 may extend vertically on the side surface of the semiconductor pattern SP constituting the first column R1. The second conductive line 225 penetrating the unit cell structure SS may be adjacent to the side surface of the semiconductor pattern SP constituting the second column R2. The second conductive line 225 may extend vertically on the side surface of the semiconductor pattern SP constituting the second column R2. A vertical insulating pattern VIP may be interposed between the first conductive line 225 and the semiconductor pattern SP of the second column R2. The vertical insulating pattern VIP may include a silicon oxide layer.

[0044] A gate insulating layer GI can be disposed between the second conductive line 225 and the channel region CH of the semiconductor pattern SP. The gate insulating layer GI can be formed or comprise at least one of a high-k dielectric material, silicon oxide, silicon nitride, and / or silicon nitride, and can have a single-layer or multi-layer structure. In one embodiment, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. The second conductive line 225 can be formed or comprise at least one of a conductive material, and the conductive material may include a doped semiconductor material, a conductive metal nitride, a metal, or a metal semiconductor compound.

[0045] The third conductive line 227 may be provided in the cell region CAR of the unit cell structure SS and extend parallel to the stack 220 in the first direction D1. The third conductive line 227 may be formed of or include at least one of conductive materials, and the conductive material may be one of doped semiconductor materials, conductive metal nitrides, metals, and metal semiconductor compounds. At least one of the third conductive lines 227 may be used as a common ground wire.

[0046] An upper insulating layer 230 may be provided on the top surface of the second buffer layer 210. An upper insulating layer 230 may be provided on a first region R1 of the peripheral circuit structure 100. The upper insulating layer 230 may cover the top surface and ends of the stack 220. The upper insulating layer 230 may be formed of or include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride).

[0047] Contact 240 may contact the first conductive line 223 and is provided on the stack 220. Contact 240 may penetrate the upper insulating layer 230 to electrically connect the interconnect layer 300 to the first conductive line 223. Contact 240 may be provided in the contact region CTR of the unit cell structure SS and on the stepped structure of the stack 220. Therefore, as the distance from one end of the unit cell region CAR decreases in the first direction D1, the level of the bottom surface of contact 240 may be raised. Contact 240 may be formed of or include at least one of conductive materials. For example, contact 240 may be formed of or include at least one of aluminum, copper, tungsten and / or cobalt.

[0048] A molded structure 260 may be provided on a second region R2 of the peripheral circuit structure 100. The molded structure 260 may include alternately stacked first layers 261 and second layers 263. The vertically stacked first layers 261 may be perpendicularly spaced from each other by the second layers 263. More specifically, the second layers 263 may be interposed between each pair of adjacent first layers 261. Each first layer 261 may be provided at the same level as a corresponding first conductive line 223 in the stack 220. Each second layer 263 may be provided at the same level as a corresponding first layer insulating layer 221 in the stack 220. The first layers 261 and second layers 263 may be formed of or comprise silicon. As an example, the first layer 261 may be a silicon layer, and the second layer 263 may be a silicon-germanium layer. The bottom surface of the molded structure 260 may contact the top surface of the second buffer layer 210, and the top surface 260a of the molded structure 260 may contact the interconnect layer 300.

[0049] A separation structure 255 may be interposed between the molded structure 260 and the upper insulating layer 230. The separation structure 255 may include an insulating pattern 251 and an insulating pad 253 surrounding the insulating pattern 251. The insulating pattern 251 and the insulating pad 253 may be formed of or comprise at least one of an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride). The upper insulating layer 230 and the molded structure 260 may be horizontally spaced apart from each other, and the separation structure 255 is interposed between them. Therefore, the separation structure 255 may have opposite side surfaces that contact the upper insulating layer 230 and the molded structure 260, respectively. As another example, the separation structure 255 may serve as a boundary between a first region R1 and a second region R2 of the peripheral circuit structure 100. However, the separation structure 255 may be omitted.

[0050] A through-hole plug 250 may be provided on a first region R1 of the peripheral circuit structure 100. The through-hole plug 250 may penetrate the upper insulating layer 230, the second buffer layer 210, and the first buffer layer 110, and may connect the interconnect layer 300 to the peripheral circuit structure 100. More specifically, the through-hole plug 250 may contact the top surface of the conductive pad 50 of the peripheral circuit structure 100. As an example, the through-hole plug 250 may be provided between the separation structure 255 and the stack 220. The through-hole plug 250 may be spaced apart from the stack 220, and the upper insulating layer 230 may be interposed between the through-hole plug 250 and the stack 220. The through-hole plug 250 may be formed of or comprise the same material as the contact 240. For example, the through-hole plug 250 may be formed of or comprise at least one of aluminum, copper, tungsten, and / or cobalt.

[0051] The second upper key region 270 can be provided on the top surface of the second buffer layer 210. The second upper key region 270 can also be provided on the second region R2 of the peripheral circuit structure 100. More specifically, the second upper key region 270 can be interposed between the molding structure 260 and the second buffer layer 210. The top and side surfaces of the second upper key region 270 can be covered by the molding structure 260, while the bottom surface of the second upper key region 270 may not be covered by the molding structure 260. The bottom surface of the second upper key region 270 may be coplanar with the bottom surface of the molding structure 260. The second upper key region 270 may be spaced apart from the penetration structure 280. For example, the second upper key region 270 may be disposed between the separation structure 255 and the penetration structure 280. The second upper key region 270 may be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, and / or cobalt). The second upper key region 270 can be vertically overlapped with the second lower key region 30 of the peripheral circuit structure 100.

[0052] Further reference Figure 2 and Figure 3A The penetrating structure 280 can be provided on the top surface of the second buffer layer 210. The penetrating structure 280 can be provided on the second region R2 of the peripheral circuit structure 100. The penetrating structure 280 can be provided as a penetrating molded structure 260. Therefore, the bottom surface 280b of the penetrating structure 280 can contact the top surface of the second buffer layer 210, and the top surface 280a of the penetrating structure 280 can contact the bottom surface of the interconnect layer 300. The top surface of the penetrating structure 280 can be coplanar with the top surface of the molded structure 260. The penetrating structure 280 can be shaped like a polygonal pillar perpendicularly penetrating the molded structure 260. However, the structure of the penetrating structure 280 is not limited to this. The penetrating structure 280 can have any shape suitable for penetrating the molded structure 260.

[0053] The side surface 280c of the penetrating structure 280 may be inclined at an angle relative to the top surface of the second buffer layer 210. The first angle q1 between the side surface 280c of the penetrating structure 280 and the top surface 210a of the second buffer layer 210 may be an acute angle. For example, the first angle q1 may be in the range of approximately 50° to 90°. The width W1 of the penetrating structure 280 in the first direction D1 may decrease as the distance from the top surface of the second buffer layer 210 increases in the third direction D3. Therefore, the width of the bottom surface 280b of the penetrating structure 280 may be greater than the width of the top surface 280a of the penetrating structure 280. The penetrating structure 280 may vertically overlap with the first key region 40 of the peripheral circuit structure 100.

[0054] The penetrating structure 280 may be spaced apart from the stack 220. For example, the distance W4 from the stack 220 to the penetrating structure 280 may be in the range of approximately 1 μm to 10 mm. The distance W4 may be the shortest distance between the first conductive line 223 and the penetrating structure 280 (i.e., the distance between the penetrating structure 280 and the end of the first conductive line 223 closest to it).

[0055] Reference Figure 3A and Figure 4A through-hole plug 250 can be provided on the top surface 50a of the conductive pad 50. The bottom surface 250b of the through-hole plug 250 can contact the top surface 50a of the conductive pad 50. The through-hole plug 250 can overlap the conductive pad 50 perpendicularly. The width W3 of the bottom surface 250b of the through-hole plug 250 in the first direction D1 can be smaller than the width W2 of the top surface 50a of the conductive pad 50 in the first direction D1. More specifically, the difference between the width W3 of the bottom surface 250b of the through-hole plug 250 in the first direction D1 and the width W2 of the top surface 50a of the conductive pad 50 in the first direction D1 can be in the range of approximately 10 nm to 30 nm. For example, the ratio of the width W3 of the bottom surface 250b of the through-hole plug 250 to the width W2 of the top surface 50a of the conductive pad 50 can be in the range of approximately 0.5 to 0.8.

[0056] Combination Figure 3A Reference Figure 4 The first key region 40 can be provided on the second peripheral insulating layer 23. The side and bottom surfaces of the first key region 40 can be covered by the second peripheral insulating layer 23. The top surface 40a of the first key region 40 may not be covered by the second peripheral insulating layer 23 and may be coplanar with the top surface of the second peripheral insulating layer 23. In one embodiment, a plurality of first key regions 40 may be provided. For example, when viewed in a plan view, each first key region 40 may be rectangular in shape, and some first key regions 40 may be aligned with each other in a first direction D1 or a second direction D2. However, the shape of the first key region 40 is not limited to the rectangular shape shown in the figures, and may be changed in various ways to, for example, polygonal and / or circular shapes, and the arrangement of the first key regions 40 is not limited to... Figure 4 The example shown is valid, and various modifications are possible. The first key region 40 may overlap perpendicularly with the through structure 280. During the formation of the through plug 250, the first key region 40 can be used as a reference point for determining the position of the through plug 250. The function of the first key region 40 will be described in more detail with reference to the manufacturing method described later.

[0057] Refer again Figure 3A Interconnect layer 300 may be provided on stack 220, upper insulating layer 230, molded structure 260, and through structure 280. Interconnect layer 300 may include contact path 325, interconnect structure 360, and first to fifth interconnect insulating layers 311, 313, 315, 317, and 319, respectively. Interconnect structure 360 ​​may include first to third interconnect lines 330, 340, and 350, and first path 335 and second path 345, respectively.

[0058] A first interconnect insulating layer 311 may be provided on the top surface of the upper insulating layer 230 and the molded structure 260. The first interconnect insulating layer 311 may be provided on the first region R1 and the second region R2 of the peripheral circuit structure 100. More specifically, the first interconnect insulating layer 311 may cover the top surface of the upper insulating layer 230, the top surface of the contact 240, the top surface of the separation structure 255, the top surface of the molded structure 260, and the top surface 280a of the penetration structure 280.

[0059] Contact passages 325 may be provided on contact 240 and through-plug 250, respectively. Contact passages 325 may be provided in the first interconnect insulating layer 311 to penetrate the first interconnect insulating layer 311. Contact passages 325 may be connected to contact 240 and through-plug 250, respectively, to connect stack 220 to interconnect layer 300.

[0060] A second interconnect insulating layer 313 may be provided on the first interconnect insulating layer 311. The second interconnect insulating layer 313 may cover the top surface of the first interconnect insulating layer 311. A first interconnect line 330 may be provided in the second interconnect insulating layer 313. The first interconnect line 330 may contact the contact passage 325, so that the interconnect structure 360 ​​may be connected to the contact 240 and the through plug 250.

[0061] A third interconnect insulating layer 315 and a fourth interconnect insulating layer 317 may be provided on the first interconnect insulating layer 311 and the second interconnect insulating layer 313. The third interconnect insulating layer 315 may cover the top surface of the first interconnect 330. A first via 335 may be provided in the third interconnect insulating layer 315. The first via 335 may contact the first interconnect 330. The third interconnect insulating layer 315 may be formed of or comprise a material different from that of the fourth interconnect insulating layer 317, and thus may be used as an etch stop layer during the formation of the interconnect layer 300.

[0062] A fourth interconnect insulating layer 317 may be provided on the third interconnect insulating layer 315. The fourth interconnect insulating layer 317 may cover the top surface of the third interconnect insulating layer 315. A second interconnect line 340 may be provided in the fourth interconnect insulating layer 317. The second interconnect line 340 may contact the first via 335.

[0063] A fifth interconnect insulating layer 319 may be provided on the second interconnect 340 and the fourth interconnect insulating layer 317. A second path 345 and a third interconnect 350 may be provided in the fifth interconnect insulating layer 319. The third interconnect 350 may be connected to the second path 345.

[0064] Contact path 325, first to third interconnects 330, 340, and 350, and first to second paths 335 and 345 may be formed of or comprise at least one of metallic materials (e.g., aluminum, copper, tungsten, and / or cobalt). First to fifth interconnect insulating layers 311, 313, 315, 317, and 319 may be formed of or comprise at least one of insulating materials (e.g., silicon oxide, silicon nitride, and / or silicon nitride). Unlike that shown in the figures, there may be no observable interface between the first to fifth interconnect insulating layers 311, 313, 315, 317, and 319, but one or more embodiments are not limited thereto.

[0065] Figures 6 to 13 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to one embodiment.

[0066] refer to Figure 6 The peripheral circuit structure 100 can be formed. The formation of the peripheral circuit structure 100 may include: preparing a semiconductor substrate 10; forming a peripheral circuit PTR on the semiconductor substrate 10; forming a peripheral path 22 and a peripheral line 24 connected to the peripheral circuit PTR; forming a peripheral insulating layer 20 to surround the peripheral path 22 and the peripheral line 24; and forming a first bond region 40 and a second lower bond region 30 whose top surface is not covered by the peripheral insulating layer 20.

[0067] Here, the semiconductor substrate 10 may be formed of or include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and / or combinations thereof. The semiconductor substrate 10 may include at least one of doped semiconductor materials and / or undoped or intrinsic semiconductor materials, and may have a crystal structure of single crystal, amorphous, or polycrystalline.

[0068] In one embodiment, the peripheral circuit PTR may include a MOS transistor, wherein the semiconductor substrate 10 is used as a channel region. As an example, forming the peripheral circuit PTR may include: forming a device isolation pattern 15 in the semiconductor substrate 10 to define an active region; sequentially forming a peripheral gate insulating layer 27 and a peripheral gate electrode 28 on the semiconductor substrate 10; and performing an impurity implantation process to form source / drain regions 25 in the semiconductor substrate 10 on both sides of the peripheral gate electrode 28. A peripheral gate spacer 26 may be formed on the side surface of the peripheral gate electrode 28. The peripheral circuit PTR may be formed on a first region R1 of the peripheral circuit structure 100.

[0069] The peripheral insulating layer 20 may include a single insulating layer or multiple stacked insulating layers covering the peripheral circuit PTR. The peripheral insulating layer 20 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low-k dielectric layer.

[0070] The first bonding region 40 and the second lower bonding region 30 can be formed on the top surface of the peripheral insulating layer 20. More specifically, the first bonding region 40 and the second lower bonding region 30 can be provided on the second region R2 of the peripheral circuit structure 100. The first bonding region 40 and the second lower bonding region 30 can be formed by forming trenches in the top surface of the peripheral insulating layer 20 and filling the trenches with a conductive material. The first bonding region 40 and the second lower bonding region 30 can be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten and / or cobalt).

[0071] The formation of the peripheral passage 22 and the peripheral line 24 may include: forming a portion of the peripheral passage 22 to penetrate the peripheral insulation layer 20; and forming the peripheral line 24 connected to the peripheral passage 22.

[0072] The first buffer layer 110 may be formed on the peripheral circuit structure 100. The first buffer layer 110 may be formed by depositing an insulating material. The first buffer layer 110 may be formed of or include at least one of silicon nitride, silicon oxide, silicon nitride and / or carbon-containing silicon nitride.

[0073] Reference Figure 7A molded structure 260 in which a first layer 261 and a second layer 263 are alternately stacked can be prepared. The molded structure 260 can be a silicon-containing substrate. More specifically, the first layer 261 of the molded structure 260 can be a silicon layer, and the second layer 263 can be a silicon-germanium layer. The molded structure 260 can have a first surface 260a and a second surface 260b that are opposite to each other. The molded structure 260 can be etched to form a first trench TR1 and a second trench TR2. The first trench TR1 can be formed to be spaced apart from the second trench TR2. The depth of the first trench TR1 can be less than the depth of the second trench TR2. More specifically, the bottom surface TR1b of the first trench TR1 can be closer to the first surface 260a of the molded structure 260 than the bottom surface TR2b of the second trench TR2.

[0074] Reference Figure 8 The second upper bonding region 270 can be formed by filling the first trench TR1 with a conductive material. The second upper bonding region 270 can be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, and / or cobalt). The penetration structure 280 can be formed by filling the second trench TR2 with an insulating material. The insulating material for the penetration structure 280 can include silicon oxide, silicon nitride, and / or silicon nitride. A planarization process can be performed on the first surface 260a of the molded structure 260, resulting in the top surface 260a of the molded structure 260, the top surface of the second upper bonding region 270, and the top surface of the penetration structure 280 being coplanar with each other. Thereafter, a second buffer layer 210 can be formed on the first surface 260a of the molded structure 260. The second buffer layer 210 can be formed using a method substantially the same as that used to form the first buffer layer 110. The second buffer layer 210 may be formed to cover the first surface 260a of the molded structure 260, the top surface of the second upper bond region 270 and the top surface of the penetrating structure 280, and may have the first surface 210a exposed to the outside.

[0075] Reference Figure 9 The molded structure 260 can be fixedly placed on the peripheral circuit structure 100. Placing the molded structure 260 on the peripheral circuit structure 100 may include providing the molded structure 260 on the top surface 110a of the first buffer layer 110 such that the second upper bond region 270 and the second lower bond region 30 overlap vertically, and then performing a heat treatment process to attach the first buffer layer 110 to the second buffer layer 210.

[0076] A molded structure 260, in which a second upper key region 270 and a through structure 280 are formed, can be provided on the peripheral circuit structure 100. Here, the molded structure 260 can be positioned such that the first surface 210a of the second buffer layer 210 faces the peripheral circuit structure 100. More specifically, the positions of the second lower key region 30 and the second upper key region 270 can be checked, and then the molded structure 260 can be positioned such that the second upper key region 270 and the second lower key region 30 overlap perpendicularly. Therefore, the second upper key region 270 and the second lower key region 30 can overlap perpendicularly to each other, and preferably, are aligned with each other in the third direction D3. The first surface 210a of the second buffer layer 210 can contact the top surface 110a of the first buffer layer 110. The second upper key region 270 and the second lower key region 30 can be used as reference points for determining the position of the molded structure 260 provided therein.

[0077] Due to the heat treatment process applied to the first buffer layer 110 and the second buffer layer 210, the first buffer layer 110 and the second buffer layer 210 can be attached to each other. Therefore, the molded structure 260 can be fastened or fixed to the peripheral circuit structure 100. As a result of the heat treatment process, the first buffer layer 110 and the second buffer layer 210 can be chemically or physically bonded to each other at their interface. Unlike what is shown in the figures, the interface between the first buffer layer 110 and the second buffer layer 210 may not be observable.

[0078] Combination Figure 9 Reference Figure 10 The separation structure 255 may be formed in the molding structure 260. Forming the separation structure 255 may include forming a trench to penetrate the molding structure 260, forming an insulating pad 253 to cover the inner surface of the trench, and forming an insulating pattern 251 to fill the remainder of the trench. The insulating pad 253 and the insulating pattern 251 may be formed of or include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride). The separation structure 255 may be formed on the boundary between the first region R1 and the second region R2 of the peripheral circuit structure 100. However, one or more embodiments are not limited thereto, and the formation of the separation structure 255 may be omitted.

[0079] An etching process can be performed on the second surface 260b of the molded structure 260 to remove the upper portion of the molded structure 260 and the upper portion of the separation structure 255. The etching process can be performed until the top surface 280a of the penetrating structure 280 is exposed. Therefore, the second surface 260b of the molded structure 260, the top surface of the separation structure 255, and the top surface of the penetrating structure 280 can be coplanar with each other.

[0080] ReferenceFigure 11 Stack 220 can be formed on the first region R1 of the peripheral circuit structure 100. The formation of stack 220 may include etching a molding structure 260 to form an initial stack, performing a replacement process on the initial stack to form stack 220, and forming an upper insulating layer 230 to cover stack 220.

[0081] The molded structure 260 can be etched to form an initial stack. More specifically, the molded structure 260 provided on a first region R1 of the peripheral circuit structure 100 can be etched to form an initial stack of a stepped structure. The initial stack may include an alternately stacked first layer 261 and a second layer 263. The first layer 261 of the initial stack may be a silicon layer, and the second layer 263 may be a silicon-germanium layer.

[0082] The replacement process may include: removing the first layer 261 of the initial stack to form a first empty region; filling the first empty region with a conductive material to form a first conductive line 223; removing the second layer 263 to form a second empty region; and filling the second empty region with an insulating material to form a first interlayer insulating layer 221. In one embodiment, the conductive material may include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The insulating material may include at least one of silicon oxide, silicon nitride, and / or silicon oxide nitride. As a result, a stack 220 can be formed.

[0083] An upper insulating layer 230 may be formed on a first region R1 of the peripheral circuit structure 100 to cover the stack 220. The upper insulating layer 230 may be formed by depositing an insulating material. The insulating material may include at least one of, for example, silicon oxide, silicon nitride, and / or silicon nitride. The upper insulating layer 230 may be formed to fill the region from which the molded structure 260 has been removed. More specifically, the upper insulating layer 230 may be formed to cover the top and side surfaces of the stack 220 and fill the gap region between the separation structure 255 and the stack 220.

[0084] Reference Figure 12 A contact 240 can be formed on the top surface of the first conductive line 223 of the stack 220. The contact 240 can be formed by forming a through-hole for penetrating the upper insulating layer 230 and filling the through-hole with a conductive material. The through-hole can be formed on the stepped structure of the stack 220 to expose the top surface of the first conductive line 223. The conductive material may include aluminum, copper, tungsten, and / or cobalt.

[0085] Reference Figure 13The penetrating plug 250 can be formed to penetrate the upper insulating layer 230, the second buffer layer 210, and the first buffer layer 110. The formation of the penetrating plug 250 may include irradiating a first light L onto the top surface of the penetrating structure 280 to obtain information about the position of the first key region 40, forming a penetrating hole at the location where the penetrating plug 250 will be formed based on the information about the position of the first key region 40, and filling the penetrating hole with a conductive material to form the penetrating plug 250.

[0086] More specifically, the first light L can be irradiated onto the top surface of the penetrating structure 280. The transmittance of the penetrating structure 280 to the first light L can be higher than that of the molded structure 260 to the first light L. The first light L can be visible light, infrared light, and / or ultraviolet light, but one or more embodiments are not limited to these examples. The position of the first bonding region 40 can be inspected using the first light L. The position of the penetrating plug 250 can be calculated using the position of the first bonding region 40. Thereafter, a through hole for the penetrating plug 250 can be formed at the calculated position. For example, the calculated position can be the location where a conductive pad 50 is formed. The penetrating plug 250 can be formed by filling the through hole with a conductive material. The conductive material can include at least one of aluminum, copper, tungsten, and / or cobalt.

[0087] In the case of manufacturing semiconductor devices by sequentially forming or stacking multiple layers and multiple patterns, it is easier to align the patterns perpendicularly to each other. Conversely, in the case of manufacturing semiconductor devices by attaching separately fabricated upper and lower plates to each other, it may be difficult to accurately align the upper and lower plates. In particular, when the pattern is formed to penetrate the upper and lower plates, it may be difficult to accurately form the pattern through the upper plate on the desired area of ​​the lower plate (e.g., landing pad). To reduce these difficulties or misalignment problems during manufacturing, the landing pads in contact with the penetrating pattern can be formed with an increased width, large enough to prevent contact failure. However, if the width of the landing pad is increased, it is difficult to increase the integration density of the semiconductor device. According to one embodiment, the penetrating structure 280 can be provided to overlap perpendicularly with the first bonding region 40. The peripheral circuit structure 100 and the stack 220 can be attached to each other by utilizing the perpendicular overlap of the second upper bonding region 270 and the second lower bonding region 30, and then the position of the first bonding region 40 can be checked using a first light L passing through the penetrating structure 280. The position of the through-hole plug 250 can be calculated more accurately based on the position of the first key region 40 being inspected. Therefore, the width of the conductive pad 50 in contact with the through-hole plug 250 can be reduced, thereby increasing the integration density of the semiconductor memory device.

[0088] Return to reference Figure 3AInterconnect layer 300 can be formed on upper insulating layer 230, molded structure 260, and through structure 280. The formation of interconnect layer 300 may include forming contact vias 325, interconnect structure 360, and first to fifth interconnect insulating layers 311, 313, 315, 317, and 319. As a result, a semiconductor memory device can be manufactured having… Figure 3A The structure.

[0089] Figure 14 This illustrates the following according to one embodiment: Figure 2 A cross-sectional view of the semiconductor memory device taken by line I-I'. In the following description, previous references... Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5 The described elements may be identified by the same reference numerals without repeating their descriptions.

[0090] Reference Figure 14 A stack 220, a contact 240, an upper insulating layer 230, a separation structure 255, and a molding structure 260 may be provided on the second semiconductor substrate 200. The second semiconductor substrate 200 may substantially be comparable to a reference. Figure 1 , Figure 2 , Figure 3A and Figure 3B The semiconductor substrate 10 described is identical, and the stack 220, contact 240, upper insulating layer 230, separation structure 255, and molding structure 260 can be configured to have the same characteristics as the referenced semiconductor substrate 10. Figure 1 , Figure 2 , Figure 3A and Figure 3B The described features are essentially the same.

[0091] The second semiconductor substrate 200 may have a first region R1 and a second region R2. The first region R1 and the second region R2 of the second semiconductor substrate 200 may be related to a reference. Figure 1 , Figure 2 , Figure 3A and Figure 3B The first region R1 and the second region R2 of the described peripheral circuit structure 100 are basically the same.

[0092] The first buffer layer 110 may cover the top surface of the upper insulating layer 230, the top surface of the separation structure 255, the top surface of the molding structure 260, the top surface of the first bond region 40', and the top surface of the second lower bond region 30'. The first buffer layer 110 may include, with reference to Figure 1 , Figure 2 , Figure 3A and Figure 3BThe first buffer layer 110 is made of the same material as the first buffer layer 110. A second buffer layer 210 may be provided on the top surface of the first buffer layer 110. The second buffer layer 210 may be formed of or comprise the same material as the first buffer layer 110.

[0093] The first bonding region 40' and the second lower bonding region 30' can be provided in the upper portion of the molding structure 260. More specifically, the first bonding region 40' and the second lower bonding region 30' can be provided on the second region R2 of the second semiconductor substrate 200. The molding structure 260 can cover the bottom and side surfaces of the first bonding region 40' and the second lower bonding region 30'. Here, the top surfaces of the first bonding region 40' and the second lower bonding region 30' may not be covered by the molding structure 260 and may be in contact with the first buffer layer 110.

[0094] A first semiconductor substrate 10 may be provided on the top surface of the second buffer layer 210. The first semiconductor substrate 10 may be configured to have a reference surface. Figure 1 , Figure 2 , Figure 3A and Figure 3B The semiconductor substrate 10 described has substantially the same features. Peripheral circuitry PTR, peripheral pathways 22, peripheral lines 24, and a peripheral insulating layer 20 covering the peripheral circuitry PTR can be provided on the first semiconductor substrate 10. The peripheral circuitry PTR, peripheral pathways 22, peripheral lines 24, and peripheral insulating layer 20 can be configured to have the same characteristics as... Figure 1 , Figure 2 , Figure 3A and Figure 3B The features are basically the same.

[0095] The second upper bonding region 270' may be provided in the lower portion of the first semiconductor substrate 10. The top and side surfaces of the second upper bonding region 270' may be covered by the first semiconductor substrate 10. The bottom surface of the second upper bonding region 270' may not be covered by the first semiconductor substrate 10 and may be in contact with the second buffer layer 210. The second upper bonding region 270' may vertically overlap with the second lower bonding region 30'.

[0096] A penetrating structure 280 may be provided on the first semiconductor substrate 10. More specifically, the penetrating structure 280 may be provided to penetrate the first peripheral insulating layer 21. The top surface of the penetrating structure 280 may be coplanar with the top surface of the first peripheral insulating layer 21, and the bottom surface of the penetrating structure 280 may be coplanar with the bottom surface of the first peripheral insulating layer 21. The side surfaces of the penetrating structure 280 may be inclined at an angle relative to the top surface of the first semiconductor substrate 10. As an example, the width of the top surface of the penetrating structure 280 may be smaller than the width of the bottom surface of the penetrating structure 280. The penetrating structure 280 may overlap perpendicularly with the first bonding region 40'.

[0097] A through-hole plug 250 may be provided to penetrate the outer insulating layer 20, the first buffer layer 110, and the second buffer layer 210, and may be connected to the contact 240. More specifically, the through-hole plug 250 may electrically connect the interconnect structure 360 ​​of the interconnect layer 300 to the first conductive line 223 of the stack 220.

[0098] Interconnect layer 300 can be formed on peripheral insulating layer 20 and peripheral lines 24. Interconnect layer 300 can be configured to have... Figure 1 , Figure 2 , Figure 3A and Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 Figure 2 Figure 3A Figure 3B Figure 1 The interconnect layer 300 has essentially the same characteristics. The interconnect structure 360 ​​can be electrically connected to the peripheral line 24.

[0099] According to one embodiment of the present invention, a semiconductor memory device may include a through-hole structure perpendicularly overlapping a first bonding region. The first bonding region can be used as a reference for accurately calculating the location where the through-hole plug will be formed, thus reducing the width of the conductive pads contacting the through-hole plug. Therefore, the integration density of the semiconductor memory device can be increased.

[0100] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0101] This application is based on and claims priority to Korean Patent Application No. 10-2020-0099201, filed with the Korean Intellectual Property Office on August 7, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: The peripheral circuit structure includes peripheral circuitry integrated on a semiconductor substrate in a first region and a first bond region disposed in a second region. A stack is provided on the first region of the peripheral circuit structure, the stack comprising a plurality of first conductive lines extending in a first direction and stacked vertically upward in a third direction perpendicular to the first direction; The upper insulating layer covering the stack; An interconnect layer is provided on the upper insulating layer; A penetrating plug, spaced apart from the stack, and provided to penetrate the upper insulating layer to connect the interconnect layer to the peripheral circuitry of the peripheral circuitry structure; A molded structure is provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; as well as A penetrating structure is provided to penetrate the molded structure and overlap perpendicularly with the first key region.

2. The semiconductor memory device according to claim 1, further comprising: A first buffer layer is provided on the top surface of the peripheral circuit structure; as well as A second buffer layer is provided on the bottom surface of the stack. The first buffer layer and the second buffer layer are in contact with each other.

3. The semiconductor memory device according to claim 2, wherein, The penetrating plug is provided to penetrate the second buffer layer and the first buffer layer.

4. The semiconductor memory device according to claim 1, further comprising: A second buffer layer covers the bottom surface of the stack and the bottom surface of the penetrating structure; as well as A second upper key region is inserted between the second buffer layer and the molded structure. The peripheral circuit structure further includes a second lower key region disposed on the second region of the peripheral circuit structure, and The second upper bond region and the second lower bond region overlap each other perpendicularly.

5. The semiconductor memory device according to claim 1, wherein, The peripheral circuit structure also includes conductive pads that contact the bottom surface of the through plug. The bottom surface of the penetrating plug has a first width. The conductive pad has a second width, and The second width is greater than the first width, and the difference between the first width and the second width is in the range of 10nm to 30nm.

6. The semiconductor memory device of claim 1, further comprising a second buffer layer, the second buffer layer covering the bottom surface of the through-structure. in, The side surface of the penetrating structure is inclined at an angle relative to the top surface of the second buffer layer.

7. The semiconductor memory device according to claim 1, wherein, The penetrating structure includes silicon oxide or silicon nitride.

8. The semiconductor memory device according to claim 1, wherein, The shortest distance from one of the plurality of first conductive lines to the penetrating structure in the first direction is in the range of 1 μm to 10 μm.

9. The semiconductor memory device of claim 1, further comprising a separation structure inserted between the molding structure and the upper insulating layer.

10. The semiconductor memory device according to claim 1, wherein, The peripheral circuit structure further includes: a first peripheral insulating layer surrounding the peripheral circuit and a second peripheral insulating layer provided on the first peripheral insulating layer, and The top surface of the first key region is coplanar with the top surface of the second peripheral insulating layer.

11. A semiconductor memory device, comprising: The peripheral circuit structure includes peripheral circuitry integrated on a semiconductor substrate in a first region and a first bond region disposed in a second region surrounding the first region. A stack is provided on the first region of the peripheral circuit structure, the stack comprising a plurality of first conductive lines extending in a first direction and stacked vertically upward in a third direction perpendicular to the first direction; The upper insulating layer covering the stack; An interconnect layer is provided on the upper insulating layer; A penetrating plug is provided on the first region of the peripheral circuit structure and spaced apart from the stack; A molded structure is provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; as well as A penetrating structure is provided to penetrate the molded structure and overlap perpendicularly with the first key region. The end of the lowest of the plurality of first conductive lines is spaced apart from the penetrating structure and is closer to the penetrating structure than the end of the highest of the plurality of first conductive lines.

12. The semiconductor memory device of claim 11, further comprising a buffer layer covering the bottom surface of the stack and the bottom surface of the upper insulating layer. in, The through-hole plug is provided to penetrate the upper insulating layer and the buffer layer to connect the interconnect layer to the peripheral circuit of the peripheral circuit structure.

13. The semiconductor memory device according to claim 11, wherein, The molded structure comprises alternating stacks of multiple first layers and multiple second layers. The first layer includes silicon, and The second layer comprises silicon germanium.

14. The semiconductor memory device according to claim 11, wherein, The peripheral circuit structure also includes conductive pads that contact the bottom surface of the through plug. The bottom surface of the penetrating plug has a first width. The conductive pad has a second width, and The ratio of the first width to the second width is in the range of 0.5 to 0.

8.

15. The semiconductor memory device of claim 11, further comprising a discrete structure, in, The side surface of the separated structure is in contact with the upper insulating layer; and The other side surface of the separated structure is in contact with the molded structure.

16. The semiconductor memory device of claim 11, further comprising a buffer layer covering the bottom surface of the penetrating structure. in, The width of the penetrating structure in the first direction decreases as the distance from the buffer layer increases in the third direction.

17. The semiconductor memory device of claim 11, further comprising: A buffer layer covers the bottom surface of the stack and the bottom surface of the penetrating structure; as well as A second upper key region is inserted between the buffer layer and the molded structure. The peripheral circuit structure further includes a second lower key region disposed in the second region of the peripheral circuit structure, and The second upper bond region and the second lower bond region overlap each other perpendicularly.

18. The semiconductor memory device according to claim 11, wherein, The top surface of the penetrating structure is coplanar with the top surface of the molded structure.

19. A semiconductor memory device, comprising: The peripheral circuit structure includes peripheral circuitry integrated on a semiconductor substrate in a first region and a first bond region disposed in a second region surrounding the first region. A stack is provided on the first region of the peripheral circuit structure, the stack comprising a plurality of first conductive lines extending in a first direction and stacked vertically upward in a third direction perpendicular to the first direction; The upper insulating layer covering the stack; An interconnect layer is provided on the upper insulating layer, the interconnect layer including a plurality of interconnect insulating layers and a plurality of channels and a plurality of interconnect lines surrounded by the plurality of interconnect insulating layers; A penetrating plug is provided on the first region of the peripheral circuit structure and spaced apart from the stack; Contacts are provided on the stacked plurality of first conductive lines and penetrate the upper insulating layer to connect the plurality of first conductive lines to the plurality of pathways; A molded structure is provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; A separation structure inserted between the molded structure and the upper insulating layer, the separation structure comprising an insulating pattern and an insulating pad surrounding the insulating pattern; as well as A penetrating structure is provided to penetrate the molded structure and overlap perpendicularly with the first key region. The end of the lowest of the plurality of first conductive lines is spaced apart from the penetrating structure in the first direction and is closer to the penetrating structure than the end of the highest of the plurality of first conductive lines.

20. The semiconductor memory device of claim 19, further comprising: The peripheral paths and peripheral lines connected to the peripheral circuit. A second buffer layer covers the bottom surface of the stack and the bottom surface of the penetrating structure; The first buffer layer contacts the second buffer layer and covers the top surface of the peripheral circuit structure; as well as Conductive pads that overlap perpendicularly with the penetrating plug.

Images