A p-gan gate enhanced hent device and a method for manufacturing the same
By first depositing a passivation layer and then performing precise etching in the fabrication of P-GaN gate-enhanced HEMT devices, combined with plasma repair treatment, the problems of incomplete etching and over-etching of the P-GaN layer are solved, thereby improving the reliability of the device and the stability of its on-resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FIRST RARE MATERIALS CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-06-19
AI Technical Summary
In the fabrication process of P-GaN gate enhancement HEMT devices, incomplete etching of the P-GaN layer leads to a decrease in the reliability of the gate switching control of the device. Over-etching of the P-GaN layer results in the etching of the barrier layer, a decrease in the 2DEG concentration, and the diffusion of Mg elements to form defects, which increases the on-resistance.
The process involves first depositing a passivation layer on the barrier layer, then exposing the gate region through wet etching, followed by plasma repair treatment. UID-GaN and P-GaN layers are then epitaxially grown on the surface, and the area outside the gate is etched using dry etching. During the etching process, the passivation layer elements are detected to stop the etching. Finally, the source and drain are formed through wet etching.
This reduces damage to the barrier layer, prevents Mg from diffusing into the barrier layer from the P-GaN layer, lowers the risk of increased on-resistance, and improves the stability of the device's breakdown voltage and threshold voltage.
Smart Images
Figure CN122248749A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, and more specifically, relates to a P-GaN gate enhancement HEMT device and its fabrication method. Background Technology
[0002] P-GaN gate enhancement-mode HEMT devices are among the most studied enhancement-mode HEMT device structures. The core principle of P-GaN gate enhancement-mode HEMT device structure to achieve the power of enhancement-mode HEMT devices is to control the device turn-off by consuming the two-dimensional electron gas (2DEG) between the barrier layer and the channel layer below the gate by the P-GaN layer.
[0003] In fabricating P-GaN gate enhancement-mode HEMT devices, to achieve device turn-off, the P-GaN layer needs to be etched using dry etching, leaving only the P-GaN layer below the gate. However, the following problems exist when etching the P-GaN layer:
[0004] 1. Incomplete etching of the P-GaN layer leads to lower reliability of the device's gate switching control;
[0005] 2. If the P-GaN layer is over-etched, the barrier layer will also be etched, which will lead to a decrease in the 2DEG concentration of the device and an increase in the on-resistance of the device.
[0006] 3. Mg in the P-GaN layer can diffuse into the 2DEG working region, forming defects and increasing the on-resistance of the device. Summary of the Invention
[0007] The main objective of this invention is to provide a P-GaN gate-enhanced HEMT device and its fabrication method, which reduces damage to the barrier layer during etching, blocks the diffusion of Mg elements from the P-GaN layer to the barrier layer, and reduces the risk of increased on-resistance.
[0008] According to a first aspect of the present invention, a method for fabricating a P-GaN gate enhancement-mode HEMT device is provided, comprising the following steps:
[0009] Step 1: Epitaxially grow the core layer, buffer layer, channel layer, insertion layer, barrier layer and passivation layer sequentially on the substrate layer;
[0010] Step 2: Expose the gate region using patterning technology, etch the passivation layer of the gate region to expose the barrier layer;
[0011] Step 3: Perform plasma repair on the surface;
[0012] Step 4: Epitaxially grow a UID-GaN layer and a P-GaN layer sequentially on the surface;
[0013] Step 5: Expose the area outside the gate using patterning technology, and etch the UID-GaN layer and P-GaN layer in the area outside the gate to expose the passivation layer;
[0014] Step 6: Perform plasma repair on the surface;
[0015] Step 7: Expose the gate region using patterning technology, deposit a metal layer on the surface of the gate region, and form the gate on the P-GaN layer;
[0016] Step 8: Expose the source and drain regions using patterning techniques, etch the passivation layers of the source and drain regions to expose the barrier layer, and fabricate the source and drain on the barrier layer.
[0017] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, the substrate is made of one of silicon, sapphire, silicon carbide, gallium nitride, and diamond.
[0018] The nucleation layer is made of AlN superlattice;
[0019] The buffer layer is made of GaN or AlGaN.
[0020] The channel layer is made of GaN or GaAs;
[0021] The material of the insertion layer is AlN;
[0022] The barrier layer is made of one of AlGaN, InAlN, AlN, and InGaN.
[0023] The passivation layer is made of SiN. x SiO x And one of Al2O3;
[0024] The metal layer is made of either Ni / Au or Ni / TiN stack;
[0025] The source and drain are made of either Ti / Al / Ni / Au or Ti / Al / Ni / Au stacked materials.
[0026] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 1, the thickness of the substrate layer is 0.5~2mm;
[0027] The thickness of the nucleation layer is 50~1000 nm;
[0028] The thickness of the buffer layer is 0.5~2.5μm;
[0029] The thickness of the channel layer is 100~1000 nm;
[0030] The thickness of the insertion layer is 0.5~3nm;
[0031] The thickness of the barrier layer is 10~30nm;
[0032] The thickness of the passivation layer is 30~150nm.
[0033] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 4, the thickness of the UID-GaN layer is 1~5 nm;
[0034] The thickness of the P-GaN layer is 30~200nm.
[0035] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 2, the passivation layer of the gate region is etched using a wet etching technique.
[0036] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 5, the UID-GaN layer and the P-GaN layer in the outer region of the gate are etched using dry etching technology.
[0037] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 5, detection is performed during the etching process, and etching is stopped after the elements contained in the passivation layer are detected.
[0038] In the above-described method for fabricating a P-GaN gate-enhanced HEMT device, in step 9, the passivation layers of the source and drain regions are etched using wet etching technology.
[0039] In the above-mentioned method for fabricating P-GaN gate enhancement HEMT devices, in steps 1 and 4, the nucleation layer, buffer layer, channel layer, insertion layer, barrier layer, UID-GaN layer and P-GaN layer are epitaxially grown by MOCVD, and the passivation layer is epitaxially generated by PECVD.
[0040] According to a second aspect of the present invention, a P-GaN gate enhancement HEMT device is provided, the device being fabricated using the fabrication method described in the first aspect;
[0041] The device includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, and a barrier layer arranged sequentially from bottom to top.
[0042] The upper surface of the barrier layer at the middle position is provided with an etched region, and a UID-GaN layer and a P-GaN layer are arranged from bottom to top in the etched region. The upper surface of the P-GaN layer is provided with a gate.
[0043] The barrier layer has a source and a drain on both sides above it, respectively;
[0044] There is a passivation layer between the source electrode and the etched region, and there is a passivation layer between the drain electrode and the etched region.
[0045] One of the above-described technical solutions of the present invention has at least one of the following advantages or beneficial effects:
[0046] In this invention, a passivation layer is first deposited on the barrier layer, and then the passivation layer is etched in the gate region, which can reduce damage to the barrier layer. When etching the area outside the gate, since the passivation layer is located between the barrier layer and the P-GaN layer, the barrier layer can be effectively avoided from being etched while ensuring complete etching of the P-GaN layer and UID-GaN layer in the area outside the gate. In addition, the passivation layer can reduce surface defects of the barrier layer.
[0047] Below the P-GaN layer is a UID-GaN layer, which can block the diffusion of Mg elements from the P-GaN layer to the barrier layer, reducing the risk of increased on-resistance.
[0048] The first plasma repair treatment can passivate the barrier layer damage caused by over-etching in the gate region. The second plasma repair treatment can passivate the passivation layer damage and form a high-resistivity layer in the outer region of the P-GaN layer, thereby increasing the breakdown voltage while suppressing threshold voltage drift. Attached Figure Description
[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments;
[0050] Figure 1 This is a schematic diagram of step 1 of the fabrication method of the P-GaN gate enhancement HEMT device of the present invention;
[0051] Figure 2 This is a schematic diagram of step 2 of the fabrication method of the P-GaN gate enhancement HEMT device of the present invention;
[0052] Figure 3 This is a schematic diagram of step 4 in the fabrication method of the P-GaN gate enhancement HEMT device of the present invention;
[0053] Figure 4 This is a schematic diagram of step 5 in the fabrication method of the P-GaN gate enhancement HEMT device of the present invention;
[0054] Figure 5 This is a schematic diagram of step 7 in the fabrication method of the P-GaN gate enhancement HEMT device of the present invention;
[0055] Figure 6 This is a schematic diagram of step 8 in the fabrication method of the P-GaN gate enhancement HEMT device of the present invention.
[0056] The figure labels for each figure are as follows:
[0057] 1. Substrate layer; 2. Nucleation layer; 3. Buffer layer; 4. Channel layer; 5. Insertion layer; 6. Barrier layer; 7. Passivation layer; 8. UID-GaN layer; 9. P-GaN layer; 10. Gate; 11. Source; 12. Drain. Detailed Implementation
[0058] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0059] The following disclosure provides many different implementations or examples for different ways of implementing the present invention.
[0060] Reference Figures 1 to 6 As shown, a method for fabricating a P-GaN gate enhancement-mode HEMT device includes the following steps:
[0061] Step 1: Using an MOCVD device, epitaxially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, an insertion layer 5, and a barrier layer 6 sequentially on the substrate layer 1. Using a PECVD device, deposit a passivation layer 7 on the barrier layer 6.
[0062] The substrate 1 is made of one of silicon, sapphire, silicon carbide, gallium nitride, and diamond; the thickness of the substrate 1 is 0.5~2mm.
[0063] The nucleation layer 2 is made of AlN superlattice; the thickness of the nucleation layer 2 is 50~1000nm;
[0064] The buffer layer 3 is made of GaN or AlGaN; the thickness of the buffer layer 3 is 0.5~2.5μm;
[0065] The channel layer 4 is made of GaN or GaAs; the thickness of the channel layer 4 is 100~1000nm;
[0066] The material of the insertion layer 5 is AlN; the thickness of the insertion layer 5 is 0.5~3nm;
[0067] The material of barrier layer 6 is one of AlGaN, InAlN, AlN and InGaN; the thickness of barrier layer 6 is 10~30nm;
[0068] The passivation layer 7 is made of SiN. x SiO x It is one of Al2O3; the thickness of passivation layer 7 is 30~150nm.
[0069] Step 2: Expose the gate region on the passivation layer 7 using patterning technology, and etch the passivation layer 7 of the gate region using wet etching technology to expose the barrier layer 6, and then strip the photoresist; since there is a passivation layer 7, etching the passivation layer 7 only in the gate region can reduce the damage to the barrier layer 6.
[0070] Step 3: Using ICP equipment, plasma repair is performed on the surface, which can passivate the damage to the barrier layer 6 caused by over-etching in the gate region.
[0071] Step 4: Using an MOCVD device, a UID-GaN layer 8 and a P-GaN layer 9 are epitaxially grown sequentially on the surface. Therefore, both the passivation layer 7 and the barrier layer 6 have UID-GaN layer 8 and P-GaN layer 9. The UID-GaN layer 8 is located below the P-GaN layer 9, which can prevent the diffusion of Mg elements from the P-GaN layer 9 to the barrier layer 6, reducing the risk of increased on-resistance. The thickness of the UID-GaN layer 8 is 1~5nm; the thickness of the P-GaN layer 9 is 30~200nm.
[0072] Step 5: Expose the area outside the gate using patterning technology. Use dry etching technology to etch the UID-GaN layer 8 and P-GaN layer 9 outside the gate until the elements contained in the passivation layer 7 are detected and then stop etching. Then peel off the photoresist to expose the passivation layer 7.
[0073] Since the passivation layer 7 is located between the barrier layer 6 and the P-GaN layer 9, it can effectively prevent the barrier layer 6 from being etched while ensuring complete etching of the P-GaN layer 9 and the UID-GaN layer 8 outside the gate. In addition, the passivation layer 7 can reduce surface defects of the barrier layer 6.
[0074] Step 6: Use ICP equipment to perform plasma repair on the surface; this can passivate the damage to the passivation layer 7 and form a high-resistivity layer in the outer region of the P-GaN layer 9, thereby increasing the breakdown voltage while suppressing threshold voltage drift.
[0075] Step 7: Expose the gate region using patterning technology, and deposit a metal layer on the surface of the gate region using an E-Beam electron beam evaporation device. The metal layer forms the gate 10 on the P-GaN layer 9. The metal layer is made of either Ni / Au or Ni / TiN stack.
[0076] Step 8: Expose the source and drain regions using patterning technology, and etch the passivation layer 7 of the source and drain regions using wet etching technology to expose the barrier layer 6. Fabricate the source 11 and drain 12 on the barrier layer 6. The source 11 and drain 12 are made of one of Ti / Al / Ni / Au and Ti / Al / Ni / Au stacked materials.
[0077] In this application, only one passivation layer 7 needs to be deposited, making the process simpler; moreover, the passivation layer 7 is removed only in a specific area, reducing damage to the barrier layer 6 and lowering the risk of interface contamination.
[0078] Example 1:
[0079] 1. Select SiC substrate as substrate, use organic cleaning solutions such as acetone and isopropanol to remove organic contaminants, and use inorganic acid mixture to remove inorganic contaminants and the natural oxide layer generated on the wafer surface;
[0080] Using an MOCVD apparatus, a 60 nm thick AlN superlattice nucleation layer 2, a 2 μm Fe-doped GaN buffer layer 3, a 400 nm GaN channel layer 4, a 1 nm AlN layer, and a 21 nm AlGaN barrier layer 6 were epitaxially grown sequentially from bottom to top on a SiC substrate. The Al element composition in the AlGaN barrier layer 6 was 25%. Using a PECVD apparatus, a 100 nm thick SiN layer was deposited on the barrier layer 6. x Passivation layer 7;
[0081] 2. On the SiNx layer, the gate region is exposed using patterning technology, and then the SiN in the gate region is etched using HF solution. x Layer 6 is exposed to reveal barrier layer 6, and then the photoresist is stripped off;
[0082] 3. Use an ICP device to perform plasma treatment on the sample surface for 20 minutes in an N2O atmosphere;
[0083] 4. Using an MOCVD device, a 1.5nm UID-GaN layer 8 and a 100nm P-GaN layer 9 are epitaxially grown sequentially on the barrier layer 6.
[0084] 5. Expose the area outside the gate using patterning technology, and use dry etching to etch the UID-GaN layer 8 and P-GaN layer 9 outside the gate. Stop etching when Ga elements are not detected by EPD, and then peel off the photoresist.
[0085] 6. Use an ICP device to perform plasma treatment on the sample surface for 5 minutes in an NH3 atmosphere;
[0086] 7. The gate region is exposed using patterning technology, and a Ti / Au (20 / 80nm) metal stack is deposited using an E-Beam electron beam evaporation device. The stack is then ultrasonically stripped and cleaned in a developing solution.
[0087] 8. Expose the source and drain regions using patterning techniques, and etch the SiN in the source and drain regions using HF solution. xThe barrier layer 6 is exposed, and then a Ti / Al / Ni / Au (30 / 200 / 50 / 150nm) metal stack is deposited using an E-Beam electron beam evaporation device. After stripping and cleaning, the sample is placed in a fast annealing furnace and fast annealed at 840℃ for 45s in a N2 atmosphere to form ohmic contacts for the gate region, source 11, and drain 12.
[0088] The present invention also provides a P-GaN gate enhancement HEMT device, which is fabricated using the above-described method for fabricating a P-GaN gate enhancement HEMT device;
[0089] The device includes a nucleation layer 2, a buffer layer 3, a channel layer 4, an insertion layer 5, and a barrier layer 6 arranged sequentially from bottom to top;
[0090] An etched region is provided on the upper surface of the middle position of the barrier layer 6. A UID-GaN layer 8 and a P-GaN layer 9 are arranged from bottom to top in the etched region. A gate 10 is provided on the upper surface of the P-GaN layer 9.
[0091] Source 11 and drain 12 are respectively provided on both sides above the barrier layer 6;
[0092] There is a passivation layer 7 between the source electrode 11 and the etched area, and there is a passivation layer 7 between the drain electrode 12 and the etched area.
[0093] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A method for fabricating a P-GaN gate enhancement-mode HEMT device, characterized in that, Includes the following steps: Step 1: Epitaxially grow the core layer, buffer layer, channel layer, insertion layer, barrier layer and passivation layer sequentially on the substrate layer; Step 2: Expose the gate region using patterning technology, etch the passivation layer of the gate region to expose the barrier layer; Step 3: Perform plasma repair on the surface; Step 4: Epitaxially grow a UID-GaN layer and a P-GaN layer sequentially on the surface; Step 5: Expose the area outside the gate using patterning technology, and etch the UID-GaN layer and P-GaN layer in the area outside the gate to expose the passivation layer; Step 6: Perform plasma repair on the surface; Step 7: Expose the gate region using patterning technology, deposit a metal layer on the surface of the gate region, and form the gate on the P-GaN layer; Step 8: Expose the source and drain regions using patterning techniques, etch the passivation layers of the source and drain regions to expose the barrier layer, and fabricate the source and drain on the barrier layer.
2. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, The substrate is made of one of the following materials: silicon, sapphire, silicon carbide, gallium nitride, and diamond. The nucleation layer is made of AlN superlattice; The buffer layer is made of GaN or AlGaN. The channel layer is made of GaN or GaAs; The material of the insertion layer is AlN; The barrier layer is made of one of AlGaN, InAlN, AlN, and InGaN. The passivation layer is made of SiN. x SiO x And one of Al2O3; The metal layer is made of either Ni / Au or Ni / TiN stack; The source and drain are made of either Ti / Al / Ni / Au or Ti / Al / Ni / Au stacked materials.
3. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In step 1, the thickness of the substrate layer is 0.5~2mm; The thickness of the nucleation layer is 50~1000 nm; The thickness of the buffer layer is 0.5~2.5μm; The thickness of the channel layer is 100~1000 nm; The thickness of the insertion layer is 0.5~3nm; The thickness of the barrier layer is 10~30nm; The thickness of the passivation layer is 30~150nm.
4. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In step 4, the thickness of the UID-GaN layer is 1~5nm; The thickness of the P-GaN layer is 30~200nm.
5. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In step 2, the passivation layer of the gate region is etched using wet etching technology.
6. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In step 5, the UID-GaN layer and P-GaN layer in the gate region are etched using dry etching technology.
7. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 6, characterized in that, In step 5, detection is performed during the etching process, and etching is stopped after the elements contained in the passivation layer are detected.
8. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In step 9, the passivation layers of the source and drain regions are etched using wet etching technology.
9. The method for fabricating a P-GaN gate enhancement-mode HEMT device according to claim 1, characterized in that, In steps 1 and 4, the nucleation layer, buffer layer, channel layer, insertion layer, barrier layer, UID-GaN layer, and P-GaN layer are epitaxially grown by MOCVD, and the passivation layer is epitaxially generated by PECVD.
10. A P-GaN gate enhancement-mode HEMT device, characterized in that, The device is prepared by any one of the preparation methods described in claims 1-9; The device includes a nucleation layer, a buffer layer, a channel layer, an insertion layer, and a barrier layer arranged sequentially from bottom to top. The upper surface of the barrier layer at the middle position is provided with an etched region, and a UID-GaN layer and a P-GaN layer are arranged from bottom to top in the etched region. The upper surface of the P-GaN layer is provided with a gate. The barrier layer has a source and a drain on both sides above it, respectively; There is a passivation layer between the source electrode and the etched region, and there is a passivation layer between the drain electrode and the etched region.