A GaN-based enhancement-mode HEMT device structure and a manufacturing method thereof

Abstract

The application provides a GaN-based enhancement-mode HEMT device structure and a manufacturing method thereof, wherein the barrier stack comprises a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer and a third barrier layer which are sequentially stacked from bottom to top, the second insertion layer serves as an etching stop layer during trench etching, the barrier layer thickness of the trench area is smaller, the 2DEG concentration under the P-type GaN part is reduced, the threshold voltage of the device is improved, the third insertion layer serves as an etching stop layer during patterning of the P-type GaN layer, the over-etching depth of the barrier layer is reduced, the remaining thickness of the barrier layer is improved, and the probability of electron tunneling to the surface of the barrier layer is reduced, the third barrier layer can effectively prevent the third insertion layer from being etched through, avoid the direct contact between the passivation layer and the second barrier layer, and further reduce the interface traps, and the application realizes the optimization of the thick barrier layer and the surface defects of the barrier layer, and is helpful to improve the performance and reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a GaN-based enhancement-mode HEMT device structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) are advanced power semiconductor devices based on gallium nitride materials, characterized by high electron mobility, high power density, small size, and high integration. GaN HEMTs utilize an AlGaN / GaN heterostructure. Through the piezoelectric effect generated during the growth of an AlGaN thin film on GaN, a large number of electrons accumulate at the interface, forming a highly mobile two-dimensional electron gas (2DEG) layer, which serves as the current path. Due to the high mobility of the 2DEG, GaN HEMTs have lower on-resistance, output capacitance, and gate capacitance, resulting in higher switching speeds and lower switching losses in high-frequency applications.

[0003] GaN-based HEMT devices are divided into standard and enhancement-mode types. Standard GaN-based HEMT devices are typically depletion-mode (D-mode), meaning the device is already in the conducting state when no voltage is applied to the gate because the 2DEG generated at the AlGaN / GaN interface allows the device to conduct even with zero gate bias. Enhancement-mode GaN-based HEMT devices, on the other hand, are normally-off (E-mode), meaning the device is off with zero gate bias and requires a positive gate voltage to turn on. The structural feature of enhancement-mode GaN HEMT devices is the growth of a P-type GaN layer on top of the AlGaN barrier layer. The positive charges in this P-GaN layer have an internal voltage greater than the voltage generated by the piezoelectric effect, thus depleting the electrons in the 2DEG and forming an enhancement-mode structure. This structure has the advantage of lower internal parasitic parameters and superior switching performance. Because enhancement-mode GaN HEMTs can deplete the 2DEG in the under-gate channel with zero gate bias, putting the device in the off state, they offer advantages in safety, energy saving, and simplified circuit design, making them an important development direction for future power devices.

[0004] Current collapse is a serious problem affecting the reliability of GaN HEMTs, leading to a decrease in device saturation current and maximum transconductance, and an increase in on-resistance. Extensive experimental analysis has revealed that the thickness of the gallium nitride barrier layer and surface defects have a significant impact on current collapse. Increasing the barrier layer thickness can reduce electron tunneling to the surface, reducing surface traps and lowering the probability of electron capture. However, increasing the barrier layer thickness leads to a decrease in the threshold voltage, potentially causing false turn-on in applications. Furthermore, simply reducing surface traps through fabrication is extremely difficult.

[0005] Therefore, how to provide a GaN-based enhanced HEMT device structure and its fabrication method to optimize the thick barrier layer and surface defects of the barrier layer has become an important technical problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a GaN-based enhancement-mode HEMT device structure and its fabrication method, so as to solve the problems of unstable threshold voltage and numerous surface defects in existing GaN-based enhancement-mode HEMT device structures.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a GaN-based enhancement-mode HEMT device structure, comprising the following steps:

[0009] A substrate is provided, one side of which has a channel layer, the channel layer comprising an undoped GaN layer;

[0010] A barrier stack is formed on the channel layer, the barrier stack comprising a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer, and a third barrier layer stacked sequentially from bottom to top;

[0011] Etching is performed to form trenches in the barrier stack, the bottom of which stops at the second insertion layer;

[0012] A P-type GaN layer is formed, which covers the top surface of the barrier stack and the inner wall of the trench;

[0013] Etching is performed to pattern the P-type GaN layer to obtain a P-type GaN portion, the P-type GaN portion at least covering the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer;

[0014] A passivation layer is formed, which covers the P-type GaN portion and the exposed surface of the third insertion layer;

[0015] A gate electrode and source and drain electrodes are formed on both sides of the gate electrode. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source and drain electrodes penetrate the passivation layer and contact the third insertion layer.

[0016] Optionally, the first insertion layer, the second insertion layer, and the third insertion layer all include an AlN layer, and the first barrier layer, the second barrier layer, and the third barrier layer all include an AlGaN layer.

[0017] Optionally, the thickness of the barrier stack ranges from 12 to 20 nm.

[0018] Optionally, the thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

[0019] Optionally, the passivation layer includes an AlN layer.

[0020] Optionally, the method for forming the barrier stack includes MOCVD.

[0021] Optionally, the P-type GaN portion includes a P-type GaN main body portion located on the inner wall of the trench and P-type GaN side wings extending horizontally from the top of the P-type GaN main body portion to both sides, and the P-type GaN side wings portion and the third insertion layer have a support portion formed by a part of the third barrier layer.

[0022] Optionally, the substrate includes a substrate layer, a nucleation layer, a buffer layer, and a C-doped GaN layer arranged sequentially from bottom to top.

[0023] Optionally, the substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

[0024] The present invention also provides a GaN-based enhancement-mode HEMT device structure, comprising:

[0025] A substrate having a channel layer on one side, the channel layer comprising an undoped GaN layer;

[0026] A barrier stack, located on the channel layer, and comprising at least a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, and a third insertion layer stacked sequentially from bottom to top;

[0027] The trench opens from the top surface of the barrier stack and extends downward to the second insertion layer;

[0028] The P-type GaN portion at least covers the bottom wall of the trench, and the top layer of the barrier stack surrounding the P-type GaN portion is the third insertion layer;

[0029] A passivation layer covers the P-type GaN portion and the third insertion layer surrounding the P-type GaN portion;

[0030] The gate electrode and the source electrode and drain electrode are respectively located on both sides of the gate electrode. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

[0031] Optionally, the first insertion layer, the second insertion layer, and the third insertion layer all include an AlN layer, and the first barrier layer and the second barrier layer both include an AlGaN layer.

[0032] Optionally, the thickness of the barrier stack ranges from 12 to 20 nm.

[0033] Optionally, the thickness of the first insertion layer is in the range of 0.1 to 1 nm, the thickness of the second insertion layer is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer is in the range of 0.3 to 1.5 nm.

[0034] Optionally, the passivation layer includes an AlN layer.

[0035] Optionally, the P-type GaN portion includes a P-type GaN main body portion located on the inner wall of the trench and P-type GaN side wings extending horizontally from the top of the P-type GaN main body portion to both sides. The barrier stack also includes a third barrier layer located on the third insertion layer. A support portion formed by the third barrier layer is provided between the P-type GaN side wings and the third insertion layer.

[0036] Optionally, the substrate includes a substrate layer, a nucleation layer, a buffer layer, and a C-doped GaN layer arranged sequentially from bottom to top.

[0037] Optionally, the substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

[0038] As described above, in the GaN-based enhancement-mode HEMT device structure and fabrication method of the present invention, the barrier stack includes a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer, and a third barrier layer stacked sequentially from bottom to top. The second insertion layer serves as an etch stop layer during trench etching, reducing the barrier layer thickness in the trench region and lowering the 2DEG concentration under the P-type GaN layer, thereby increasing the device's threshold voltage. The third insertion layer serves as an etch stop layer during patterning of the P-type GaN layer, reducing the over-etch depth of the barrier layer, increasing the remaining thickness of the barrier layer, and decreasing the probability of electrons tunneling to the barrier layer surface, thus reducing surface traps and the likelihood of electron capture. The presence of the third barrier layer effectively prevents the third insertion layer from being etched through, avoids direct contact between the passivation layer and the second barrier layer, and further reduces interface traps. In summary, the present invention optimizes the thick barrier layer and surface defects of the barrier layer, contributing to improved device performance and reliability. Attached Figure Description

[0039] Figure 1 The diagram shown is a schematic of a GaN HEMT structure.

[0040] Figure 2 This is shown as a process in which an electron tunnels from a two-dimensional electron gas into a surface trap.

[0041] Figure 3 The diagram shows a process flow chart illustrating the fabrication method of the GaN-based enhancement-mode HEMT device structure according to the present invention.

[0042] Figure 4 The diagram shows a schematic of the substrate provided by the method for fabricating a GaN-based enhancement-mode HEMT device structure according to the present invention.

[0043] Figure 5 The diagram shows a schematic of the structure obtained after forming a barrier stack on the channel layer, which is a method for fabricating the GaN-based enhancement-mode HEMT device structure of the present invention.

[0044] Figure 6 The diagram shows a schematic of the structure obtained after forming trenches in a barrier stack, which is a method for fabricating a GaN-based enhancement-mode HEMT device structure according to the present invention.

[0045] Figure 7 The diagram shown is a schematic of the structure obtained after forming a P-type GaN layer, which is a method for fabricating a GaN-based enhancement-mode HEMT device structure according to the present invention.

[0046] Figure 8 The diagram shown illustrates the structure obtained after graphically layering a P-type GaN layer, which is a method for fabricating a GaN-based enhancement-mode HEMT device structure according to the present invention.

[0047] Figure 9The diagram shown is a schematic of the structure obtained after forming the passivation layer in the fabrication method of the GaN-based enhancement-mode HEMT device structure of the present invention.

[0048] Figure 10 The diagram shows a schematic of the structure obtained after forming the gate electrode, source electrode, and drain electrode according to the fabrication method of the GaN-based enhancement-mode HEMT device structure of the present invention.

[0049] Explanation of reference numerals in the attached figures

[0050] 101 Si substrate

[0051] 102 nucleation layer

[0052] 103 Stress Relief Layer

[0053] 104C-doped GaN layer

[0054] 105 Undoped GaN layer

[0055] 106 AlGaN barrier layer

[0056] 107 P-type GaN layer

[0057] 108 passivation layer

[0058] 109 gate electrode

[0059] 110 Source Electrode

[0060] 111 Drain electrode

[0061] 112 Two-dimensional electron gas

[0062] 113, 114, 115 Charge carriers

[0063] 116 Surface Traps

[0064] Steps S1 to S7

[0065] 201 Substrate

[0066] 202 nucleation layer

[0067] 203 Buffer Layer

[0068] 204C-doped GaN layer

[0069] 205 Channel Layer

[0070] 206 Barrier Stack

[0071] 2061 First Insertion Layer

[0072] 2062 First Barrier Layer

[0073] 2063 Second Insertion Layer

[0074] 2064 Second Barrier Layer

[0075] 2065 Third Insertion Layer

[0076] 2066 Third Barrier Layer

[0077] 207 Trench

[0078] 208 P-type GaN layer

[0079] 208a P-type GaN

[0080] 2081 P-type GaN main body

[0081] 2082 P-type GaN flank

[0082] 209 Passivation layer

[0083] 210 gate electrode

[0084] 211 Source Electrode

[0085] 212 Drain electrode Detailed Implementation

[0086] Please see Figure 1 The diagram shows a schematic of a GaN HEMT structure, including a Si substrate layer 101, a nucleation layer 102, a stress relief layer 103 (also called a buffer layer), a C-doped GaN layer 104, an undoped GaN layer 105, an AlGaN barrier layer 106, a P-type GaN layer 107, a passivation layer 108, a gate electrode 109, a source electrode 110, and a drain electrode 111. The undoped GaN layer 105 serves as a channel layer, and the AlGaN barrier layer 106 and the undoped GaN layer 105 form a heterostructure. A two-dimensional electron gas 112 with high electron mobility can be generated at the interface between the two.

[0087] Figure 1 The diagram further illustrates the source contact resistance R. C,S Source connection resistor R AC,S Channel resistance R CH Drain connection resistor R AC,D Contact resistance R with drain C,D .exist Figure 1 In the structure shown, the dynamic on-resistance (Dynamic R) is affected. on There are three main factors:

[0088] (1) Buffer trapping: In the buffer layer, charge carriers may be trapped, affecting device performance. Figure 1 The diagram illustrates the charge carriers 113 trapped on the surface of the stress relief layer 103;

[0089] (2) Gate instability: Gate instability may be related to fluctuations in the gate voltage, leading to an increase in the threshold voltage (V). TH The change in ΔV TH ,in, Figure 1 The diagram illustrates the charge carriers 114 at the interface between the AlGaN barrier layer 106 and the P-type GaN layer 107.

[0090] (3) Surface trapping: On the device surface, charge carriers may be trapped by surface states, affecting the device's conduction performance. Figure 1 The diagram illustrates the charge carriers 115 at the interface between the AlGaN barrier layer 106 and the passivation layer 108. For further details, please refer to [link to relevant documentation]. Figure 2 This is illustrated by the process of an electron (e-) tunneling from a two-dimensional electron gas (2DEG) to a surface trap 116. This is because defects may exist on the surface of the AlGaN / GaN heterostructure, which can act as surface traps 116 to capture or release electrons. When an electron (e-) is captured by the surface trap 116, the electron concentration in the 2DEG decreases, leading to an increase in the device's on-resistance. Additionally, spontaneous radiative recombination (SRL) occurs when electrons and holes recombine.

[0091] Through extensive analysis and research, the inventors of this application have optimized factors that may lead to an increase in dynamic on-resistance when designing and manufacturing GaN-based enhancement-mode HEMT device structures, which helps to improve the performance and reliability of the devices.

[0092] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0093] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0094] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0095] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0096] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0097] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0098] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0099] This invention provides a method for fabricating a GaN-based enhancement-mode HEMT device structure. Please refer to [link to relevant documentation]. Figure 3 The diagram shows the process flow of this method, which includes the following steps:

[0100] S1: A substrate is provided, one side of which has a channel layer, the channel layer comprising an undoped GaN layer;

[0101] S2: A barrier stack is formed on the channel layer, the barrier stack comprising a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer, and a third barrier layer stacked sequentially from bottom to top;

[0102] S3: Etch to form trenches in the barrier stack, the bottom of the trenches stopping at the second insertion layer;

[0103] S4: Form a P-type GaN layer, which covers the top surface of the barrier stack and the inner wall of the trench;

[0104] S5: Etch to pattern the P-type GaN layer to obtain a P-type GaN portion, the P-type GaN portion at least covering the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer;

[0105] S6: Form a passivation layer that covers the P-type GaN portion and the exposed surface of the third insertion layer;

[0106] S7: Form a gate electrode and source and drain electrodes located on both sides of the gate electrode respectively. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source and drain electrodes penetrate the passivation layer and contact the third insertion layer.

[0107] The following section will detail each of the above steps in conjunction with the structural diagram.

[0108] Please refer to the following first. Figure 4 Perform step S1: Provide a substrate, one side of which has a channel layer 205, the channel layer 205 including an undoped GaN layer.

[0109] Specifically, the use of an undoped GaN layer in the channel layer 205 can reduce impurity scattering, thereby improving electron mobility and helping to reduce leakage current in the device, thus improving the device's turn-off characteristics.

[0110] As an example, the substrate includes a substrate layer 201, a nucleation layer 202, a buffer layer 203 and a C-doped GaN layer 204 arranged sequentially from bottom to top, wherein the channel layer 205 is located on the surface of the C-doped GaN layer 204.

[0111] Specifically, the nucleation layer 202 is used to promote crystal growth, the buffer layer 203 is used to reduce stress caused by lattice mismatch, and the C-doped GaN layer 204 serves as a high-resistivity layer to reduce device leakage.

[0112] In some embodiments, the substrate layer 201 includes a Si layer, the nucleation layer 202 includes an AlN layer, and the buffer layer 203 includes an AlGaN-AlN superlattice layer (SL).

[0113] Specifically, the AlGaN-AlN superlattice layer is composed of alternating stacks of AlGaN and AlN layers. This structure helps to suppress the accumulation of internal strain, create a high-insulation buffer layer with good crystal quality, and reduce defects in the buffer layer. This helps to reduce the dynamic on-resistance of the device and enable the device to have low parasitic leakage current under high voltage bias.

[0114] Specifically, the thickness of each layer in the substrate can be set according to actual needs, and the scope of protection of the present invention should not be excessively limited. In one embodiment of the present invention, the thickness of the substrate layer 201 is about 1 mm, the thickness of the nucleation layer 202 is about 200 nm, the thickness of the buffer layer 203 is about 4 μm, and the average thickness of the C-doped GaN layer 204 is about 1 μm.

[0115] Please see again Figure 5 Step S2 is performed: a barrier stack 206 is formed on the channel layer 205. The barrier stack includes a first insertion layer 2061, a first barrier layer 2062, a second insertion layer 2063, a second barrier layer 2064, a third insertion layer 2065, and a third barrier layer 2066 stacked sequentially from bottom to top.

[0116] Specifically, the first insertion layer 2061 is located between the channel layer 205 and the first barrier layer 2062, which helps to improve the mobility of the two-dimensional electron gas (2DEG).

[0117] As an example, the first insertion layer 2061, the second insertion layer 2063 and the third insertion layer 2065 all include an AlN layer, and the first barrier layer 2062, the second barrier layer 2064 and the third barrier layer 2066 all include an AlGaN layer.

[0118] As an example, the thickness of the barrier stack 206 is in the range of 12 to 20 nm, that is, the total thickness of the first insertion layer 2061, the first barrier layer 2062, the second insertion layer 2063, the second barrier layer 2064, the third insertion layer 2065 and the third barrier layer 2066 is in the range of 12 to 20 nm.

[0119] As an example, the thickness of the first insertion layer 2061 is in the range of 0.1 to 1 nm, the thickness of the second insertion layer 2063 is in the range of 0.3 to 1.5 nm, and the thickness of the third insertion layer 2065 is in the range of 0.3 to 1.5 nm.

[0120] In one embodiment of the present invention, the total thickness of the barrier stack 206 is approximately 16 nm, wherein the thickness of the first insertion layer 2061 is approximately 0.3 nm, the thickness of the second insertion layer 2063 is approximately 0.5 nm, and the thickness of the third insertion layer 2065 is approximately 0.5 nm.

[0121] As an example, the method for forming the barrier stack includes metal-organic chemical vapor deposition (MOCVD), an epitaxial technique for growing semiconductor materials, particularly suitable for growing III-V compound semiconductor materials. It can provide high-precision, high-purity, high-uniformity and high-repeatability thin film growth, with fewer thermal defects and intrinsic impurities in the resulting thin film, and the film thickness can be controlled with atomic precision.

[0122] Please see again Figure 6 Step S3 is performed: etching is performed to form a trench 207 in the barrier stack 206, the bottom of the trench 207 stopping at the second insertion layer 2063.

[0123] As an example, the trench 207 is formed in the barrier stack 206 by semiconductor processes such as photolithography and etching. During the trench etching process, the second insertion layer 2063 serves as an etching stop layer.

[0124] Specifically, the trench 207 can reduce the barrier layer thickness of the gate region, thereby helping to reduce the 2DEG concentration under the P-type GaN portion and thus increase the threshold voltage of the device. The area around the trench 207 still has a relatively thick barrier layer, resulting in a higher 2DEG concentration. Furthermore, because the barrier layer around the trench 207 is relatively thick, it can reduce electron tunneling to the surface, reduce surface traps in the barrier layer, and lower the probability of electrons being trapped.

[0125] Please see again Figure 7 Step S4 is performed: a P-type GaN layer 208 is formed by epitaxial growth, the P-type GaN layer 208 covering the top surface of the barrier stack 206 and the inner wall of the trench 207.

[0126] Specifically, the inner wall of the groove 207 mentioned in this invention includes the bottom wall and the side wall of the groove 207.

[0127] As an example, the growth thickness of the P-type GaN layer 208 ranges from 0.5 to 1.5 micrometers, for example, it can be 0.8 micrometers.

[0128] Please see again Figure 8Step S5 is performed: etching is performed to pattern the P-type GaN layer 208 to obtain a P-type GaN portion 208a, the P-type GaN portion 208a at least covers the bottom wall of the trench 207, and the etched area around the P-type GaN portion 208a stops at the third insertion layer 2065.

[0129] As an example, the P-type GaN layer 208 is patterned using semiconductor processes such as photolithography and etching. During the etching of the P-type GaN layer 208, the third insertion layer 2065 serves as an etching stop layer, which can reduce the over-etching depth of the barrier layer, increase the retention thickness of the barrier layer, and reduce the probability of electrons tunneling to the surface of the barrier layer, thereby reducing surface traps in the barrier layer and lowering the chance of electrons being trapped.

[0130] It should be noted that although the third insertion layer 2065 serves as an etch stop layer during the patterning process of the P-type GaN layer 208, it has been found to be easily etched through during actual production. Therefore, this invention adds a third barrier layer 2066 to the third insertion layer 2065. During the etching process of the P-type GaN layer 208, the presence of the third barrier layer 2066 on the third insertion layer 2065 effectively prevents the third insertion layer 2065 from being etched through, thereby avoiding direct contact between the subsequently formed passivation layer and the second barrier layer 2064. This further reduces interface traps and improves device performance.

[0131] In some embodiments, the P-type GaN portion 208a is located only in the trench 207. In other embodiments, by controlling the photolithography pattern, the P-type GaN portion 208a obtained after etching includes not only the P-type GaN main body portion 2081 located on the inner wall of the trench 207, but also P-type GaN side wings 2082 extending horizontally from the top of the P-type GaN main body portion 2081 to both sides. In this case, the P-type GaN side wings 2082 and the third insertion layer 2065 have a support portion formed by a part of the third barrier layer 2066, which helps to improve the stability of the gate pattern and make the threshold voltage of the device more stable.

[0132] Please see again Figure 9 Step S6 is performed: a passivation layer 209 is formed, which covers the P-type GaN portion 208a and the exposed surface of the third insertion layer 2065.

[0133] Specifically, the passivation layer 209 is used to protect the device surface and reduce the influence of surface states.

[0134] In some embodiments, the passivation layer 209 includes an AlN layer, and the method for forming the passivation layer 209 includes MOCVD. Since both the passivation layer 209 and the third insertion layer 2065 are made of AlN, i.e., the same material is used, the passivation layer 209 is in direct contact with the third insertion layer 2065 rather than with the second barrier layer 2064, which helps to improve interface traps.

[0135] Please see again Figure 10 Step S7 is performed: a gate electrode 210 and a source electrode 211 and a drain electrode 212 located on both sides of the gate electrode 210 are formed. The gate electrode 210 penetrates the passivation layer 209 and contacts the P-type GaN portion 208a. The source electrode 211 and the drain electrode 213 penetrate the passivation layer 209 and contact the third insertion layer 2065.

[0136] As an example, contact holes are first formed at corresponding positions on the passivation layer 209 using semiconductor processes such as photolithography and etching. Then, a metal layer is deposited and patterned to obtain the gate electrode 210, the source electrode 211, and the drain electrode 213. The spacing between the gate electrode 210 and the source electrode 211, and the spacing between the gate electrode 210 and the drain electrode 213, can be set according to the performance parameter requirements of the actual device. No specific limitations are imposed in this invention.

[0137] Thus, a GaN-based enhancement-mode HEMT device structure has been fabricated. The fabrication method of the GaN-based enhancement-mode HEMT device structure of the present invention utilizes multiple insertion layers combined with epitaxial regeneration to optimize the thick barrier layer and surface defects of the barrier layer. The thick barrier layer reduces the probability of electron tunneling to the surface of the barrier layer, and the contact between the passivation layer and the third insertion layer greatly reduces surface traps.

[0138] The present invention also provides a GaN-based enhancement-mode HEMT device structure, which can be prepared by the above method.

[0139] For details, please refer to Figure 10The GaN-based enhancement-mode HEMT device structure includes a substrate, a barrier stack 206, a trench 207, a p-type GaN layer 208a, a passivation layer 209, a gate electrode 210, and source electrodes 211 and drain electrodes 212 located on both sides of the gate electrode 210, respectively. One side of the substrate has a channel layer 205, which includes an undoped GaN layer. The barrier stack 206 is located on the channel layer 205 and includes at least a first insertion layer 2061, a first barrier layer 2062, a second insertion layer 2063, a second barrier layer 2064, and a third insertion layer 2065 stacked sequentially from bottom to top. The trench 207 extends from the gate electrode 208a. The top surface of the stacked layer 206 is open and extends downward to the second insertion layer 2063. The P-type GaN portion 208a at least covers the bottom wall of the trench 207. The top layer of the barrier stacked layer 206 surrounding the P-type GaN portion 208a is the third insertion layer 2065. The passivation layer covers the P-type GaN portion 208a and the third insertion layer 2065 surrounding the P-type GaN portion 208a. The gate electrode 210 penetrates the passivation layer 209 and contacts the P-type GaN portion 208a. The source electrode 211 and the drain electrode 212 penetrate the passivation layer 209 and contact the third insertion layer 2065.

[0140] In some embodiments, the P-type GaN portion 208a is located only in the trench 207. In other embodiments, the P-type GaN portion 208a includes not only the P-type GaN body portion 2081 located on the inner wall of the trench 207, but also P-type GaN side wing portions 2082 extending horizontally from the top of the P-type GaN body portion 2081 to both sides. The barrier stack 206 also includes a third barrier layer 2066 located on the third insertion layer 2065. In this case, there is a support portion formed by the third barrier layer 2066 between the P-type GaN side wing portion 2082 and the third insertion layer 2065, which helps to improve the stability of the gate pattern and make the threshold voltage of the device more stable.

[0141] In summary, the GaN-based enhancement-mode HEMT device structure and its fabrication method of the present invention include a barrier stack comprising, from bottom to top, a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer, and a third barrier layer. The second insertion layer serves as an etch stop layer during trench etching, reducing the barrier layer thickness in the trench region and lowering the 2DEG concentration under the P-type GaN layer, thereby increasing the device's threshold voltage. The third insertion layer serves as an etch stop layer during patterning of the P-type GaN layer, reducing the over-etch depth of the barrier layer, increasing the remaining thickness of the barrier layer, and decreasing the probability of electrons tunneling to the barrier layer surface, thus reducing surface traps and the likelihood of electron capture. The presence of the third barrier layer effectively prevents the third insertion layer from being etched through, avoiding direct contact between the passivation layer and the second barrier layer, further reducing interface traps. In conclusion, the present invention optimizes the thick barrier layer and surface defects of the barrier layer, contributing to improved device performance and reliability. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0142] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a GaN-based enhancement-mode HEMT device structure, characterized in that, Includes the following steps: A substrate is provided, one side of which has a channel layer, the channel layer comprising an undoped GaN layer; A barrier stack is formed on the channel layer, the barrier stack comprising a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, a third insertion layer, and a third barrier layer stacked sequentially from bottom to top; Etching is performed to form trenches in the barrier stack, the bottom of which stops at the second insertion layer; A P-type GaN layer is formed, which covers the top surface of the barrier stack and the inner wall of the trench; Etching is performed to pattern the P-type GaN layer to obtain a P-type GaN portion, the P-type GaN portion at least covering the bottom wall of the trench, and the etched area around the P-type GaN portion stops at the third insertion layer; A passivation layer is formed, which covers the P-type GaN portion and the exposed surface of the third insertion layer; A gate electrode and source and drain electrodes are formed on both sides of the gate electrode. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source and drain electrodes penetrate the passivation layer and contact the third insertion layer.

2. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to claim 1, characterized in that: The first insertion layer, the second insertion layer, and the third insertion layer all include an AlN layer, and the first barrier layer, the second barrier layer, and the third barrier layer all include an AlGaN layer.

3. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to claim 1, characterized in that: The thickness of the barrier stack ranges from 12 to 20 nm.

4. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The thickness of the first insertion layer is 0.1–1 nm, the thickness of the second insertion layer is 0.3–1.5 nm, and the thickness of the third insertion layer is 0.3–1.5 nm.

5. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The passivation layer includes an AlN layer.

6. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: Methods for forming the barrier stack include MOCVD.

7. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The P-type GaN portion includes a P-type GaN main body portion located on the inner wall of the trench and P-type GaN side wings portion extending horizontally from the top of the P-type GaN main body portion to both sides. The P-type GaN side wings portion and the third insertion layer have a support portion formed by a part of the third barrier layer.

8. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to any one of claims 1 to 3, characterized in that: The substrate comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, and a C-doped GaN layer.

9. The method for fabricating a GaN-based enhancement-mode HEMT device structure according to claim 8, characterized in that: The substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

10. A GaN-based enhancement-mode HEMT device structure, characterized in that, include: A substrate having a channel layer on one side, the channel layer comprising an undoped GaN layer; A barrier stack, located on the channel layer, and comprising at least a first insertion layer, a first barrier layer, a second insertion layer, a second barrier layer, and a third insertion layer stacked sequentially from bottom to top; The trench opens from the top surface of the barrier stack and extends downward to the second insertion layer; The P-type GaN portion at least covers the bottom wall of the trench, and the top layer of the barrier stack surrounding the P-type GaN portion is the third insertion layer; A passivation layer covers the P-type GaN portion and the third insertion layer surrounding the P-type GaN portion; The gate electrode and the source electrode and drain electrode are respectively located on both sides of the gate electrode. The gate electrode penetrates the passivation layer and contacts the P-type GaN portion. The source electrode and the drain electrode penetrate the passivation layer and contact the third insertion layer.

11. The GaN-based enhancement-mode HEMT device structure according to claim 10, characterized in that: The first insertion layer, the second insertion layer and the third insertion layer all include an AlN layer, and the first barrier layer and the second barrier layer both include an AlGaN layer.

12. The GaN-based enhancement-mode HEMT device structure according to claim 10, characterized in that: The thickness of the barrier stack ranges from 12 to 20 nm.

13. The GaN-based enhancement-mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The thickness of the first insertion layer is 0.1–1 nm, the thickness of the second insertion layer is 0.3–1.5 nm, and the thickness of the third insertion layer is 0.3–1.5 nm.

14. The GaN-based enhancement-mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The passivation layer includes an AlN layer.

15. The GaN-based enhancement-mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The P-type GaN portion includes a P-type GaN main body portion located on the inner wall of the trench and P-type GaN side wings portion extending horizontally from the top of the P-type GaN main body portion to both sides. The barrier stack also includes a third barrier layer located on the third insertion layer. A support portion formed by the third barrier layer is provided between the P-type GaN side wings portion and the third insertion layer.

16. The GaN-based enhancement-mode HEMT device structure according to any one of claims 10 to 12, characterized in that: The substrate comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, and a C-doped GaN layer.

17. The GaN-based enhancement-mode HEMT device structure according to claim 16, characterized in that: The substrate layer includes a Si layer, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN-AlN superlattice layer.

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