Semiconductor structure, forming method and semiconductor device

Abstract

This invention relates to the field of semiconductor technology, and particularly to a semiconductor structure, a method for forming it, and a semiconductor device. The semiconductor structure includes a substrate, a buried layer on the substrate, the buried layer having a different conductivity type than the substrate, a deep well layer on the buried layer, the deep well layer having the same conductivity type as the substrate, and a transistor structure on the deep well layer. The transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure. The drift region and the body region are located on the deep well layer, and the source region is located within the body region. The buried layer has at least one via to expose a predetermined area of ​​the substrate, thereby preventing the buried layer from exhausting the deep well layer and preserving a path for the deep well layer to collect avalanche holes, thus eliminating the DIBL problem of LDMOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for forming it, and a semiconductor device. Background Technology

[0002] In integrated circuit manufacturing, various types of devices are typically integrated, such as laterally diffused metal oxide semiconductor (LDMOS) devices, which are often used in microwave / RF circuits and can withstand high voltages. However, the high leakage caused by the leakage inductive barrier reduction (DIBL) problem in the existing LDMOS structure often leads to device function degradation or even breakdown. Summary of the Invention

[0003] To address the aforementioned technical problems, this application discloses a semiconductor structure comprising:

[0004] Substrate;

[0005] A buried layer located on the substrate; the buried layer has a different conductivity type than the substrate;

[0006] A deep well layer located on the buried layer; the deep well layer has the same conductivity type as the substrate;

[0007] The transistor structure is located on the deep well layer; the transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure; the drift region and the body region are located on the deep well layer, and the source region is provided in the body region;

[0008] The buried layer has at least one through hole to expose a predetermined area of ​​the substrate.

[0009] For example, at least one of the through holes is disposed in the region corresponding to the drift region.

[0010] For example, the buried layer is provided with at least three through holes;

[0011] At least one through hole is provided at each of the two ends and the middle part of the buried layer.

[0012] For example, a transistor array is provided on the deep well layer;

[0013] The transistor array includes a plurality of the transistor structures;

[0014] Each of the transistor structures has at least one via in its buried layer.

[0015] For example, the substrate has a P-type conductivity.

[0016] The buried layer has an N-type conductivity.

[0017] The conductivity type of the deep well layer is N-type.

[0018] For example, the N-type ion concentration in the buried layer is 10. 14 Units per square centimeter to 10 16 pcs / square centimeter

[0019] For example, the conductivity type of the drift region is N-type;

[0020] The conductivity type of the body region is P-type;

[0021] Both the source region and the drain region are heavily doped N-type regions;

[0022] The drift region and the body region are arranged side by side on the deep well layer along a predetermined direction; the predetermined direction is a direction perpendicular to the height direction of the transistor structure.

[0023] The gate structure includes a gate oxide layer and a polysilicon layer located on the gate oxide layer; a portion of the gate oxide layer is located on the drift region, and another portion of the gate oxide layer is located on the body region.

[0024] In another aspect, this application discloses a method for forming a semiconductor structure, comprising:

[0025] A substrate structure is provided; the substrate structure includes a substrate and a buried layer located on the substrate; the buried layer has a different conductivity type than the substrate; the buried layer has at least one via to expose a predetermined area of ​​the substrate;

[0026] A deep well layer is formed on the buried layer; the deep well layer has the same conductivity type as the substrate.

[0027] A transistor structure is formed on the deep well layer; the transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure; the drift region and the body region are located on the deep well layer, and the source region is provided within the body region.

[0028] For example, the provision of a substrate structure includes:

[0029] Provide a base;

[0030] Ion doping is performed on a predetermined region of the substrate to form an initial buried layer within the substrate;

[0031] The initial embedded layer is graphically represented to form at least one through-hole in the initial embedded layer, thereby obtaining the embedded layer.

[0032] In another aspect, this application discloses a semiconductor device comprising the aforementioned semiconductor structure.

[0033] In another aspect, this application discloses an electronic device characterized by comprising the aforementioned semiconductor device.

[0034] The semiconductor structure provided in this application includes a substrate, a buried layer on the substrate, the buried layer having a different conductivity type from the substrate, a deep well layer on the buried layer, the deep well layer having the same conductivity type as the substrate, and a transistor structure on the deep well layer. The transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure. The drift region and the body region are located on the deep well layer, and the source region is located within the body region. The buried layer has at least one via to expose a predetermined area of ​​the substrate. This structure prevents the buried layer from exhausting the deep well layer, preserving the path for the deep well layer to collect avalanche holes, thereby eliminating the DIBL problem of LDMOS. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a cross-sectional view of an exemplary semiconductor structure of this application;

[0037] Figure 2 This is a top view of an exemplary buried layer in this application;

[0038] Figure 3 This is a cross-sectional view of another exemplary semiconductor structure of this application;

[0039] Figure 4 This is a schematic flowchart illustrating a method for forming a semiconductor structure, as exemplified in this application.

[0040] The following is supplementary explanation of the attached figures:

[0041] 1-Substrate; 2-Buried layer; 21-Through hole; 3-Deep well layer; 4-Drift region; 5-Bulk region; 6-Source region; 7-Drain region; 8-Gate structure; 81-Polysilicon layer; 82-Sidewall; 9-First lead-out region; 10-Isolation structure; 11-Medium voltage well region; 12-High voltage region; 13-Second lead-out region; 14-Third lead-out region; 15-Barrier structure. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0044] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0045] Please see Figure 1The diagram shows a cross-sectional view of an exemplary semiconductor structure of this application. The semiconductor structure includes a substrate 1; a buried layer 2 located on the substrate 1; the buried layer 2 having a different conductivity type from the substrate 1; a deep well layer 3 located on the buried layer 2; the deep well layer 3 having the same conductivity type as the substrate 1; and a transistor structure located on the deep well layer 3. The transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8. The drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is disposed within the body region 5.

[0046] For example, semiconductors are generally classified into two types based on their conductivity: P-type semiconductors and N-type semiconductors. N-type semiconductors are formed by doping pure silicon crystals with N-type elements (such as pentavalent elements like phosphorus), causing them to replace silicon atoms in the crystal lattice. Similarly, P-type semiconductors are formed by doping pure silicon crystals with P-type elements (such as trivalent elements like boron), causing them to replace silicon atoms in the crystal lattice. Generally, N-type semiconductors doped with N-type elements are characterized by a much higher concentration of free electrons than holes; they are electronic semiconductors. In N-type materials, electrons are the primary charge carriers responsible for current conduction. When an N-type material is forward biased, electrons move in the conduction band, generating current. P-type semiconductors doped with P-type elements are characterized by being hole-type semiconductors, with positively charged holes being the primary charge carriers. In P-type materials, holes are the primary charge carriers responsible for current conduction. When a P-type material is forward biased, holes move in the valence band, thus forming a current. The combination of N-type and P-type semiconductors forms a PN junction. Due to the difference in carrier concentration between them, an electric field is generated, which is a key characteristic of diodes. The PN junction has nonlinear conductivity, enabling unidirectional current conduction and providing a foundation for diode applications. Optionally, the substrate 1 can be an N-type substrate or a P-type substrate, but correspondingly, the buried layer 2 and the ion doping type in the transistor device will also be adjusted accordingly. To better understand the technical solution of this application, the following will describe it in detail with substrate 1 as a P-type substrate. When substrate 1 is a P-type substrate, the conductivity type of the buried layer 2 is N-type, the conductivity type of the deep well layer 3 is P-type, the conductivity type of the drift region 4 is N-type, the conductivity type of the body region 5 is P-type, and the source region 6 and drain region 7 are both heavily N-type doped regions.

[0047] For example, substrate 1 may specifically be a silicon substrate, silicon-on-insulator substrate, etc.

[0048] Taking the above semiconductor structure as an example of a semiconductor manufactured using LDMOS technology (i.e., an LDMOS device), an LDMOS device is a transistor capable of withstanding high voltages. To improve the DIBL problem of LDMOS devices, it is necessary to control the doping concentration of N-type ions in the buried layer 2 (i.e., the N-type doped layer). Please refer to [link to relevant documentation]. Figure 1 Because the deep well layer 3, buried layer 2, and substrate 1 in an LDMOS device form a parasitic PNP transistor, when it is turned on, the buried layer 2 acts as the base region. When the N-type ion concentration in the base region is too low, the amplification factor (i.e., β) of this parasitic transistor becomes too high, resulting in more leakage current. However, when the N-type ion concentration in the base region is too high, it depletes the holes in the deep well layer 3, weakening the ability of the deep well layer 3 to assist in the depletion of the drift region 4. This weakens the depletion capability of the drift region 4, thereby reducing the voltage withstand capability of the LDMOS device. In addition, the drift region 4 and body region 5 in the LDMOS device also form a PN junction, creating a depletion region. This depletion region is usually quite wide, making it prone to avalanche breakdown. When an LDMOS device is subjected to high voltage, avalanche electrons are collected by the drain, while holes are collected by the body region 5 or the deep well layer 3. That is, electron-hole pairs generated in the drift region 4 can flow to the deep well layer 3 for collection, while the other part flows to the body region 5 for collection. When the concentration of N-type ions in the buried region is too high, the collection ability of the deep well layer 3 will weaken, causing most of the electrons to go to the body region 5. This results in an increasing number of holes in the body region 5, causing the aforementioned depletion region (also known as the space barrier region) to narrow, thus causing the DIBL leakage problem.

[0049] To improve the DIBL leakage problem of the LDMOS mentioned above, please refer to... Figure 2 In this embodiment, vias 21 are provided on the buried layer 2. The number of vias 21 can be one, two, three, four, five, etc., without limitation. These vias 21 enable the deep well layer 3 to form a conductive path with the substrate 1, allowing some of the electron-hole pairs in the drift region 4 to be collected by the substrate 1, while the others can flow out through the body region 5-first lead-out region 9, thus reducing the likelihood of avalanche breakdown. Moreover, the vias 21 effectively reduce the effective area of ​​the buried layer 2, thereby indirectly increasing the concentration of N-type ions in the buried layer 2, i.e., the electron concentration per unit area on the buried layer 2 is higher, but the total number of electrons in the entire effective area of ​​the buried layer 2 may still be relatively small, thereby improving the parasitic effect of the parasitic transistor. An inverting diode (drift region 4-deep well layer 3-substrate 1) can be formed at the location of the via 21, which can eliminate the parasitic effect of the aforementioned parasitic transistor (deep well layer 3-buried layer 2-substrate 1).

[0050] In one exemplary embodiment, the N-type ion concentration in the buried layer 2 is 10. 14 Units per square centimeter to 1016 The concentration of N-type ions in the buried layer 2 can be 10 ions / square centimeter. 14 Units / square centimeter, 10 15 Units per square centimeter or 10 16 The ion concentration in buried layer 2 varies depending on the voltage withstand capability of the specific LDMOS device. Typically, the voltage withstand capability of LDMOS devices can be set to 10 volts, 12 volts, 16 volts, 20 volts, etc. The higher the voltage withstand capability of the LDMOS device, the higher the concentration of N-type ions in buried layer 2. It should be noted that the ion concentration here refers to the number of ions per unit area (excluding vias 21) in the effective area of ​​buried layer 2. Therefore, the effective area of ​​buried layer 2 can be adjusted according to the voltage withstand capability of the designed device. Generally, the higher the voltage withstand capability of the device, the smaller the effective area of ​​buried layer 2, meaning the more area occupied by vias 21 in buried layer 2. This can be achieved by setting a large but few vias 21 or a small but numerous vias 21 in buried layer 2.

[0051] The specific location, shape, and size of the via 21 are not limited here. They can be adjusted according to the electrical performance of the fabricated LDMOS device. Optionally, the shape of the via 21 can be circular, elliptical, square, rectangular, or triangular, etc., without limitation. In one exemplary embodiment, at least one via 21 is disposed in the region corresponding to the drift region 4. In fact, the via 21 can also be disposed below the body region 5, without limitation. In another exemplary embodiment, at least three vias 21 are provided on the buried layer 2; at least one via 21 is provided at each end and the middle of the buried layer 2, that is, at least one via 21 is provided at each end and the middle of the buried layer 2. The remaining vias 21 can be randomly arranged. In other embodiments, multiple vias 21 can also be arranged as follows: Figure 2 The layers are evenly arranged along the length of the buried layer 2, as shown.

[0052] In one exemplary embodiment, a transistor array is provided on the deep well layer 3; the transistor array includes a plurality of transistor structures; and each transistor structure has at least one via 21 in the buried layer 2. See also... Figure 3 A cross-sectional view of a transistor array is shown as an example. Figure 3 The example semiconductor structure is symmetrical along the dashed line in the figure. It includes at least 4 parallel LDMOS devices. Since the buried layer 2 corresponding to these LDMOS devices is integrally formed, the entire buried layer 2 is also distributed with vias 21. For example, if the transistor array is a 3*3 array, then the buried layer 2 has at least 3*3 vias 21.

[0053] For example, the buried layer 2 is further provided with a buried layer of different conductivity types to form a PN junction, thereby preventing impurities in the substrate 1 from diffusing into the transistor structure and reducing the transistor's functionality. Specifically, when the conductivity type of the substrate 1 is P-type, an N-type buried layer and a P-type buried layer are sequentially provided on it, meaning that the conductivity type of the buried layer near the substrate 1 is different from the conductivity type of the substrate 1. Similarly, when the conductivity type of the substrate 1 is N-type, a P-type buried layer and an N-type buried layer are sequentially provided on it.

[0054] For example, please refer to Figure 3 The drift region 4 and the body region 5 are arranged side-by-side on the deep well layer 3 along a preset direction; the preset direction is a direction perpendicular to the height direction of the transistor structure. Specifically, the preset direction may refer to... Figure 3 In the x-direction, the drain region 7 is located in the drift region 4, and the source region 6 and the first lead-out region 9 are located in the body region 5. The drain region 7, source region 6, first lead-out region 9, drift region 4, and body region 5 can all be obtained through existing doping processes, and the conductivity types of the drain region 7, source region 6, and drift region 4 can be the same. The conductivity types of the first lead-out region 9 and body region 5 can also be the same. The drain region 7 is the drain of the LDMOS device, the source region 6 is the source of the LDMOS device, and the first lead-out region 9 is connected to the body region 5 to export the electron-hole pairs formed in the body region 5. Since... Figure 3 The example shows a parallel connection of multiple transistor structures. The body regions 5 of two adjacent transistor structures are connected together. After integral molding, the two adjacent transistor structures share a body region 5. Two source regions 6 and a first lead-out region 9 are provided in the body region 5. The first lead-out region 9 is located between the two source regions 6.

[0055] A portion of the gate structure 8 covers the drift region 4, and another portion covers the body region 5. Specifically, the gate structure 8 may include a gate oxide layer and a polysilicon layer 81 located on the gate oxide layer, as well as sidewalls 82 located on both sides of the polysilicon layer 81. Specifically, the source region 6 and the drain region 7 are located on both sides of the gate structure 8; that is, the source region 6 is located on one side of the gate structure 8, and the drain region 7 is located on the other side. Optionally, the gate structure 8 may also include a blocking structure 15, which covers a portion of the top of the gate structure 8, one sidewall, and the drift region 4.

[0056] Doping is generally achieved through implantation. The higher the required ion doping concentration, the higher the implantation dose should be during the implantation process. Generally, the ion doping concentration in drift region 4 is relatively low, which is equivalent to forming a high-resistivity layer between source region 6 and drain region 7. This can improve the breakdown voltage and reduce the parasitic capacitance between source region 6 and drain region 7, which is beneficial to improving frequency characteristics.

[0057] The doping concentration in body region 5 is relatively high, and the implantation dose is correspondingly high.

[0058] For example, please continue reading Figure 3 The transistor structure has a medium-voltage well region 11 and a high-voltage region 12 on both sides. The conductivity type of the medium-voltage well region 11 is the same as that of the deep well layer 3. The medium-voltage well region 11 also has a second lead-out region 13 for electrical connection with other devices. The medium-voltage well region 11 is connected to the deep well layer 3 and is located on the buried layer 2. The conductivity type of the high-voltage region 12 can be the same as that of the buried layer 2. The high-voltage region 12 also has a third lead-out region 14 for electrical connection with other devices. The high-voltage region 12 is located on the buried layer 2 and is connected to the buried layer 2. Optionally, an isolation structure 10 is provided between the second lead-out region 13 adjacent to the drain region 7, and an isolation structure 10 is also provided between the adjacent second lead-out region 13 and the third lead-out region 14. Specifically, the isolation structure 10 can be a shallow trench isolation region (STI). Shallow trench isolation zones can typically be filled with low-dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped glass, and / or any other suitable low-dielectric materials.

[0059] An isolation structure 10 can also be formed within the drift region 4 and between the gate structure 8 and the drain region 7. The isolation structure 10 can isolate the source region 6 and the drain region 7, thereby effectively increasing the breakdown voltage of the LDMOS device.

[0060] An isolation structure 10 may also be provided within the body region 5 and between the source region 6 and the first lead-out region 9. This isolation structure 10 can isolate the source region 6 and the first lead-out region 9.

[0061] The semiconductor structure provided in this application includes a substrate 1, a buried layer 2 on the substrate 1, the buried layer 2 having a different conductivity type from the substrate 1, a deep well layer 3 on the buried layer 2, the deep well layer 3 having the same conductivity type as the substrate 1, and a transistor structure on the deep well layer 3. The transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8. The drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is provided within the body region 5. The buried layer 2 has at least one via 21 to expose a predetermined area of ​​the substrate 1. By simply modifying the structure of the buried layer 2, the DIBL effect of the device can be effectively eliminated. Specifically, based on the above structural design, the doping concentration of the buried layer 2 can be indirectly increased, thereby increasing the base region concentration, increasing the hole recombination rate, and finally reducing the parasitic effect of the parasitic transistor composed of the deep well layer 3, the buried layer 2, and the substrate 1. Meanwhile, due to the setting of via 21, the effective area of ​​buried layer 2 is reduced, which indirectly increases the doping concentration of buried layer 2. Firstly, the deep well layer 3 can fully deplete the drift region 4, which can make the breakdown voltage (i.e., BV) of the LDMOS device higher. Secondly, the buried layer 2 cannot deplete the deep well layer 3, thus preserving the path for the deep well layer 3 to collect avalanche holes, thereby eliminating the DIBL problem of the LDMOS device. That is, the semiconductor structure provided by the embodiments of this application can not only eliminate the above-mentioned parasitic effects, but also eliminate the DIBL effect of the LDMOS device.

[0062] Please see Figure 4 The diagram illustrates a process flow of an exemplary semiconductor structure formation method according to this application. In another aspect, this application discloses a method for forming a semiconductor structure, comprising:

[0063] S401: Provide a substrate structure; the substrate structure includes a substrate and a buried layer located on the substrate; the buried layer has a different conductivity type than the substrate; the buried layer has at least one through-hole to expose a predetermined area of ​​the substrate.

[0064] In an exemplary embodiment, step S401 may specifically include: providing a substrate; performing ion doping on a predetermined region of the substrate to form an initial buried layer 2 within the substrate; and patterning the initial buried layer 2 to form at least one via 21 in the initial buried layer 2, thereby obtaining the buried layer 2.

[0065] Specifically, the substrate is usually a wafer. Since impurities exist in wafers, they can affect the electrical performance of electronic devices fabricated on them. Therefore, for electronic devices with high precision requirements, they cannot be directly formed on the wafer. Instead, P-type and N-type buried layers are first formed on the wafer to create a PN junction, which acts as an isolation layer, preventing impurities from the substrate 1 from entering the upper layer. Then, a pure epitaxial layer is formed on the buried layer 2. The epitaxial layer has the advantages of fewer impurities and a dense and complete lattice arrangement, enabling the fabrication of higher precision electronic devices. Subsequent transistor structures and well layers are fabricated in the epitaxial layer.

[0066] When the substrate is a P-type substrate, the aforementioned buried layer 2 refers to an N-type buried layer. To form a PN junction region, a P-type buried layer also needs to be formed. The specific methods for forming the N-type and P-type buried layers can include the following two: In an exemplary embodiment, N-type doping is first performed at a predetermined depth on the substrate, followed by N-type doping diffusion, then P-type doping and diffusion, so that the P-type doped layer (P-type buried layer) is located above the N-type doped layer (N-type buried layer), forming a PN junction region. This can prevent impurities in the substrate 1 from entering the upper deep well layer 3 and other structures, effectively improving the reliability of the device. However, in reality, since the P-type dopant element is usually boron, and boron ions are highly reactive ions, after boron ion implantation, subsequent P-type doping diffusion, under high temperature conditions, can easily cause boron ions to escape from the substrate 1. This results in a lack of holes in the P-region of the PN junction formed by P-type and N-type doping, weakening the isolation effect and making it easier for impurities in the substrate 1 to enter the subsequent upper epitaxial layer, ultimately affecting the electrical performance of the electronic device in the epitaxial layer. Furthermore, the aforementioned process steps are quite complex. Therefore, another exemplary implementation scheme is provided. Specifically, P-type doping is first performed on a region at a first predetermined depth of the substrate to form a first doped layer on the substrate 1. The first doped layer has the same conductivity type as the substrate. N-type doping is then performed on a region at a second predetermined depth of the substrate to form a second doped layer in the substrate 1, resulting in a doped substrate 1 where the position of the second predetermined depth is lower than the position corresponding to the first predetermined depth. The doped substrate 1 is then processed using a diffusion process, so that the P-type doped layer (P-type buried layer) is located above the N-type doped layer (N-type buried layer). This scheme, by first forming a doped layer with the same conductivity type as the substrate 1, then performing ion doping of a different conductivity type on the substrate 1, and subsequently performing a unified diffusion process to form a PN junction in the substrate 1, and then growing an epitaxial layer on it, not only simplifies the entire forming process and avoids the diffusion of impurities from the substrate 1 to the epitaxial layer, but also reduces the dislocation situation (i.e., lattice defects) in the epitaxial layer, thereby improving the quality of the epitaxial layer. The implantation surface for performing different types of ion doping on the substrate is the same.

[0067] When the substrate is an N-type substrate, the above-mentioned buried layer 2 refers to a P-type buried layer. In order to form a PN junction region, an N-type buried layer also needs to be formed. The specific schemes for forming the N-type buried layer and the P-type buried layer can include the following two: In an exemplary embodiment, the substrate is first P-type doped at a predetermined depth, then P-type doping diffusion is performed, and then N-type doping and N-type doping diffusion are performed, so that the N-type doped layer (N-type buried layer) is located above the P-type doped layer (P-type buried layer), forming a PN junction region. This can prevent impurities in the substrate 1 from entering the upper deep well layer 3 and other structures, and can effectively improve the reliability of the device. In another exemplary embodiment, N-type doping can be performed on a region at a first predetermined depth of the substrate to form a first doped layer on the substrate 1; the first doped layer has the same conductivity type as the substrate; P-type doping is then performed on a region at a second predetermined depth of the substrate to form a second doped layer in the substrate 1, resulting in a doped substrate 1, where the position of the second predetermined depth is lower than the position corresponding to the first predetermined depth; the doped substrate 1 is then processed based on a diffusion process, so that the N-type doped layer (N-type buried layer) is located above the P-type doped layer (P-type buried layer). This scheme, by first forming a doped layer with the same conductivity type as the substrate 1, then performing ion doping of another conductivity type on the substrate 1, and subsequently performing a unified diffusion process to form a PN junction in the substrate 1, and then growing an epitaxial layer on it, not only simplifies the entire forming process and avoids the diffusion of impurities in the substrate 1 to the epitaxial layer, but also reduces the dislocation situation (i.e., lattice defects) in the epitaxial layer, thereby improving the quality of the epitaxial layer. The implantation surface for performing different types of ion doping on the substrate is the same.

[0068] For example, before forming the buried layer 2, the formation method further includes forming a sacrificial layer on the surface of the substrate. Specifically, the sacrificial layer is a silicon oxide layer, which can subsequently serve as a mask for ion implantation, blocking areas where ion implantation is not required. Therefore, before ion implantation, the formation method further includes: forming a sacrificial layer on the surface of the substrate 1, and patterning the sacrificial layer based on photolithography and etching processes. This allows a doped layer to be formed in a predetermined region at a first predetermined depth on the substrate. Optionally, the thickness of the sacrificial layer is 150 angstroms to 300 angstroms.

[0069] Since two different types of buried layers 2 with different conductivity are required, after the first doping, a patterned mask needs to be formed on the surface of the substrate after the first doping. Based on the patterned mask, ion implantation of another type of conductivity is performed on a predetermined region at a second predetermined depth of the substrate via the implantation face of the substrate 1 to form a doped layer of another type of conductivity on the substrate 1. Specifically, masks can be divided into photoresist and hard mask types. Photoresist, also known as photoresist, refers to a thin film etchant material whose solubility changes upon irradiation or radiation by ultraviolet light, electron beams, ion beams, X-rays, etc. In semiconductor forming processes, to obtain a very thin barrier layer, spin coating is usually used to coat the photoresist onto the surface of the semiconductor material. Of course, for some applications where linewidth accuracy requirements are not high and to improve manufacturing efficiency, roll coating can also be used to coat the photoresist onto the surface of the semiconductor material. Another type is the hard mask, which is an inorganic thin film material generated through a deposition process. Its main components are usually TiN, SiN, SiO2, etc.

[0070] S403: A deep well layer is formed on the buried layer; the deep well layer has the same conductivity type as the substrate.

[0071] For example, step S403 may specifically include forming an epitaxial layer on the buried layer 2, and performing a doping treatment on a predetermined region at a predetermined depth in the epitaxial layer to form a deep well layer 3 in the epitaxial layer, the deep well layer 3 being located on the buried layer 2. Optionally, the epitaxial layer is specifically formed by an epitaxial growth process, which can continue to grow along the lattice direction of the substrate 1 to form the epitaxial layer. The specific growth temperature can be the same as the existing process, or it can be adaptively adjusted.

[0072] S405: A transistor structure is formed on the deep well layer 3; the transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8; the drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is provided in the body region 5.

[0073] For example, the transistor structure described above is specifically formed in the epitaxial layer, which gives the final transistor structure the advantage of high reliability.

[0074] For example, the drift region 4 and the body region 5 are arranged side by side on the deep well layer 3 along a preset direction; the preset direction is a direction perpendicular to the height direction of the transistor structure. The drain region 7 is located in the drift region 4, and the source region 6 and the first lead-out region 9 are located in the body region 5. The drain region 7, the source region 6, the first lead-out region 9, the drift region 4, and the body region 5 can all be obtained by existing doping processes, and the conductivity types of the drain region 7, the source region 6, and the drift region 4 can be the same. The conductivity types of the first lead-out region 9 and the body region 5 can be the same. The drain region 7 is the drain of the LDMOS device, the source region 6 is the source of the LDMOS device, and the first lead-out region 9 is connected to the body region 5 to export the electron-hole pairs formed in the body region 5.

[0075] Generally, the ion doping concentration in drift region 4 is relatively low, which is equivalent to forming a high-resistivity layer between source region 6 and drain region 7. This can improve the breakdown voltage and reduce the parasitic capacitance between source region 6 and drain region 7, which is beneficial to improving frequency characteristics.

[0076] The doping concentration in body region 5 is relatively high, and the implantation dose is correspondingly high.

[0077] The semiconductor structure prepared by the above method includes a substrate 1, a buried layer 2 on the substrate 1, the buried layer 2 having a different conductivity type from the substrate 1, a deep well layer 3 on the buried layer 2, the deep well layer 3 having the same conductivity type as the substrate 1, and a transistor structure on the deep well layer 3. The transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8. The drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is provided in the body region 5. The buried layer 2 has at least one via 21 to expose a predetermined area of ​​the substrate 1. Thus, by simply modifying the structure of the buried layer 2, not only can the parasitic effect of the parasitic transistor composed of the deep well layer 3-buried layer 2-substrate 1 be eliminated, but the DIBL effect of the device can also be eliminated.

[0078] This application discloses, in another aspect, a semiconductor device comprising the aforementioned semiconductor structure. The semiconductor device may be an LDMOS device, specifically including LNDOMS and LPDMOS devices, or a combination thereof. The semiconductor structure includes a substrate 1, a buried layer 2 on the substrate 1; the buried layer 2 having a different conductivity type than the substrate 1; a deep well layer 3 on the buried layer 2; the deep well layer 3 having the same conductivity type as the substrate 1; and a transistor structure on the deep well layer 3; the transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8; the drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is disposed within the body region 5; and at least one via 21 is provided on the buried layer 2 to expose a predetermined area of ​​the substrate 1. Only a simple structural modification to the buried layer 2 is needed to eliminate not only the parasitic effects of the parasitic transistor formed by the deep well layer 3-buried layer 2-substrate 1, but also the DIBL effect of the device. Therefore, the semiconductor device incorporating this semiconductor structure has the same advantages.

[0079] In another aspect, this application discloses an electronic device characterized by comprising the aforementioned semiconductor device.

[0080] Specifically, the electronic device includes semiconductor devices and electronic components connected to the semiconductor devices. The semiconductor structure includes a substrate 1, a buried layer 2 on the substrate 1; the buried layer 2 has a different conductivity type than the substrate 1; a deep well layer 3 on the buried layer 2; the deep well layer 3 has the same conductivity type as the substrate 1; and a transistor structure on the deep well layer 3; the transistor structure includes a drift region 4, a body region 5, a source region 6, a drain region 7, and a gate structure 8; the drift region 4 and the body region 5 are located on the deep well layer 3, and the source region 6 is located within the body region 5; and the buried layer 2 has at least one via 21 to expose a predetermined area of ​​the substrate 1. Only a simple structural modification to the buried layer 2 is needed to eliminate not only the parasitic effects of the parasitic transistor formed by the deep well layer 3-buried layer 2-substrate 1, but also the DIBL effect of the device. This electronic component can be any electronic component, such as a transistor.

[0081] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or any intermediate product including the above-mentioned semiconductor devices.

[0082] The electronic device of this invention, since it uses the semiconductor device described above, also has the advantages described above.

[0083] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0084] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0086] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; Buried layer located on the substrate; The buried layer has a different conductivity type than the substrate; A deep well layer located on the buried layer; The deep well layer has the same conductivity type as the substrate; The transistor structure is located on the deep well layer; the transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure; the drift region and the body region are located on the deep well layer, and the source region is provided in the body region; The buried layer has at least one through hole to expose a predetermined area of ​​the substrate.

2. The semiconductor structure according to claim 1, characterized in that, At least one of the through holes is disposed in the region corresponding to the drift region, or disposed below the body region.

3. The semiconductor structure according to claim 1, characterized in that, The buried layer is provided with at least three through holes; At least one through hole is provided at each of the two ends and the middle part of the buried layer.

4. The semiconductor structure according to claim 1, characterized in that, A transistor array is provided on the deep well layer; The transistor array includes a plurality of the transistor structures; Each of the transistor structures has at least one via in its buried layer.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The substrate has a P-type conductivity. The buried layer has an N-type conductivity. The conductivity type of the deep well layer is N-type.

6. The semiconductor structure according to claim 5, characterized in that, The N-type ion concentration in the buried layer is 10. 14 Units per square centimeter to 10 16 pcs / square centimeter 7. The semiconductor structure according to claim 5, characterized in that, The drift region has an N-type conductivity. The conductivity type of the body region is P-type; Both the source region and the drain region are heavily doped N-type regions; The drift region and the body region are arranged side by side on the deep well layer along a predetermined direction; the predetermined direction is a direction perpendicular to the height direction of the transistor structure. The gate structure includes a gate oxide layer and a polysilicon layer located on the gate oxide layer; a portion of the gate oxide layer is located on the drift region, and another portion of the gate oxide layer is located on the body region.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate structure is provided; the substrate structure includes a substrate and a buried layer located on the substrate; The buried layer has a different conductivity type than the substrate; The buried layer is provided with at least one through hole to expose a predetermined area of ​​the substrate; A deep well layer is formed on the buried layer; the deep well layer has the same conductivity type as the substrate. A transistor structure is formed on the deep well layer; the transistor structure includes a drift region, a body region, a source region, a drain region, and a gate structure; the drift region and the body region are located on the deep well layer, and the source region is provided within the body region.

9. The forming method according to claim 8, characterized in that, The provision of a substrate structure includes: Provide a base; Ion doping is performed on a predetermined region of the substrate to form an initial buried layer within the substrate; The initial embedded layer is graphically represented to form at least one through-hole in the initial embedded layer, thereby obtaining the embedded layer.

10. A semiconductor device, characterized in that, Includes the semiconductor structure as described in any one of claims 1-7.

11. An electronic device, characterized in that, Including the semiconductor device as described in claim 10.

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