Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: a substrate having a deep well region therein, the deep well region having a first conductivity type; a drift region and a body region adjacent to each other within the deep well region, the body region having a second conductivity type, the drift region having the first conductivity type, and the first and second conductivity types being opposite; a source region within the body region, and the source region having the first conductivity type; a drain region within the deep well region, the drain region having the first conductivity type, and a top of the drain region being lower than a bottom of the source region; and a gate structure on a portion of a surface of the body region and a portion of a surface of the drift region. The performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a kind of power device formed by planar diffusion on the surface of a semiconductor substrate to form a lateral current path, which is often used in radio frequency power circuits, and in high-voltage power integrated circuits, high-voltage LDMOS is often used to meet the requirements of high-voltage resistance and power control. Compared with traditional MOS transistors, a lightly doped region is usually provided between the source region and the drain region of the LDMOS transistor, which is called the drift region. Therefore, when the LDMOS transistor is connected with a high voltage between the source region and the drain region, the drift region can withstand a higher voltage drop due to the low impurity concentration of the drift region, so the LDMOS transistor can have a higher breakdown voltage.

[0003] The LDMOS transistor is compatible with the CMOS (Complementary Metal Oxide Semiconductor) process, so it is widely used in power devices. For LDMOS transistors used as power integrated circuits, Rdson (on-resistance) and BV (Breakdown Voltage) are two important indicators for measuring the performance of the device.

[0004] However, the performance of the existing LDMOS transistor is still poor. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the lateral double diffusion metal oxide semiconductor.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate has a deep well region inside, the deep well region has a first conductivity type; a drift region and a body region adjacent to each other in the deep well region, the body region has a second conductivity type, the drift region has the first conductivity type, and the first conductivity type and the second conductivity type are opposite; a source region in the body region, and the source region has the first conductivity type; a drain region in the deep well region, the drain region has the first conductivity type, and the top of the drain region is lower than the bottom of the source region; a gate structure on part of the surface of the body region and part of the surface of the drift region.

[0007] Optionally, the drift region includes opposite first and second sides; the body region is adjacent the first side of the drift region, and the drain region is within the deep well region of the second side wall of the drift region.

[0008] Optionally, the substrate further includes a shallow well region within a portion of the deep well region, the shallow well region having a second conductivity type; the body region and the drift region are within the shallow well region, and the shallow well region is in communication with the deep well region of the second side wall of the drift region.

[0009] Optionally, a top of the drain region is lower than a bottom of the drift region.

[0010] Optionally, further comprising a first plug within the deep well region, the first plug is electrically connected to the drain region, and a first isolation layer is between a sidewall of the first plug and the deep well region.

[0011] Optionally, a material of the first plug includes doped polysilicon or a metal, the metal includes one or a combination of copper, tungsten, aluminum, titanium, and nickel.

[0012] Optionally, further comprising a second isolation layer within the deep well region and within the drift region, the deep well region exposes a surface of the second isolation layer, and a bottom of the second isolation layer is connected to a top of the first isolation layer.

[0013] Optionally, further comprising a conductive region within the deep well region, the first plug penetrates the conductive region, and the conductive region has a first conductivity type.

[0014] Optionally, a bottom of the conductive region is higher than a top of the drain region.

[0015] Optionally, the deep well region has a first doping concentration, the conductive region has a second doping concentration, and the second doping concentration is greater than the first doping concentration.

[0016] Optionally, further comprising a second plug on a surface of the substrate, the second plug is electrically connected to the source region.

[0017] Optionally, further comprising a barrier layer on a surface of the drift region and on a sidewall of one side of the gate structure, and the one side of the gate structure is on the drift region; a third plug on the barrier layer, and the barrier layer is between the gate structure and the third plug.

[0018] Correspondingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a deep well region in the substrate, the deep well region having a first conductivity type; forming an adjacent drift region and body region in the deep well region, the body region having a second conductivity type, the drift region having the first conductivity type, and the first conductivity type and the second conductivity type being opposite; forming a source region in the body region, and the source region having the first conductivity type; forming a drain region in the deep well region, the drain region having the first conductivity type, and a top of the drain region being lower than a bottom of the source region; and forming a gate structure on a part of a surface of the body region and a part of a surface of the drift region.

[0019] Optionally, the top of the drain region is lower than the bottom of the drift region.

[0020] Optionally, the method further comprises: forming a shallow well region in a part of the deep well region, the shallow well region having the second conductivity type; and the body region and the drift region being located in the shallow well region, and the shallow well region being in communication with the deep well region located on a second side sidewall of the drift region.

[0021] Optionally, the method further comprises: forming a first plug in the deep well region and electrically connected with the drain region, and a first isolation layer being between a sidewall of the first plug and the deep well region.

[0022] Optionally, the method further comprises: before forming the first plug, forming a second isolation layer in the deep well region and the drift region, a surface of the second isolation layer being exposed by the deep well region, and a bottom of the second isolation layer being connected with a top of the first isolation layer.

[0023] Optionally, the forming method of the first isolation layer and the second isolation layer comprises: forming a first opening in the deep well region and the drift region; forming an initial isolation layer in the first opening; forming a second opening in the initial isolation layer and the deep well region, the second opening exposing a surface of the drain region, and a bottom of the second opening being lower than a bottom of the initial isolation layer; and filling insulating material in the second opening, the insulating material in the second opening being lower than the bottom of the first opening forming the first isolation layer, and the initial isolation layer in the first opening and the insulating material in a part of the second opening forming the second isolation layer.

[0024] Optionally, the method further comprises: forming a second plug on a surface of the substrate, and the second plug being electrically connected with the source region.

[0025] Optionally, the method further comprises: forming a barrier layer on a surface of the drift region and a side sidewall surface of the gate structure, and one side of the gate structure being located on the drift region; forming a third plug on the barrier layer, and the barrier layer being located between the gate structure and the third plug.

[0026] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0027] The semiconductor structure provided by the technical scheme has the advantages that the deep well region has the adjacent body region and the drift region, and the gate structure is located on the surface of the body region and the surface of the drift region. Since the drain region is located in the deep well region, and the top of the drain region is lower than the bottom of the source region, that is, the size of the drain region along the vertical direction of the substrate surface is large, and the distance between the drain region and the gate structure is large, the increase of the distance between the drain region and the gate structure is beneficial to the improvement of the breakdown voltage, so that the high-voltage resistance of the formed semiconductor structure is improved.

[0028] Further, the deep well region has the shallow well region, the conduction type of the shallow well region is opposite to that of the deep well region, and the shallow well region is in communication with the deep well region located on the sidewall of the second side of the drift region, so that the area where the shallow well region and the deep well region are in contact can form a depletion region, which is beneficial to the improvement of the breakdown voltage of the device, so that the high-voltage resistance of the formed semiconductor structure is further improved.

[0029] Further, the top of the drain region is lower than the bottom of the drift region, that is, the size of the drain region along the vertical direction of the substrate surface is large. Since the depth of the drain region is large, the breakdown voltage is improved, so that when the distance between the drain region and the gate structure in the horizontal direction is reduced, the breakdown voltage of the formed semiconductor structure remains unchanged, so that more devices can be formed in a unit area without reducing the breakdown voltage, and the integration is improved.

[0030] Further, the semiconductor structure further comprises a blocking layer located on the surface of the drift region and the sidewall surface of one side of the gate structure, and one side of the gate structure is located on the drift region; a third plug located on the blocking layer, and the blocking layer is located between the gate structure and the third plug. During the operation of the semiconductor device, the corner where the gate structure and the drift region meet and the drift region have a high electric field. The third plug located on the surface of the blocking layer can redistribute the high electric field near the gate structure and the drift region, so as to reduce the electric field, and further improve the voltage resistance of the formed semiconductor structure.

[0031] Further, the deep well region has a conduction region, the conduction region and the deep well region have the same conduction type, and the second doping concentration of the conduction region is greater than the first doping concentration of the deep well region. When the device is in operation, the conduction resistance of the conduction region located in the deep well region is small when the current flows from the drain region to the source region through the deep well region, so as to improve the conduction current, and further improve the performance of the formed semiconductor structure.

[0032] The forming method of the semiconductor structure provided in the technical scheme has the advantages that the deep well region is formed in the substrate, the drain region is formed in the deep well region, and the top of the drain region is lower than the bottom of the source region, that is, the size of the drain region along the vertical substrate surface direction is large, so that the distance between the drain region and the gate structure is large, and the increased distance between the drain region and the gate structure is beneficial to improve the breakdown voltage, so that the high-voltage resistance of the formed semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a semiconductor structure in an embodiment.

[0034] Figures 2 to 12 is a structural schematic diagram of each step of the forming method of the semiconductor structure in an embodiment. DETAILED DESCRIPTION

[0035] As described in the background, the performance of the existing lateral double diffusion metal oxide semiconductor needs to be improved.

[0036] It should be noted that the "surface", "upper", in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0037] First, the reasons for the poor performance of the existing semiconductor structure are described in detail in combination with the drawings, Figure 1 is a structural schematic diagram of a semiconductor structure in an embodiment.

[0038] Please refer to Figure 1 , the semiconductor structure comprises a substrate 100, the substrate 100 has a drift region 120 and a body region 110, and the conductivity type of the drift region 120 and the conductivity type of the body region 110 are opposite; a gate structure 150 located on the substrate 100, part of the gate structure 150 is located on the drift region 120, and part of the gate structure 150 is located on the body region 110; a blocking layer 160 located on the surface of part of the drift region 120 adjacent to the gate structure 150, and the blocking layer 160 is located on the top surface and the side wall surface of the gate structure 150; a drain region 140 located in the drift region 120 on one side of the blocking layer 160 and the gate structure 150, and a source region 130 located in the body region 110 on one side of the gate structure 150.

[0039] In the above structure, the blocking layer 160 serves to increase the distance between the drain region 140 and the gate structure 110, thereby improving the breakdown voltage of the device.

[0040] However, when the device is turned on, the distance between the drain region and the channel is still close, i.e. the distance between the drain region and the gate structure in the direction parallel to the substrate surface is close, so that the breakdown voltage of the formed device is still low.

[0041] To solve the technical problem, the embodiment of the present application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a deep well region in the substrate, the deep well region has a second conductive type, and the sidewall of the deep well region is in contact with the sidewall of the drift region; a source region in the body region, and the source region has a first conductive type; a drain region in the deep well region, the drain region has the second conductive type, and the bottom of the drain region is lower than the bottom of the drift region, the distance between the drain region with a deep depth and a device on the drift region is large, the device comprises a gate structure, and the increase of the distance between the drain region and the gate structure is beneficial to improve the breakdown voltage, so that the high voltage resistance of the formed semiconductor structure is improved.

[0042] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0043] Figures 2 to 12 is a structural schematic diagram of each step of the forming method of the semiconductor structure in the embodiment of the present application.

[0044] Please refer to Figure 2 , a substrate 200 is provided.

[0045] The material of the substrate 200 comprises silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), and can also comprise silicon on insulator (SOI), germanium on insulator (GOI), or can also be other materials, such as group III-V compound of gallium arsenide, etc. In the embodiment, the material of the substrate 200 is silicon.

[0046] Please continue to refer to Figure 2 , a deep well region 210 is formed in the substrate 200, and the deep well region 210 has a first conductive type.

[0047] In the embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the conductive type of the deep well region 210 is N-type.

[0048] In the embodiment, N-type ions are doped in the substrate 200 through an ion implantation process to form the deep well region 210.

[0049] It should be noted that the substrate 200 exposes the surface of the deep well region 210.

[0050] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the deep well region has a P-type conductivity.

[0051] The N-type ions are one or more of phosphorus ions, arsenic ions and antimony ions; and the P-type ions are one or more of boron ions, indium ions and gallium ions.

[0052] In other embodiments, the method for forming the substrate and the deep well region comprises: providing an initial substrate; forming an initial first deep well region in the initial substrate; forming an initial second deep well region on the surface of the initial substrate by an epitaxial growth process, the initial substrate and the initial second deep well region form the substrate, and the initial first deep well region and the initial second deep well region form the deep well region.

[0053] Referring to Figure 3 A shallow well region 220 is formed in the deep well region 210, and the shallow well region 220 has a second conductivity type.

[0054] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the shallow well region 220 has a P-type conductivity.

[0055] In this embodiment, the shallow well region 220 is formed by doping P-type ions into the substrate 200 by an ion implantation process.

[0056] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the shallow well region has an N-type conductivity.

[0057] Specifically, the ion implantation process for forming the shallow well region 220 has a smaller implantation energy than the ion implantation process for forming the deep well region 210, so that the depth of the shallow well region 220 is smaller than the depth of the deep well region 210.

[0058] In other embodiments, the shallow well region can not be formed.

[0059] Referring to Figure 4 Adjacent drift regions 230 and body regions 240 are formed in the deep well region 210, the body regions 240 have a second conductivity type, the drift regions 230 have a first conductivity type, and the first conductivity type and the second conductivity type are opposite.

[0060] Specifically, in this embodiment, the drift regions 230 and the body regions 240 are formed in the shallow well region 220.

[0061] The drift regions 220 are used to separate the drain region and the channel region formed subsequently, thereby extending the current path of the semiconductor structure and improving the breakdown voltage.

[0062] The body region 230 is used to separate the subsequently formed source region and channel region.

[0063] The method for forming the drift region 230 includes: forming a first mask layer (not shown in the figure) on the surface of the substrate 200, the first mask layer being used to define the position and size of the drift region 230; performing ion implantation process on the substrate 200 with the first mask layer as a mask, so as to form the drift region 230 in the shallow well region 220.

[0064] In the embodiment, the semiconductor structure to be formed is an N-type LDMOS, and N-type ions are doped in the substrate 200 by the ion implantation process, so as to form the drift region 230.

[0065] Specifically, the implantation energy of the ion implantation process for forming the drift region 230 is less than the implantation energy of the ion implantation process for forming the shallow well region 220, so that the depth of the drift region 230 is less than the depth of the shallow well region 220.

[0066] The method for forming the body region 240 includes: forming a second mask layer (not shown in the figure) on the surface of the substrate 200, the second mask layer being used to define the position and size of the body region 240; performing ion implantation process on the substrate 200 with the second mask layer as a mask, so as to form the body region 240 in the shallow well region 220.

[0067] In the embodiment, the semiconductor structure to be formed is an N-type LDMOS, and P-type ions are doped in the substrate 200 by the ion implantation process, so as to form the body region 240.

[0068] Specifically, the implantation energy of the ion implantation process for forming the body region 240 is less than the implantation energy of the ion implantation process for forming the shallow well region 220, so that the depth of the body region 240 is less than the depth of the shallow well region 220.

[0069] Specifically, the drift region 230 includes opposite first side 231 and second side 232; the body region 240 is adjacent to the first side 231 of the drift region 230.

[0070] By forming the shallow well region 220 in the deep well region 210, and the conductive type of the shallow well region 220 being opposite to the conductive type of the deep well region 210, and the shallow well region 220 being in communication with the deep well region 210 located at the sidewall of the second side of the drift region 230, the region where the shallow well region 220 and the deep well region 210 are in contact can form a depletion region A, which is beneficial to improve the breakdown voltage of the device, so as to further improve the high-voltage resistance of the formed semiconductor structure.

[0071] Please refer to Figure 5A gate structure 250 is formed on the surface of the body region 240 and the surface of the drift region 230.

[0072] The forming method of the gate structure 250 includes: forming a gate structure material layer (not shown in the figure) on the substrate 200; forming a patterning layer (not shown in the figure) on the gate structure material layer, the patterning layer covering part of the gate structure material layer on the drift region 230 and part of the gate structure material layer on the body region 240; etching the gate structure material layer with the patterning layer as a mask until the surface of the substrate 200 is exposed, thereby forming the gate structure 250.

[0073] The gate structure 250 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) on the gate dielectric layer.

[0074] In the embodiment, the gate structure 250 further includes a protective layer (not shown in the figure) on the top surface of the gate electrode layer, which is used to protect the top surface of the gate electrode layer and reduce the influence of subsequent processes, thereby improving the performance of the formed semiconductor structure.

[0075] Please continue to refer to Figure 5 A sidewall (not shown in the figure) is formed on the sidewall of the gate structure 250.

[0076] The sidewall is used to protect the sidewall surface of the gate structure 250 from the influence of subsequent processes, thereby maintaining the morphology and improving the stability of the electrical performance; on the other hand, the sidewall is used to position the positions of the source region and the drain region formed subsequently.

[0077] The forming method of the sidewall includes: forming a sidewall material layer (not shown in the figure) on the surface of the substrate 200 and the top surface and the sidewall surface of the gate structure 250; etching back the sidewall material layer until the surface of the substrate 200 and the top surface of the gate electrode layer are exposed, thereby forming the sidewall.

[0078] The material of the sidewall includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride. In the embodiment, the material of the sidewall includes silicon nitride.

[0079] Please refer to Figure 6 A source region 260 is formed in the body region 240, and the source region 260 has the first conductivity type.

[0080] The forming method of the source region 260 includes: performing ion implantation on the body region 240 with the sidewall and the gate structure 250 as a mask, thereby forming the source region 260.

[0081] In the embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the source region 260 is of N-type.

[0082] It should be noted that the substrate 200 exposes the top surface of the source region 260.

[0083] In the embodiment, the semiconductor structure to be formed is a P-type LDMOS, and the source region 260 is of P-type.

[0084] Please refer to Figure 7 The drain region 270 is formed in the deep well region 210, the drain region 270 is of the first conductivity type, and the top of the drain region 270 is lower than the bottom of the source region 260.

[0085] In the embodiment, the top of the drain region 270 is lower than the bottom of the drift region 230.

[0086] The drift region 230 includes opposite first and second sides 231 and 232; the body region 240 is adjacent to the first side 231 of the drift region 230, and the drain region 270 is located in the deep well region 210 on the sidewall of the second side 232 of the drift region 230.

[0087] The method for forming the drain region 270 includes: forming a third mask layer (not shown in the figure) on the substrate 200, the third mask layer exposes the surface of the deep well region 210 on the sidewall of the second side 232 of the drift region 230; taking the third mask layer as a mask, performing ion implantation on the deep well region 210 to form the drain region 270.

[0088] By forming the deep well region 210 in the substrate 200, forming the drain region 270 in the deep well region 210, and the top of the drain region 270 being lower than the bottom of the source region 260, that is, the size of the drain region 270 in the vertical direction of the substrate 200 is large, so that the drain region 270 with large depth is far away from the gate structure 250 formed on the drift region 230, and the distance between the drain region 270 and the gate structure 250 is increased, which is conducive to improving the breakdown voltage, so that the high voltage resistance of the formed semiconductor structure is improved.

[0089] In the embodiment, the source region 260 is formed first, and then the drain region 270 is formed. In other embodiments, the drain region can also be formed before the source region.

[0090] In the embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the source region 260 is of N-type.

[0091] Please refer to Figure 8A conducting region 280 is formed in the deep well region 210, and the conducting region 280 has the first conductivity type.

[0092] In this embodiment, the bottom of the conducting region 280 is higher than the top of the drain region 270.

[0093] In this embodiment, the conducting region 280 has a second doping concentration, the deep well region 270 has a first doping concentration, and the second doping concentration is greater than the first doping concentration.

[0094] The forming method of the conducting region 280 includes: forming a fourth mask layer (not shown in the figure) on the substrate 200, the fourth mask layer exposes the surface of the deep well region 210 on the sidewall of the second side 232 of the drift region 230; taking the fourth mask layer as a mask, ion implantation is performed on the deep well region 210 to form the conducting region 280.

[0095] By forming the conducting region 280 in the deep well region 210, the conducting region 280 and the deep well region 210 have the same conductivity type, and the second doping concentration of the conducting region 280 is greater than the first doping concentration of the deep well region 210. When the device is working, the conducting resistance of the conducting region 280 in the deep well region 210 is small when the current flows from the drain region 270 to the source region 260 through the deep well region 210, thereby facilitating the increase of the conducting current, thereby improving the performance of the formed semiconductor structure.

[0096] In this embodiment, the bottom of the conducting region 280 is higher than the top of the drain region 270.

[0097] In other embodiments, the bottom of the conducting region can also be flush with or lower than the top of the drain region.

[0098] In other embodiments, the conducting region can also not be formed.

[0099] Next, a first isolation layer is formed in the deep well region 210; a second isolation layer is formed in the deep well region 210 and the drift region 230, the deep well region 210 exposes the surface of the second isolation layer, and the bottom of the second isolation layer is connected to the top of the first isolation layer. For the forming process of the first isolation layer and the second isolation layer, please refer to Figures 9 to 10 .

[0100] Please refer to Figure 9 A first opening (not shown in the figure) is formed in the deep well region 210 and the drift region 230; an initial isolation layer 291 is formed in the first opening.

[0101] In this embodiment, after the conducting region 280 is formed, the first opening is formed in the deep well region 210, the drift region 230, and the conducting region 280.

[0102] In the embodiment, the initial isolation layer 291 is also located on the surface of the substrate 200.

[0103] Referring to Figure 10 A second opening (not shown in the figure) exposing the surface of the drain region 270 is formed in the initial isolation layer 291 and the deep well region 210, and the bottom of the second opening is lower than the bottom of the initial isolation layer 291; the second opening is filled with insulating material, and the insulating material in the second opening lower than the bottom of the first opening forms a first isolation layer 2921, and the initial isolation layer 291 in the first opening and the insulating material in the second opening form a second isolation layer 2922.

[0104] The first isolation layer 2921 functions to electrically isolate the sidewall of the first plug formed subsequently and the deep well region 210, so as to apply voltage to the drain region 270 through the first plug.

[0105] The second isolation layer 2922 functions to increase the distance between the drain region 280 and the gate structure 250, so as to increase the path of the working current of the semiconductor structure, thereby improving the breakdown voltage of the semiconductor structure.

[0106] The insulating material includes one or more of a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride.

[0107] In the embodiment, the material of the first isolation layer 2921 is silicon oxide, and the material of the second isolation layer 2922 is silicon oxide.

[0108] In other embodiments, the first isolation layer can be formed first, and then the second isolation layer is formed.

[0109] In other embodiments, the first isolation layer and the second isolation layer can also be formed by conventional means in the art, which are not limited herein.

[0110] Referring to Figure 11 A first plug 310 electrically connected to the drain region 270 is formed in the deep well region 210, and the first plug 310 has the first isolation layer 2921 between the sidewall of the first plug 310 and the deep well region 210.

[0111] The first plug 310 has the first isolation layer 2921 between the sidewall of the first plug 310 and the deep well region 210, so that the first isolation layer 2921 can form an isolation effect between the first plug 310 and the deep well region 210.

[0112] Specifically, in the embodiment, the deep well region 210 has a conducting region 280, and the first plug 310 also penetrates the conducting region 280.

[0113] Specifically, the first plug 310 also penetrates the second isolation layer 2922.

[0114] Please refer to Figure 12 A second plug 320 is formed on the surface of the substrate 200 and is electrically connected to the source region 260.

[0115] The source region 260 is electrically connected to the peripheral circuit through the second plug 320.

[0116] Please continue to refer to Figure 12 A barrier layer 331 is formed on the surface of the drift region 230 and the sidewall surface of one side of the gate structure 250, and one side of the gate structure 250 is located on the drift region 230; a third plug 330 is formed on the barrier layer 331, and the barrier layer 331 is located between the gate structure 250 and the third plug 330.

[0117] In other embodiments, the barrier layer and the third plug located on the barrier layer can also not be formed.

[0118] By forming the barrier layer 331 on the surface of the drift region 230 and the sidewall surface of one side of the gate structure 250, and one side of the gate structure 250 is located on the drift region 230; a third plug 330 is formed on the barrier layer 331, and the barrier layer 331 is located between the gate structure 250 and the third plug 330. When the semiconductor device works, the corner where the gate structure 250 and the drift region 230 intersect and the drift region 230 have a relatively high electric field. By the third plug 330 located on the surface of the barrier layer 331, the third plug 330 can redistribute the relatively high electric field near the gate structure 250 and the drift region 230, thereby reducing the electric field, and further improving the withstand voltage of the formed semiconductor structure.

[0119] In this embodiment, the method for forming the semiconductor structure further includes: forming a fourth plug 340 on the surface of the substrate 200, and the fourth plug 340 is electrically connected to the first plug 310.

[0120] The drain region 270 is electrically connected to the peripheral circuit through the first plug 310 and the fourth plug 340.

[0121] Correspondingly, the embodiment of the present application also provides a semiconductor structure, please continue to refer to Figure 12The system includes: a substrate 200 having a deep well region 210 having a first conductivity type; a drift region 230 and a body region 240 located adjacent to each other within the deep well region 210, the body region 240 having a second conductivity type and the drift region 230 having a first conductivity type, wherein the first conductivity type and the second conductivity type are opposite; a source region 260 located within the body region 240 having a first conductivity type; a drain region 270 located within the deep well region 210 having a first conductivity type, wherein the top of the drain region 270 is lower than the bottom of the source region 260; and a gate structure 250 located on a portion of the surface of the body region 240 and a portion of the surface of the drift region 230.

[0122] The deep well region 210 has adjacent body regions 240 and drift regions 230. The gate structure 250 is located on the surface of the body region 240 and the surface of the drift region 230. Since the drain region 270 is located in the deep well region 210 and the top of the drain region 270 is lower than the bottom of the source region 260, that is, the size of the drain region 270 is large along the direction perpendicular to the surface of the substrate 200. As a result, the distance between the deeper drain region 270 and the gate structure 250 is larger. The increased distance between the drain region 270 and the gate structure 250 is beneficial to improving the breakdown voltage, thereby improving the high voltage resistance of the formed semiconductor structure.

[0123] The following is a detailed description in conjunction with the accompanying drawings.

[0124] Specifically, the drift region 230 includes opposing first sides 231 ( Figure 4 (as shown) and the second side 232 ( Figure 4 (as shown in the diagram); the body region 240 is adjacent to the first side 231 of the drift region 230, and the drain region 270 is located in the deep trap region 210 of the sidewall of the second side 231 of the drift region 230.

[0125] In this embodiment, the substrate 200 further includes: a shallow well region 220 located within a portion of the deep well region 210, the shallow well region 220 having a second conductivity type; the body region 240 and the drift region 230 are located within the shallow well region 220, and the shallow well region 220 is connected to the deep well region 210 located on the sidewall of the second side 232 of the drift region 230.

[0126] Because the deep well region 210 contains a shallow well region 220, and the conductivity type of the shallow well region 220 is opposite to that of the deep well region 210, and the shallow well region 220 is connected to the deep well region 210 located on the second side 232 sidewall of the drift region 230, the region where the shallow well region 210 and the deep well region 220 are in contact can form a depletion region A. Figure 4As shown in the figure, the depletion region A helps to improve the breakdown voltage of the device, thereby further improving the high voltage resistance of the formed semiconductor structure.

[0127] In this embodiment, the top of the leak area 270 is lower than the bottom of the drift area 230.

[0128] The top of the drain region 270 is lower than the bottom of the drift region 230, that is, the size of the drain region 270 is larger in the direction perpendicular to the surface of the substrate 200. Since the drain region 270 is deeper, it is beneficial to improve the breakdown voltage. This allows the breakdown voltage of the semiconductor structure to remain unchanged when the horizontal distance between the drain region 270 and the gate structure 250 is reduced. This enables the formation of more devices per unit area without reducing the breakdown voltage, which is beneficial to improving the integration density.

[0129] In this embodiment, the semiconductor structure further includes a first plug 310 located within the deep well region 210, the first plug 310 being electrically connected to the drain region 270, and a first isolation layer 2921 being provided between the sidewall of the first plug 270 and the deep well region 210.

[0130] The material of the first plug 310 includes: doped polycrystalline silicon or metal, wherein the metal includes one or a combination of copper, tungsten, aluminum, titanium and nickel.

[0131] In this embodiment, the first plug 310 is made of polycrystalline silicon. In other embodiments, the first plug is made of tungsten.

[0132] In this embodiment, the semiconductor structure further includes a second isolation layer 2922 located within the deep well region 210 and the drift region 230, wherein the deep well region 210 exposes the surface of the second isolation layer 2922, and the bottom of the second isolation layer 2922 is connected to the top of the first isolation layer 2921.

[0133] Specifically, the first plug 310 also penetrates the second isolation layer 2922.

[0134] In this embodiment, the semiconductor structure further includes a conductive region 280 located within the deep well region 210, the first plug 310 passing through the conductive region 280, and the conductive region 280 having a first conductivity type.

[0135] Specifically, the bottom of the conductive area 280 is higher than the top of the drain area 270.

[0136] In this embodiment, the deep well region 210 has a first doping concentration, the conducting region 280 has a second doping concentration, and the second doping concentration is greater than the first doping concentration.

[0137] The deep well region 210 has a conducting region 280, the conducting region 280 and the deep well region 210 have the same conductive type, and the conducting region 280 has a second doping concentration greater than the first doping concentration of the deep well region 210. When the device works, the conducting resistance of the conducting region 280 in the deep well region 210 is small when the current flows from the drain region 270 to the source region 260 through the deep well region 210, thereby facilitating the increase of the on-current, and thereby improving the performance of the formed semiconductor structure.

[0138] In the embodiment, the semiconductor structure further comprises a second plug 320 on the surface of the substrate 200, and the second plug 320 is electrically connected with the source region 260.

[0139] In the embodiment, the semiconductor structure further comprises a barrier layer 331 on the surface of the drift region 230 and the sidewall surface of one side of the gate structure 250, and one side of the gate structure 250 is located on the drift region 230; and a third plug 330 on the barrier layer 331, and the barrier layer 331 is located between the gate structure 250 and the third plug 330.

[0140] The semiconductor structure further comprises a barrier layer 331 on the surface of the drift region 230 and the sidewall surface of one side of the gate structure 250, and a third plug 330 on the barrier layer 331. When the semiconductor device works, the corner of the gate structure 250 and the drift region 230 has a high electric field. The third plug 330 on the surface of the barrier layer 331 can redistribute the high electric field near the gate structure 250 and the drift region 230, thereby reducing the electric field, and thereby improving the withstand voltage of the formed semiconductor structure.

[0141] In the embodiment, the semiconductor structure further comprises a fourth plug 340 on the surface of the substrate 200, and the fourth plug 340 is electrically connected with the first plug 310.

[0142] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate having a deep well region therein, the deep well region having a first conductivity type; a drift region and a body region adjacent within the deep well region, the body region having a second conductivity type, the drift region having the first conductivity type, and the first and second conductivity types being opposite; a source region within the body region, and the source region having the first conductivity type; a drain region within the deep well region, the drain region having the first conductivity type, and a top of the drain region being lower than a bottom of the source region; a gate structure on a portion of a surface of the body region and a portion of a surface of the drift region; a shallow well region within a portion of the deep well region, the shallow well region having the second conductivity type; the body region and the drift region being within the shallow well region, and the shallow well region being in communication with the deep well region on a second side of the drift region; the drift region including opposite first and second sides; the body region being adjacent the first side of the drift region, the drain region being within the deep well region on the second side of the drift region; and a top of the drain region being lower than a bottom of the drift region.

2. The semiconductor structure of claim 1, wherein, Further comprising: a first plug within the deep well region, the first plug being in electrical communication with the drain region, and a first isolation layer between a sidewall of the first plug and the deep well region.

3. The semiconductor structure of claim 2, wherein, The first plug material comprising: doped polysilicon or a metal, the metal comprising one or a combination of copper, tungsten, aluminum, titanium, and nickel.

4. The semiconductor structure of claim 2, wherein, Further comprising: a second isolation layer within the deep well region and within the drift region, the deep well region exposing a surface of the second isolation layer, and a bottom of the second isolation layer being in communication with a top of the first isolation layer.

5. The semiconductor structure of claim 2, wherein, Further comprising: a conductive region within the deep well region, the first plug extending through the conductive region, and the conductive region having the first conductivity type.

6. The semiconductor structure of claim 5, wherein, A bottom of the conductive region being higher than a top of the drain region.

7. The semiconductor structure of claim 5, wherein, The deep well region having a first doping concentration, the conductive region having a second doping concentration, and the second doping concentration being greater than the first doping concentration.

8. The semiconductor structure of claim 1, wherein, Further comprising: a second plug on a surface of the substrate, the second plug being in electrical communication with the source region.

9. The semiconductor structure of claim 1, wherein, Further comprising: a barrier layer on a surface of the drift region and on a sidewall surface of a side of the gate structure, and the side of the gate structure being on the drift region; a third plug on the barrier layer, and the barrier layer being between the gate structure and the third plug.

10. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate; forming a deep well region within the substrate, the deep well region having a first conductivity type; forming a drift region and a body region adjacent within the deep well region, the body region having a second conductivity type, the drift region having the first conductivity type, and the first and second conductivity types being opposite; forming a source region within the body region, and the source region having the first conductivity type; forming a drain region within the deep well region, the drain region having the first conductivity type, and a top of the drain region being lower than a bottom of the source region; forming a gate structure on a portion of a surface of the body region and a portion of a surface of the drift region; forming a shallow well region within a portion of the deep well region, the shallow well region having the second conductivity type; the body region and the drift region being within the shallow well region, and the shallow well region being in communication with the deep well region on a second sidewall of the drift region; The body region is adjacent to a first side of the drift region, and the drain region is located in the deep well region on a second side of the drift region; a top of the drain region is lower than a bottom of the drift region.

11. The method of forming a semiconductor structure of claim 10, wherein Further comprising: A first plug is formed in the deep well region and electrically connected to the drain region, and a first isolation layer is formed between a sidewall of the first plug and the deep well region.

12. The method of forming a semiconductor structure of claim 11, wherein, Further comprising: A second isolation layer is formed in the deep well region and the drift region before the first plug is formed, the deep well region exposes a surface of the second isolation layer, and a bottom of the second isolation layer is connected to a top of the first isolation layer.

13. The method of forming a semiconductor structure of claim 12, wherein, The forming method of the first isolation layer and the second isolation layer comprises: forming a first opening in the deep well region and the drift region; forming an initial isolation layer in the first opening; forming a second opening in the initial isolation layer and the deep well region to expose a surface of the drain region, a bottom of the second opening is lower than a bottom of the initial isolation layer; filling insulating material in the second opening, the insulating material in the second opening lower than the bottom of the first opening forms the first isolation layer, and the initial isolation layer in the first opening and the insulating material in part of the second opening form the second isolation layer.

14. The method of forming a semiconductor structure of claim 10, wherein, Further comprising: A second plug is formed on the surface of the substrate, and the second plug is electrically connected to the source region.

15. The method of forming a semiconductor structure of claim 10, wherein, Further comprising: A barrier layer is formed on a surface of the drift region and a sidewall surface of one side of the gate structure, and one side of the gate structure is located on the drift region; A third plug is formed in the barrier layer, and the barrier layer is located between the gate structure and the third plug. Further comprising: A barrier layer is formed on a surface of the drift region and a sidewall surface of one side of the gate structure, and one side of the gate structure is located on the drift region; A third plug is formed in the barrier layer, and the barrier layer is located between the gate structure and the third plug.

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