Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

Description

Semiconductor structure manufacturing methods and semiconductor structures Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] With the continuous development of semiconductor technology, the size of complementary metal-oxide-semiconductor (CMOS) devices continues to shrink, and the requirements for device performance are also increasing. In high-kJ metal gate (HKMG) processes, improving the performance of PMOS (P-type metal-oxide-semiconductor) devices has become one of the key technical challenges. To improve the hole mobility and drive current of PMOS devices, the industry generally adopts a technique of forming germanium-silicon epitaxial layers in the source and drain regions of PMOS devices. This technique is achieved by pre-forming sigma trenches of a specific shape in the substrate and then selectively epitaxially growing silicon germanide (SiGe) in them. However, the existing process for forming sigma trenches usually requires the introduction of an additional photoresist layer as a mask: this photoresist layer covers the NMOS device region and only opens in the PMOS device region, thereby achieving selective etching of the PMOS region. This additional photolithography step not only increases the process complexity and manufacturing cost, but more importantly, during the etching process to form sigma trenches, the dummy gate structure of the PMOS device region is significantly damaged by the etching process, resulting in the dummy gate height of the PMOS device being lower than that of the NMOS device. This height difference poses a serious challenge to the subsequent High-kMetal Electrode Etch Back (HMEB) step, affecting etching uniformity and process control, and consequently reducing device yield and reliability. Summary of the Invention

[0003] In view of the above problems, the purpose of this application is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, which aims to eliminate the height difference between the pseudo gate in the PMOS device region and the pseudo gate in the NMOS device region, improve device yield and reliability, and reduce process complexity and manufacturing cost.

[0004] According to a first aspect of the present application, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, the substrate including an NMOS device region and a PMOS device region; forming a high-dielectric-constant dielectric layer over the substrate covering the NMOS device region and the PMOS device region; forming a gate stack structure over the high-dielectric-constant dielectric layer, the gate stack structure being located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer in the PMOS device region covered by the gate stack structure; and after forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundaries of sigma trenches, using the patterned high-dielectric-constant dielectric layer as a mask, forming sigma trenches between the isolation sidewalls of the gate stack structure in the PMOS device region using an etching process.

[0005] Optionally, after forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundary of the sigma trench, forming the sigma trench between the isolation sidewalls of the gate stack structure in the PMOS device region using an etching process with the patterned high-dielectric-constant dielectric layer as a mask includes: using a dry etching process to etch the substrate in the NMOS device region and PMOS device region with the patterned high-dielectric-constant dielectric layer as a mask to form a pre-existing trench between the isolation sidewalls of the gate stack structure in the PMOS device region; and using a wet etching process to etch the substrate in the NMOS device region and PMOS device region with the patterned high-dielectric-constant dielectric layer as a mask to widen the pre-existing trench to form the sigma trench.

[0006] Optionally, during the formation of the sigma trench, the top surface of the gate stack structure in the NMOS device region and the PMOS device region is simultaneously etched.

[0007] Optionally, forming a gate stack structure above the high-dielectric-constant dielectric layer, the gate stack structure being located in the NMOS device region and the PMOS device region, includes: sequentially depositing a gate conductor layer, a gate insulating layer, and a top protective layer above the high-dielectric-constant dielectric layer, the gate conductor layer, the gate insulating layer, and the top protective layer covering the surface of the high-dielectric-constant dielectric layer; forming a photoresist layer above the location where the top protective layer is expected to form the gate stack structure; using the photoresist layer as a mask, patterning the top protective layer, the gate insulating layer, and the gate conductor layer using an etching process to form the gate stack structure, wherein the etching process stops on the surface of the high-dielectric-constant dielectric layer, and the gate stack structure includes a stacked structure formed by layering the patterned gate conductor layer, the gate insulating layer, and the top protective layer.

[0008] Optionally, forming a high-dielectric-constant dielectric layer covering the NMOS device region and the PMOS device region on the substrate includes: forming a gate oxide layer covering the NMOS device region and the PMOS device region on the substrate; and forming a high-dielectric-constant dielectric layer covering the gate oxide layer on the substrate.

[0009] Optionally, patterning the high-dielectric-constant dielectric layer to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region includes: forming a photoresist layer above the gate stack structure in the NMOS device region and the PMOS device region; using the photoresist layer as a mask, using an etching process to remove the uncovered high-dielectric-constant dielectric layer and gate oxide layer, thus retaining the high-dielectric-constant dielectric layer and gate oxide layer in the NMOS device region, and the high-dielectric-constant dielectric layer and gate oxide layer covered by the gate stack structure in the PMOS device region.

[0010] Optionally, after patterning the high-dielectric-constant dielectric layer to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region, the manufacturing method further includes: forming an isolation sidewall on the sidewall of the gate stack structure; in the PMOS device region, the isolation sidewall covers the sidewall of the gate stack structure and the exposed sidewall of the high-dielectric-constant dielectric layer and the gate oxide layer; in the NMOS device region, the isolation sidewall covers the sidewall of the gate stack structure; the dummy gate includes the gate stack structure and the isolation sidewall; and sequentially forming a functional layer and a surface protection layer above the dummy gate in the NMOS device region and the PMOS device region, the functional layer and the surface protection layer covering the dummy gate in the NMOS device region and the PMOS device region, as well as the exposed substrate, the gate oxide layer and the high-dielectric-constant dielectric layer.

[0011] Optionally, during the formation of the sigma trench, the functional layer and the surface protection layer above the dummy gate in the NMOS device region and the PMOS device region are simultaneously etched.

[0012] Optionally, the material of the high dielectric constant dielectric layer includes hafnium oxide, zirconium oxide, or aluminum oxide.

[0013] According to a second aspect of the embodiments of this application, a semiconductor structure is provided, which is manufactured according to the manufacturing method described above.

[0014] The unexpected technical effect of this application is as follows: A substrate is provided, which includes an NMOS device region and a PMOS device region. A high-dielectric-constant dielectric layer is formed on the substrate, covering the NMOS device region and the PMOS device region. A gate stack structure is formed on the high-dielectric-constant dielectric layer, which is located in the NMOS device region and the PMOS device region. The high-dielectric-constant dielectric layer is patterned to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region. After forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundary of the sigma trench, the patterned high-dielectric-constant dielectric layer is used as a mask, and an etching process is used to form sigma trenches between the isolation sidewalls of the gate stack structure in the PMOS device region. In this way, by selectively retaining the high-dielectric-constant dielectric layer (HIK) in the NMOS device region during the pseudo-gate formation stage and using it as a natural etching barrier layer, this application ingeniously achieves region-selective control of the sigma trench etching process. This high-dielectric-constant dielectric layer continuously covers the area beneath and around the gate stack in the NMOS region. During the subsequent etching process to form sigma trenches, it acts as a self-aligned mask, ensuring that sigma trenches are formed only in the substrate of the PMOS device region. Since this layer is part of the existing gate dielectric structure and is patterned in a single photolithography and etching step, it eliminates the need for additional photoresist coating and separate photomask alignment and exposure before sigma trench etching, as is required in traditional processes. This directly eliminates the need for the pseudo-gate etch-back (PREB) photomask process used to protect the NMOS region, significantly reducing the number of photolithography steps. This design not only avoids the risks of alignment deviations, pattern distortion, and process fluctuations introduced by additional photomasks but also simplifies the overall process, reduces material consumption and equipment downtime, saves at least one critical photomask, and reduces process complexity and manufacturing costs.

[0015] Furthermore, the high-dielectric-constant dielectric layer is patterned to preserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region. Isolation sidewalls are formed on the sidewalls of the gate stack structure in the NMOS and PMOS device regions. During the formation of the sigma trench, the top surface of the gate stack structure in the NMOS and PMOS device regions is etched simultaneously. In this way, since the pseudo-gate structures in the NMOS and PMOS device regions undergo synchronous processing in the same etching environment, and the NMOS region exhibits a higher etching selectivity due to the presence of the high-dielectric-constant dielectric layer, the sigma trench etching process effectively suppresses damage to areas outside the gate stack structure in the NMOS device region. Placing the gate stack structure in the NMOS and PMOS device regions in the same etching environment for synchronous processing ensures that both maintain a high degree of consistency in etching rate and surface morphology. This consistency provides a uniform structural basis for subsequent key steps such as pseudo-gate removal, high-dielectric-constant metal gate deposition, and high-etch-back (HMEB), improving device yield and reliability. Attached Figure Description

[0016] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings, in which: Figures 1A-1D show cross-sectional schematic diagrams of different stages of forming germanium-silicon trenches in the related art; Figure 2 shows a flowchart of an exemplary semiconductor structure manufacturing method according to an embodiment of this application; Figures 3A-3E show cross-sectional schematic diagrams of different stages of an exemplary semiconductor structure manufacturing method according to an embodiment of this application.

[0017] Explanation of reference numerals in the attached figures: 110-substrate; 111-isolation structure; 121-gate oxide layer; 122-high dielectric constant dielectric layer; 123-functional layer; 124-surface protective layer; 130-dummy gate; 131-gate conductor layer; 132-gate insulating layer; 133-top protective layer; 134-isolation sidewall; 141-first photoresist layer; 142-second photoresist layer; 151-sigma trench. Detailed Implementation

[0018] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0019] This application may be presented in various forms, some of which will be described below.

[0020] It should be noted that, for ease of illustration, some film layers are omitted in the accompanying drawings of this application. The spacing and line width in the drawings are used to illustrate the corresponding components and the relative positional relationship between components; the actual spacing and line width shall conform to the process specifications.

[0021] In germanium-silicon epitaxy, after the NMOS device is covered by a photoresist layer, germanium-silicon trenches are formed only in the substrate of the PMOS device. This increases the compressive stress on the PMOS device and improves its drive current. Figures 1A-1D show cross-sectional schematic diagrams of different stages of germanium-silicon trench formation in related technologies. The following section provides a detailed introduction to existing technologies for forming germanium-silicon trenches, referring to Figures 1A-1D.

[0022] As shown in Figure 1A, the substrate 110 includes an NMOS device region and a PMOS device region. An isolation structure 111 extends inward from the surface of the substrate 110, separating the NMOS device region and the PMOS device region. After forming the NMOS device region, the PMOS device region, and the isolation structure 111, a gate oxide layer 121 and a high-dielectric-constant dielectric layer 122 are sequentially deposited on the substrate 110. The gate oxide layer 121 can be made of silicon dioxide (SiO2) and formed on the surface of the substrate 110 through a thermal oxidation process. The high-dielectric-constant dielectric layer 122 can be made of materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or aluminum oxide (Al2O3) and deposited on the gate oxide layer 121 through an atomic layer deposition (ALD) process.

[0023] As shown in Figure 1B, a gate conductor layer 131, a gate insulating layer 132, and a top protective layer 133 are sequentially deposited on the NMOS device region and the PMOS device region. The gate conductor layer 131, gate insulating layer 132, and top protective layer 133 are located above the high-dielectric-constant dielectric layer 122, covering the surface of the high-dielectric-constant dielectric layer 122. A photoresist layer (not shown) is formed above the location where the top protective layer 133 is expected to form the gate stack structure. Using this photoresist layer as a mask, an etching process is used to pattern the gate oxide layer 121, the high-dielectric-constant dielectric layer 122, the gate conductor layer 131, the gate insulating layer 132, and the top protective layer 133 to form the gate stack structure. The photoresist layer is then removed. The gate stack structure comprises a stacked structure formed by layering the gate conductor layer 131, the gate insulating layer 132, and the top protective layer 133. After etching, the gate oxide layer 121 and the high dielectric constant dielectric layer 122 are located only in the area directly below the gate stack structure, and the remaining areas are removed to expose the surface of the substrate 110.

[0024] As shown in Figure 1C, isolation sidewalls 134 are formed on the sidewalls of the gate stack structure in the NMOS and PMOS device regions. The dummy gate 130 includes the gate stack structure and the isolation sidewalls 134. In some embodiments, a functional layer 123 and a surface protection layer 124 are sequentially formed above the dummy gate 130 in the NMOS and PMOS device regions. The functional layer 123 and the surface protection layer 124 cover the dummy gate 130, the exposed substrate 110 surface, and the sidewalls of the exposed gate oxide layer 121 and high-dielectric-constant dielectric layer 122 in the NMOS and PMOS device regions. The top protection layer 133 and the isolation sidewalls 134 together protect the gate conductor layer 131 and the gate insulating layer 132. Combined with the protective effect of the surface protection layer 124, this further ensures that the gate conductor layer 131 and the gate insulating layer 132 are not damaged during the formation of the germanium-silicon trench. The gate conductor layer 131 can be made of polysilicon, the gate insulating layer 132 can be made of silicon nitride, the top protective layer 133 can be made of silicon oxide, and the isolation sidewall 134 can be made of silicon nitride.

[0025] As shown in Figure 1D, a first photoresist layer 141 is formed in the NMOS device region, covering the dummy gate 130 and the surface protection layer 124 above the substrate 110 in the NMOS device region. Simultaneously, an opening is formed in the PMOS device region to expose the dummy gate 130 and the surface protection layer 124 above the substrate 110. Subsequently, using the first photoresist layer 141 as a mask, and with the isolation sidewalls of the dummy gate 130 defining the boundaries of the sigma trench, a sigma trench 151 is formed between the isolation sidewalls 134 of the dummy gate 130 in the PMOS device region using an etching process. During the etching process of the sigma trench 151, only the substrate 110 of the PMOS device region is exposed to the etching atmosphere and etched, thereby forming a sigma trench 151 structure with a specific depth and morphology in the substrate 110. It should be noted that only one sigma trench 151 is shown in Figure 1D as an example. It should be understood that in practice, sigma trench 151 structures can be formed on both sides of each dummy gate 130 in the PMOS device region. Since the dummy gate 130 in the PMOS device region is exposed to the etching atmosphere, its surface protective layer 124, functional layer 123, and top protective layer 133 may be etched simultaneously during the etching process. However, the dummy gate 130 in the NMOS device region, covered by the first photoresist layer 141, retains its surface protective layer 124, functional layer 123, and top protective layer 133, avoiding etching damage. This results in a significant difference in the dummy gate 130 between the PMOS and NMOS device regions, affecting the subsequent replacement process of the high-dielectric metal gate and the uniformity of device performance.

[0026] Based on this, this application proposes a semiconductor structure manufacturing method and semiconductor structure to eliminate the height difference between the dummy gate 130 of the PMOS device region and the NMOS device region, improve device yield and reliability, and reduce process complexity and manufacturing cost.

[0027] Figure 2 is a flowchart illustrating an exemplary semiconductor structure manufacturing method according to an embodiment of this application. Figures 3A-3E are cross-sectional views of different stages of an exemplary semiconductor structure manufacturing method according to an embodiment of this application. The manufacturing process of the germanium-silicon trench according to an embodiment of this application will be described in detail below with reference to Figures 2 and 3A-3E. As shown in Figure 2, the semiconductor structure manufacturing method according to an embodiment of this application includes:

[0028] In step S210, a substrate is provided, the substrate including an NMOS device region and a PMOS device region.

[0029] In step S220, a high dielectric constant dielectric layer is formed over the substrate, covering the NMOS device region and the PMOS device region.

[0030] In steps S210 and S220, in some embodiments, as shown in FIG3A, a substrate 110 is provided. The substrate 110 may be a silicon substrate, a germanium-silicon substrate, or a silicon-on-insulator substrate, wherein an isolation structure 111 is formed extending inward from the surface of the substrate 110, such as a shallow trench isolation structure (STI) or a localized silicon oxide isolation structure (LOCOS). The isolation structure 111 divides the substrate 110 into an NMOS device region and a PMOS device region. After forming the isolation structure 111, a gate oxide layer 121 and a high-dielectric-constant dielectric layer 122 are sequentially deposited on the substrate 110. The gate oxide layer 121 and the high-dielectric-constant dielectric layer 122 cover the surface of the substrate 110. The gate oxide layer 121 may be made of silicon dioxide (SiO2) material and is formed on the surface of the substrate 110 by a thermal oxidation process. The high dielectric constant dielectric layer 122 can be made of materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2) or aluminum oxide (Al2O3) and deposited on the gate oxide layer 121 by atomic layer deposition (ALD) process.

[0031] In step S230, a gate stack structure is formed above the high dielectric constant dielectric layer, the gate stack structure being located in the NMOS device region and the PMOS device region.

[0032] In some embodiments, as shown in FIG3B, a gate conductor layer 131, a gate insulating layer 132, and a top protective layer 133 are sequentially deposited over a high-dielectric-constant dielectric layer 122 in the NMOS device region and the PMOS device region. The gate conductor layer 131, the gate insulating layer 132, and the top protective layer 133 cover the surface of the high-dielectric-constant dielectric layer 122. A photoresist layer (not shown) is formed above the location where the top protective layer 133 is expected to form a gate stack structure. Using this photoresist layer as a mask, an etching process is used to pattern the gate oxide layer 121, the high-dielectric-constant dielectric layer 122, and the gate conductor layer 131 to form a gate stack structure. Subsequently, the photoresist layer is removed. The gate stack structure includes a stacked structure formed by layering the gate conductor layer 131, the gate insulating layer 132, and the top protective layer 133. The etching process stops at the surface of the high-dielectric-constant dielectric layer 122. After the etching process, the gate oxide layer 121 and the high-dielectric-constant dielectric layer 122 cover the surface of the substrate 110. The gate conductor layer 131 can be made of polysilicon or metal and is formed by chemical vapor deposition. The gate insulating layer 132 can be silicon nitride or silicon oxide and is used to isolate the gate conductor layer from the top protective layer. The top protective layer 133 is typically made of silicon nitride to protect the gate stack structure from damage in subsequent processes. The gate stack structure defines the gate regions of the NMOS device region and the PMOS device region.

[0033] In step S240, the high dielectric constant layer is patterned to retain the high dielectric constant layer in the NMOS device region and the high dielectric constant layer in the PMOS device region covered by the gate stack structure.

[0034] In some embodiments, as shown in FIG3C, a second photoresist layer 142 is deposited in the NMOS device region and the PMOS device region. The photoresist layer is patterned by photolithography to cover the top surface of the gate stack structure in the NMOS device region and the PMOS device region. As shown in FIG3D, the high dielectric constant layer 122 and the gate oxide layer 121 are then etched in the area not covered by the second photoresist layer 142 as the exposed area to remove the portion of the high dielectric constant layer and the portion of the gate oxide layer not covered by the gate stack structure in the PMOS device region. After that, the second photoresist layer 142 is removed, thus completing the selective retention of the high dielectric constant layer 122 and the gate oxide layer 121. During the selective etching of the high dielectric constant dielectric layer 122 and the gate oxide layer 121, the second photoresist layer 142 covering the gate stack structure of the PMOS device region plays a protective role, preventing the gate stack structure from being damaged by etching, and ensuring that the high dielectric constant dielectric layer 122 and the gate oxide layer 121 are only retained below the gate stack structure of the NMOS device region and the PMOS device region.

[0035] It should be noted that, in some embodiments, the second photoresist layer 142 can also be patterned by photolithography so that it only covers the NMOS device region while forming an opening in the PMOS device region to expose the PMOS device region. Then, using the patterned second photoresist layer 142 as a mask, the high dielectric constant layer 122 and the gate oxide layer 121 in the exposed region are etched to remove the unprotected high dielectric constant layer portion and the gate oxide layer portion in the PMOS device region. After that, the second photoresist layer 142 is removed, thus completing the selective retention of the high dielectric constant layer 122 and the gate oxide layer 121, thereby retaining only the high dielectric constant layer 122 and the gate oxide layer 121 in the NMOS device region and the portion of the high dielectric constant layer 122 and the portion of the gate oxide layer 121 covered by the gate stack structure in the PMOS device region. However, during the selective etching of the high dielectric constant dielectric layer 122 and the gate oxide layer 121, the gate stack structure of the PMOS device region is not protected by the second photoresist layer 142, and the top protective layer 133 of the gate stack structure will be etched to some extent.

[0036] In step S250, after forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundaries of the sigma trenches, using the patterned high dielectric constant dielectric layer as a mask, sigma trenches are formed between the isolation sidewalls of the gate stack structure in the PMOS device region using an etching process.

[0037] In some embodiments, as shown in FIG3D, isolation sidewalls 134 are formed on the sidewalls of the gate stack structure in the NMOS device region and the PMOS device region. In the PMOS device region, the isolation sidewalls 134 cover the sidewalls of the gate stack structure and the exposed sidewalls of the high-dielectric-constant dielectric layer 122 and the gate oxide layer 121. In the NMOS device region, the isolation sidewalls 134 cover the sidewalls of the gate stack structure. The dummy gate 130 includes the gate stack structure and the isolation sidewalls 134. The isolation sidewalls of the dummy gate 130 define the boundary of the sigma trench. In some embodiments, a functional layer 123 and a surface protection layer 124 are also sequentially formed above the dummy gate 130 in the NMOS device region and the PMOS device region. The functional layer 123 and the surface protection layer 124 cover the dummy gate 130 in the NMOS device region and the PMOS device region, as well as the exposed substrate 110, the gate oxide layer 121, and the high-dielectric-constant dielectric layer 122. The top protective layer 133 and the isolation sidewall 134 together protect the gate conductor layer 131 and the gate insulating layer 132. Combined with the protective effect of the surface protective layer 124, this further ensures that the gate conductor layer 131 and the gate insulating layer 132 are not damaged during the formation of the germanium-silicon trench. The gate conductor layer 131 can be made of polysilicon, the gate insulating layer 132 can be made of silicon nitride, the top protective layer 133 can be made of silicon oxide, and the isolation sidewall 134 can be made of silicon nitride. In some embodiments, after forming the isolation sidewall 134, an ion implantation process is used to form the source and drain regions (not shown in the figure) within the substrate of the PMOS device region.

[0038] In some embodiments, as shown in FIG3E, an anisotropic dry etching process is used to etch the substrate in the NMOS device region and PMOS device region using a patterned high-dielectric-constant dielectric layer 122 as a mask, forming a pre-existing trench between the isolation sidewalls 134 of the gate stack structure in the PMOS device region. A wet etching process is then used to etch the substrate in the NMOS device region and PMOS device region using a patterned high-dielectric-constant dielectric layer 122 as a mask, widening the pre-existing trench to form a sigma trench 151. It should be noted that FIG3E only shows one sigma trench 151 as an example; it should be understood that in practice, sigma trench 151 structures can be formed on both sides of each dummy gate 130 in the PMOS device region.

[0039] It is understandable that the high dielectric constant layer 122 is patterned to retain the high dielectric constant layer 122 in the NMOS device region and the high dielectric constant layer 122 covered by the gate stack structure in the PMOS device region. Isolation sidewalls are formed on the sidewalls of the gate stack structure in the NMOS device region and the PMOS device region. In the process of forming the sigma trench 151 in the NMOS device region and the PMOS device region using the patterned high dielectric constant layer 122 as a mask and the etching process, the top surface of the gate stack structure in the NMOS device region and the PMOS device region (i.e., the surface protection layer 124, the functional layer 123 and the top protection layer 133) will be etched simultaneously. Since the dummy gate structures of the NMOS and PMOS device regions undergo synchronous processing in the same etching environment, and the NMOS region exhibits a higher etching selectivity due to the presence of the high dielectric constant dielectric layer 122, the etching process of the sigma trench 151 effectively suppresses the damage to the area outside the gate stack structure in the NMOS device region. By placing the gate stack structures in the NMOS and PMOS device regions in the same etching environment for synchronous processing, it is ensured that the two maintain a high degree of consistency in etching rate and surface morphology. This consistency provides a uniform structural basis for subsequent key steps such as dummy gate removal, high dielectric constant metal gate deposition, and etch-back (HMEB), thereby improving device yield and reliability.

[0040] In some embodiments, a silicon germanium layer is selectively epitaxially grown in the sigma trench 151 shown in FIG. 3E, thereby completing the formation process of the silicon germanium trench. Subsequently, a wet etching process is used to remove the high-dielectric-constant dielectric layer 122 outside the gate stack structure and the isolation sidewall 134 of the gate stack structure in the NMOS device region. During the removal of the high-dielectric-constant dielectric layer 122 outside the isolation sidewall of the gate stack structure in the NMOS device region, the gate stack structures in the NMOS and PMOS device regions are processed synchronously in the same etching environment, and the top surfaces (i.e., surface protection layer 124, functional layer 123, and top protection layer 133) of the gate stack structures in the NMOS and PMOS device regions are etched simultaneously. This further ensures a reduction in the difference in dummy gate height between the NMOS and PMOS device regions.

[0041] Understandably, by selectively retaining the high-dielectric-constant dielectric layer (HIK) in the NMOS device region during the dummy gate formation stage and using it as a natural etch barrier layer, this application ingeniously achieves region-selective control of the sigma trench etching process. This high-dielectric-constant dielectric layer 122 continuously covers the exposed area below and around the gate stack structure in the NMOS region. During the subsequent etching process to form the sigma trench 151, it acts as a self-aligned mask, ensuring that the sigma trench is formed only in the substrate of the PMOS device region. Since this layer is part of the existing gate dielectric structure and is patterned in a single photolithography and etching step, it eliminates the need for additional photoresist coating and independent photomask alignment exposure before sigma trench etching, as is required in conventional processes. Therefore, the dummy gate etch back (PREB) photomask process used to protect the NMOS region is directly eliminated, significantly reducing the number of photolithography steps. This design not only avoids risks such as alignment deviations, pattern distortions, and process fluctuations introduced by additional photomasks, but also simplifies the overall process, reduces material consumption and equipment downtime, saves at least one critical photomask, and reduces process complexity and manufacturing costs.

[0042] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, the substrate comprising an NMOS device region and a PMOS device region; A high-dielectric-constant dielectric layer is formed over the substrate, covering the NMOS device region and the PMOS device region; A gate stack structure is formed above the high dielectric constant layer, the gate stack structure being located in the NMOS device region and the PMOS device region; the high dielectric constant layer is patterned to retain the high dielectric constant layer in the NMOS device region and the high dielectric constant layer in the PMOS device region covered by the gate stack structure; After forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundaries of the sigma trenches, using the patterned high-dielectric-constant dielectric layer as a mask, sigma trenches are formed between the isolation sidewalls of the gate stack structure in the PMOS device region using an etching process.

2. The manufacturing method according to claim 1, wherein, After forming isolation sidewalls on the sidewalls of the gate stack structure to define the boundaries of the sigma trench, the sigma trench is formed between the isolation sidewalls of the gate stack structure in the PMOS device region using an etching process with a patterned high-dielectric-constant dielectric layer as a mask. This includes: using a dry etching process to etch the substrate in the NMOS and PMOS device regions with a patterned high-dielectric-constant dielectric layer as a mask to form a pre-existing trench between the isolation sidewalls of the gate stack structure in the PMOS device region; and using a wet etching process to etch the substrate in the NMOS and PMOS device regions with a patterned high-dielectric-constant dielectric layer as a mask to widen the pre-existing trench to form the sigma trench.

3. The manufacturing method according to claim 2, wherein, During the formation of the sigma trench, the top surface of the gate stack structure in the NMOS device region and the PMOS device region is simultaneously etched.

4. The manufacturing method according to claim 1, wherein, The method of forming a gate stack structure above the high-dielectric-constant dielectric layer, the gate stack structure being located in the NMOS device region and the PMOS device region, includes: sequentially depositing a gate conductor layer, a gate insulating layer, and a top protective layer above the high-dielectric-constant dielectric layer, the gate conductor layer, the gate insulating layer, and the top protective layer covering the surface of the high-dielectric-constant dielectric layer; forming a photoresist layer above the location where the top protective layer is expected to form the gate stack structure; using the photoresist layer as a mask, patterning the top protective layer, the gate insulating layer, and the gate conductor layer using an etching process to form the gate stack structure, wherein the etching process stops on the surface of the high-dielectric-constant dielectric layer; the gate stack structure comprising a stacked structure formed by layering the patterned gate conductor layer, the gate insulating layer, and the top protective layer.

5. The manufacturing method according to claim 1, wherein, The step of forming a high-dielectric-constant dielectric layer covering the NMOS device region and the PMOS device region on the substrate includes: forming a gate oxide layer covering the NMOS device region and the PMOS device region on the substrate; and forming a high-dielectric-constant dielectric layer covering the gate oxide layer on the substrate.

6. The manufacturing method according to claim 5, wherein, The step of patterning the high-dielectric-constant dielectric layer to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region includes: forming a photoresist layer above the gate stack structure in the NMOS device region and the PMOS device region; using the photoresist layer as a mask, using an etching process to remove the uncovered high-dielectric-constant dielectric layer and gate oxide layer, thus retaining the high-dielectric-constant dielectric layer and gate oxide layer in the NMOS device region and the high-dielectric-constant dielectric layer and gate oxide layer covered by the gate stack structure in the PMOS device region.

7. The manufacturing method according to claim 6, wherein, After patterning the high-dielectric-constant dielectric layer to retain the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region, the manufacturing method further includes: forming an isolation sidewall on the sidewall of the gate stack structure; in the PMOS device region, the isolation sidewall covers the sidewall of the gate stack structure and the exposed sidewall of the high-dielectric-constant dielectric layer and the gate oxide layer; in the NMOS device region, the isolation sidewall covers the sidewall of the gate stack structure; the dummy gate includes the gate stack structure and the isolation sidewall; and a functional layer and a surface protection layer are sequentially formed above the dummy gate in the NMOS device region and the PMOS device region, the functional layer and the surface protection layer covering the dummy gate in the NMOS device region and the PMOS device region, as well as the exposed substrate, the gate oxide layer and the high-dielectric-constant dielectric layer.

8. The manufacturing method according to claim 7, wherein, During the formation of the sigma trench, the functional layer and the surface protection layer above the dummy gate in the NMOS device region and PMOS device region are simultaneously etched.

9. The manufacturing method according to claim 1, wherein, The high dielectric constant dielectric layer is made of materials including hafnium oxide, zirconium oxide, or aluminum oxide.

10. A semiconductor structure, said semiconductor structure being manufactured according to the manufacturing method according to any one of claims 1 to 9.

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