A vertical power device, a manufacturing method thereof and a chip

Abstract

The application belongs to the technical field of semiconductors, and provides a vertical power device, which comprises a substrate, a buffer layer, a first insulating layer and a second insulating layer, a first metal layer, a second metal layer, a first contact layer, a second contact layer and a third contact layer, the first contact layer is a first type of metal, the third contact layer is in contact with the buffer layer in the first type, and the third contact layer, the first contact layer and the second contact layer are the first type of metal, so that the technical problem of high manufacturing cost of the semiconductor device in the prior art is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a vertical power device and its fabrication method and chip. Background Technology

[0002] Since the process of gallium nitride high electron mobility transistors (GaN HEMTs) requires the epitaxial growth of AlGaN and GaN layers on the substrate at the beginning of the process, many planar designs of gallium nitride high electron mobility transistors compatible with GaN HEMT processes have emerged. In order to obtain a high-voltage planar diode, a larger area is required. In order to save area, quasi-vertical and vertical gallium nitride high electron mobility transistors have been proposed.

[0003] Because gallium nitride (GaN) often uses non-GaN substrates for cost reasons, quasi-vertical GaN high electron mobility transistors (HEP transistors) have become the primary choice. Photomasks, or photomasks, are an essential step in semiconductor manufacturing. The process of using a photomask involves: after each thin film is formed on the substrate, a photoresist layer is first applied to define the pattern of that film. Then, the photoresist layer with the photomask pattern is applied, followed by etching of the areas of the film not covered by the photoresist. Finally, the photoresist layer is peeled off, forming a thin film with a specific pattern. This is the complete process of one photomask step. Traditional photomasks consist of a quartz substrate and a chromium metal layer covering it, with the photomask pattern formed on the chromium metal layer. One photomask can only manufacture a specific thin film on the substrate, resulting in higher manufacturing costs for semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a vertical power device and its fabrication method and chip, which can solve the technical problem that quasi-vertical diodes in the prior art require higher costs to obtain high withstand voltage characteristics.

[0005] A first aspect of this invention provides a vertical power device, the vertical power device comprising:

[0006] Substrate;

[0007] A buffer layer is disposed on the substrate;

[0008] A first insulating layer is disposed on the buffer layer and located on the first side of the buffer layer, wherein the first insulating layer has a through hole;

[0009] A second insulating layer is disposed on the buffer layer and located on the second side of the buffer layer, wherein the second insulating layer has through holes;

[0010] A first metal layer is disposed in a through-hole of the first insulating layer and is in contact with the buffer layer;

[0011] The second metal layer is disposed in the through-hole of the second insulating layer and is in contact with the buffer layer;

[0012] A first contact layer, wherein the first contact layer is in contact with the first metal layer;

[0013] The second contact layer is in contact with the second metal layer;

[0014] The third contact layer and the buffer layer are either type 1 or type 2 contact;

[0015] The first contact layer, the second contact layer, and the third contact layer are either a first type of metal corresponding to a first type of contact or a second type of metal corresponding to a second type of contact.

[0016] Wherein, the first type of metal is a Schottky metal and the second type of metal is an ohmic metal; and the first type of metal is an ohmic metal and the second type of metal is a Schottky metal.

[0017] In one possible implementation of the first aspect, the vertical power device further includes: a barrier layer disposed between the third contact layer and the buffer layer, and a two-dimensional electron gas interface formed between the barrier layer and the buffer layer.

[0018] In one possible implementation of the first aspect, the first insulating layer and the second insulating layer are configured to pass through a portion of the structure of the barrier layer and the buffer layer.

[0019] In one possible implementation of the first aspect, the through hole is a recessed area.

[0020] In one possible implementation of the first aspect, the surfaces of the first insulating layer and the second insulating layer are flush with the surface of the barrier layer.

[0021] In one possible implementation of the first aspect, the first metal layer is in contact with the buffer layer and is physically isolated from the barrier layer by the first insulating layer;

[0022] The second metal layer is in contact with the buffer layer and is physically isolated from the barrier layer by the second insulating layer.

[0023] In one possible implementation of the first aspect, the metal type of the first metal layer is the same as the metal type of the second metal layer.

[0024] A second aspect of this invention provides a method for fabricating a vertical power device, comprising:

[0025] A buffer layer is epitaxially grown sequentially on the substrate;

[0026] In the epitaxial growth direction perpendicular to the buffer layer, two electrically isolated etching regions are selected, and the two etching regions are etched until the etching depth is close to the substrate and does not penetrate the buffer layer.

[0027] An insulating layer with through holes is deposited in each of the two etched areas;

[0028] Metal deposition is performed on the via to form two metal layers spaced apart from the buffer layer;

[0029] Contact layers of a first type of metal are respectively provided on the two metal layers and the barrier layer along the epitaxial growth direction, and the buffer layer and the contact layers are either first type contact or second type contact.

[0030] In one possible implementation of the second aspect, after the step of sequentially epitaxially growing the buffer layer on the substrate, the method further includes:

[0031] A barrier layer is epitaxially grown on the buffer layer.

[0032] In a third aspect, the present invention provides a chip comprising the vertical power device described above.

[0033] The beneficial effects of the embodiments in this application compared with the prior art are:

[0034] Through the above scheme, through-holes can be provided in the first insulating layer and the second insulating layer respectively. A first metal layer is provided in the through-hole of the first insulating layer, and a second metal layer is provided in the through-hole of the second insulating layer. Since the first insulating layer and the second insulating layer are located in the buffer layer, and the first insulating layer and the second insulating layer are separated from the buffer layer by a certain structure, it can be ensured that the bottom layer of the first metal layer and the second metal layer descends to a certain depth to improve the withstand voltage. In addition, a third contact layer is provided to make a first type contact with the buffer layer. The first contact layer, the second contact layer and the third contact layer are all of the first type metal corresponding to the first type contact or the second type metal corresponding to the second type contact. Thus, the photolithography of the above three contact layers can be achieved by a single photomask, thereby reducing the number of photomask processes used in semiconductor manufacturing and saving manufacturing costs. Therefore, the above scheme solves the technical problem that quasi-vertical diodes in the prior art require higher costs to obtain high withstand voltage characteristics. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a vertical power device provided in one embodiment of this application;

[0037] Figure 2 This is another schematic diagram of a vertical power device provided in one embodiment of this application;

[0038] Figure 3 This is a schematic flowchart of a method for fabricating a vertical power device according to an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the semi-finished product structure after step S1 is performed in the manufacturing method of the vertical power device provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the semi-finished product structure after step S2 is performed in the manufacturing method of the vertical power device provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the semi-finished product structure after step S3 is performed in the manufacturing method of the vertical power device provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the semi-finished product preparation structure after step S4 is performed in the fabrication method of the vertical power device provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of the finished product structure after step S5 is performed in the manufacturing method of the vertical power device provided in an embodiment of this application. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] The term "comprising" and any variations thereof in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0046] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0047] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0048] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0049] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0050] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0051] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0052] To address the issue that quasi-vertical diodes in the prior art require higher costs to achieve high voltage withstand characteristics, this application proposes a vertical power device, its fabrication method, and a chip.

[0053] In one embodiment, Figure 1 This application provides a schematic diagram of the structure of a vertical power device. Figure 1 As shown, the vertical power device in this embodiment includes a substrate 80, a buffer layer 10, a first insulating layer 30, a second insulating layer 60, a first metal layer 40, a second metal layer 70, a first contact layer 90, a second contact layer 100, and a third contact layer 110.

[0054] A buffer layer 10 is disposed on a substrate 80. A first insulating layer 30 is disposed on the buffer layer and located on a first side of the buffer layer 10, wherein the first insulating layer 30 has a through hole. A second insulating layer 60 is disposed on the buffer layer and located on a second side of the buffer layer 10, wherein the second insulating layer has a through hole. A first metal layer is disposed in the through hole of the first insulating layer 30 and is in contact with the buffer layer. A second metal layer is disposed in the through hole of the second insulating layer 60 and is in contact with the buffer layer 10. A third contact layer is in a first type of contact with the buffer layer 10 and is a first type of metal. The first contact layer is in contact with the first metal layer 40 and is a first type of metal. The second contact layer is in contact with the second metal layer 70 and is a first type of metal.

[0055] In the aforementioned vertical power device, electrons originate from the cathode, pass through the first metal layer 40 or the second metal layer 70, overcome the horizontal and vertical path impedances of the buffer layer 10, and tunnel through the buffer layer 10 due to the tunneling effect. They then overcome the energy band structure of the first type of metal to reach the anode. (Refer to...) Figure 1 The direction of the middle arrow indicates the direction of the current; the electron path is opposite to that of the arrow.

[0056] Through the above scheme, through holes can be provided in the first insulating layer 30 and the second insulating layer 60 respectively. The first metal layer 40 is provided in the through hole of the first insulating layer 30, and the second metal layer 70 is provided in the through hole of the second insulating layer 60. Since the first insulating layer 30 and the second insulating layer 60 are provided in the buffer layer 10, and the first insulating layer 30 and the second insulating layer 60 are partially separated from the buffer layer 10, it can be ensured that the bottom layer of the first metal layer and the second metal layer 70 descends to a certain depth to improve the withstand voltage. In addition, the third contact layer 110 forms a first type of contact with the buffer layer 10. The type of the third contact layer 110 is the first type of metal corresponding to the first type of contact. The first contact layer 90, the second contact layer 100 and the third contact layer 110 are all the first type of metal corresponding to the first type of contact. In the above embodiment, the first metal layer and the first contact layer constitute a cathode, the second metal layer and the first contact layer constitute another cathode, and the barrier layer or the buffer layer is the anode. By designing the first contact layer 90, the second contact layer 100, and the third contact layer 110 all as the first type of metal, the photolithography of the above three contact layers can be achieved with a single photomask. This avoids the need for separate photomasks to be used for photolithography of the cathode and anode, thereby reducing the number of times photomask processes are used in semiconductor manufacturing and saving manufacturing costs. Therefore, the above solution solves the technical problem of high cost of semiconductor devices in the prior art.

[0057] In particular, the above solution can be applied not only to vertical power devices such as gallium nitride high electron mobility transistors (GaN), but also to the fabrication of unclamped inductive switches (UIS). When applied to gallium nitride high electron mobility transistors (GaN), using ohmic metals for the first metal layer 40 and the second metal layer 70, and Schottky metals for the first contact layer 90, the second contact layer 100, and the third contact layer 110, can achieve superior performance, namely, better voltage withstand capability.

[0058] Optionally, the first type of metal is a Schottky metal or an ohmic metal.

[0059] Optionally, when the third contact layer 110 and the buffer layer are in a second type of contact, the first contact layer 90, the second contact layer 100 and the third contact layer 110 are second type metals corresponding to the second type of contact.

[0060] When the first type of metal is a Schottky metal, the second type of metal is an ohmic metal.

[0061] In an optional embodiment, the first contact layer 90, the second contact layer 100, and the third contact layer 110 are located in the first photomask fabrication layer.

[0062] In an alternative embodiment, the first metal layer 40 and the second metal layer 70 are located in the second photomask fabrication layer.

[0063] By designing the cathode metal as a deep cathode metal according to the above scheme, and constructing the cathode using a first metal layer 40, a first contact layer 90, a second metal layer 70, and a second contact layer 100 respectively, the first contact layer 90 and the second contact layer 100 of the cathode are flush with the third contact layer 110 in the direction perpendicular to the buffer layer 10. Since the metal types are the same, the first contact layer 90 and the second contact layer 100 can be directly fabricated by using a photomask to fabricate the third contact layer 110, thereby reducing the number of times the photomask process is used and saving manufacturing costs.

[0064] Optionally, the material of the buffer layer 10 is GaN.

[0065] Optionally, the first type of metal is a Schottky metal or an ohmic metal.

[0066] In one possible implementation of the first aspect, the vertical power device further includes: a barrier layer 20 disposed between the third contact layer 110 and the buffer layer 10, and a two-dimensional electron gas interface is formed between the barrier layer 20 and the buffer layer 10.

[0067] The two-dimensional electron gas interface (2DEG) ensures the confinement of electrons' three-dimensional movement, limiting them to two-dimensional motion and enabling rapid electron transmission over a wide effective distance. In the aforementioned vertical power device, electrons originate from the cathode, pass through the first metal layer 40 or the first type of metal in the first contact layer, overcome the horizontal and vertical path impedances of the buffer layer 10, reach the two-dimensional electron gas interface (2DEG), tunnel through the AlGaN layer due to the tunneling effect, and then overcome the energy band of the first type of metal to reach the anode. Figure 2 The arrow indicates the direction of the current, and the electron path is opposite to that of the arrow.

[0068] Optionally, the barrier layer 20 is made of AlGaN. The buffer layer 10 is made of GaN.

[0069] In one possible implementation of the first aspect, the first insulating layer 30 and the second insulating layer 60 pass through a portion of the structure of the barrier layer 20 and the buffer layer 10.

[0070] The above structure can maximize the thickness of the barrier layer 20 and the buffer layer 10 for electron passage, thereby further improving the voltage withstand capability of the vertical power device.

[0071] In one possible implementation of the first aspect, the first filling region and the second filling region are recessed regions.

[0072] By designing the first filling area and the second filling area as recessed areas, the first metal layer 40 and the second metal layer 70 can be connected with the buffer layer 10, ensuring their connection stability and reliability. This results in the final vertical power device having good conduction conditions and good withstand voltage. In addition, setting it as a recessed area can reduce the volume occupied by the vertical power device, saving production costs. In mass production, it has a significant effect on reducing production costs.

[0073] In one possible implementation of the first aspect, the surfaces of the first insulating layer 30 and the second insulating layer 60 are flush with the surface of the barrier layer 20.

[0074] By aligning the surfaces of the first insulating layer 30 and the second insulating layer 60 with the surface of the barrier layer 20, issues such as metal layer overflow or poor contact caused by the low surface area of ​​the first insulating layer 30 and the second insulating layer 60 can be avoided. This ensures that the metal layer is completely physically isolated from the barrier layer 20 during subsequent metal layer filling.

[0075] In one possible implementation of the first aspect, the first metal layer 40 is in contact with the buffer layer 10 and is physically isolated from the barrier layer 20 by the first insulating layer 30.

[0076] By controlling the physical isolation between the first insulating layer 30 and the barrier layer 20, it can be ensured that there is only one current channel.

[0077] In one possible implementation of the first aspect, the second metal layer 70 is in contact with the buffer layer 10 and is physically isolated from the barrier layer 20 by the second insulating layer 60.

[0078] By controlling the physical isolation between the second insulating layer 60 and the barrier layer 20, it can be ensured that there is only one current path.

[0079] In one possible implementation of the first aspect, the metal type of the first metal layer 40 is the same as the metal type of the second metal layer.

[0080] The first metal layer 40 is either a Schottky metal or an ohmic metal. The second metal layer 70 is either a Schottky metal or an ohmic metal. The buffer layer 10 is a semiconductor layer; the Schottky metal is the metal that forms a Schottky contact with the buffer layer 10, and the ohmic metal is the metal that forms an ohmic contact with the buffer layer 10. When the metal type of the first metal layer 40 is the same as the metal type of the second metal layer, both can be deposited using a single photomask without requiring additional photomask operations.

[0081] In one possible implementation of the first aspect, the first metal layer 40 and the first contact layer constitute a cathode, the second metal layer 70 and the first contact layer constitute another cathode, and the barrier layer 20 or the buffer layer is the anode.

[0082] In the embodiments of this case, the first metal layer 40 and the first contact layer can be the same metal or different metals. When they are different, it is only necessary to ensure that the first contact layer, the second contact layer and the third contact layer are all of the same type of metal. In this case, the cathode can be said to be made of a uniform metal, but the actual contact type between the cathode and the buffer layer 10 is completely determined by the contact type between the first metal layer 40 and the buffer layer 10 and the contact type between the second metal layer 70 and the buffer layer 10.

[0083] In one embodiment, Figure 3 A schematic flowchart of the fabrication method of the vertical power device provided in this application is shown. The fabrication method of the vertical power device includes:

[0084] S1. Buffer layer 10 is epitaxially grown sequentially on substrate;

[0085] See Figure 4 As shown, the substrate 80 can be a single crystal substrate, and a buffer layer 10 can be formed on the surface of the substrate 80 through an epitaxial process.

[0086] Epitaxial growth refers to the growth of a single crystal layer with certain requirements on a single crystal substrate 80 (substrate) that has the same crystal orientation as the substrate 80.

[0087] In one specific application embodiment, the substrate 80 can be a silicon substrate such as silicon carbide or silicon dioxide, and the buffer layer 10 can be a GaN semiconductor.

[0088] S2. In the epitaxial growth direction perpendicular to the buffer layer 10, select two electrically isolated etching areas and etch the two etching areas until the etching depth is close to the substrate and does not penetrate the buffer layer 10.

[0089] See Figure 5 As shown, etching is a technique that removes material using chemical reactions or physical impact. In this application, specific etching areas can be formed by wet etching or dry etching. By setting etchable areas, a region can be directly delineated.

[0090] S3. An insulating layer with through holes is deposited in each of the two etched areas, and the through holes are in contact with the buffer layer.

[0091] See Figure 6As shown, deposition includes three main categories: physical vapor deposition (PVD), chemical vapor deposition (CVD), and epitaxy. PVD refers to a technology that uses physical processes such as thermal evaporation or atomic sputtering when a target surface is bombarded by particles to transfer atoms of the aforementioned material to the surface of a silicon wafer to form a thin film. It is mostly used for metal deposition. CVD refers to a process of depositing thin films on the surface of a silicon wafer through a chemical reaction of gas mixtures. It can be applied to the deposition of insulating films, polycrystalline silicon, and metal films. Epitaxy is a process of growing single-crystal thin films on the surface of a silicon wafer according to the crystal orientation of the substrate.

[0092] In one specific embodiment, the insulating layer may be SiN / SiO2, etc.

[0093] S4. Metal deposition is performed on the through-hole to form a metal layer with two spaced buffer layers 10.

[0094] See Figure 7 As shown, metal deposition includes physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD refers to the technology of transferring atoms of the aforementioned substances to the silicon wafer surface and forming a thin film through physical processes such as thermal evaporation or atomic sputtering when the target surface is bombarded by particles. It is mostly used for metal deposition. CVD refers to the process of depositing a thin film on the silicon wafer surface through a chemical reaction of gas mixing. It can be applied to the deposition of insulating films, polycrystalline silicon and metal films. The deposition of specific metal layers can be achieved through the above processes.

[0095] In one specific embodiment, the metal layer can be an ohmic metal or a Schottky metal, where the Schottky metal is the metal that forms a Schottky contact with the buffer layer 10, and the ohmic metal is the metal that forms an ohmic contact with the buffer layer 10.

[0096] S5. Contact layers of a first type of metal are respectively provided on the two metal layers and the barrier layer 20 along the epitaxial growth direction, and the buffer layer and the contact layers are in the first type of contact.

[0097] See Figure 8 As shown, at this point, a contact layer composed of a first type of metal can be set using a deposition process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Since the contact layer between the two metal layers is in contact with the metal itself, and the contact between the buffer layer and the contact layer is a first type of contact, i.e., a Schottky contact or an ohmic contact, once the metal of the contact layer with the buffer layer is determined to be a Schottky metal or an ohmic metal, the metal type of the contact layer that is the same as it can be determined. Therefore, the metal type of the contact layer that contacts the other two metal layers is determined by the metal type of the buffer layer, and the type should be kept consistent.

[0098] In the vertical power device fabricated using the above-described method, electrons originate from the cathode, pass through the first metal layer 40 or the second metal layer 70, overcome the horizontal and vertical path resistance of the buffer layer 10, pass through the buffer layer 10 due to the tunneling effect, and then overcome the energy band of the first type of metal to reach the anode. (Refer to...) Figure 2 The direction of the middle arrow indicates the direction of the current; the electron path is opposite to that of the arrow.

[0099] Through the above solution, through-holes are respectively provided in the first insulating layer 30 and the second insulating layer 60. A first metal layer 40 is disposed in the through-hole of the first insulating layer 30, and a second metal layer 70 is disposed in the through-hole of the second insulating layer 60. Since the first insulating layer 30 and the second insulating layer 60 are disposed on the buffer layer 10, and the first insulating layer 30 and the second insulating layer 60 are partially separated from the buffer layer 10, the bottom layer of the first metal layer and the second metal layer 70 can be lowered to a certain depth to improve the withstand voltage. Furthermore, a first type of contact is formed between the third contact layer 110 and the buffer layer 10. The third contact layer 110 is of the first type of metal. Since the first contact layer 90, the second contact layer 100, and the third contact layer 110 are all of the first type of metal, photolithography of the above three contact layers can be achieved using a single photomask. This reduces the number of photomask processes used in semiconductor fabrication, saving manufacturing costs. Therefore, the above solution solves the technical problem of high cost in existing semiconductor devices. Optionally, the first type of metal is a Schottky metal or an ohmic metal.

[0100] In one possible implementation of the second aspect, the step of depositing metal on the via to form two spaced buffer layers 10 further includes:

[0101] A second type of metal contact layer is provided on the two metal layers and the barrier layer 20 respectively along the epitaxial growth direction, and the buffer layer and the contact layer are in a second type of contact.

[0102] In this design, the first contact layer 90, the second contact layer 100, and the third contact layer 110 are all made of a second type of metal. Photolithography of these three contact layers can be achieved using a single photomask, thereby reducing the number of photomask processes used in semiconductor fabrication and saving manufacturing costs. Therefore, this solution addresses the technical problem of high cost in existing semiconductor devices. Optionally, the second type of metal is a Schottky metal or an ohmic metal.

[0103] In one possible implementation of the second aspect, after the step of depositing metal into the via to form a metal layer, the method further includes:

[0104] A barrier layer is epitaxially grown on the buffer layer.

[0105] See Figure 2 As shown, a two-dimensional electron gas interface (2DEG) can be formed between the barrier layer 20 and the buffer layer 10, thereby ensuring a more stable electron flow.

[0106] The barrier layer 20 is typically implemented using AlGaN semiconductor.

[0107] It should be noted that in certain scenarios, the materials of both the buffer layer 10 and the barrier layer 20 can be GaN semiconductors, that is, only the buffer layer 10 exists, which can also be regarded as a Schottky transistor with AlGaN removed.

[0108] Electrons originate from the cathode, pass through the first metal layer 40 or the second metal layer 70, overcome the horizontal and vertical path resistance of the buffer layer 10, and reach the two-dimensional electron gas interface (2DEG). Due to the tunneling effect, they pass through the buffer layer 10, then overcome the energy band of the Schottky metal to reach the anode. Figure 2 The direction of the middle arrow indicates the direction of the current; the electron path is opposite to that of the arrow.

[0109] Corresponding to the vertical power device 10 in the above embodiments, this application also provides a chip including the vertical power device 10 as described above.

[0110] It should be noted that, since the chip of the present invention includes all embodiments of the vertical power device 10 described above, the chip of the present invention has all the beneficial effects of the vertical power device 10 described above, which will not be repeated here.

[0111] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A vertical power device, characterized in that, The vertical power device includes: Substrate; A buffer layer is disposed on the substrate; A first insulating layer is disposed on the buffer layer and located on the first side of the buffer layer, wherein the first insulating layer has a through hole; A second insulating layer is disposed on the buffer layer and located on the second side of the buffer layer, wherein the second insulating layer has through holes; A first metal layer is disposed in a through-hole of the first insulating layer and is in contact with the buffer layer; The second metal layer is disposed in the through-hole of the second insulating layer and is in contact with the buffer layer; A first contact layer, wherein the first contact layer is in contact with the first metal layer; A second contact layer is in contact with the second metal layer; The third contact layer and the buffer layer are either type 1 or type 2 contact; The first contact layer, the second contact layer, and the third contact layer are either a first type of metal corresponding to a first type of contact or a second type of metal corresponding to a second type of contact. Wherein, the first type of metal is a Schottky metal and the second type of metal is an ohmic metal; and the first type of metal is an ohmic metal and the second type of metal is a Schottky metal.

2. The vertical power device as described in claim 1, characterized in that, The vertical power device further includes a barrier layer disposed between the third contact layer and the buffer layer, and a two-dimensional electron gas interface is formed between the barrier layer and the buffer layer.

3. The vertical power device as described in claim 2, characterized in that, The first insulating layer and the second insulating layer are partially disposed through the barrier layer and the buffer layer.

4. The vertical power device as described in claim 1, characterized in that, The through hole is a recessed area.

5. The vertical power device as described in claim 2, characterized in that, The surfaces of the first insulating layer and the second insulating layer are flush with the surface of the barrier layer.

6. The vertical power device as described in claim 2, characterized in that, The first metal layer is in contact with the buffer layer and is physically isolated from the barrier layer by the first insulating layer; The second metal layer is in contact with the buffer layer and is physically isolated from the barrier layer by the second insulating layer.

7. The vertical power device as described in claim 1, characterized in that, The first metal layer and the second metal layer have the same metal type.

8. A method for fabricating a vertical power device, characterized in that, include: A buffer layer is epitaxially grown sequentially on the substrate; In the epitaxial growth direction perpendicular to the buffer layer, two electrically isolated etching regions are selected, and the two etching regions are etched until the etching depth is close to the substrate and does not penetrate the buffer layer. An insulating layer with through holes is deposited in each of the two etched areas; Metal deposition is performed on the via to form two metal layers spaced apart from the buffer layer; Contact layers of a first type of metal are respectively provided on the two metal layers and the buffer layer along the epitaxial growth direction, and the contact between the buffer layer and the contact layer is either a first type of contact or a second type of contact.

9. The method for fabricating a vertical power device as described in claim 8, characterized in that, The step of sequentially epitaxially growing the buffer layer on the substrate further includes: A barrier layer is epitaxially grown on the buffer layer.

10. A chip, characterized in that, The chip includes at least one vertical power device as described in any one of claims 1-7.

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