Lead frame and package structure

Abstract

This invention provides a lead frame and a packaging structure. In the lead frame, a ground interconnect structure is at least partially arranged around the periphery of the chip. Multiple ground pads of the chip are electrically connected to the ground interconnect structure via corresponding first bonding wires. A power interconnect structure is at least partially arranged around the periphery of the chip, with at least a portion of one of the power interconnect structure and the ground interconnect structure surrounding the other. Multiple power pads of the chip are electrically connected to the power interconnect structure via corresponding second bonding wires. A first insulating connection structure connects the ground interconnect structure and the power interconnect structure. The power interconnect structure is electrically connected to a power pin via a third bonding wire. This lead frame structure enhances the ESD protection capability of the packaging structure and reduces voltage drop and signal interference. The packaging structure includes the aforementioned lead frame.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a lead frame and a packaging structure. Background Technology

[0002] In modern integrated circuit design, electromagnetic compatibility (EMC) and system-level electrostatic discharge (ESD) are crucial considerations. ESD events pose a potential risk of damaging the transistor structure within integrated circuits, leading to device malfunction or failure. Therefore, enhancing system-level ESD protection has become a key measure to improve the reliability of electronic products. In the field of microelectronic packaging, the lead frame, as a bridge for electrical connections between the chip and the outside world, not only provides mechanical support but also handles current input and output. Especially in high-performance integrated circuits, stable power and ground connections are critical to the performance and stability of the entire system.

[0003] Traditional leadframe designs have several drawbacks. Due to leadframe pin resource limitations, most of the power and ground pads on the chip surface cannot be brought out, leading to issues such as increased current density, uneven heat distribution, increased ESD (Electro-Static Discharge) susceptibility, and degraded electrical performance. Furthermore, in high-frequency or high-current applications, the inductance and resistance of the leadframe can cause voltage drops and signal interference, affecting chip performance. Summary of the Invention

[0004] One of the objectives of this invention is to provide a lead frame and a packaging structure that can enhance the ESD protection capability of the packaging structure and reduce voltage drop and signal interference.

[0005] To achieve the above objectives, the present invention provides a lead frame. The lead frame includes: a ground interconnect structure, at least partially surrounding the periphery of a chip, the surface of which has a plurality of ground pads and a plurality of power pads, the plurality of ground pads being electrically connected to the ground interconnect structure via corresponding first bonding wires; a power interconnect structure, at least partially surrounding the periphery of the chip, one of which, at least partially surrounding the periphery of the ground interconnect structure, is further surrounded by the other, the plurality of power pads being electrically connected to the power interconnect structure via corresponding second bonding wires; a first insulating connection structure connecting the ground interconnect structure and the power interconnect structure; and a plurality of pins, disposed on the outer side of the power interconnect structure and the ground interconnect structure away from the chip, including power pins, the power pins being electrically connected to the power interconnect structure via third bonding wires.

[0006] Optionally, the first insulating connection structure is one of a pre-encapsulated body, insulating tape, or a multi-layer composite structure.

[0007] Optionally, the power interconnect structure is at least partially arranged around the periphery of the ground interconnect structure.

[0008] Optionally, the ground interconnect structure is arranged around the periphery of the chip; the lead frame further includes a second insulating connection structure, which connects the ground interconnect structure and the chip.

[0009] Optionally, the first insulating connection structure and the second insulating connection structure are one of the following: a pre-encapsulated body, insulating tape, or a multi-layer composite structure.

[0010] Optionally, the first insulating connection structure fills the gap between the ground interconnect structure and the power interconnect structure, and further extends to cover a portion of the top and bottom surfaces of the ground interconnect structure and a portion of the top and bottom surfaces of the power interconnect structure; the second insulating connection structure fills the gap between the ground interconnect structure and the chip, and further extends to cover a portion of the top and bottom surfaces of the ground interconnect structure and a portion of the top and bottom surfaces of the chip.

[0011] Optionally, the first insulating connection structure and the second insulating connection structure are connected to form an insulating connection body, and the chip, the ground interconnection structure and the power interconnection structure are located on the insulating connection body.

[0012] Optionally, the lead frame further includes a chip carrier structure and a second insulating connection structure; the ground interconnect structure is arranged around the periphery of the chip carrier structure, and the chip is mounted on the chip carrier structure; the second insulating connection structure connects the ground interconnect structure and the chip carrier structure.

[0013] Optionally, the ground interconnect structure carries the chip, the chip is mounted on the central region of the ground interconnect structure, and one end of the first bonding wire is disposed on the edge region of the ground interconnect structure.

[0014] Optionally, the power interconnect structure, the first insulation connection structure, and the ground interconnect structure are stacked from bottom to top, and the chip is disposed on the ground interconnect structure.

[0015] Optionally, the top surface of the grounding interconnection structure and the top surface of the power interconnection structure are located on the same horizontal plane.

[0016] Optionally, the first insulating connection structure is insulating tape.

[0017] Optionally, at least one decoupling capacitor is provided on the first insulating connection structure, one end of the decoupling capacitor is electrically connected to the ground interconnection structure, and the other end of the decoupling capacitor is electrically connected to the power interconnection structure.

[0018] Optionally, the plurality of pins includes a ground pin, and the ground interconnect structure is electrically connected to the ground pin via a fourth bonding wire.

[0019] Optionally, the number of the fourth bonding wires is less than the number of the first bonding wires, and / or the number of the third bonding wires is less than the number of the second bonding wires.

[0020] The present invention also provides a packaging structure. The packaging structure includes a chip and the lead frame described above.

[0021] The lead frame provided by this invention includes a ground interconnect structure, a power interconnect structure, a first insulating connection structure, and multiple pins. The ground interconnect structure is at least partially disposed around the periphery of the chip. The surface of the chip has multiple ground pads and multiple power pads. The multiple ground pads are electrically connected to the ground interconnect structure via corresponding first bonding wires. The power interconnect structure is at least partially disposed around the periphery of the chip. At least part of one of the power interconnect structure and the ground interconnect structure is disposed around the periphery of the other. The multiple power pads are electrically connected to the power interconnect structure via corresponding second bonding wires. The first insulating connection structure connects the ground interconnect structure and the power interconnect structure. The multiple pins are disposed on the outer side of the power interconnect structure and the ground interconnect structure away from the chip and include power pins. The power pins and the power interconnect structure are connected via third bonding wires. This design change to the leadframe allows multiple ground pads to be led out through a ground interconnect structure, and multiple power pads to be led out through a power interconnect structure. This prevents problems such as increased current density and uneven heat distribution, enhances the ESD protection capability of the package structure, improves the current paths for power (VDD) and ground (VSS), and helps improve the stability of the power supply. Compared to the pins, the ground interconnect structure and the power interconnect structure have a larger area, which can reduce the resistance and inductance of the VDD and VSS paths, helping to reduce voltage drop and signal interference, and optimize the electrical performance of the package structure. The leadframe provided by this invention has a wide range of applications, such as LQFP, QFN, SOIC, etc., and has broad market application prospects. Attached Figure Description

[0022] Figure 1 This is a top view of a lead frame provided in an embodiment of the present invention.

[0023] Figures 2 to 6 Cross-sectional views of packaging structures including lead frames provided for different embodiments of the present invention.

[0024] Figure 7 This is a top view of a lead frame with a decoupling capacitor provided in one embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 10-lead frame; 101-ground interconnect structure; 102-power interconnect structure; 103-first insulating connection structure; 104-second insulating connection structure; 105-pin; 105a-power pin; 105b-ground pin; 106-chip carrier structure; 107-insulating connector; 20-chip; 201-ground pad; 202-power pad; 301-first bonding wire; 302-second bonding wire; 303-third bonding wire; 304-fourth bonding wire; 40-molding package; 50-decoupling capacitor. Detailed Implementation

[0026] The lead frame and packaging structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] The terms "first," "second," and similar terms used in this specification do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise stated, terms such as "upper / upper layer" and / or "lower / lower layer," and similar terms, are for illustrative purposes only and are not limited to a location or spatial orientation.

[0028] Figure 1 This is a top view of a lead frame provided according to an embodiment of the present invention. (See reference...) Figure 1 As shown, the lead frame 10 provided in this application includes a ground interconnect structure 101, a power interconnect structure 102, a first insulating connection structure 103, and a plurality of pins 105. The ground interconnect structure 101 is at least partially disposed around the periphery of the chip 20. The surface of the chip 20 has a plurality of ground pads 201 and a plurality of power pads 202. The plurality of ground pads 201 are electrically connected to the ground interconnect structure 101 via corresponding first bonding wires 301. The power interconnect structure 102 is at least partially disposed around the periphery of the chip 20. At least a portion of one of the power interconnect structure 102 and the ground interconnect structure 101 is disposed around the periphery of the other. The plurality of power pads 202 are electrically connected to the power interconnect structure 102 via corresponding second bonding wires 302. The first insulating connection structure 103 connects the ground interconnect structure 101 and the power interconnect structure 102. Multiple pins 105 are disposed on the outer side of the power interconnect structure 102 and the ground interconnect structure 101 away from the chip 20. The multiple pins 105 include a power pin 105a, and the power pin 105a and the power interconnect structure 102 are electrically connected by a third bonding wire 303.

[0029] In this application, the material of the first insulating connection structure is an insulating material, and the first insulating connection structure makes a non-electrical connection to the ground interconnection structure 101 and the power interconnection structure 102.

[0030] In this application, chip 20 is a wire-bonded type chip. Exemplarily, chip 20 has opposing front and back sides, as shown in the reference... Figure 1 As shown, the front side of the chip 20 may have multiple pads, which may be arranged along the edge area of ​​the front side of the chip. The multiple pads include, but are not limited to, multiple ground pads 201, multiple power pads 202, and multiple signal input / output pads.

[0031] In some embodiments of this application, the power interconnect structure 102 is at least partially disposed around the periphery of the ground interconnect structure 101. In other embodiments of this application, the ground interconnect structure 101 may be at least partially disposed around the periphery of the power interconnect structure 102. The following description uses the example of the power interconnect structure 102 at least partially disposed around the periphery of the ground interconnect structure 101.

[0032] In this application, the area of ​​the grounding interconnection structure 101, the area of ​​the power interconnection structure 102, and the ratio between the grounding interconnection structure 101 and the power interconnection structure 102 can be freely adjusted according to actual needs.

[0033] Figures 2 to 6 Cross-sectional views of packaging structures including lead frames provided for different embodiments of the present invention.

[0034] In one embodiment of this application, reference is made to... Figure 1 and Figure 2 As shown, the ground interconnect structure 101 is arranged around the periphery of the chip 20. The lead frame 10 may further include a second insulating connection structure 104, which connects the ground interconnect structure 101 and the chip 20. In this embodiment, the ground interconnect structure 101 can be U-shaped, with a hollowed-out central area, allowing the chip 20 to be inserted and mounted in the ground interconnect structure 101, which helps to reduce the thickness of the package structure.

[0035] In some embodiments of this application, reference is made to Figure 3As shown, the lead frame 10 also includes a chip carrier structure 106 and a second insulating connection structure 104; a ground interconnect structure 101 is arranged around the periphery of the chip carrier structure 106, and the back side of the chip 20 can be mounted on the chip carrier structure 106; the second insulating connection structure 104 connects the ground interconnect structure 101 and the chip carrier structure 106. Thus, a separate chip carrier structure 106 is provided for the chip 20 within the lead frame 10, facilitating the mounting and fixing of the chip 20 onto the lead frame 10 during packaging.

[0036] For example, the first insulating connection structure 103 and the second insulating connection structure 104 are one of a pre-encapsulated body, insulating tape, or a multi-layer composite structure.

[0037] When the first insulating connection structure 103 and the second insulating connection structure 104 are insulating tapes, the lead frame is easy to process, which helps to reduce costs and is suitable for various packaging designs, making it widely applicable. For example, the material of the pre-encapsulation body includes, but is not limited to, epoxy molding compound (EMC). When the first insulating connection structure 103 and the second insulating connection structure 104 are pre-encapsulation bodies, the insulation effect between the ground interconnection structure 101 and the power interconnection structure 102 is good, the connection structure is structurally stable, which helps to improve the reliability of the packaging structure and is also suitable for high-density packaging requirements. It should be noted that when a multilayer composite structure is used as the first insulating connection structure 103 and / or the second insulating connection structure 104 in this application, the connection established by the multilayer composite structure is a non-electrical connection.

[0038] In some embodiments of this application, such as Figure 2 and Figure 3 As shown, the first insulating connection structure 103 can fill the gap between the ground interconnect structure 101 and the power interconnect structure 102, and also extends to cover part of the top and bottom surfaces of the ground interconnect structure 101 and to cover part of the top and bottom surfaces of the power interconnect structure 102.

[0039] In one embodiment, such as Figure 2 As shown, the second insulating connection structure 104 can fill the gap between the ground interconnect structure 101 and the chip 20, and also extends to cover part of the top and bottom surfaces of the ground interconnect structure 101 and part of the top and bottom surfaces of the chip 20.

[0040] In one embodiment, such as Figure 3 As shown, the second insulating connection structure 104 can fill the gap between the ground interconnect structure 101 and the chip carrier structure 106, and also extends to cover part of the top and bottom surfaces of the ground interconnect structure 101 and part of the top and bottom surfaces of the chip carrier structure 106.

[0041] In some embodiments of this application, the top surface of the ground interconnect structure 101 and the top surface of the power interconnect structure 102 are located on the same horizontal plane. In one embodiment, as... Figure 2 As shown, the top surface of the ground interconnect structure 101, the top surface of the power interconnect structure 102, and the top surface of the chip 20 can be located on the same horizontal plane. In one embodiment, as... Figure 3 As shown, the top surface of the ground interconnection structure 101, the top surface of the power interconnection structure 102, and the top surface of the chip carrier structure 106 can be located on the same horizontal plane.

[0042] In some embodiments, such as Figure 4 As shown, the first insulating connection structure 103 and the second insulating connection structure 104 are connected to form an insulating connector 107. The chip 20, the ground interconnection structure 101 and the power interconnection structure 102 are located on the insulating connector 107. The insulating connector 107 connects the chip 20 and the ground interconnection structure 101 and connects the ground interconnection structure 101 and the power interconnection structure 102.

[0043] In some embodiments of this application, such as Figure 5 and Figure 6 As shown, the ground interconnect structure 101 carries the chip 20. The chip 20 is mounted on the central area of ​​the ground interconnect structure 101. One end of the first bonding line 301 connecting the ground pad 201 is attached to the edge area of ​​the ground interconnect structure 101. This makes it easy to install and fix the chip 20 on the lead frame 10, and the structure of the lead frame 10 is relatively simple.

[0044] In one embodiment, such as Figure 6 As shown, the grounding interconnection structure 101 and the power interconnection structure 102 are located on the first insulating connection structure 103. The first insulating connection structure 103 also fills the gap between the grounding interconnection structure 101 and the power interconnection structure 102. In this way, the first insulating connection structure 103 not only connects the grounding interconnection structure 101 and the power interconnection structure 102, but also limits the grounding interconnection structure 101 and the power interconnection structure 102.

[0045] In some embodiments of this application, the power interconnect structure 102, the first insulating connection structure 103, and the ground interconnect structure 101 can all be plate-shaped. The power interconnect structure 102, the first insulating connection structure 103, and the ground interconnect structure 101 can be stacked from bottom to top. The width of the power interconnect structure 102 is greater than the width of the first insulating connection structure 103, and the width of the ground interconnect structure 101 is less than the width of the power interconnect structure 102. The chip 20 can be mounted on the ground interconnect structure 101.

[0046] In this application, the ground interconnect structure 101 and the power interconnect structure 102 can be made of the same material. For example, the materials of the ground interconnect structure 101 and the power interconnect structure 102 include, but are not limited to, one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0047] like Figure 1 As shown, the lead frame 10 includes a plurality of pins 105, which can be arranged around the power interconnect structure 102. The pins 105, the ground interconnect structure 101, and the power interconnect structure 102 can be made of the same material. The material of the pins 105 can also be different from the materials of the ground interconnect structure 101 and the power interconnect structure 102, depending on the specific requirements. In this embodiment, the plurality of pins 105 are arranged on three sides of the power interconnect structure 102. In other embodiments, the plurality of pins 105 can be arranged on one, two, or four sides of the power interconnect structure 102.

[0048] refer to Figure 2 As shown, the top surface of pin 105 near the chip 20 can be on the same horizontal plane as the top surfaces of ground interconnect structure 101 and power interconnect structure 102, but is not limited to this. The ends of multiple pins 105 away from the chip 20 can be located in the same horizontal plane.

[0049] refer to Figures 1 to 6 As shown, multiple ground pads 201 on the front side of chip 20 are electrically connected to ground interconnect structure 101 via corresponding first bonding wires 301. Since the ground interconnect structure 101 surrounds the periphery of chip 20 and has a large area, multiple ground pads 201 can be electrically connected to the ground interconnect structure 101 via corresponding first bonding wires 301 to bring out multiple ground pads 201. The number of ground pads 201 brought out can be selected as needed without being limited by lead frame pin resources. For example, all ground pads 201 are connected to the ground interconnect structure 101 via corresponding first bonding wires 301.

[0050] like Figures 1 to 6 As shown, in some embodiments, the plurality of pins 105 may include a ground pin 105b, and the ground interconnect structure 101 may be electrically connected to the ground pin 105b via a fourth bonding wire 304 to bring out the ground interconnect structure 101. In other embodiments, the ground interconnect structure 101 may also be directly grounded.

[0051] refer to Figures 1 to 6As shown, multiple power pads 202 on the front side of chip 20 are electrically connected to power interconnect structure 102 via corresponding second bonding wires 302. Since the power interconnect structure 102 surrounds the periphery of chip 20 and has a large area, multiple power pads 202 can be electrically connected to the power interconnect structure 102 via corresponding second bonding wires 302 to bring out multiple power pads 202. The number of power pads 202 brought out can be selected as needed without being limited by lead frame pin resources. For example, all power pads 202 are connected to the power interconnect structure 102 via corresponding second bonding wires 302.

[0052] refer to Figures 1 to 6 As shown, the plurality of pins 105 include a power supply pin 105a, and the power interconnect structure 102 is electrically connected to the power supply pin 105a via a third bonding wire 303 to bring out the power interconnect structure 102.

[0053] The linewidths of the second bonding wire 302 and the third bonding wire 303 may be different, and the linewidths of the first bonding wire 301 and the fourth bonding wire 304 may be different, but are not limited to these. The materials of the bonding wires include, but are not limited to, gold, silver, copper, aluminum and their alloys.

[0054] It should be noted that the multiple ground pads 201 on the front of the chip 20 are electrically connected to the ground interconnect structure 101 through the corresponding first bonding wire 301. The ground interconnect structure 101 is electrically connected to the ground pin 105b through the fourth bonding wire 304. The multiple power pads 202 on the front of the chip 20 are electrically connected to the power interconnect structure 102 through the corresponding second bonding wire 302. The power interconnect structure 102 is electrically connected to the power pin 105a through the third bonding wire 303. In this way, the number of ground pads 201 and power pads 202 brought out is not limited by pin resources or by the setting position. Thus, multiple power pads 202 and multiple ground pads 201, or even all power pads and ground pads on the front of the chip, can be brought out to the pins. As a result, static charge can be preferentially discharged through the power (VDD) circuit and the ground circuit, which enhances the electrostatic discharge protection performance of the package structure, improves power integrity, and does not require changes to the chip design itself, thus having strong compatibility.

[0055] Furthermore, the number of fourth bonding wires 304 is less than the number of first bonding wires 301, and / or the number of third bonding wires 303 is less than the number of second bonding wires 302. In this way, while realizing ESD protection by bringing out the power pad 202 and the ground pad 201, the pin resources occupied by bringing out the power pad 202 and the ground pad 201 are reduced.

[0056] It should be noted that there are also multiple signal input / output pads on the front side of chip 20, which can be connected to the corresponding pins 105 via the corresponding fifth bonding wires.

[0057] Figure 7 This is a top view of a lead frame with a decoupling capacitor provided in one embodiment of the present invention. (See reference) Figure 7 As shown, at least one decoupling capacitor 50 may be provided on the first insulating connection structure 103. The decoupling capacitor 50 extends from the edge region of the ground interconnect structure 101 across the first insulating connection structure 103 to the edge region of the power interconnect structure 102. One end of the decoupling capacitor 50 is in contact with the ground interconnect structure 101, and the other end of the decoupling capacitor 50 is in contact with the power interconnect structure 102.

[0058] It should be noted that in this embodiment, a decoupling capacitor 50 is placed between the ground interconnection structure 101 and the power interconnection structure 102, which can achieve the shortest discharge path for VDD and VSS and enhance the ESD protection performance of the chip.

[0059] In this embodiment, a decoupling capacitor 50 is provided on each of the four sides of the grounding interconnection structure 101. In other embodiments, the number and location of the decoupling capacitors 50 can be selected according to the actual situation.

[0060] In the lead frame 10 provided by the present invention, a ground interconnect structure 101 is at least partially disposed around the periphery of a chip 20. The surface of the chip 20 has a plurality of ground pads 201 and a plurality of power pads 202. The plurality of ground pads 201 are electrically connected to the ground interconnect structure 101 through corresponding first bonding wires 301. The power interconnect structure 102 is at least partially disposed around the periphery of the chip 20. At least a portion of one of the power interconnect structure 102 and the ground interconnect structure 101 is disposed around the periphery of the other. The plurality of power pads 202 are electrically connected to the power interconnect structure 102 through corresponding second bonding wires 302. A first insulating connection structure 103 connects the ground interconnect structure 101 and the power interconnect structure 102. A plurality of pins 105 are disposed on the outer side of the power interconnect structure 102 and the ground interconnect structure away from the chip and include a power pin 105a. The power pin 105a and the power interconnect structure 102 are connected through a third bonding wire 303. This design change to the leadframe 10 allows multiple ground pads 201 to be led out through the ground interconnect structure 101, and multiple power pads 202 to be led out through the power interconnect structure 102. This improves issues such as increased current density and uneven heat distribution, enhances the ESD protection capability of the package structure, improves the current paths of VDD and VSS, and helps improve the stability of the power supply. Compared to pins 105, the ground interconnect structure 101 and the power interconnect structure 102 have a larger area, which can reduce the resistance and inductance of the VDD and VSS paths, helping to reduce voltage drop and signal interference, and optimize the electrical performance of the package structure. The leadframe provided by this invention has a wide range of applications, such as LQFP, QFN, SOIC, etc., and has broad market application prospects.

[0061] The present invention also provides a packaging structure, the packaging structure including the lead frame 10 described above and a chip 20 mounted on the lead frame 10. The structure and features of the lead frame 10 and the chip 20 are as described above, and will not be repeated here.

[0062] refer to Figure 7 As shown, the package structure may also include a decoupling capacitor 50, which is mounted on the lead frame 10 and extends from the edge region of the ground interconnect structure 101 across the first insulating connection structure 103 to the edge region of the power interconnect structure 102. One end of the decoupling capacitor 50 is in contact with the ground interconnect structure 101, and the other end of the decoupling capacitor 50 is in contact with the power interconnect structure 102.

[0063] refer to Figures 2 to 6As shown, the packaging structure may further include a molding compound 40, which encapsulates the end of the pin 105 near the chip 20, the chip 20, the bonding wires, the ground interconnect structure 101, the power interconnect structure 102, and the first insulating connection structure 103, with the end of the pin 105 away from the chip 20 exposed in the molding compound 40. Exemplarily, the material of the molding compound 40 includes, but is not limited to, epoxy molding compound.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A leadframe, characterized by, include: A ground interconnect structure is at least partially arranged around the periphery of a chip, the surface of which has multiple ground pads and multiple power pads, and the multiple ground pads are electrically connected to the ground interconnect structure through corresponding first bonding wires; A power interconnect structure is at least partially disposed around the periphery of the chip, and at least partially disposed around the periphery of one of the power interconnect structure and the ground interconnect structure, and a plurality of power pads are electrically connected to the power interconnect structure via corresponding second bonding wires; A first insulating connection structure connects the grounding interconnection structure and the power interconnection structure; as well as Multiple pins are disposed on the outer side of the power interconnect structure and the ground interconnect structure away from the chip, including power pins, which are electrically connected to the power interconnect structure via a third bonding wire.

2. The leadframe of claim 1, wherein, The first insulating connection structure is one of a pre-encapsulated body, insulating tape, or a multi-layer composite structure.

3. The leadframe of claim 1, wherein, The power interconnect structure is at least partially arranged around the periphery of the ground interconnect structure.

4. The leadframe of claim 3, wherein, The grounding interconnect structure is arranged around the periphery of the chip; the lead frame also includes a second insulating connection structure, which connects the grounding interconnect structure and the chip.

5. The leadframe of claim 4, wherein, The first insulating connection structure and the second insulating connection structure are one of the following: a pre-encapsulated body, insulating tape, or a multi-layer composite structure.

6. The leadframe of claim 4, wherein, The first insulating connection structure fills the gap between the ground interconnect structure and the power interconnect structure, and extends to cover a portion of the top and bottom surfaces of the ground interconnect structure and a portion of the top and bottom surfaces of the power interconnect structure; the second insulating connection structure fills the gap between the ground interconnect structure and the chip, and extends to cover a portion of the top and bottom surfaces of the ground interconnect structure and a portion of the top and bottom surfaces of the chip.

7. The leadframe of claim 4, wherein, The first insulating connection structure and the second insulating connection structure are connected to form an insulating connection body, and the chip, the ground interconnection structure and the power interconnection structure are located on the insulating connection body.

8. The lead frame as described in claim 3, characterized in that, The lead frame further includes a chip carrier structure and a second insulating connection structure; the grounding interconnect structure is arranged around the periphery of the chip carrier structure, and the chip is mounted on the chip carrier structure; the second insulating connection structure connects the grounding interconnect structure and the chip carrier structure.

9. The lead frame as described in claim 3, characterized in that, The grounding interconnect structure carries the chip, the chip is mounted on the central region of the grounding interconnect structure, and one end of the first bonding wire is disposed on the edge region of the grounding interconnect structure.

10. The lead frame as described in claim 3, characterized in that, The power interconnect structure, the first insulation connection structure, and the ground interconnect structure are stacked from bottom to top, and the chip is disposed on the ground interconnect structure.

11. The lead frame as claimed in claim 1, characterized in that, The top surface of the grounding interconnection structure and the top surface of the power interconnection structure are located on the same horizontal plane.

12. The lead frame as claimed in claim 1, characterized in that, The first insulating connection structure is provided with at least one decoupling capacitor. One end of the decoupling capacitor is electrically connected to the grounding interconnection structure, and the other end of the decoupling capacitor is electrically connected to the power supply interconnection structure.

13. The lead frame as described in claim 1, characterized in that, The plurality of pins includes a ground pin, and the ground interconnect structure is electrically connected to the ground pin via a fourth bonding wire.

14. The lead frame as described in claim 13, characterized in that, The number of the fourth bonding wires is less than the number of the first bonding wires, and / or the number of the third bonding wires is less than the number of the second bonding wires.

15. A packaging structure, characterized in that, Includes a chip and a lead frame as described in any one of claims 1 to 14.

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