Packaging structure
By embedding passive components within the package structure to form passive power filters and decoupling capacitors, the problems of large PCB area occupied by passive components and high-frequency noise radiation are solved, achieving the effects of reducing electromagnetic interference and improving electromagnetic compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GIGADEVICE SEMICON (BEIJING) INC
- Filing Date
- 2025-05-13
- Publication Date
- 2026-05-26
AI Technical Summary
In existing technologies, passive devices occupy a large PCB area and generate radiated noise at high frequencies due to the antenna effect, which affects EMC.
By embedding passive components within the package structure, electrically connecting them to the chip pads via a lead frame, and encapsulating them with a plastic package, passive power filters and decoupling capacitors are formed, shortening interconnection distances and reducing electromagnetic interference.
It significantly reduces PCB layout space, lowers parasitic inductance in high-frequency signal paths, reduces magnetic field radiation, improves electromagnetic compatibility, and solves the bottleneck of multi-power domain chip design.
Smart Images
Figure CN224290627U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of packaging technology, and in particular to a packaging structure. Background Technology
[0002] Currently, passive components such as decoupling capacitors and inductors are typically mounted on PCBs (Printed Circuit Boards) to address the increasingly serious EMI (Electromagnetic Interference) problem. With the stringent size and weight requirements of mobile devices, the Internet of Things (IoT), and wearable devices, the issue of passive components occupying PCB space is becoming increasingly prominent. Furthermore, passive components often require long PCB traces to connect to chips; these traces can create an "antenna effect" at high frequencies, generating radiated noise and easily coupling with external interference, thus affecting EMC (Electromagnetic Compatibility). Utility Model Content
[0003] One of the purposes of this invention is to provide a packaging structure that can prevent passive components from occupying PCB area, reduce electromagnetic interference, and improve electromagnetic compatibility.
[0004] To achieve the above objectives, this utility model provides a packaging structure. The packaging structure includes: a lead frame including at least two solder pads; a chip with its back side mounted on the lead frame and its front side having multiple solder pads, at least a portion of the solder pads of the lead frame being electrically connected to the solder pads of the chip via bonding wires; at least one passive device disposed between and electrically connected to the two solder pads; and a molding compound encapsulating the chip and the bonding wires, and covering at least a portion of the surfaces of the solder pads and at least a portion of the surface of the passive device.
[0005] Optionally, the lead frame includes a chip carrier pad and a power ring, the power ring being disposed around the chip carrier pad and including at least one of the pads; the chip is mounted on the chip carrier pad, the front side of the chip having multiple power pads, at least a portion of the power pads being connected to the power ring via a first bonding wire.
[0006] Optionally, the at least one passive device includes a plurality of first passive devices; the power ring includes a plurality of pads arranged around and spaced apart from the chip carrier pads, and adjacent pads of the power ring are electrically connected through the first passive devices.
[0007] Optionally, the first passive device is an inductor or a ferrite bead.
[0008] Optionally, the first passive device is soldered onto two adjacent pads of the power ring.
[0009] Optionally, for two adjacent solder pads of the power ring, each solder pad has an L-shaped groove at its end closest to each other, with the openings of the two L-shaped grooves facing each other, and the two solder ends of the first passive device are respectively soldered into the two L-shaped grooves.
[0010] Optionally, the lead frame includes multiple power rings, each power ring surrounding the chip carrier pad and each including at least one of the pads. Each power ring is connected to a corresponding power pad via the first bonding wire, wherein the voltage of the power networks corresponding to the multiple power rings is different.
[0011] Optionally, the lead frame includes a plurality of grounding rings, each grounding ring being an annular pad surrounding the chip-carrying pad; the front side of the chip has a plurality of grounding pads, and one of the grounding rings is connected to at least a portion of the grounding pads via a second bonding wire; the grounding ring is adjacent to at least one power ring, and the at least one passive device includes a plurality of decoupling capacitors, the decoupling capacitors being disposed between adjacent power rings and grounding rings and connecting adjacent power rings and grounding rings.
[0012] Optionally, a power ring is provided on both the inner and outer sides of one of the grounding rings, and the grounding ring is connected to the power rings on both sides of it through the decoupling capacitor.
[0013] Optionally, the molding compound covers the sidewalls and top surface of the chip carrier pads, the power ring, and the ground ring, and exposes the bottom surface of the chip carrier pads, the power ring, and the ground ring.
[0014] Optionally, the decoupling capacitor is soldered onto the power ring and the ground ring.
[0015] Optionally, at least a portion of the ground pad on the front side of the chip is connected to the chip carrier pad via a third bonding wire; the chip carrier pad and the power ring adjacent to the chip carrier pad are electrically connected via a decoupling capacitor.
[0016] In the packaging structure provided in this application, the lead frame includes at least two solder pads. The back of the chip is mounted on the lead frame, and the front of the chip has multiple solder pads. At least a portion of the solder pads of the lead frame are electrically connected to the solder pads of the chip via bonding wires. Passive devices are disposed between the two solder pads of the lead frame and are electrically connected to the two solder pads. The molding compound encapsulates the chip and bonding wires, covers at least a portion of the surface of the solder pads and at least a portion of the surface of the passive devices. That is, the passive devices are disposed within the packaging structure, specifically embedded inside the molding compound. This avoids mounting passive devices on the PCB outside the packaging structure, which can significantly reduce the PCB layout space. Moreover, directly embedding passive devices inside the packaging structure can greatly shorten the interconnection distance between the passive devices and the chip, reduce the current loop area, reduce the parasitic inductance of the high-frequency signal path, reduce magnetic field radiation (i.e., reduce electromagnetic interference), improve high-frequency performance, and reduce coupling with external interference, thus improving electromagnetic compatibility.
[0017] Furthermore, the lead frame includes multiple power rings, each of which is arranged around the chip carrier pad. Each power ring is connected to the corresponding power pad of the chip via a first bonding wire. The power networks corresponding to the multiple power rings have different voltages, which can solve the bottleneck of multi-power domain chip design and meet the needs of multiple power domains of the chip.
[0018] Furthermore, the power ring and ground ring, and / or the power ring and chip carrier pads are connected by decoupling capacitors, which are housed within the plastic package. This allows the decoupling capacitors to be placed close to the chip's power pads, which helps to bypass high-frequency noise, quickly absorb chip switching noise (such as transient current), prevent noise from being conducted to external circuits through the power / ground plane, and reduce power impedance, providing a low-impedance path to suppress power voltage fluctuations over a wide frequency band.
[0019] Furthermore, the power ring includes multiple pads arranged around and spaced apart from the chip's carrier pads. Adjacent pads of the power ring are electrically connected through a first passive device, which is an inductor or a ferrite bead. This allows the formation of a passive power filter (LC power filter) within the package structure, which can suppress high-frequency harmonics and filter out high-frequency noise on the signal lines to reduce radiated emissions. Attached Figure Description
[0020] Figure 1 This is a top view of the packaging structure provided in an embodiment of the present invention.
[0021] Figure 2 This is a cross-sectional schematic diagram of the packaging structure provided in an embodiment of the present invention.
[0022] Figure 3 This is a top view of the packaging structure provided in another embodiment of the present invention.
[0023] Figure 4 A cross-sectional view of the packaging structure provided in another embodiment of this utility model.
[0024] Figure 5 This is a cross-sectional schematic diagram showing the connection between the first passive device and the power supply ring in one embodiment of the present invention.
[0025] Figure 6 This is a cross-sectional schematic diagram showing the connection between the decoupling capacitor, the power supply loop, and the grounding loop in one embodiment of the present invention.
[0026] Figure reference numerals: 100-solder pad; 101-chip carrier pad; 102-power ring; 102a-first power ring; 102b-second power ring; 103-ground ring; 104-pin; 200-chip; 301-first bonding wire; 302-second bonding wire; 303-third bonding wire; 304-fourth bonding wire; 400-molding package. Detailed Implementation
[0027] The packaging structure proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.
[0028] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly stated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly stated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly stated.
[0029] Figure 1 This is a top view of the packaging structure provided in an embodiment of the present invention. Figure 2 This is a cross-sectional schematic diagram of the packaging structure provided in an embodiment of the present invention.
[0030] refer to Figure 1 and Figure 2 As shown, the packaging structure provided in this application includes a lead frame, a chip 200, at least one passive device, and a molding compound 400. The lead frame includes at least two solder pads. The back side of the chip 200 is mounted on the lead frame, and the front side of the chip 200 has multiple pads (not shown). At least a portion of the solder pads of the lead frame are electrically connected to the pads of the chip 200 via bonding wires. The passive device (including a first passive device 201 and / or a decoupling capacitor 202) is disposed between the two solder pads of the lead frame and electrically connected to the two solder pads. The molding compound 400 encapsulates the chip 200 and the bonding wires, and covers at least a portion of the surface of the solder pads of the lead frame and at least a portion of the surface of the passive device.
[0031] In this embodiment, reference Figure 2 As shown, the lead frame may include a chip carrier pad 101 and a power ring 102. The power ring 102 is disposed around the chip carrier pad 101 and includes at least one pad. The back side of the chip 200 is mounted on the chip carrier pad 101, and the front side of the chip 200 has multiple power pads. At least some of the power pads are connected to the power ring 102 via corresponding first bonding wires 301. Exemplarily, the chip 200 may be mounted on the chip carrier pad 101 via an adhesive layer 201, which includes, but is not limited to, resin adhesive.
[0032] In this embodiment, as Figure 1 and Figure 2 As shown, the lead frame may also include multiple pins 104, which are arranged around the chip carrier pads 101 and the power ring 102. Specifically, they are arranged around the chip carrier pads 101 and the power ring 102.
[0033] For example, the power ring 102 can also be connected to the corresponding pin 104 via a fifth bonding wire (not shown). It should be noted that the power ring 102 surrounds the chip carrier pad 101. Multiple power pads on the front side of the chip 200 can be connected to the power ring 102 via corresponding first bonding wires 301. The power ring 102 is then connected to the corresponding pin 104 via a fifth bonding wire. This allows multiple power pads of the chip 200 to be connected to the corresponding pins 104. The number of power pads can be led out without being limited by pin resources, and the leading out of the power pads is not limited by their placement, thus improving power integrity.
[0034] Figure 5 This is a cross-sectional schematic diagram showing the connection between a first passive device and a power loop according to an embodiment of the present invention. In one embodiment of this application, reference is made to… Figure 1 , Figure 2 and Figure 5As shown, at least one passive device may include a plurality of first passive devices 201, and the power ring 102 may include a plurality of pads 100 arranged around the chip carrier pads 101 and spaced apart. Two adjacent pads 100 of the power ring 102 are electrically connected through the first passive devices 201, and all the pads 100 of the power ring 102 can be connected into a closed circuit by the plurality of first passive devices 201.
[0035] For example, refer to Figure 1 As shown, the power ring 102 may include four solder pads, with adjacent solder pads connected by a first passive device 201. Thus, the power ring 102 has four first passive devices 201, but is not limited to this. The number of solder pads included in the power ring 102 and the number of first passive devices 201 disposed on the power ring 102 can be designed as needed. For example, the first passive device 201 is an inductor or a ferrite bead.
[0036] It should be noted that the two adjacent pads of the power ring 102 are electrically connected through the first passive device 201, which can form a passive power filter (LC power filter) within the package structure, which can suppress high-frequency harmonics and filter out high-frequency noise on the signal line to reduce radiated emissions.
[0037] In one embodiment of this application, the lead frame may include multiple power rings 102, each power ring 102 being arranged around the chip carrier pad 101 and each including at least one pad. Each power ring 102 is connected to a corresponding power pad via a first bonding wire 301. The voltages of the power networks corresponding to the multiple power rings 102 are different, which can solve the bottleneck of multi-power domain chip design and meet the needs of more than 200 power domains of the chip.
[0038] For example, refer to Figure 1 and Figure 2 As shown, the lead frame includes a first power ring 102a and a second power ring 102b. The first power ring 102a surrounds the periphery of the chip carrier pad 101, and the second power ring 102b surrounds the periphery of the first power ring 102a, but is not limited thereto. The number of power rings in the lead frame can be set as needed.
[0039] In this embodiment, adjacent pads of each power ring 102 of the lead frame are electrically connected via a first passive device 201, which improves the suppression of high-frequency harmonics and the filtering of high-frequency noise. In other embodiments, the first passive device 201 can be provided on some power rings 102 as needed. It should be noted that if the first passive device 201 is not required on the power ring 102, the power ring 102 can be a continuous annular pad, in which case there are no breaks in the power ring 102.
[0040] In one embodiment of this application, the first passive device 201 can be welded to two adjacent pads of the power ring 102 using a laser welding process, but is not limited thereto. Specifically, refer to... Figure 5 As shown, for two adjacent solder pads of the power ring 102, L-shaped grooves are provided at the ends of the two solder pads that are close to each other. The openings of the two L-shaped grooves are opposite to each other. The two solder ends of the first passive device 201 are respectively soldered into the two L-shaped grooves. In this way, by setting L-shaped grooves on the solder pads to solder the first passive device 201, the soldering reliability of the first passive device 201 is improved.
[0041] In one embodiment of this application, reference is made to... Figure 1 and Figure 2 As shown, the lead frame may also include several grounding rings 103, which are annular pads surrounding the chip carrier pads 101. The front side of the chip 200 has multiple grounding pads. One grounding ring 103 is connected to at least a portion of the grounding pads via a second bonding wire 302. This allows multiple grounding pads of the chip 200 to be connected to the grounding ring 103. The number of grounding pads is not limited by pin resources, and the grounding pads are not limited by their location. As a result, static charge can be effectively discharged through the grounding (VSS) circuit, which helps to enhance the static charge discharge capability of the package structure and improve the electrostatic discharge protection performance of the package structure.
[0042] Continue to refer to Figure 1 and Figure 2 As shown, ground ring 103 and at least one power ring 102 are adjacent. The passive components in the package structure may include several decoupling capacitors 202. The decoupling capacitors 202 are disposed between adjacent power rings 102 and ground rings 103 and connected to adjacent power rings 102 and ground rings 103. Thus, the decoupling capacitors 202 can be disposed within the molding compound 400 and can be placed close to the power pads of the chip 200, which helps to achieve high-frequency noise bypass, quickly absorb chip switching noise (such as transient current), prevent noise from being conducted to external circuits through the power / ground plane, and at the same time reduce power supply impedance, providing a low-impedance path to suppress power supply voltage fluctuations over a wide frequency band.
[0043] It should be noted that the grounding ring 103 and the adjacent power ring 102 can be connected by one or more decoupling capacitors 202, and the specific number of decoupling capacitors 202 can be set as needed.
[0044] In one embodiment, reference Figure 1 and Figure 2As shown, a power ring 102 is provided on both the inner and outer sides of a grounding ring 103, that is, the grounding ring 103 is located between two adjacent power rings 102, and the grounding ring 103 can be connected to the power rings 102 on both sides of it through a decoupling capacitor 202.
[0045] In one embodiment, at least a portion of the ground pad on the front side of the chip 200 can be connected to the chip carrier pad 101 via a third bonding wire 303, and the first power ring 102a adjacent to the chip carrier pad 101 and the chip carrier pad 101 can be connected via a plurality of decoupling capacitors 202.
[0046] For example, the lead frame material can be a metal, such as one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The bonding wire material includes metals or metal alloys such as gold, silver, copper, or aluminum.
[0047] In one embodiment of this application, the decoupling capacitor 202 can be welded to the pads of the power ring 102 and the ground ring 103 using a laser welding process. Exemplarily, the decoupling capacitor 202 can be a miniature multilayer ceramic capacitor, but is not limited thereto.
[0048] Figure 6 This is a cross-sectional schematic diagram showing the connection between the decoupling capacitor, the power supply loop, and the ground loop according to an embodiment of the present invention. Specifically, refer to... Figure 6 As shown, for adjacent power ring 102 and ground ring 103, the power ring 102 and the ground ring 103 have a pair of L-shaped grooves with corresponding positions and opposite openings. One of the pair of L-shaped grooves is disposed on the power ring 102 and the other is disposed on the ground ring 103. The two solder ends of the decoupling capacitor 202 are respectively soldered in the two L-shaped grooves, which helps to improve the soldering reliability of the decoupling capacitor 202.
[0049] Continue to refer to Figure 2 As shown, the front side of the chip 200 may also have multiple signal input / output pads (not shown), and the signal input / output pads can be connected to the corresponding pins 104 via the fourth bonding wire 304.
[0050] refer to Figure 2 As shown, in one embodiment, the molding compound 400 of the package structure covers the sidewalls and top surface of the chip carrier pad 101, power ring 102, and ground ring 103, and exposes the bottom surface of the chip carrier pad 101, power ring 102, and ground ring 103. This makes the chip carrier pad 101 an exposed pad, which is beneficial for chip heat dissipation and also facilitates the soldering of the power ring 102 and ground ring 103 onto the PCB. In other embodiments, the molding compound 400 may also cover the bottom surface of the chip carrier pad 101, the bottom surface of the power ring 102, and / or the bottom surface of the ground ring 103.
[0051] refer to Figure 2 As shown, in one embodiment, the package structure can be a QFN (Quad Flat No-leads Package), in which multiple pins 104 of the lead frame do not extend from the sidewalls of the molding compound 400. The molding compound 400 covers the top surface and sidewalls of the pins 104 and exposes the bottom surface of the pins 104. Exemplarily, the bottom surface of the chip carrier pad 101, the bottom surface of the power ring 102, the bottom surface of the ground ring 103, and the bottom surfaces of the multiple pins 104 can be located in the same plane, which facilitates soldering, but is not limited thereto.
[0052] Figure 3 This is a top view of the packaging structure provided in another embodiment of the present invention. Figure 4 This is a cross-sectional schematic diagram of a packaging structure provided according to another embodiment of the present invention. In one embodiment, reference is made to... Figure 3 and Figure 4 As shown, the package structure can be an LQFP (Low-profile Quad Flat Package), where the molding compound 400 encloses the end of the pin 104 near the chip 200, and the end of the pin 104 away from the chip 200 extends from the sidewall of the molding compound 400. For example, the end of the pin 104 away from the chip 200 extends into the plane containing the bottom surface of the chip-carrying pad 101, the bottom surface of the power ring 102, and the bottom surface of the ground ring 103.
[0053] In the packaging structure provided in this application, the lead frame includes at least two pads. The back side of the chip 200 is mounted on the lead frame, and the front side of the chip 200 has multiple pads. At least a portion of the pads of the lead frame are electrically connected to the pads of the chip 200 via bonding wires. Passive devices are disposed between the two pads of the lead frame and are electrically connected to the two pads. The molding compound 400 encapsulates the chip 200 and the bonding wires, covers at least a portion of the surface of the pads and at least a portion of the surface of the passive devices. That is, the passive devices are disposed within the packaging structure, specifically embedded inside the molding compound 400. This avoids mounting passive devices on the PCB outside the packaging structure, which can significantly reduce the PCB layout space. Moreover, directly embedding passive devices inside the packaging structure can greatly shorten the interconnection distance between the passive devices and the chip, reduce the current loop area, reduce the parasitic inductance of the high-frequency signal path, reduce magnetic field radiation (i.e., reduce electromagnetic interference), improve high-frequency performance, and reduce coupling with external interference, thus improving electromagnetic compatibility.
[0054] Furthermore, the lead frame includes multiple power rings 102, all of which are arranged around the chip carrier pad 101. Each power ring 102 is connected to the corresponding chip power pad through a first bonding wire. The power networks corresponding to the multiple power rings 102 have different voltages, which can solve the bottleneck of multi-power domain chip design and meet the needs of multiple power domains of the chip.
[0055] Furthermore, the power ring 102 and the ground ring 103, and / or the power ring 102 and the chip carrier pad 101 are connected by a decoupling capacitor 202, and the decoupling capacitor 202 is disposed inside the molding compound 400. Thus, the decoupling capacitor 202 can be placed close to the power pad of the chip 200, which helps to achieve high-frequency noise bypass, quickly absorb chip switching noise (such as transient current), prevent noise from being conducted to external circuits through the power / ground plane, and at the same time reduce the power impedance, providing a low impedance path to suppress power voltage fluctuations in a wide frequency band.
[0056] Furthermore, the power ring 102 includes a plurality of pads arranged and spaced apart around the chip carrier pad 101. Adjacent pads of the power ring 102 are electrically connected through a first passive device 201, which is an inductor or a ferrite bead. This allows a passive power filter (LC power filter) to be formed within the package structure, which can suppress high-frequency harmonics and filter out high-frequency noise on the signal line to reduce radiated emissions.
[0057] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.
Claims
1. A packaging structure, characterized in that, include: A lead frame, the lead frame comprising at least two solder pads; The chip has its back side mounted on the lead frame, and its front side has multiple pads. At least a portion of the pads of the lead frame are electrically connected to the pads of the chip via bonding wires. At least one passive device is disposed between and electrically connected to the two said solder pads; as well as A molding compound that encapsulates the chip and the bonding wires, and covers at least a portion of the surface of the solder pads and at least a portion of the surface of the passive device.
2. The packaging structure as described in claim 1, characterized in that, The lead frame includes a chip carrier pad and a power ring. The power ring is arranged around the chip carrier pad and includes at least one of the pads. The chip is mounted on the chip carrier pad. The front side of the chip has multiple power pads, and at least some of the power pads are connected to the power ring via a first bonding wire.
3. The packaging structure as described in claim 2, characterized in that, The at least one passive device includes a plurality of first passive devices; the power ring includes a plurality of pads arranged around the chip carrier pads and spaced apart, and adjacent pads of the power ring are electrically connected through the first passive devices.
4. The packaging structure as described in claim 3, characterized in that, The first passive device is an inductor or a ferrite bead.
5. The packaging structure as described in claim 3, characterized in that, The first passive device is soldered onto two adjacent pads of the power ring.
6. The packaging structure as described in claim 5, characterized in that, For the two adjacent solder pads of the power ring, each solder pad has an L-shaped groove at its end closest to each other, and the openings of the two L-shaped grooves face each other. The two solder ends of the first passive device are respectively soldered into the two L-shaped grooves.
7. The packaging structure as described in claim 2, characterized in that, The lead frame includes multiple power rings, each power ring surrounding the chip carrier pad and each including at least one of the pads. Each power ring is connected to a corresponding power pad via the first bonding wire, wherein the voltage of the power network corresponding to the multiple power rings is different.
8. The packaging structure as described in claim 7, characterized in that, The lead frame includes several grounding rings, each grounding ring being an annular pad surrounding the chip's bonding pads; the front side of the chip has multiple grounding pads, and one grounding ring is connected to at least a portion of the grounding pads via a second bonding wire; the grounding ring is adjacent to at least one power ring, and the at least one passive device includes several decoupling capacitors, which are disposed between adjacent power rings and grounding rings and connected to adjacent power rings and grounding rings.
9. The packaging structure as described in claim 8, characterized in that, The grounding ring has power rings on both its inner and outer sides, and the grounding ring is connected to the power rings on both sides of it through the decoupling capacitor.
10. The packaging structure as described in claim 8, characterized in that, The molding compound covers the sidewalls and top surface of the chip carrier pads, the power ring, and the ground ring, and exposes the bottom surface of the chip carrier pads, the power ring, and the ground ring.
11. The packaging structure as described in claim 8, characterized in that, The decoupling capacitor is soldered onto the power ring and the ground ring.
12. The packaging structure as described in claim 2, characterized in that, At least a portion of the ground pad on the front side of the chip is connected to the chip carrier pad via a third bonding wire; the chip carrier pad and the power ring adjacent to the chip carrier pad are electrically connected via a decoupling capacitor.