Electronic device, interposer and method of manufacturing thereof

Abstract

This disclosure provides an electronic device, an intermediate component, and a method for manufacturing the same. The intermediate component includes a packaging structure. The packaging structure includes a plurality of connection units, a first packaging layer, and a first circuit structure. The plurality of connection units are spaced apart from each other and arranged in an array, wherein each connection unit includes a substrate layer and a first conductive element disposed in the substrate layer. The first packaging layer surrounds the plurality of connection units. The first circuit structure is disposed on a first side of the first packaging layer and electrically connected to the plurality of connection units.

Description

Technical Field

[0001] This disclosure relates to an electronic device, a middleware, and a method of manufacturing the same, and more particularly to an electronic device, a middleware, and a method of manufacturing the same that helps improve reliability. Background Technology

[0002] As electronic devices continue to evolve towards lighter, thinner, shorter, and smaller designs, and as users' performance requirements for these devices continue to increase, the integration density of various electronic components (such as chips) within these devices also needs to increase accordingly. Generally, various electronic components and / or packages containing various electronic components typically have different wiring densities, spacing, or dimensions, and in some cases, they may not be compatible. Therefore, placing various electronic components and / or packages containing various electronic components on an interposer substrate, or adding one or more interposer substrates between them, is one way to address these issues.

[0003] However, the coefficient of thermal expansion (CTE) of various electronic components and / or packages containing various electronic components may not be compatible with the materials used in the substrate in some cases. This can cause thermal stress generated during subsequent high-temperature processes such as reflow soldering to damage the various electronic components and / or packages containing various electronic components (e.g., cracks), making it difficult to meet the reliability requirements of electronic devices now or in the future.

[0004] Therefore, those skilled in the art continue to improve the reliability of electronic devices to meet current and future requirements. Summary of the Invention

[0005] This disclosure provides an electronic device, an intermediate component, and a method for manufacturing the same, which can help improve the reliability of the electronic device.

[0006] According to embodiments of this disclosure, the intermediate includes a packaging structure. The packaging structure includes a plurality of connection units, a first packaging layer, and a first circuit structure. The plurality of connection units are spaced apart from each other and arranged in an array, wherein each connection unit includes a substrate layer and a first conductive element disposed in the substrate layer. The first packaging layer surrounds the plurality of connection units and includes portions disposed between the plurality of connection units. The first circuit structure is disposed on a first side of the first packaging layer and electrically connected to the plurality of connection units.

[0007] According to embodiments of this disclosure, an electronic device includes an intermediary, a plurality of electronic units, and an external component. The intermediary includes an encapsulation structure and a second circuit structure. The encapsulation structure includes a plurality of connection units, a first encapsulation layer, and a first circuit structure. The plurality of connection units are spaced apart from each other and arranged in an array, wherein each connection unit includes a substrate layer and a first conductive element disposed in the substrate layer. The first encapsulation layer encapsulates the plurality of connection units and includes portions disposed between the plurality of connection units. The first circuit structure is disposed on a first side of the first encapsulation layer and electrically connected to the plurality of connection units. The second circuit structure is disposed on a second side of the first encapsulation layer opposite to the first side and electrically connected to the plurality of connection units. The plurality of electronic units are disposed on the second circuit structure and electrically connected to the second circuit structure. The external component is disposed under the first circuit structure and electrically connected to the first circuit structure.

[0008] According to embodiments of this disclosure, a method for manufacturing an intermediary includes the following steps: A plurality of connection units are arranged in an array on a first circuit structure, wherein the plurality of connection units are electrically connected to the first circuit structure, and each connection unit includes a substrate layer and a first conductive element disposed in the substrate layer. A first underfill is provided between the first circuit structure and the substrate layer. A first encapsulation layer is provided on the first underfill to encapsulate the plurality of connection units to form an encapsulation structure, wherein the first encapsulation layer includes portions formed between the plurality of connection units.

[0009] Based on the above, in the embodiments of this disclosure, the first encapsulation layer encapsulates a plurality of connection units spaced apart from each other and arranged in an array, and includes portions disposed between the plurality of connection units. This can mitigate the difference in coefficient of thermal expansion (CTE) between the base layer of the connection unit and other various electronic components and / or various packages containing various electronic components, thereby helping to improve the reliability of the intermediary and / or the electronic device containing the intermediary.

[0010] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings are included to further illustrate this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figures 1 to 5B This is a schematic diagram of a method for manufacturing an electronic device according to a first embodiment of the present disclosure;

[0013] Figure 6 This is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present disclosure;

[0014] Figure 7A and Figure 7B These are, respectively, a cross-sectional view and a top view of an electronic device according to a third embodiment of the present disclosure;

[0015] Figure 8 This is a cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present disclosure; and

[0016] Figures 9A to 9C This is a cross-sectional schematic diagram of an intermediary according to different embodiments of the present disclosure. Detailed Implementation

[0017] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure show only a portion of the semiconductor package, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. For example, for clarity, the relative dimensions, thicknesses, and locations of various film layers, regions, and / or structures may be reduced or enlarged.

[0018] Certain terms are used throughout this specification and the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "having" and "comprising" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0019] In this document, the phrase "one element is disposed on another element" is used to conveniently describe the relative position between the element and the other element, and is not intended to define the process steps or sequence of the element and the other element.

[0020] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting this disclosure. It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, the element or membrane may be directly on or directly connected to the other element or membrane, or there may be an inserted element or membrane between them (in a non-direct case). Conversely, when an element or membrane is referred to as being "directly" on or "directly connected" to another element or membrane, there is no inserted element or membrane between them. Furthermore, when an element or membrane is referred to as overlapping another element, the element or membrane at least partially overlaps with the other element or membrane.

[0021] The terms “about,” “approximately,” “substantially,” or “roughly” used in this document generally mean falling within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Furthermore, the phrases “given range is from a first value to a second value” or “given range falls within the range of a first value to a second value” indicate that the given range includes the first value, the second value, and other values ​​in between.

[0022] In some embodiments of this disclosure, terms such as “connection” and “interconnection” are used to refer to two structures in direct contact, or two structures that are not in direct contact but have other structures disposed between them, unless otherwise defined. Terms such as “connection” and “interconnection” can also include situations where both structures are movable or both structures are fixed. Furthermore, the terms “electrical connection” and “coupling” encompass any direct or indirect electrical connection means.

[0023] In the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals, and their descriptions will be omitted. Furthermore, features in different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it, and simple equivalent changes and modifications made in accordance with this specification or claims are still within the scope of this disclosure. That is, the embodiments described below can be completed by replacing, recombining, or mixing technical features in several different embodiments without departing from the spirit of this disclosure. In addition, the terms "first," "second," etc., mentioned in this specification or claims are only used to name different elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor are they used to limit the manufacturing order or installation order of the elements.

[0024] In this disclosure, the thickness, length and width may be measured selectively using an optical microscope (OM) and / or an electron microscope such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM), but are not limited thereto.

[0025] The electronic devices described in this disclosure can be applied, for example, to wafer-level package (WLP) processes, such as chip-on-wafer-on-substrate (CoWoS) technology, but are not limited thereto. Alternatively, they can be applied to panel-level package (PLP) processes, such as chip-on-panel-on-substrate (CoPoS) technology, but are not limited thereto. In some embodiments, the manufacturing process of the electronic devices described in this disclosure can, for example, employ a chip-last process or a chip-first process. The electronic devices described in this disclosure can be applied to high-speed computing modules, power modules, semiconductor packaging devices, optical communication modules, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but are not limited thereto.

[0026] The following examples illustrate exemplary embodiments of this disclosure, and the same element symbols are used in the drawings and description to denote the same or similar parts.

[0027] Figures 1 to 5B This is a schematic diagram of a method for manufacturing an electronic device according to a first embodiment of the present disclosure. Figure 1 , Figure 2 , Figure 3A , Figure 4 as well as Figure 5A It is a cross-sectional diagram, and Figure 3B It corresponds Figure 3A A top view schematic diagram of one embodiment, Figure 5B yes Figure 5A A top view schematic diagram of one embodiment, for example Figure 5A It corresponds to the edge Figure 5B A schematic diagram of the cross-section intercepted by line A-A'. For ease of explanation, Figure 5B Only the connection unit 100, electronic unit EU1, second encapsulation layer ML1, and conductive vias TMV1 and TMV2 are shown.

[0028] In this embodiment, electronic devices (e.g.) Figure 5A The manufacturing method of the electronic device ED1 shown may include the following steps.

[0029] First, please refer to Figure 1A carrier substrate Csub1 is provided. In some embodiments, the material of the carrier substrate Csub1 may include glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, other suitable substrate materials, or combinations thereof, but is not limited thereto. Next, an anti-warping layer WAL1 and a release layer RL1 are sequentially formed on the carrier substrate Csub1. In some embodiments, the anti-warping layer WAL1 may be a single-layer or multi-layer structure comprising organic and / or inorganic materials, wherein the inorganic materials may include silicon dioxide (SiO2), silicon nitride (SiO2), etc. x N y ), silicon oxynitride (SiO) x N y Other suitable inorganic materials, but not limited thereto. In some embodiments, the release layer RL1 may be a temporary bonding layer, which may include a thermally-type or optically-type release material with adhesive properties to temporarily adhere subsequently formed working units, elements, or films to the release layer RL1. In other words, the release layer RL1 can assist in the removal of working units, elements, or films subsequently formed on the carrier plate Csub1 from the carrier plate Csub1. When a thermally-type release material is used to form the release layer RL1, the thermally-type release material loses its adhesiveness upon heating, allowing the elements or films formed thereon to be peeled off from the release layer RL1. For example, the release layer RL1 may be a thermally-release tape (HRT) or a light-to-heat-conversion (LTHC) release coating. When an optical release material is used to form a release layer RL1, the optical release material loses its adhesiveness when exposed to radiation, such as ultraviolet light (UV light), so that the elements or films formed on it can be peeled off from the release layer RL1.

[0030] Then, a first circuit structure CS1 is provided on the release layer RL1. In this embodiment, the first circuit structure CS1 may include an insulating layer IL1 and a wiring structure WS1 formed in the insulating layer IL1. In some embodiments, the insulating layer IL1 may include a plurality of insulating layers alternately stacked in a vertical direction (e.g., the Z direction). The wiring structure WS1 may include a plurality of conductive patterns / conductive layers formed in the insulating layer IL1 and alternately stacked in a vertical direction, and conductive vias connecting the conductive patterns / conductive layers. The wiring structure WS1 may include any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but is not limited thereto. The insulating layer IL1 may contain organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), poly-p-xylylene (also known as Parylene), benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials.

[0031] Subsequently, multiple connection units 100 are arranged in an array on the first circuit structure CS1, wherein the multiple connection units 100 are electrically connected to the first circuit structure CS1. In this embodiment, the wiring structure WS1 may include pads WS1p and WS1pbf electrically connected to the multiple connection units 100, wherein the pads WS1pbf may include a test portion for detection. Thus, after the connection units 100 are arranged on the first circuit structure CS1, an electrical test can be performed by probing the test portion of the pads WS1pbf with a probe PB1 to determine whether the electrical connection between the connection units 100 and the first circuit structure CS1 meets the expected requirements. For example, region R1 may be the region where the electrical connection between the connection units 100 and the first circuit structure CS1 meets the expected requirements, while region R2 may be the region where the electrical connection between the connection units 100 and the first circuit structure CS1 does not meet the expected requirements. In other embodiments, before the connection unit 100 is placed on the first circuit structure CS1, the first circuit structure CS1 can also be electrically tested by probing the test portion of the pad WS1pbf with the probe PB1 to determine whether there are any parts of the first circuit structure CS1 that do not meet the expected requirements.

[0032] In this embodiment, each connection unit 100 includes a substrate layer 102 and a conductive element 104 disposed in the substrate layer 102. The substrate layer 102 may include polyimide, glass, silicon, organic materials, inorganic materials, or other suitable substrate materials. The conductive element 104 may include any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but is not limited thereto. In this embodiment, the conductive element 104 may be a through-substrate via (TSV) penetrating the substrate layer 102.

[0033] In this embodiment, each connection unit 100 may further include insulating layers 103 and 105 disposed on opposite sides of the base layer 102 in the vertical direction (e.g., the Z direction), as well as conductive elements 106 and 108. Insulating layers 103 and 105 may each comprise any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, photosensitive polyimide (PSPI), polybenzoxazole (PBO), benzocyclobutene (BCB), or a dielectric layer formed of other suitable dielectric materials, but are not limited thereto. Conductive elements 106 and 108 may each comprise any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but are not limited thereto. In some embodiments, conductive elements 106 and 108 may comprise copper pillars, but are not limited thereto.

[0034] In this embodiment, the connection unit 100 can be coupled to the first circuit structure CS1 via a connection element CE1 disposed between the conductive element 106 and the pad WS1p. The material of the connection element CE1 may include, but is not limited to, tin-silver (SnAg), tin, silver, nickel, gold, copper, conductive adhesive, or suitable conductive materials. The connection element CE1 may include solder balls. In some embodiments, the connection element CE1 may employ a C4 bump (controlled collapse chip connection bump, C4 bump).

[0035] Next, please refer to the following: Figure 1 and Figure 2 A first underfiller UF1 is provided between the first circuit structure CS1 and the substrate layer 100 to ensure a signal transmission path between the connection unit 100 and the first circuit structure CS1, thereby helping to improve the reliability of the electronic device. In this embodiment, the first underfiller UF1 may surround the conductive element 106, the connection element CE1, and the pad WS1p. In this embodiment, "one component surrounds another component" may mean that the component can at least contact the side surface of the other component in the cross-sectional view. For example, such as Figure 2 As shown, the first bottom filler UF1 can contact the side surfaces of the conductive element 106, the connecting element CE1, and the pad WS1p.

[0036] In this embodiment, as Figure 2 As shown, region R1 can be the region where the electrical connection between the connection unit 100 and the first circuit structure CS1 meets the desired requirements, while region R2 (NG) can be the region where the electrical connection between the connection unit 100 and the first circuit structure CS1 does not meet the desired requirements. In this case, the first bottom filler UF1 can be formed only in region R1 where the desired requirements are met, and not in region R2 (NG) where the desired requirements are not met, which can help save process costs.

[0037] Then, a first encapsulation layer 110 is provided on the first underfiller UF1 to surround the plurality of connection units 100 to form an encapsulation structure 10. According to some embodiments, the first encapsulation layer 110 may surround the plurality of connection units 100, with a portion of the first encapsulation layer 110 disposed in the spacing between the plurality of connection units 100. The first encapsulation layer 110 may contact at least a portion of the surfaces of the plurality of connection units 100, such as side surfaces, thereby preventing the connection units 100 from being affected by external moisture, thereby improving the reliability of the connection units 100. The first encapsulation layer 110 may include any suitable encapsulation material, such as organic materials, polymers, epoxy molding compounds (EMC), silicone, silicon-containing materials, glass encapsulation materials, or nanofiller composite resins, but is not limited thereto. In some embodiments, the first encapsulation layer 110 may be formed, for example, by a deposition process or a molding process, but is not limited thereto.

[0038] Subsequently, after forming the first encapsulation layer 110, the release layer RL1 and the carrier plate Csub2 are removed by de-adhesion. Then, the encapsulation structure 10 is flipped so that the first circuit structure CS1 faces upwards and the first encapsulation layer 110 faces the carrier plate Csub2, on which the anti-warping layer WAL2 and the release layer RL2 are sequentially formed. The anti-warping layer WAL2 may include materials listed above as anti-warping layer WAL1. The release layer RL2 may include materials listed above as release layer RL1.

[0039] Next, conductive pillars WS1pbr are formed on the first circuit structure CS1. Then, a monomerization process is performed along the dicing line SL1 to form multiple independent package structures 10. Then, after the monomerization process, the release layer RL2 and the carrier plate Csub2 (e.g., RL2) are removed by making the release layer RL2 lose its adhesiveness. Figure 3AThe encapsulation structure 10 shown. The conductive post WS1pbr may comprise any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but is not limited thereto. In some embodiments, the conductive post WS1pbr may serve as a component for subsequent probe probing to perform electrical testing.

[0040] Next, please refer to Figure 3A A second circuit structure CS2 is provided on a carrier plate Csub3 on which an anti-warping layer WAL3, a release layer RL3, and a seed layer SL1 are sequentially formed. The material of the carrier plate Csub3 may include the materials listed above for the carrier plate Csub1. The anti-warping layer WAL3 may include the materials listed above for the anti-warping layer WAL1. The release layer RL3 may include the materials listed above for the release layer RL1. The seed layer SL1 may include any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), tungsten (W), nickel (Ni), tantalum (Ta), nitrides, carbides, other suitable metals, or alloys thereof, or combinations thereof.

[0041] In this embodiment, the second circuit structure CS2 may include an insulating layer IL2 and a wiring structure WS2 formed in the insulating layer IL2. In some embodiments, the insulating layer IL2 may include a plurality of insulating layers alternately stacked in a vertical direction (e.g., the Z direction). The wiring structure WS2 may include a plurality of conductive patterns / conductive layers formed in the insulating layer IL2 and alternately stacked in a vertical direction, and conductive vias connecting the conductive patterns / conductive layers. The wiring structure WS2 may include any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials, but is not limited thereto. In some embodiments, the conductive patterns / conductive layers in the wiring structure WS2 and the conductive vias connecting the conductive patterns / conductive layers may be formed by electroplating the seed layer SL1 to grow the seed layer, but is not limited thereto. The insulating layer IL2 may contain organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials.

[0042] After that, as Figure 3A As shown, multiple conductive vias TMV1 and TMV2 are formed on the second circuit structure CS2. Next, as... Figure 3A and Figure 3BAs shown, the package structure 10 is bonded to the second circuit structure CS2 via alignment mark AM1, wherein the package structure 10 is electrically connected to the second circuit structure CS2. In this embodiment, since the conductive vias TMV1 and TMV2 are formed on the second circuit structure CS2 first, and then the package structure 10 is bonded to the second circuit structure CS2, the impact of the process of forming the conductive vias TMV1 and TMV2 on the package structure 10 can be reduced, thereby helping to improve the reliability of the package structure 10.

[0043] In some embodiments, the package structure 10, which has undergone electrical testing and meets the desired requirements, may be selectively bonded to the second circuit structure CS2 to help improve the yield and reliability of the intermediate IP1 as shown in this disclosure, as can be referred to Figure 4 , Figure 5A However, this is not a limitation. For example, one can selectively include... Figure 2 The package structure 10 in region R1 shown is bonded to the second circuit structure CS2.

[0044] In some embodiments, after the second circuit structure CS2 is formed, an electrical test can be performed on the second circuit structure CS2 using probes to determine whether the second circuit structure CS2 meets the desired requirements. For example, such as Figure 3B As shown, the second circuit structure CS2 may be a portion that meets the desired requirements after electrical testing, while the second circuit structure CS2(NG) may be a portion that does not meet the desired requirements after electrical testing. In some embodiments, the package structure 10 that meets the desired requirements after electrical testing may be selectively bonded to the second circuit structure CS2 that meets the desired requirements after electrical testing, in order to help improve, for example Figure 4 The yield and reliability of the intermediate component IP1 are shown.

[0045] In other embodiments, package structures 10 that do not meet the desired requirements after electrical testing may be selectively excluded (e.g., Figure 2 The package structure 10 in region R2(NG) shown is bonded to the second circuit structure CS2(NG) which does not meet the desired requirements after electrical testing. In this way, the package structure 10 which does not meet the desired requirements after electrical testing and is placed on the second circuit structure CS2(NG) can be used as a support structure, which helps to improve the stability of the process.

[0046] In some embodiments, conductive vias TMV1 and TMV2 may include through mold vias (TMVs). The materials of conductive vias TMV1 and TMV2 may include any suitable conductive material, such as metallic materials like copper (Cu), aluminum (Al), or silver (Ag). In some embodiments, conductive vias TMV1 and TMV2 may be copper pillars formed on the second circuit structure CS2, but are not limited thereto. In some embodiments, the height of one of the plurality of conductive vias TMV1 and TMV2 may differ from the height of another of the plurality of conductive vias TMV1 and TMV2, which may help to improve the warpage of the interposer IP1. In this embodiment, "the height of an assembly" may refer to the maximum height of the assembly measured in the vertical direction (e.g., the Z direction). For example, the height H2 of conductive via TMV2 may be greater than the height H1 of conductive via TMV1. The conductive vias described in this disclosure include copper pillars that penetrate the second encapsulation layer ML1 and extend to a portion of the second circuit structure CS2.

[0047] In this embodiment, the package structure 10 can be bonded to the second circuit structure CS2 via a connecting element CE2 disposed between the conductive element 108 and the pad WS2p. The material of the connecting element CE2 may include, but is not limited to, tin-silver (SnAg), tin, silver, nickel, gold, copper, conductive adhesive, or suitable conductive materials thereof. In some embodiments, the connecting element CE2 may include solder balls.

[0048] In this embodiment, the conductive post WS1pbr of the package structure 10 can be used as a probe for electrical testing. Thus, after the package structure 10 is placed on the second circuit structure CS2, electrical testing can be performed by probing the conductive post WS1pbr to determine whether the electrical connection between the package structure 10 and the second circuit structure CS2 meets the desired requirements (i.e., whether the formed intermediary IP1 meets the desired electrical requirements). For example, such as... Figure 4 As shown, the intermediary IP1 in region R1 can be a region where the electrical test meets the expected requirements, while the intermediary IP1 in region R2 (NG) can be a region where the electrical test does not meet the expected requirements.

[0049] Then, please refer to the following: Figure 3A and Figure 4A second underfiller UF2 is provided between the second circuit structure CS2 and the first package layer 110 to ensure a signal transmission path between the package structure 10 and the second circuit structure CS2, thereby helping to improve the reliability of the electronic device. In this embodiment, the second underfiller UF2 may surround the connecting element CE2 and the pad WS2p. In this embodiment, "one component surrounds another component" may mean that the component can at least contact the side surface of the other component in the cross-sectional view. For example, such as Figure 4 As shown, the second bottom filler UF2 can contact the side surfaces of the connecting element CE2 and the pad WS2p.

[0050] In this embodiment, as Figure 4 As shown, region R1 can be the region where the intermediate component IP1 meets the expected requirements in electrical testing, while region R2 (NG) can be the region where the intermediate component IP1 does not meet the expected requirements in electrical testing. In this case, the second bottom filler UF2 can be formed only in the region R1 that meets the expected requirements, and not in the region R2 (NG) that does not meet the expected requirements, which can help save process costs.

[0051] Then, please refer to Figure 3A and Figure 4 A second encapsulation layer ML1 is formed on the second circuit structure CS2, surrounding the encapsulation structure 10. The second encapsulation layer ML1 prevents the encapsulation structure 10 and the conductive vias TMV1 and TMV2 from being affected by external moisture, thereby improving the reliability of the intermediate IP1. The second encapsulation layer ML1 may include any suitable encapsulation material, such as organic materials, polymers, epoxy molding compounds (EMC), silicone, glass encapsulation materials, or nanofiller composite resins, but is not limited thereto. In some embodiments, the second encapsulation layer ML1 may be formed, for example, by a deposition process or a molding process, but is not limited thereto.

[0052] Subsequently, a monomerization process is performed along the dicing line SL2 to form multiple independent intermediates IP1. Then, after the monomerization process, the release layer RL3 and the carrier plate Csub3 are removed by de-adhesiveizing the release layer RL3, and the seed layer SL1 is then removed using any suitable process to form... Figure 5A The intermediary IP1 is shown.

[0053] The following will be through Figure 5A and Figure 5B The intermediary IP1 according to this embodiment will be explained. Although the intermediary IP1 of this embodiment is formed in the manner described above, it is not limited thereto.

[0054] Please refer to Figure 5AThe intermediate component IP1 includes a package structure 10. The package structure 10 includes multiple connection units 100, a first package layer 110, and a first circuit structure CS1. The multiple connection units 100 are spaced apart from each other and arranged in an array (e.g., ...). Figure 5B As shown in the diagram, in a top view, the plurality of connection units 100 can be arranged along the X or Y direction. Each connection unit 100 includes a substrate layer 102 and a first conductive element 104 disposed in the substrate layer 102. In this embodiment, one of the plurality of connection units 100 may include a plurality of second conductive elements 106, 108 respectively disposed on opposite sides of the substrate layer 100, wherein the first conductive element 104 can penetrate the substrate layer 102 to connect the plurality of second conductive elements 106, 108. A first encapsulation layer 110 encapsulates the plurality of connection units 100 and includes a portion disposed between the plurality of connection units 100. A first circuit structure CS1 is disposed on a first side 110S1 of the first encapsulation layer 110 and electrically connected to the plurality of connection units 100.

[0055] In this embodiment, the intermediary IP1 further includes a second circuit structure CS2 disposed on the package structure 10, and the second circuit structure CS2 is electrically connected to at least one of the plurality of connection units 100. In this embodiment, the second circuit structure CS2 may be disposed on the second side 110S2 of the first package layer 110 relative to the first side 110S1. The second circuit structure CS2 can be electrically connected to the first circuit structure CS1 through at least one of the plurality of connection units 100. In this embodiment, the intermediary IP1 further includes a second package layer ML1 disposed on the first side of the second circuit structure CS2 and surrounding the package structure 10, wherein the first side of the second circuit structure CS2 is adjacent to the second side 110S2 of the first package layer 110. The intermediary IP1 further includes a plurality of conductive vias TMV1, TMV2 penetrating the second package layer ML1 and electrically connected to the second circuit structure CS2. In this embodiment, the height of one of the plurality of conductive vias TMV1, TMV2 may be different from the height of the other of the plurality of conductive vias TMV1, TMV2. For example, the height H2 of the conductive via TMV2 can be greater than the height H1 of the conductive via TMV1.

[0056] In this embodiment, the plurality of connection units 100 may be spaced apart from each other by a gap, such that a portion of the first encapsulation layer 110 is disposed within the gap. This helps to mitigate the difference in the coefficient of thermal expansion (CTE) between the connection units 100 and the second circuit structure CS2, thereby improving the reliability of the interposer IP1 and / or the electronic device ED1 containing the interposer IP1. In some embodiments, the plurality of connection units 100 may have a gap of about 20 micrometers to about 1000 micrometers, or 50 micrometers to about 800 micrometers, or 100 micrometers to about 500 micrometers.

[0057] In this embodiment, the encapsulation structure 10 further includes a first underfiller UF1 disposed between the first circuit structure CS1 and the first encapsulation layer 110. In this embodiment, the intermediary IP1 further includes a second underfiller UF2 disposed between the second circuit structure CS2 and the first encapsulation layer 110. According to some embodiments, the first underfiller UF1 and the second underfiller UF2 are insulating materials, which may include organic materials, inorganic materials, or combinations thereof. The thickness variance of the first underfiller UF1 and the second underfiller UF2 is less than the thickness variance of the first encapsulation layer 110, thereby improving the quality of subsequent processes or improving the electrical performance of the electronic device. The thickness variance referred to in this disclosure can be obtained by measuring the thickness (Xi) at at least five (N) different locations and obtaining the average thickness (μ) of the thickness at these different locations, and then using a variance formula (such as Equation 1 below).

[0058] [Formula 1]

[0059]

[0060] In Equation 1, Var(X) represents the variance, σ 2 Let x represent the population variance, N represent the population size, and x represent the population variation. i Let μ represent the i-th data point in the population, and let μ represent the population mean.

[0061] The following will be through Figure 5A and Figure 5B To illustrate the electronic device ED1 according to this embodiment, the same or similar components are represented by the same or similar symbols, and will not be repeated here.

[0062] Please refer to Figure 5A The electronic device ED1 includes an intermediary IP1, multiple electronic units EU1, and external components 200.

[0063] Intermediate component IP1 includes a package structure 10 and a second circuit structure CS2. The package structure 10 includes multiple connection units 100, a first package layer 110, and the first circuit structure CS1. The multiple connection units 100 are spaced apart from each other and arranged in an array (e.g., ...). Figure 5B(As shown). Each connection unit 100 includes a substrate layer 102 and a first conductive element 104 disposed in the substrate layer 102. In this embodiment, one of the multiple connection units 100 may include multiple second conductive elements 106, 108 respectively disposed on opposite sides of the substrate layer 100, wherein the first conductive element 104 can penetrate the substrate layer 102 to connect the multiple second conductive elements 106, 108. A first encapsulation layer 110 encapsulates the multiple connection units 100 and includes a portion disposed between the multiple connection units 100. A first circuit structure CS1 is disposed on a first side of the first encapsulation layer 110 and electrically connected to the multiple connection units 100. In this embodiment, the encapsulation structure 10 further includes a first underfiller UF1 disposed between the first circuit structure CS1 and the first encapsulation layer 110. A second circuit structure CS2 is disposed on a second side of the first encapsulation layer 110 opposite to the first side and electrically connected to the multiple connection units 100.

[0064] In this embodiment, the intermediary IP1 further includes a second encapsulation layer ML1 disposed under the second circuit structure CS2 and surrounding the encapsulation structure 10, and a plurality of conductive vias TMV1 and TMV2 penetrating the second encapsulation layer ML1 and electrically connecting the second circuit structure CS2 to the external component 200. In this embodiment, the height of one of the plurality of conductive vias TMV1 and TMV2 may be different from the height of the other of the plurality of conductive vias TMV1 and TMV2. In this embodiment, the intermediary IP1 further includes a second underfill UF2 disposed between the second circuit structure CS2 and the first encapsulation layer 110.

[0065] Multiple electronic units EU1 are disposed on and electrically connected to the second circuit structure CS2. The electronic units EU1 may include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or a memory such as high bandwidth memory (HBM). The multiple electronic units EU1 may be identical or different from each other. In this embodiment, as... Figure 5B As shown, multiple electronic units EU1 can be arranged in an array on the second circuit structure CS2 of the intermediary IP1.

[0066] An external component 200 is disposed under and electrically connected to the first circuit structure CS1. In some embodiments, the external component 200 may be a circuit board (e.g., a printed circuit board), but is not limited thereto.

[0067] In this embodiment, the external component 200 can be connected to the first circuit structure CS1 via a connecting element CE3 disposed between the external component 200 and the first circuit structure CS1. In this embodiment, multiple electronic units EU1 can be connected to the second circuit structure CS2 via a connecting element CE4 disposed between the multiple electronic units EU1 and the second circuit structure CS2. Connecting elements CE3 and CE4 may each comprise, but are not limited to, tin-silver (SnAg), tin, silver, nickel, gold, copper, conductive adhesive, or suitable conductive materials thereof. In some embodiments, connecting element CE3 or connecting element CE4 may comprise solder balls or microbumps.

[0068] Figure 6 This is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present disclosure. Figure 6 The intermediate component IP1' of the electronic device ED1' shown is... Figure 5A The intermediate component IP1 of the electronic device ED1 shown is similar, with the main difference being... Figure 6 The second bottom filler UF2' shown is different Figure 5A The second bottom filler UF2 is shown. Other identical or similar components are indicated by the same or similar symbols and will not be described again here.

[0069] like Figure 6 As shown, there may be multiple second underfillers UF2' of the intermediary IP1', which are respectively disposed between the second circuit structure CS2 and the base layer 102. The second encapsulation layer ML1 may surround multiple second underfillers UF2', which can further mitigate the difference in coefficient of thermal expansion (CTE) between the base layer 102 of the connection unit 100 and other various electronic components and / or various packages containing various electronic components (e.g., the difference in coefficient of thermal expansion between the electronic unit EU1 and the external component 200), thereby helping to improve the reliability of the intermediary IP1' and / or the electronic device containing the intermediary IP1'.

[0070] Figure 7A and Figure 7B These are a cross-sectional view and a top view of an electronic device according to a third embodiment of the present disclosure. Figure 7B yes Figure 7A A top view schematic diagram of one embodiment, for example Figure 7A It corresponds to the edge Figure 7B A schematic diagram of the cross-section intercepted by line A-A'. For ease of explanation, Figure 7B Only the connection unit 100, the electronic unit EU1, the second encapsulation layer ML1, and the conductive vias TMV1, TMV2a, and TMV2b are shown. Figure 7A The intermediate component IP2 of the electronic device ED2 shown is... Figure 5AThe intermediate component IP1 of the electronic device ED1 shown is similar, with the main difference being... Figure 7A The package structure 20 shown includes electronic component 100a and heat dissipation structure HDS1. Other identical or similar components are represented by the same or similar symbols and will not be described again here.

[0071] Please refer to Figure 7A The packaging structure 20 may include electronic components 100a arranged in an array together with a plurality of connection units 100 (such as...). Figure 7B As shown in the diagram, electronic component 100a can be integrated into intermediate component IP2 to help improve the component integration of electronic device ED2. Electronic component 100a may include various active or passive components. For example, electronic component 100a may include components such as capacitors, resistors, inductors, diodes, transistors, or combinations thereof, but is not limited thereto. In some embodiments, electronic component 100a may include chips such as power management integrated circuits (PMICs) to help reduce the power consumption of electronic device ED2. In other embodiments, electronic component 100a may also include chips with other functions, such as logic chips, memory chips, or sensor chips. In some alternative embodiments, electronic component 100a may also include a DC-DC converter, a regulator, or a combination thereof. In some embodiments, the regulator may include a linear regulator or a low dropout linear regulator (LDO), etc.

[0072] In this embodiment, the packaging structure 20 may include a heat dissipation structure HDS1 disposed in the first circuit structure CS1, and the heat dissipation structure HDS1 may overlap with the electronic component 100a. This facilitates the transfer of heat generated by the electronic component 100a to other components (e.g., external component 200) through the heat dissipation structure HDS1 and other wiring structures in the first circuit structure CS1 used to establish heat transfer paths. The heat dissipation structure HDS1 may include any suitable thermally conductive material such as gold, silver, copper, or aluminum, but is not limited thereto. In some embodiments, the heat dissipation structure HDS1 may be integrated into the manufacturing process of forming the first circuit structure CS1.

[0073] In this embodiment, electronic component 100a can be thermally coupled to heat dissipation structure HDS1. In this embodiment, thermal coupling refers to the connection between two objects to enable the transfer of heat between them, and it can include the following forms: direct contact between the two or indirect contact between the two separated by a thermally conductive material. In this embodiment, "one component overlapping another component" can refer to the component overlapping the other component in the top view direction (e.g., the Z direction) of electronic device ED2.

[0074] In this embodiment, the height of the conductive via TMV1 may be different from the heights of the conductive vias TMV2a and TMV2b, while the height of the conductive via TMV2a may be approximately equal to the height of the conductive via TMV2b.

[0075] Figure 8 This is a cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. Figure 8 The intermediate component IP3 of the electronic device ED3 shown is... Figure 5A The intermediate component IP1 of the electronic device ED1 shown is similar, with the main difference being... Figure 8 The package structure 30 shown is different from Figure 5A The encapsulation structure 10 shown is used for other identical or similar components, which are represented by the same or similar symbols and will not be described again here.

[0076] Please refer to Figure 8 In the package structure 30, one of the plurality of connection units 100 may include a plurality of second conductive elements disposed on one side of the substrate layer 102, wherein the first conductive element disposed in the substrate layer 102 may include connection lines connecting the second conductive elements. For example, connection unit 100b may include a plurality of conductive elements 108 disposed on one side of the substrate layer 102, wherein the conductive elements disposed in the substrate layer 102 may include connection lines CW1 connecting the conductive elements 108, thus satisfying an electronic unit with a high number of input / output pads (I / O pads). For example, when Figure 8In the case where the central electronic unit EU1 is a graphics processing unit (GPU), the connection unit 100 located below the GPU in the intermediary IP3 can be replaced with connection unit 100b to meet the requirement of the GPU having a high number of I / O pads. Based on the above, the intermediary IP3 can implement different connection methods in different areas as needed. In other words, the intermediary IP3 can be matched with different types of connection units according to different types of electronic units, making the intermediary IP3 easy to integrate into various different products. In some embodiments, the connection unit 100b can be a silicon bridge. The connection line CW1 can include any suitable conductive material, such as copper, titanium, nickel, gallium (Ga), ruthenium (Ru), tantalum (Ta), or combinations or alloys of the above materials, but is not limited thereto.

[0077] In some embodiments, the packaging structure 30 may include a heat dissipation structure HDS2 arranged in an array with a plurality of connection units 100, 100b. In this embodiment, the heat dissipation structure HDS2 may be placed below the electronic unit EU1, which requires more heat dissipation. For example, when Figure 8 In the case where the central electronic unit EU1 is a graphics processing unit (GPU), the connection unit 100 located below the GPU in the intermediate component IP3 can be replaced with a heat dissipation structure HDS2 to meet the heat dissipation requirements of the GPU. In some embodiments, the heat dissipation structure HDS2 may include a material with high thermal conductivity and low coefficient of thermal expansion to mitigate the difference in coefficient of thermal expansion between the heat dissipation structure HDS2 and the second circuit structure CS2 and / or external components 200 while achieving good heat transfer. For example, the heat dissipation structure HDS2 may include ceramic materials (e.g., AlSiC, SiC, or AlN), alloy materials (e.g., Invar, or nickel-steel alloy), or carbon materials with a specific thermal conductivity direction or good thermal conductivity (e.g., graphene, carbon nanotubes, or diamond, etc.) or combinations thereof.

[0078] In this embodiment, the first circuit structure CS1' in the packaging structure 30 may include an Ajinomoto build-up film (ABF). In this case, the first circuit structure CS1' may include a plurality of insulating layers IL3a, IL3b, IL3c, and IL3d alternately stacked along a vertical direction (e.g., the Z direction). The wiring structure WS3 may include a plurality of wiring layers WS3a, WS3b, WS3c, and WS3d respectively formed in the insulating layers IL3a, IL3b, IL3c, and IL3d and alternately stacked along a vertical direction.

[0079] In some embodiments, the intermediate component IP3 can be formed as follows: First, a plurality of connection units 100 are bonded to a second circuit structure CS2. Next, a plurality of conductive vias TMV1, TMV2 are formed on the second circuit structure CS2. Then, a second underfill UF2' is provided between the second circuit structure CS2 and the first encapsulation layer 110. Afterward, a second encapsulation layer ML1 surrounding the encapsulation structure 30 is formed on the second circuit structure CS2. Then, a first circuit structure CS1' is formed on the second encapsulation layer ML1. Finally, a monomerization process is performed to form as shown in the figure. Figure 8 The middleware IP3 is shown.

[0080] In some embodiments, the electronic device ED3 may further include a reinforcement structure 300 disposed on the second circuit structure CS2 and surrounding the plurality of electronic units EU1. In some embodiments, conductive vias TMV1 and TMV2 may be thermally coupled to the reinforcement structure 300, so that the heat generated by the electronic units EU1 (e.g., Figure 8 The central electronic unit EU1 can transfer heat to the conductive vias TMV1 and TMV2 through the wiring layer in the lower heat dissipation structure HDS2 and the first circuit structure CS1', ​​and then to the reinforcement structure 300. This may help improve the heat dissipation efficiency of the electronic device ED3, so that the electronic unit EU1 has the desired performance and / or stability.

[0081] In some embodiments, the reinforcement structure 300 may be a stiffener ring surrounding a plurality of electronic units EU1. In this embodiment, the reinforcement structure 300 may include any suitable thermally conductive material (e.g., copper) to improve the heat dissipation efficiency of the electronic device ED3.

[0082] Figures 9A to 9C This is a cross-sectional schematic diagram of an intermediary according to different embodiments of the present disclosure. Figures 9A to 9C This describes the different connection methods between the connection unit 100 and the first circuit structure CS1 and the second circuit structure CS2.

[0083] Please refer to Figure 9AThe first circuit structure CS1 may include a plurality of insulating layers IL1a, IL1b, and IL1c alternately stacked along a vertical direction (e.g., the Z direction). The wiring structure WS1 may include a plurality of wiring layers WS1a, WS1b, and WS1c, respectively formed in the insulating layers IL1a, IL1b, and IL1c and alternately stacked along a vertical direction. The second circuit structure CS2 may include a plurality of insulating layers IL2a, IL2b, and IL2c alternately stacked along a vertical direction (e.g., the Z direction). The wiring structure WS2 may include a plurality of wiring layers WS2a, WS2b, and WS2c, respectively formed in the insulating layers IL2a, IL2b, and IL2c and alternately stacked along a vertical direction. In this embodiment, the connecting unit 100 can be joined to the first circuit structure CS1 and the second circuit structure CS2 through connecting elements CE1 and CE2 respectively. The first underfiller UF1 can be provided between the base layer 100 of the connecting unit 100 and the first circuit structure CS1 to surround the connecting element CE1, while the second underfiller UF2 can be provided between the connecting unit 100 and the second circuit structure CS2 to surround the connecting element CE2.

[0084] Please refer to Figure 9B The wiring layers WS1a' and WS2c' adjacent to the connection unit 100 can be formed with a grooved pattern, such as grooved under-bump metallization (UBM). This can help improve the bonding stability between the conductive elements 106, 108 and the wiring layers WS1a' and WS2c', and can also selectively omit the first underfiller UF1 and the second underfiller UF2 to help reduce process costs.

[0085] Please refer to Figure 9CIn this embodiment, the second circuit structure CS2 can be bonded to the connection unit 100 via hybrid bonding, while the first circuit structure CS1 can be bonded to the connection unit 100 by designing the wiring layer WS1a' adjacent to the connection unit 100 with a grooved pattern (e.g., grooved under-bump metal (UBM)). In this embodiment, the insulating layer 105' may have a top surface with substantially the same horizontal height as the conductive element 108, and the insulating layer IL2c' may have a top surface with substantially the same horizontal height as the wiring layer WS2c. Thus, the bonding interface between the second circuit structure CS2 and the connection unit 100 may include metal-to-metal bonding between the conductive element 108 and the wiring layer WS2c, and oxide-to-oxide bonding or polyimide-to-polyimide bonding between the insulating layer 105' and the insulating layer IL2c'. In this disclosure, "substantially identical" means that the height difference in the Z direction between adjacent surfaces of two elements is less than or equal to 10 micrometers.

[0086] In summary, in the embodiments of this disclosure, the first encapsulation layer encapsulates a plurality of interconnecting units spaced apart from each other and arranged in an array, and includes portions disposed between the plurality of interconnecting units. This can mitigate the difference in coefficient of thermal expansion (CTE) between the base layer of the interconnecting units and other various electronic components and / or various packages containing various electronic components, thereby helping to improve the reliability of the intermediary and / or the electronic device containing the intermediary.

[0087] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure. Features between embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0088] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of this disclosure, and features between the various embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Those skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. An intermediary, characterized in that, include: The packaging structure includes: Multiple connection units are spaced apart from each other and arranged in an array, wherein each connection unit includes a base layer and a first conductive element disposed in the base layer; A first encapsulation layer surrounds the plurality of connection units and includes a portion disposed between the plurality of connection units; and A first circuit structure is disposed on a first side of the first encapsulation layer and electrically connected to the plurality of connection units.

2. The intermediary according to claim 1, characterized in that, Also includes: A second circuit structure is disposed on a second side of the first encapsulation layer relative to the first side and electrically connected to at least one of the plurality of connection units.

3. The intermediary according to claim 2, characterized in that, Also includes: The second encapsulation layer is disposed on the first side of the second circuit structure adjacent to the second side of the first encapsulation layer and surrounds the encapsulation structure. as well as Multiple conductive vias penetrate the second encapsulation layer and are electrically connected to the second circuit structure.

4. The intermediary according to claim 3, characterized in that, The height of one of the plurality of conductive vias is different from the height of another of the plurality of conductive vias.

5. The intermediary according to claim 3, characterized in that, The packaging structure includes a first underfill material disposed between the first circuit structure and the first packaging layer.

6. The intermediary according to claim 5, characterized in that, Also includes: A plurality of second underfillers are disposed between the second circuit structure and the substrate layer, wherein the second encapsulation layer surrounds the plurality of second underfillers.

7. The intermediary according to claim 1, characterized in that, The packaging structure includes electronic components arranged in an array together with the plurality of connection units.

8. The intermediary according to claim 7, characterized in that, The packaging structure includes a heat dissipation structure disposed in the first circuit structure, and the heat dissipation structure overlaps with the electronic component.

9. The intermediary according to claim 1, characterized in that, The packaging structure includes a heat dissipation structure arranged in an array together with the plurality of connection units.

10. The intermediary according to claim 1, characterized in that, One of the plurality of connection units includes a plurality of second conductive elements disposed on opposite sides of the substrate layer, wherein the first conductive element penetrates the substrate layer to connect the plurality of second conductive elements.

11. The intermediary according to claim 1, characterized in that, One of the plurality of connection units includes a plurality of second conductive elements disposed on one side of the substrate layer, wherein the first conductive element includes a connection line connecting the plurality of second conductive elements.

12. An electronic device, characterized in that, include: Intermediary documents, including: The packaging structure includes: Multiple connection units are spaced apart from each other and arranged in an array, wherein each connection unit includes a base layer and a first conductive element disposed in the base layer; A first encapsulation layer encapsulates the plurality of connection units and includes a portion disposed between the plurality of connection units; and A first circuit structure is disposed on a first side of the first encapsulation layer and electrically connected to the plurality of connection units; and The second circuit structure is disposed on the second side of the first encapsulation layer opposite to the first side and electrically connected to the plurality of connection units; Multiple electronic units are disposed on and electrically connected to the second circuit structure; and An external component is disposed under the first circuit structure and electrically connected to the first circuit structure.

13. The electronic device according to claim 12, characterized in that, The intermediary includes: A second encapsulation layer is disposed below and surrounds the second circuit structure; and Multiple conductive vias penetrate the second encapsulation layer and electrically connect the second circuit structure to the external component.

14. The electronic device according to claim 13, characterized in that, The height of one of the plurality of conductive vias is different from the height of another of the plurality of conductive vias.

15. The electronic device according to claim 13, characterized in that, The packaging structure includes a first underfill material disposed between the first circuit structure and the first packaging layer, and The intermediary includes a plurality of second underfills disposed between the second circuit structure and the substrate layer, wherein the second encapsulation layer surrounds the plurality of second underfills.

16. The electronic device according to claim 12, characterized in that, The packaging structure includes electronic components arranged in an array together with the plurality of connection units.

17. The electronic device according to claim 16, characterized in that, The packaging structure includes a heat dissipation structure disposed in the first circuit structure and overlapping with the electronic components.

18. The electronic device according to claim 12, characterized in that, The packaging structure includes a heat dissipation structure arranged in an array together with the plurality of connection units.

19. The electronic device according to claim 12, characterized in that, Also includes: A reinforcing structure is disposed on the second circuit structure and surrounds the plurality of electronic units.

20. A method for manufacturing an intermediary component, characterized in that, include: Multiple connection units are arranged in an array on a first circuit structure, wherein the multiple connection units are electrically connected to the first circuit structure, and each connection unit includes a base layer and a first conductive element disposed in the base layer; A first underfill is provided between the first circuit structure and the substrate layer; as well as A first encapsulation layer is provided on the first bottom filler to encapsulate the plurality of connecting units to form an encapsulation structure, wherein the first encapsulation layer includes portions formed between the plurality of connecting units.

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