Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device comprises a first substrate structure, a first circuit structure and a packaging structure. The first circuit structure is disposed on a surface of the first substrate structure. The first circuit structure includes a first sub-structure. The packaging structure is arranged on the first circuit structure and is electrically connected with the first circuit structure. The first substructure has a first thermal expansion coefficient, the packaging structure has a second thermal expansion coefficient, and the ratio of the second thermal expansion coefficient to the first thermal expansion coefficient is larger than or equal to 0.8 and smaller than or equal to 1.5.

Description

Technical Field

[0001] This invention relates to an electronic device and a method for manufacturing the electronic device, and more particularly to an electronic device and a method for manufacturing the electronic device that are advantageous in reducing warpage. Background Technology

[0002] In the field of integrated circuits, depending on the application and requirements, electronic devices may require larger sizes (e.g., larger areas) and more layers. These layers may include, for example, the carrier board used in the manufacturing process, the substrate structure that is part of the product, and redistribution layers. For instance, using a large-area carrier board in production can improve the output efficiency of the packaging unit or reduce manufacturing costs. However, as the size of electronic devices increases and the number of layers increases, the warpage of the electronic devices also increases significantly, affecting the yield of the electronic devices. Summary of the Invention

[0003] The purpose of this invention is to provide an electronic device and a method for manufacturing the same.

[0004] This invention provides an electronic device, including a first substrate structure, a first circuit structure, and a package structure. The first circuit structure is disposed on a surface of the first substrate structure and includes a first substructure. The package structure is disposed on the first circuit structure and electrically connected to it. The first substructure has a first coefficient of thermal expansion, and the package structure has a second coefficient of thermal expansion, wherein the ratio of the second coefficient of thermal expansion to the first coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.5.

[0005] The present invention also provides a method for manufacturing an electronic device, comprising providing a substrate structure and providing a circuit structure disposed on the substrate structure. Providing the circuit structure disposed on the substrate structure may include the following steps: providing a first substructure on the substrate structure, wherein the first substructure includes a first adjustment member; calculating a warpage degree of the first substructure; and providing a second substructure on the first substructure, and determining whether to provide a second adjustment member in the second substructure based on the warpage degree. Attached Figure Description

[0006] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 yes Figure 1 Cross-sectional view of the electronic device along section line A-A'

[0008] Figure 3 and Figure 4 yes Figure 2 A cross-sectional schematic diagram of the manufacturing method of electronic devices.

[0009] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0010] Figure 6 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0011] Figure 7 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0012] Figure 8 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0013] Figure 9 This is a flowchart of the steps of a method for manufacturing an electronic device according to another embodiment of the present invention.

[0014] Figure 10 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present invention.

[0015] Explanation of reference numerals in the attached figures: 1A, 1B, 1C, 1D, 1E, 1F - Electronic devices; 110A, 110B, 110C, 110E, 150C, 150D, 150E - Substrate structures; 112A, 112B, 112C, 112E, 152C, 152D - Substrate layers; 114A, 114B, 114C, 114E, 154C, 154D - Conductive elements; 1141, 1541 - Buffer layers; 120A, 120B, 120C, 160C, 220 - Circuit structures; 121A, 122A, 123A, 124A, 125A, 126A, 121B, 122B, 123B, 124B, 125B, 126 B, 121C, 122C, 123C, 124C, 125C, 161C, 162C, 163C, 164C, 165C - Substructure; 130A, 130B, 130C, 230 - Encapsulation structure; 118, 132, 134, 232 - Electronic unit; 116B, 136 - Warp adjustment layer; 140, 234 - Encapsulation layer; 156D - Stress-resistant layer; 170 - Protective layer; 210 - Carrier plate; 212 - Marking element; 222 - First substructure; 224 - Second substructure; 270 - Warp adjustment layer; 280 - Release layer; 300 - Manufacturing method of electronic device; 310, 320, 330, 340, 342, 344, 34 6, 348, 350 - Steps; AE1 - First Adjustment Component; AE2 - Second Adjustment Component; AP1 - Arc-shaped Part; C21, C22, C23, C24, C25, C26, C61, C62, C63, C64, C65, C222, C224, 1142, 1542 - Conductor Layers; C21b, C22b, C23a, C23c, C24a, C62a, C63a, CP1, CP2, CP3 - Pads; C21a, C22a, C23b - Connecting Elements; CE1, CE2, CE3, CE4 - Joining Elements; G1 - Gap; H1, H2 - Height; I21, I22, I23, I24, I25, I26, I 61, I62, I63, I64, I65, I222, I224 - Insulating layer; P1, P3 - First part; P2, P4 - Second part; RP1, RP2 - Recess; S1, S2, S41, S42, S43, S5, S6 - Surface; S11, S31, S35 - Upper surface; S21 - Lower surface; S32, S33, S36, S37 - Side surface; T21, T22, T23, T24, T25, T26, TH1 - Thickness; TD1 - Aperture; TV10, TV50 - Perforation; TV21, TV22, TV23 - Hole; UF1, UF2, UF3 - Filling material; W1, W2 - Width; X, Y, Z - Direction. Detailed Implementation

[0016] The present invention will now be described in detail with reference to exemplary embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0017] Throughout this specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0018] The directional terms used in this invention, such as "up," "down," "front," "back," "left," and "right," are merely for reference to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit the invention. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of various film layers, regions, and / or structures may be reduced or enlarged.

[0019] In this invention, a structure (or layer, component, substrate) located on / above another structure (or layer, component, substrate) can refer to two structures being adjacent and directly connected, or to two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate spacer) between the two structures, with the lower surface of one structure adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single or multiple solid or non-solid structure, without limitation. In this invention, when a structure is disposed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0020] In this invention, the term "connection" may include physical connection or electrical connection, and may include direct contact or indirect contact.

[0021] In this invention, the term "disposed on" is used for ease of description and does not limit the process steps or order.

[0022] The terms “equal to,” “same as,” “identical,” or “approximately” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0023] Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of about 10% between the two values; if the first direction is perpendicular to or "approximately" perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to or "approximately" parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0024] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0025] In addition, the terms "given range is from the first value to the second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between.

[0026] In this invention, the term "one element surrounding another element" can refer to a situation in which, in a cross-sectional view, the one element contacts at least one side surface of the other element.

[0027] The manufacturing process of the electronic device in this invention can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, and can be chip-first or chip-last (RDL first) processes.

[0028] The electronic device disclosed in this invention can be applied to power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but is not limited thereto. The display device can be a non-self-emissive display device or a self-emissive display device. The antenna device can be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device can be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited thereto. The electronic components included in the electronic device can include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes can include light-emitting diodes (LEDs) or photodiodes. Light-emitting diodes can include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. The splicing device can be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. Furthermore, the electronic device can be a bendable or flexible electronic device. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device can have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (e.g., Augmented Reality (AR) or Virtual Reality (VR) devices), automotive devices (e.g., automotive windshields), or splicing devices. The electronic device can include packaging devices such as High Bandwidth Memory (HBM) packages, System on a Chip (SoC), System in a Package (SiP), Antenna in Package (AiP), Co-packaged Optics (CPO), or various combinations of the above, but is not limited thereto.

[0029] In this invention, the chip may include an active side with pads and a back side opposite the active side.

[0030] In this invention, the redistribution layer structure can be electrically connected to individual chips or electronic units via bonding elements such as bumps, solder balls, or pads. The redistribution layer structure may include at least one conductor layer and at least one insulating layer. The redistribution layer structure can be used to redefine wiring and / or further increase the fan-out area of ​​wiring, or to electrically connect different electronic components to each other. Methods of forming the redistribution layer structure may include providing a stack of at least one insulating layer and at least one conductor layer, and may include processes such as photolithography, etching, surface treatment, laser treatment, and electroplating. Surface treatment may include roughening the surface of the insulating layer or the conductor layer to improve its adhesion. Alternatively, the redistribution layer structure may be a substrate used as an electrical interface wiring between one connection and another. The purpose of the redistribution layer structure is to extend interconnects to a wider spacing or to redistribute interconnects to another interconnect with a different spacing.

[0031] In this invention, the term "modification" can refer to the decrease in mechanical strength of the modified portion.

[0032] It should be understood that, according to embodiments of the present invention, the depth, thickness, width, or height of each element, or the spacing or distance between elements, can be measured using an optical microscope (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. According to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image including the element to be measured, and to measure the depth, thickness, width, or height of each element, or the spacing or distance between elements.

[0033] In this invention, roughness is defined, for example, by observation using a scanning electron microscope. If the peaks and valleys of surface undulations on the observed surface have a distance difference of 0.15–1 μm, it can be determined as rough. The roughness determination is measured using, for example, a scanning electron microscope or a transmission electron microscope (TEM) at an appropriate magnification to observe the surface undulations. The undulations are compared by taking a unit length (e.g., 10 μm). Here, "appropriate magnification" means that at least one surface can show at least 10 peaks of undulations in the field of view at this magnification.

[0034] It should be understood that the features described in the following embodiments can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0036] In this invention, the number of components in the electronic device shown in the following figures, such as packaging structures, electronic units, circuit structures, substructures, substrate structures, through holes, conductive elements, pads, bonding elements, adjustment components, etc., are merely illustrative and are not limited to the structures shown in the figures.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 This is a perspective view of an electronic device 1A according to an embodiment of the present invention. Figure 2 yes Figure 1 A cross-sectional view of the electronic device 1A along section line A-A'. Figure 1 and Figure 2 In this example, electronic device 1A is used as a package device, but it is not limited to this. Electronic device 1A includes a substrate structure 110A, a circuit structure 120A, and a package structure 130A. The circuit structure 120A is disposed on surfaces S1 and S2 of the substrate structure 110A. The circuit structure 120A may include at least one substructure. Here, the circuit structure 120A is exemplified by having six substructures, namely substructure 121A, substructure 122A, substructure 123A, substructure 124A, substructure 125A, and substructure 126A, but it is not limited to these. The number of substructures in the circuit structure 120A can be adjusted according to actual needs. The package structure 130A is disposed on the circuit structure 120A and electrically connected to the circuit structure 120A. Substructures 121A, 122A, 123A, 124A, 125A, and 126A each have a coefficient of thermal expansion, and package structure 130A has a coefficient of thermal expansion. The ratio of the coefficient of thermal expansion of package structure 130A to at least one of the coefficients of thermal expansion of substructures 121A, 122A, 123A, 124A, 125A, and 126A is greater than or equal to 0.8 and less than or equal to 1.5. This improves the matching degree of the coefficients of thermal expansion between package structure 130A and circuit structure 120A, thereby reducing the warpage of electronic device 1A.

[0038] In some embodiments, the ratio of the coefficient of thermal expansion of the packaging structure 130A to the coefficients of thermal expansion of any one of the substructures 121A, 122A, 123A, 124A, 125A, and 126A is greater than or equal to 0.8 and less than or equal to 1.5. This helps to further reduce the warpage of the electronic device 1A.

[0039] The substrate structure 110A may have a coefficient of thermal expansion, and the ratio of the coefficient of thermal expansion of the package structure 130A to the coefficient of thermal expansion of the substrate structure 110A may be greater than or equal to 0.8 and less than or equal to 1.5. This is beneficial for further reducing the warpage of the electronic device 1A.

[0040] In detail, the substrate structure 110A may include a substrate layer 112A and conductive elements 114A. The substrate layer 112A may have through holes TV10, and the conductive elements 114A may be disposed in the through holes TV10. Here, it is taken that the substrate layer 112A has multiple through holes TV10 as an example, but it is not limited to this. The number of through holes TV10 in the substrate layer 112A can be adjusted according to actual needs. Each through hole TV10 is provided with a conductive element 114A, so that the first part P1 of the circuit structure 120A located above the substrate structure 110A and the second part P2 of the circuit structure 120A located below the substrate structure 110A can be electrically connected through the conductive elements 114A.

[0041] In some embodiments, in a direction (direction X) perpendicular to the normal direction (parallel direction Z), the conductive element 114A may include a buffer layer 1141 and a conductor layer 1142, with the buffer layer 1141 disposed between the conductor layer 1142 and the substrate layer 112A. The buffer layer 1141 is disposed on the wall of the through-hole TV 10 and surrounds the conductor layer 1142. The buffer layer 1141 helps to reduce the probability of microcracks forming in the substrate layer 112A, but is not limited thereto. In some instances, the conductive element 114A may not include the buffer layer 1141 and may only include the conductor layer 1142. Here, the conductor layer 1142 is exemplified as a single-layer structure, but is not limited thereto. In some embodiments, the conductor layer 1142 may be a multi-layer structure, for example, the conductor layer 1142 may further include a seed layer (not shown) and / or a barrier layer (not shown), but is not limited thereto. By including different metals in the conductor layer 1142, the coefficient of thermal expansion of the conductor layer 1142 can be further adjusted, thereby adjusting the coefficient of thermal expansion of the substrate structure 110A.

[0042] The material of the substrate layer 112A may include, for example, glass, bismaleimide-triazine (BT), flame retardant 4 (FR4), silicon, other suitable materials, or combinations of the above materials, but is not limited thereto.

[0043] The toughness of the buffer layer 1141 can be 0.1 kJ / m. 2 Up to 100kJ / m 2 The material of the buffer layer 1141 may include, for example, polyimide (PI) resin, parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-containing compounds, other suitable materials, or combinations thereof, but is not limited thereto. In some embodiments, the thickness TH1 of the buffer layer 1141 may be from 0.01 μm to 10 μm, and the aforementioned thickness TH1 of the buffer layer 1141 may refer to the thickness of the buffer layer 1141 on the surface of the hole wall of the perforated TV 10 along the horizontal direction (e.g., direction X). In some embodiments, the ratio of the thickness TH1 of the buffer layer 1141 to the hole diameter TD1 of the perforated TV 10 may be from 0.02 to 0.2.

[0044] The material of the conductor layer 1142 may include, for example, titanium, iron, aluminum, copper, nickel, tungsten, gold, platinum, other suitable materials, or combinations thereof, but is not limited thereto. The material of the seed layer may include, for example, titanium, tungsten, nickel, other suitable materials, or combinations thereof. According to one embodiment, the seed layer may include titanium copper or titanium nitride. The material of the barrier layer may include, for example, titanium (Ti), tantalum (Ta), copper, other suitable materials, or combinations thereof, but is not limited thereto.

[0045] The circuit structure 120A may include, for example, a redistribution layer (RDL) structure. Here, the circuit structure 120A is illustrated by including a first portion P1 and a second portion P2, which are redistribution layer structures respectively. The first portion P1 and the second portion P2 are disposed on opposite sides of the substrate structure 110A, wherein the first portion P1 is disposed on surface S1 of the substrate structure 110A and located above the substrate structure 110A, and the second portion P2 is disposed on surface S2 of the substrate structure 110A and located below the substrate structure 110A. The substrate layer 112A has a normal direction (e.g., parallel direction Z), and includes surfaces S1 and S2, which are disposed opposite to each other in the normal direction. The first part P1 may sequentially include substructures 121A, 122A, and 123A from top to bottom in the normal direction (e.g., parallel direction Z), and the second part P2 may sequentially include substructures 124A, 125A, and 126A from top to bottom in the normal direction, but is not limited thereto. The circuit structure 120A may further include a plurality of pads CP1 disposed on the surface S41 of the substructure 126A and electrically connected to the conductor layer C26 of the substructure 126A.

[0046] Substructure 121A may include an insulating layer I21 and a conductor layer C21, wherein the conductor layer C21 is disposed within the insulating layer I21, for example, in a through-hole or blind via of the insulating layer I21, thus the insulating layer I21 surrounds the conductor layer C21, that is, in a cross-sectional view, the insulating layer I21 contacts the side of the conductor layer C21. In substructure 121A, the content (or volume percentage) of the conductor layer C21 may be from 2 volume percentage to 55 volume percentage. Substructure 122A may include an insulating layer I22 and a conductor layer C22, wherein the conductor layer C22 is disposed within the insulating layer I22 and surrounds the conductor layer C22. In substructure 122A, the content of the conductor layer C22 may be from 2 volume percentage to 55 volume percentage. Substructure 123A may include an insulating layer I23 and a conductor layer C23, wherein the conductor layer C23 is disposed within the insulating layer I23 and surrounds the conductor layer C23. In substructure 123A, the content of conductor layer C23 can be from 2 volume percentage to 55 volume percentage. Substructure 124A may include an insulating layer I24 and a conductor layer C24, with conductor layer C24 disposed within and surrounding the insulating layer I24. In substructure 124A, the content of conductor layer C24 can be from 2 volume percentage to 55 volume percentage. Substructure 125A may include an insulating layer I25 and a conductor layer C25, with conductor layer C25 disposed within and surrounding the insulating layer I25. In substructure 125A, the content of conductor layer C25 can be from 2 volume percentage to 55 volume percentage. Substructure 126A may include an insulating layer I26 and a conductor layer C26, with conductor layer C26 disposed within and surrounding the insulating layer I26. In substructure 126A, the content of conductor layer C26 can be from 2 volume percentage to 55 volume percentage. In this invention, the "content of conductor layer" can be measured, for example, by using an optical detection instrument, such as an X-ray device, to measure the size or volume of the conductor layer in each film layer, but is not limited thereto.

[0047] In some embodiments, the dimensions (e.g., width and / or thickness) of conductor layers C21, C22, C23, C24, C25, and C26 can be configured to increase from the vicinity of package structure 130A toward the direction away from package structure 130A, i.e., the closer to package structure 130A, the smaller the dimensions. The dimensions of the aforementioned conductor layers C21, C22, C23, C24, C25, and C26 can guide the comparison of the lengths of corresponding portions of the body layers C21, C22, C23, C24, C25, and C26 in one direction. For example, the thickness of the pads in conductor layers C21, C22, C23, C24, C25, and C26 is configured to gradually increase from the vicinity of package structure 130A toward the direction away from package structure 130A (i.e., opposite to direction Z), i.e. Figure 3 The thickness of the intermediate pad C21b is less than the thickness of the pad C22b, the thickness of the pad C22b is less than the thickness of the pad C23c, and the thickness of the pad C23c is less than the thickness of the pad C23a, but is not limited thereto. The aforementioned thicknesses may be the maximum length of the pads in the vertical direction (e.g., direction Z). The smaller conductor layer C21 is configured in the substructure 121A closer to the package structure 130A, which is beneficial for increasing the number of I / O (in-put / out-put) ports of electronic units 132 and 134, thereby improving the I / O density of the electronic device 1A.

[0048] The materials of insulating layers I21, I22, I23, I24, I25, and I26 may each independently include organic or inorganic materials, such as polyimide (PI) resin, photosensitive polyimide (PSPI) resin, poly(p-phenylene benzobisoxazole) (PBO), epoxy resin, polymer, acrylonitrile-butadiene-styrene copolymer (ABS), and silicon dioxide (SiO2). x ), silicon nitride (SiN) x Other suitable materials or combinations thereof, but not limited to these.

[0049] Conductor layers C21, C22, C23, C24, C25, C26, and pad CP1 are illustrated herein as a single-layer structure. The materials of conductor layers C21, C22, C23, C24, C25, C26, and pad CP1 may each independently include titanium, iron, aluminum, copper, nickel, tungsten, gold, platinum, other suitable materials, or combinations thereof, but are not limited thereto. According to one embodiment of the invention, the materials of conductor layers C21, C22, C23, C24, C25, C26, and pad CP1 may include copper. In other embodiments, conductor layers C21, C22, C23, C24, C25, C26 and pad CP1 may be multilayer structures. For example, each conductor layer C21, C22, C23, C24, C25, C26 and pad CP1 may optionally include a seed layer (not shown) and / or a barrier layer (not shown), but are not limited thereto. For information on the materials of the seed layer and the barrier layer, please refer to the relevant description above.

[0050] In some embodiments, the thicknesses T21 of insulating layer I21, T22 of insulating layer I22, T23 of insulating layer I23, T24 of insulating layer I24, T25 of insulating layer I25, and T26 of insulating layer I26 of circuit structure 120A may be greater than the thickness TH1 of buffer layer 1141. The aforementioned thicknesses T21, T22, T23, T24, T25, and T26 may be the maximum lengths of insulating layer I21, I22, I23, I24, I25, or I26 in the vertical direction (e.g., direction Z), respectively. The aforementioned thicknesses T21, T22, T23, T24, T25 and T26 can be from 1 μm to 25 μm, from 3 μm to 20 μm or from 5 μm to 15 μm, and each of the thicknesses T21, T22, T23, T24, T25 and T26 can be the same or different.

[0051] Although Figure 1 , Figure 2 Not shown in the figure, substructure 121A may optionally include at least one adjustment element (see Figure 121A). Figure 10 The first adjusting member AE1 and the second adjusting member AE2 are disposed in the insulating layer I21 to adjust the coefficient of thermal expansion of the substructure 121A, thereby adjusting the overall stress of the substructure 121A. Similarly, substructures 122A, 123A, 124A, 125A, and 126A may each independently and selectively include at least one adjusting member. For information on adjusting members, please refer to [link to relevant documentation]. Figure 10 Related explanations.

[0052] Package structure 130A may include at least one electronic unit. Taking package structure 130A as an example, which includes electronic units 132 and 134, electronic units 132 and 134 are electrically connected to circuit structure 120A. Electronic units 132 and 134 may be chips, such as System on Chip (SoC), Dynamic Random-Access Memory (DRAM), High Bandwidth Memory (HBM), Photonic Integrated Circuit (PIC), Application-Specific Integrated Circuit (ASIC), or other logic integrated circuit chips, but are not limited thereto. The chip may include an active side with pads (not shown) and a back side opposite the active side. The pads may be, for example, I / O pads. Here, the active side of the chip faces circuit structure 120A, and the chip can be electrically connected to circuit structure 120A through the pads of the active side. In some embodiments, electronic units 132 and 134 may be unpackaged or known-good bare dies, but are not limited thereto. The active surface referred to in this invention may include an active element layer, such as a transistor and an associated dielectric layer. Electronic units 132 and 134 may be of the same or different types.

[0053] like Figure 1 As shown, there are eight electronic units 132, four of which are arranged in a straight line along a first horizontal direction (e.g., direction Y), and another four are arranged in another straight line along the first horizontal direction. There are two electronic units 134, which are arranged in a straight line along the first horizontal direction. The electronic units 132 and 134 are arranged alternately along a second horizontal direction (e.g., direction X). However, this is not the only possibility; the type, number, and arrangement of the electronic units in the package structure 130A can be adjusted according to actual needs.

[0054] The encapsulation structure 130A may optionally include a warpage adjustment layer 136. By providing the warpage adjustment layer 136, the overall thermal expansion coefficient of the encapsulation structure 130A can be adjusted, thereby adjusting the overall stress of the encapsulation structure 130A. Figure 2In this embodiment, the warpage adjustment layer 136 partially covers the upper surface S31 of the electronic unit 132 and the upper surface S35 of the electronic unit 134. The warpage adjustment layer 136 is disposed in the gap G1 between the electronic units 132 and 134 and covers the opposing side surfaces S32 and S36 of the electronic units 132 and 134, but does not cover the outward-facing side surfaces S33 and S37 of the electronic units 132 and 134. Therefore, the warpage adjustment layer 136 does not completely cover the electronic units 132 and 134, which is beneficial for heat dissipation of the electronic units 132 and 134, but is not limited to this. The volume of the warpage adjustment layer 136 and the extent to which it covers the electronic units 132 and 134 can be adjusted according to the required coefficient of thermal expansion of the package structure 130A. The adjustment of the coefficient of thermal expansion described in this invention includes: a) adjusting the volume ratio of the components to achieve the target coefficient of thermal expansion; b) in addition to adjusting the volume ratio of the components, different components in a certain structural layer have different thermal expansion trends. Specifically, the structural layer includes component A and component B, where component A may have tensile stress and component B may have compressive stress.

[0055] In electronic device 1A, a warpage adjustment layer 136 is provided in the packaging structure 130A as an example, but it is not limited to this. Any substructure in the substrate structure 110A and circuit structure 120A may also have at least one warpage adjustment layer provided on its upper and lower surfaces as needed. In other words, at least one of the substrate structure 110A, the substructure of the circuit structure 120A, and the packaging structure 130A may optionally include at least one warpage adjustment layer. The warpage adjustment layer may be in direct contact with at least one of the substrate structure 110A, the substructure of the circuit structure 120A, and the packaging structure 130A. The material of the warpage adjustment layer 136 may include organic materials, inorganic materials, or combinations thereof.

[0056] Electronic device 1A may further include a plurality of bonding elements CE1 disposed between package structure 130A and circuit structure 120A, the package structure 130A and circuit structure 120A being electrically connected via the plurality of bonding elements CE1. In some embodiments, pad C21b (see Figure 3 A recess may be formed on the surface facing the bonding element CE1 (see [reference]). Figure 5The recess RP2). Thus, the bonding element CE1 can extend into the recess of the pad C21b, thereby increasing the bonding strength between the bonding element CE1 and the pad C21b. The electronic device 1A may further include a filler material UF1 disposed in the gaps between the plurality of bonding elements CE1. The filler material UF1 may include a material with low hygroscopicity. In some embodiments, the filler material UF1 may include organic or inorganic materials, such as acrylic, epoxy resin, resin, photoresist, oxide, other suitable materials, or combinations thereof, but not limited thereto. The filler material UF1 can protect and fix the bonding elements CE1, reducing their susceptibility to moisture and / or detachment or poor electrical connection due to external forces.

[0057] The electronic device 1A may further include a plurality of bonding elements CE2 disposed on the surface of the circuit structure 120A away from the package structure 130A, specifically on the surface S41 of the substructure 126A away from the substrate structure 110A. More specifically, the circuit structure 120A is disposed between the substrate structure 110A and the plurality of bonding elements CE2. The circuit structure 120A can be electrically connected to other external components (not shown) via the bonding elements CE2. Here, the plurality of bonding elements CE2 are electrically connected to the circuit structure 120A via a plurality of pads CP1 disposed on the surface S41 of the substructure 126A. In some embodiments, the surface of the pads CP1 facing the bonding elements CE2 may have recesses (see [reference]). Figure 5 (The recess RP1). In this way, the bonding element CE2 can extend into the recess of the pad CP1, thereby improving the bonding strength between the bonding element CE2 and the pad CP1.

[0058] The bonding elements CE1 and CE2 may be made of conductive materials to provide conductivity. These conductive materials may include metals such as tin, tin-silver, tin-silver-bismuth, tin-gold, tin-nickel-gold, nickel-gold, copper, other suitable materials, or combinations thereof, but are not limited thereto. The conductive materials of the multiple bonding elements CE1 and CE2 may be independently the same or different. The multiple bonding elements CE1 and CE2 may, for example, be independently bumps, solder balls, or pads, but are not limited thereto. In this embodiment, the size of at least one of the multiple bonding elements CE1 is smaller than the size of at least one of the multiple bonding elements CE2. Furthermore, the sizes of the multiple bonding elements CE1 may be equal, and the sizes of the multiple bonding elements CE2 may be equal. The aforementioned "size" may refer to the maximum length of each bonding element CE1 and bonding element CE2 in the horizontal direction (e.g., direction X).

[0059] In this invention, when a structure or layer contains n components and / or elements, where n is a positive integer greater than 0, the coefficient of thermal expansion of the structure or layer can be calculated using formula (I):

[0060]

[0061] In the above formula, α is the coefficient of thermal expansion of the structure or the layer, and V i α represents the volume percentage of the i-th component and / or element in the structure or layer. i The coefficient of thermal expansion of the i-th component and / or element is given. The aforementioned "volume percentage of the i-th component and / or element in the structure or layer" can be measured by optical detection instruments, such as X-ray equipment, to determine the size or volume of the i-th component and / or element in the structure or layer, but is not limited thereto.

[0062] Taking substrate structure 110A as an example, substrate structure 110A includes three components: substrate layer 112A, buffer layer 1141, and conductor layer 1142. V1 can be the volume percentage of substrate layer 112A in substrate structure 110A, α1 can be the coefficient of thermal expansion of substrate layer 112A, V2 can be the volume percentage of buffer layer 1141 in substrate structure 110A, α2 can be the coefficient of thermal expansion of buffer layer 1141, V3 can be the volume percentage of conductor layer 1142 in substrate structure 110A, α3 can be the coefficient of thermal expansion of conductor layer 1142. The calculation method of the coefficient of thermal expansion α of substrate structure 110A is as follows: The calculation methods for the thermal expansion coefficients of the package structure 130A, circuit structure 120A, and each substructure can be deduced similarly, and will not be elaborated here.

[0063] Please refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 yes Figure 2 A cross-sectional schematic diagram of the manufacturing method of electronic device 1A. (See attached diagram.) Figure 3 As shown, firstly, a substrate structure 110A is provided, which may include the following steps: A substrate layer 112A is provided, the substrate layer 112A having a plurality of through holes TV10. The through holes TV10 are formed in the substrate layer 112A, for example, using a laser modification combined with an etching process, or using a laser drilling method.

[0064] Next, conductive element 114A is formed in the through-hole TV 10. First, a buffer layer 1141 is formed. The buffer material layer can be formed by electroplating, chemical electroplating, physical vapor deposition or other suitable processes to conformally cover the surface of the substrate layer 112A, including the hole wall in the through-hole TV 10 and the upper surface S11 and lower surface S21 of the substrate layer 112A. Then, the buffer material layer on the upper surface S11 and lower surface S21 of the substrate layer 112A can be removed by a planarization process, and the buffer material layer on the hole wall is the buffer layer 1141. Next, a conductor layer 1142 is formed. The conductor material layer can be formed by electroplating, chemical electroplating, physical vapor deposition or other suitable processes to fill the via TV10. The conductor material layer located on the upper surface S11 and lower surface S21 of the substrate layer 112A is removed by a planarization process. The conductor material layer remaining in the via TV10 is the conductor layer 1142.

[0065] Next, a circuit structure 120A is provided on a substrate structure 110A, which may include the following steps: forming pad C23a on surface S1 of substrate structure 110A and forming pad C24a on surface S2 of substrate structure 110A. For example, a seed layer (not shown) may be selectively formed to blanket-cover surfaces S1 and S2 of substrate layer 112A, and a patterned photoresist (not shown) is formed on the seed layer to define the positions of pads C23a and C24a. The patterned photoresist has at least one opening on the seed layer to expose the seed layer. Then, a conductive film layer is formed on the exposed seed layer. Afterward, the patterned photoresist and the seed layer below the patterned photoresist are removed to complete the fabrication of pads C23a and C24a. The conductive film layer may be formed by electroplating, chemical electroplating, physical vapor deposition, or other suitable processes. In some implementations, conductive film layers can be directly formed to blanket the substrate structure 110A on surfaces S1 and S2, and then a patterning process (e.g., using grinding or photolithography) can be performed to remove part of the conductive film layer, resulting in pads C23a and C24a.

[0066] Next, an insulating material layer is formed on surface S1 and covers pad C23a. The insulating material layer can be formed by a coating process, but is not limited to this. Then, at least one hole TV23 is formed in the insulating material layer to expose the underlying pad C23a. The hole TV23 can be formed, for example, by an exposure lithography process, but is not limited to this. Next, optionally, another seed layer (not shown) is formed to blanket the insulating material layer and the hole TV23. Next, a patterned photoresist (not shown) is formed on the other seed layer to define the position of pad C23c. The patterned photoresist has at least one opening to expose the other seed layer. Then, a conductive film layer is formed on the exposed other seed layer. Afterward, the patterned photoresist and the other seed layer located below the patterned photoresist are removed, thus completing the fabrication of connecting element C23b and pad C23c. Next, an insulating material layer is formed to cover the pads C23c and fill the gaps between the pads C23c. Then, a planarization process, such as chemical mechanical polishing or sandblasting, is used to expose the pads C23c from the insulating material layer, thus completing the fabrication of substructure 123A. In this substructure, pads C23a, connecting element C23b, and pads C23c together constitute the conductor layer C23, and the aforementioned multiple insulating material layers together constitute the insulating layer I23. Afterward, similar steps to those used to fabricate substructure 123A can be employed to form holes TV22, connecting element C22a, and pads C22b to complete the fabrication of substructure 122A, and holes TV21, connecting element C21a, and pads C21b to complete the fabrication of substructure 121A, thus completing the fabrication of the first part P1 of circuit structure 120A. In some embodiments, the pad C21b may be etched or surface-treated to roughen its surface and form a recess (not shown), allowing the subsequently formed bonding element CE1 to extend into the recess of the pad C21b, thereby improving the bonding strength between the bonding element CE1 and the pad C21b. In circuit structure 120A, the connecting element may serve as a vertical conductor for electrically connecting pads disposed at different horizontal positions in the vertical direction (e.g., direction Z). The pad may serve as a connecting pad or as a laterally extending conductor, but is not limited thereto.

[0067] Subsequently, package structure 130A is provided on circuit structure 120A. For example... Figure 4As shown, electronic units 132 and 134 can be connected and fixed to circuit structure 120A using bonding elements CE1. One end of each bonding element CE1 corresponds to a pad C21b in substructure 121A, and the other end of each bonding element CE1 corresponds to a pad on the active surface of electronic unit 132 or electronic unit 134 (not shown). Then, a filler material UF1 is provided to cover the bonding elements CE1. For example, capillary action can be used to fill the space between substructure 121A and electronic units 132 and 134, and to fill the gaps between the multiple bonding elements CE1, but this is not limited to this method. In some embodiments, hybrid bonding can be used. The bonding element CE1 is formed using a bonding technique. In this case, a passivation layer can replace the filler material UF1. For example, a first passivation material layer (not shown) can be formed on the surface of substructure 121A facing electronic units 132 and 134, and a second passivation material layer (not shown) can be formed on the surfaces of electronic units 132 and 134 facing substructure 121A (here, the active surfaces). Holes are formed in the first passivation material layer using an exposure lithography process to expose the pad C21b of substructure 121A, and in the second passivation material layer… A layer is formed to expose the active surfaces of electronic units 132 and 134 via holes (pads not shown). Conductive materials are then filled into the holes of the first passivation material layer and the second passivation material layer to form a first sub-bonding element and a second sub-bonding element, respectively. The first and second sub-bonding elements are then aligned and bonded together using a heat treatment process to form a bonding element CE1. The first and second passivation material layers together form a passivation layer, which covers the bonding element CE1. In other words, in some embodiments, the filler material UF1 can be replaced with a passivation layer. Subsequently, a warpage adjustment layer 136 is provided to partially cover the upper surface S31 of electronic unit 132 and the upper surface S35 of electronic unit 134 and fill the gap G1 between electronic units 132 and 134. The warpage adjustment layer 136 can be formed, for example, using a coating process. This completes the fabrication of the package structure 130A.

[0068] After that, as Figure 2 As shown, similar steps to those used to fabricate substructure 123A can be employed to sequentially fabricate substructures 124A, 125A, 126A, and pad CP1, thereby completing the fabrication of the second part P2 of circuit structure 120A and pad CP1. In some embodiments, the pad CP1 can be etched or surface-treated to roughen its surface and form a recess (not shown), allowing the subsequently formed bonding element CE2 to extend into the recess of the pad CP1, thus improving the bonding strength between the bonding element CE2 and the pad CP1. The bonding element CE2 is then formed on the pad CP1, completing the fabrication of electronic device 1A.

[0069] Please refer to Figure 5 This is a cross-sectional schematic diagram of an electronic device 1B according to another embodiment of the present invention. The electronic device 1B includes a substrate structure 110B, a circuit structure 120B, and a package structure 130B. The circuit structure 120B is disposed on surfaces S1 and S2 of the substrate structure 110B. The circuit structure 120B may include at least one substructure. Here, six substructures are used as an example: substructure 121B, substructure 122B, substructure 123B, substructure 124B, substructure 125B, and substructure 126B, but the method is not limited thereto. The number of substructures in the circuit structure 120B can be adjusted according to actual needs. The package structure 130B is disposed on the circuit structure 120B and electrically connected to the circuit structure 120B.

[0070] The main differences between electronic device 1B and electronic device 1A are that the structure of substrate structure 110B is different from that of substrate structure 110A, the packaging structure 130B does not have a warpage adjustment layer, and electronic device 1B further includes packaging layer 140.

[0071] The substrate structure 110B may include a substrate layer 112B, a conductive element 114B, and optionally a warpage adjustment layer 116B. By providing the warpage adjustment layer 116B, the overall coefficient of thermal expansion of the substrate structure 110B can be adjusted. The substrate layer 112B may have a through-hole TV10, and the conductive element 114B may be disposed in the through-hole TV10. Here, the conductive element 114B includes a conductor layer (not otherwise labeled) but does not include a buffer layer. There are two warpage adjustment layers 116B, which are respectively disposed on the upper surface S11 and the lower surface S21 of the substrate layer 112B. The thickness (i.e., the maximum length in the vertical direction (e.g., direction Z)) and material of the two warpage adjustment layers 116B may be the same or different, and the warpage trends of the two warpage adjustment layers 116B may be the same or different, which can be flexibly adjusted according to the required coefficient of thermal expansion of the substrate structure 110B as a whole. In some embodiments, the number of warpage adjustment layers 116B may be one, and they may be disposed on the upper surface S11 or the lower surface S21 of the substrate layer 112B.

[0072] The encapsulation layer 140 surrounds the substrate structure 110B, the circuit structure 120B, and the encapsulation structure 130B. The encapsulation layer 140 fills the gap G1 between electronic units 132 and 134, but does not cover the upper surface S31 of electronic unit 132 or the upper surface S35 of electronic unit 134. The material of the encapsulation layer 140 may include, for example, organic or inorganic materials, such as epoxy resin, polymer, silicon oxide, silicon nitride, other suitable materials, or combinations thereof, but is not limited thereto.

[0073] The manufacturing method of electronic device 1B is described below. First, a substrate structure 110B is provided, which may include the following steps: A substrate layer 112B is provided, having a plurality of through holes TV10. The formation method of the through holes TV10 is described above. Next, a conductive element 114B is formed in the through holes TV10. A conductive material layer can be formed to fill the through holes TV10 using an electroplating process, a chemical electroplating process, a physical vapor deposition process, or other suitable processes. The conductive material layer located on the upper surface S11 and the lower surface S21 of the substrate layer 112B is removed using a planarization process, and the remaining conductive material layer located in the through holes TV10 is the conductive element 114B. Next, a warp adjustment material layer can be formed to blanket the upper surface S11 and lower surface S21 of the substrate layer 112B. Then, a patterning process (such as using a grinding or photolithography process) is performed to remove part of the warp adjustment material layer and expose the conductive element 114B located in the perforated TV 10, thus completing the fabrication of the warp adjustment layer 116B.

[0074] Next, a circuit structure 120B is provided on the substrate structure 110B, and a package structure 130B is provided on the circuit structure 120B, as described in the relevant description of the electronic device 1A above. Then, a package layer 140 is provided surrounding the substrate structure 110B, the circuit structure 120B, and the package structure 130B, filling the gap G1 between the electronic units 132 and 134. The package layer 140 can be formed, for example, by a molding process, but is not limited thereto. Since in this embodiment, the warp adjustment layer 116B is fabricated first, followed by the pads C23a and C24a of the circuit structure 120B, the pads C23a and C24a are partially disposed on the conductive element 114B and partially disposed on the warp adjustment layer 116B.

[0075] Please refer to Figure 6 This is a cross-sectional schematic diagram of an electronic device 1C according to another embodiment of the present invention. The electronic device 1C includes a substrate structure 150C, a circuit structure 160C, a substrate structure 110C, a circuit structure 120C, and a package structure 130C.

[0076] Substrate structure 110C may include a substrate layer 112C and a conductive element 114C. The substrate layer 112C may have a through-hole TV10, and the conductive element 114C may be disposed in the through-hole TV10. Substrate structure 150C may include a substrate layer 152C and a conductive element 154C. The substrate layer 152C may have a through-hole TV50, and the conductive element 154C may be disposed in the through-hole TV50. The main difference between substrate structures 110C and 150C and substrate structure 110B is that substrate structures 110C and 150C do not include a warpage adjustment layer 116B. Substrate structure 150C is located further away from package structure 130C than substrate structure 110C, and the size of conductive element 154C may be larger than the size of conductive element 114C. For example, the height H2 of conductive element 154C may be greater than the height H1 of conductive element 114C, and the width W2 of conductive element 154C may be greater than the width W1 of conductive element 114C, but is not limited thereto.

[0077] Circuit structure 120C is disposed on surfaces S1 and S2 of substrate structure 110C. Circuit structure 120C may include at least one substructure. Here, circuit structure 120C is exemplified by having five substructures. The first part P1 of circuit structure 120C is disposed on surface S1 of substrate structure 110C and includes substructures 121C, 122C, and 123C. The second part P2 of circuit structure 120C is disposed on surface S2 of substrate structure 110C and includes substructures 124C and 125C. However, this is not a limitation, and the number of substructures in circuit structure 120C can be adjusted according to actual needs. Substructure 121C may include an insulating layer I21 and a conductor layer C21, with conductor layer C21 disposed within insulating layer I21. Substructure 122C may include an insulating layer I22 and a conductor layer C22, with conductor layer C22 disposed within insulating layer I22. Substructure 123C may include an insulating layer I23 and a conductor layer C23, wherein the conductor layer C23 is disposed within the insulating layer I23. Substructure 124C may include an insulating layer I24 and a conductor layer C24, wherein the conductor layer C24 is disposed within the insulating layer I24. Substructure 125C may include an insulating layer I25 and a conductor layer C25, wherein the conductor layer C25 is disposed within the insulating layer I25.

[0078] Circuit structure 160C is disposed on surfaces S5 and S6 of substrate structure 150C. Circuit structure 160C may include at least one substructure. Here, we take an example where circuit structure 160C includes five substructures. The first part P3 of circuit structure 160C is disposed on surface S5 of substrate structure 150C and includes substructures 161C, 162C, and 163C. The second part P4 of circuit structure 160C is disposed on surface S6 of substrate structure 150C and includes substructures 164C and 165C. However, this is not a limitation, and the number of substructures in circuit structure 160C can be adjusted according to actual needs. Substructure 161C may include an insulating layer I61 and a conductor layer C61, with conductor layer C61 disposed within insulating layer I61. Substructure 161C may further include an arc-shaped portion AP1 disposed at the top edge of insulating layer I61. This helps reduce the risk of substructure 161C peeling off from encapsulation layer 140. Substructure 162C may include an insulating layer I62 and a conductor layer C62, wherein the conductor layer C62 is disposed within the insulating layer I62. Substructure 163C may include an insulating layer I63 and a conductor layer C63, wherein the conductor layer C63 is disposed within the insulating layer I63. Substructure 164C may include an insulating layer I64 and a conductor layer C64, wherein the conductor layer C64 is disposed within the insulating layer I64. Substructure 165C may include an insulating layer I65 and a conductor layer C65, wherein the conductor layer C65 is disposed within the insulating layer I65.

[0079] The package structure 130C is disposed on the circuit structure 120C and is electrically connected to the circuit structure 120C. Figure 6 In this embodiment, the electronic device 1C can be an integrated fan-out package unit, with the package structure 130C disposed on the substrate structure 110C and the substrate structure 150C, wherein the substrate structure 110C can serve as an interposer.

[0080] The electronic device 1C may further include multiple bonding elements CE1, multiple bonding elements CE2, and multiple bonding elements CE3. The multiple bonding elements CE1 are disposed between the package structure 130C and the circuit structure 120C, and the package structure 130C is electrically connected to the circuit structure 120C via the multiple bonding elements CE1. The multiple bonding elements CE2 are disposed between the circuit structure 120C and the circuit structure 160C, and the circuit structure 120C is electrically connected to the circuit structure 160C via the multiple bonding elements CE2. The circuit structure 120C may further include multiple pads CP1 disposed on the surface S42 of the substructure 125C and electrically connected to the conductor layer C25 of the substructure 125C. The multiple bonding elements CE2 are electrically connected to the circuit structure 120C via the multiple pads CP1 disposed on the surface S42 of the substructure 125C. Multiple bonding elements CE3 are disposed on the surface of circuit structure 160C away from package structure 130C, specifically on the surface S43 of substructure 165C away from substrate structure 150C. Circuit structure 160C can be electrically connected to other external components (not shown) via bonding elements CE3. Circuit structure 160C further includes multiple pads CP2 disposed on surface S43 of substructure 165C and electrically connected to conductor layer C65 of substructure 165C. Multiple bonding elements CE3 are electrically connected to circuit structure 160C via multiple pads CP2 disposed on surface S43 of substructure 165C.

[0081] In this embodiment, at least one of the plurality of bonding elements CE1 is smaller than the size of at least one of the plurality of bonding elements CE2, and at least one of the plurality of bonding elements CE2 is smaller than the size of at least one of the plurality of bonding elements CE3. Furthermore, the sizes of the plurality of bonding elements CE1, CE2, and CE3 may be equal. The aforementioned "size" may refer to the maximum length of each bonding element CE1, CE2, and CE3 in the horizontal direction (e.g., direction X). The materials of the plurality of bonding elements CE1, CE2, and CE3 may be independently the same or different. Further details regarding bonding element CE3 can be found in the descriptions of bonding elements CE1 and CE2 above.

[0082] The electronic device 1C may further include filler material UF1 and filler material UF2, wherein filler material UF1 is disposed in the gaps between the plurality of bonding elements CE1, and filler material UF2 is disposed in the gaps between the plurality of bonding elements CE2. Filler material UF1 and filler material UF2 may be independently the same or different; for other details regarding filler material UF2, please refer to the relevant description of filler material UF1 above.

[0083] The electronic device 1C may further include an encapsulation layer 140 surrounding the substrate structure 150C, the circuit structure 160C, the substrate structure 110C, the circuit structure 120C, and the encapsulation structure 130C, and the encapsulation layer 140 filling the gap G1 between the electronic unit 132 and the electronic unit 134.

[0084] The electronic device 1C may further include a protective layer 170 disposed on the lower surface of the circuit structure 160C, i.e., the surface S43 of the substructure 165C away from the substrate structure 150C. A portion of the protective layer 170 may be disposed in the gaps between the plurality of bonding elements CE3. The protective layer 170 can be used to prevent moisture or contaminants from entering the metal traces of the circuit structure 160C and can be used to define the size of the bonding elements CE3. According to one embodiment, the protective layer 170 may be solder resist ink, but is not limited thereto.

[0085] Please refer to Figure 7 This is a cross-sectional schematic diagram of an electronic device 1D according to another embodiment of the present invention. The main differences between electronic device 1D and electronic device 1C are described below. The conductive element 154D of the substrate structure 150D may include a buffer layer 1541 and a conductor layer 1542, wherein the buffer layer 1541 may be disposed between the conductor layer 1542 and the substrate layer 152D. The pad C62a of the conductor layer C62 partially covers the upper surface of the conductive element 154D exposed by the substrate layer 152D, and the pad C63a of the conductor layer C63 partially covers the lower surface of the conductive element 154D exposed by the substrate layer 152D. Further details regarding electronic device 1D can be found in the description of electronic device 1C above.

[0086] Please refer to Figure 8This is a cross-sectional schematic diagram of an electronic device 1E according to another embodiment of the present invention. The main difference between electronic device 1E and electronic device 1D is that substrate structure 110E further includes an electronic unit 118 disposed within substrate structure 110E, and substrate structure 150E further includes a stress-resistant layer 156D. Specifically, substrate structure 110E includes a substrate layer 112E, a conductive element 114E, and an electronic unit 118. The conductive element 114E and the electronic unit 118 are disposed in the substrate layer 112E, which surrounds the conductive element 114E and the electronic unit 118. The stress-resistant layer 156D and the warpage adjustment layer 270 may be made of the same or different materials. The fact that the electronic unit 118 is disposed within substrate structure 110E means that the electronic unit 118 can be disposed in a groove in substrate layer 112E of substrate structure 110E. The disposal method includes pick-and-place methods, surface mount technology (SMT), thin film deposition technology, combinations thereof, or other suitable methods, but is not limited thereto. Electronic unit 118 may include semiconductor structures, active elements, passive elements, combinations thereof or other suitable elements, but is not limited thereto.

[0087] Electronic unit 118, electronic units 132, and electronic unit 134 can be electrically connected via circuit structure 120C and bonding element CE1. At least one of electronic unit 118, electronic unit 132, and electronic unit 134 can completely or partially overlap in the vertical direction (e.g., direction Z), which helps to maximize the utilization of planar space and allows for a denser arrangement of electronic components in the electronic device 1E, meeting the current trend of miniaturization in electronic products. Furthermore, electronic unit 118, electronic unit 132, and electronic unit 134 can be connected via vertical wires, which, compared to horizontal wire connections, reduces signal loss and provides better signal transmission performance.

[0088] In some embodiments, electronic unit 118 may be a passive element, such as a resistor, capacitor, or inductor, but is not limited thereto. In some embodiments, electronic unit 118 may also be an active element, such as a chip of a different type than electronic unit 132 and electronic unit 134, but is not limited thereto.

[0089] The substrate structure 150E includes a substrate layer 152D, a conductive element 154D, and a stress-resistant layer 156D. The conductive element 154D is disposed in the substrate layer 152D, the substrate layer 152D surrounds the conductive element 154D, and the stress-resistant layer 156D surrounds the substrate layer 152D. In some embodiments, the substrate layer 152D may have an arcuate side surface, and the stress-resistant layer 156D is disposed on the arcuate side surface of the substrate layer 152D. This helps to reduce the risk of peeling between the stress-resistant layer 156D and the substrate layer 152D. By providing the stress-resistant layer 156D, the overall coefficient of thermal expansion of the substrate structure 150E can be adjusted, thereby adjusting the overall stress of the substrate structure 150E to mitigate the warping of the substrate structure 150E. Alternatively, according to some embodiments, by providing the stress-resistant layer 156D around the substrate layer 152D, the risk of cracking of the substrate layer 152D can be reduced, but this is not a limitation.

[0090] Please refer to Figure 9 and Figure 10 , Figure 9 This is a flowchart of the steps of a method for manufacturing an electronic device according to another embodiment of the present invention, 300. Figure 10 This is a cross-sectional schematic diagram of an electronic device 1F according to another embodiment of the present invention. Here, the description will focus on manufacturing the electronic device 1F using the electronic device manufacturing method 300, but is not limited thereto. The electronic device manufacturing method 300 of the present invention can be used to manufacture other electronic devices.

[0091] The method 300 for manufacturing an electronic device includes steps 310 and 340, and optionally includes steps 320, 330, and 350. Step 310 involves providing a carrier plate 210. The carrier plate 210 is illustrated herein as a single-layer structure, but is not limited thereto. In other embodiments, the carrier plate 210 may be a multi-layer structure, such as a two-layer structure, a three-layer structure, or a structure with more than three layers. The material of the carrier plate 210 may include, for example, glass, bismaleimide-triazine (BT), flame retardant 4 (FR4), silicon, other suitable materials, or combinations thereof, but is not limited thereto. The carrier plate 210 may optionally include marking elements 212, which may be, for example, alignment mark elements and / or test key elements, but are not limited thereto. Alignment markers can be used to assist in alignment, thereby improving alignment accuracy between different layers and reducing pattern misalignment. Test key elements can be used to monitor process variations, such as detecting warpage.

[0092] Step 320 involves providing a warpage adjustment layer 270 disposed on the carrier board 210. The warpage adjustment layer 270 is used to mitigate the warpage of the subsequently formed circuit structure 220. The warpage adjustment layer 270 is configured to have a warpage direction opposite to that of the circuit structure 220. For example, if the circuit structure 220 is known to warp upwards based on the materials of insulating layers I222 and I224, the warpage adjustment layer 270 is selected from materials that warp downwards; that is, the warpage adjustment layer 270 can be selected from materials with a warpage trend opposite to that of the circuit structure 220. The warpage adjustment layer 270 can be a single-layer or multi-layer structure (not shown), and the material of the warpage adjustment layer 270 can include inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In this embodiment, the number of warpage adjustment layers 270 is one, and it is disposed on the upper surface of the carrier board 210, but it is not limited thereto. In some embodiments, the warpage adjustment layer 270 may be disposed on the lower surface of the carrier plate 210. In other embodiments, there are two warpage adjustment layers 270, which are disposed on the upper and lower surfaces of the carrier plate 210, respectively.

[0093] Step 330 involves providing a release layer 280 disposed on the carrier plate 210. The release layer 280 is used to separate the carrier plate 210 from the formed element after subsequent steps are completed. The release layer 280 may include, for example, a polyethylene (PE) release film, a PET release film, an oriented polypropylene (OPP) release film, a composite release film (i.e., the substrate is composed of two or more materials), etc., but is not limited thereto. In some embodiments, when the carrier plate 210 is part of the final product, the release layer 280 is not required. In this embodiment, the release layer 280 may be disposed above or below the warpage adjustment layer 270, depending on whether the warpage adjustment layer 270 is part of the final product. When the release layer 280 is positioned above the warpage adjustment layer 270, during the separation of the release layer 280 from the circuit structure 220, the warpage adjustment layer 270 and the carrier board 210 will separate from the circuit structure 220 together with the release layer 280; that is, the warpage adjustment layer 270 is not part of the final product. When the release layer 280 is positioned below the warpage adjustment layer 270, during the separation of the release layer 280 from the circuit structure 220, the stress layer 270 can remain on the circuit structure 220 and can be part of the final product. In other words, the order of steps 320 and 330 can be adjusted according to actual needs.

[0094] Step 340 involves providing a circuit structure 220 disposed on the carrier board 210. This will be illustrated using an example where the circuit structure 220 comprises two substructures: a first substructure 222 and a second substructure 224. Optionally, the circuit structure 220 may further include multiple pads CP3 disposed on the second substructure 224.

[0095] Step 340 may include steps 342, 344, and 346, and optionally include step 348. Step 342 involves providing a first substructure 222 on the carrier plate 210, wherein the first substructure 222 includes a first adjustment member AE1. Specifically, the first substructure 222 includes an insulating layer I222, a conductor layer C222, and the first adjustment member AE1, the conductor layer C222 and the first adjustment member AE1 being disposed within the insulating layer I222 and surrounding the conductor layer C222 and the first adjustment member AE1. The coefficient of thermal expansion of the first substructure 222 can be adjusted via the first adjustment member AE1. In some embodiments, the first adjustment member AE1 may provide a heat dissipation function.

[0096] The material of the first adjustment element AE1 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof, copper, any other material with a hardness greater than and a coefficient of thermal expansion lower than that of the insulating layer surrounding it (here, insulating layer I222), other suitable materials, or combinations of the above materials, but is not limited thereto.

[0097] Here, the number of first adjusting members AE1 is two, and the thickness of the first adjusting member AE1 is less than the thickness of the first substructure 222, but it is not limited to this. In some embodiments, the number of first adjusting members AE1 may be equal to one or greater than two. In some embodiments, the thickness of the first adjusting member AE1 may be equal to the thickness of the first substructure 222. When the number of first adjusting members AE1 is multiple, the material and thickness of the multiple first adjusting members AE1 may be independently the same or different. In other words, the material, number, and thickness of the first adjusting members AE1 can be adjusted according to actual needs.

[0098] Step 344 involves calculating the degree of warpage of the first substructure 222. The calculation of the degree of warpage is as follows: the warpage direction or height of the element in the Z-direction is measured using an optical instrument. Specifically, with the X-axis as the reference 0-axis, the distance between at least two edges of the element and the 0-axis represents the degree of warpage. In some embodiments, a warpage falling within 8 mm indicates that the warpage is within an acceptable range, but this is not a limitation.

[0099] Step 346 involves providing a second substructure 224 on the first substructure 222, and determining whether to provide a second adjustment member AE2 in the second substructure 224 based on the degree of warpage. Specifically, the second substructure 224 includes an insulating layer I224 and a conductor layer C224, and may selectively include a second adjustment member AE2 depending on the degree of warpage of the first substructure 222. The conductor layer C224 and the second adjustment member AE2 are disposed within the insulating layer I224, and the insulating layer I224 surrounds the conductor layer C224 and the second adjustment member AE2. For example, when the degree of warpage of the first substructure 222 is within an acceptable range, it is not necessary to provide a second adjustment member AE2 in the second substructure 224 to balance the degree of warpage of the first substructure 222. When the degree of warpage of the first substructure 222 falls outside the desired range, it is necessary to provide a second adjustment member AE2 in the second substructure 224 to balance the degree of warpage of the first substructure 222. Figure 10 Since the warping of the first substructure 222 falls outside the expected range, a second adjustment member AE2 is provided in the second substructure 224.

[0100] The second adjusting member AE2 and the first adjusting member AE1 may or may not overlap in the vertical direction (e.g., direction Z). Regarding the material of the second adjusting member AE2, please refer to the relevant description of the material of the first adjusting member AE1. The materials of the first adjusting member AE1 and the second adjusting member AE2 may be the same or different independently.

[0101] Here, the number of second adjusting members AE2 is two, and the thickness of the second adjusting member AE2 is less than the thickness of the second substructure 224, but is not limited thereto. In some embodiments, the number of second adjusting members AE2 may be one or more. In some embodiments, the thickness of the second adjusting member AE2 may be equal to the thickness of the second substructure 224. When there are multiple second adjusting members AE2, the material and thickness of the multiple second adjusting members AE2 may be independently the same or different. In other words, the material, number, and thickness of the second adjusting members AE2 can be adjusted according to actual needs.

[0102] In some embodiments, when the number of substructures of circuit structure 220 is greater than three, the warpage of the second substructure 224 can be calculated after the second substructure 224 is completed. When providing a third substructure (not shown) on the second substructure 224, it can be determined whether to provide a third adjustment element in the third substructure based on the warpage of the second substructure 224, and so on, until the number of substructures of circuit structure 220 reaches the required number, but is not limited thereto. As long as the aforementioned steps are performed on two adjacent substructures in circuit structure 220, it is beneficial to reduce the overall warpage of circuit structure 220. In other words, the manufacturing method 300 of the electronic device of the present invention can monitor the warpage of the newly completed substructure in real time, and can determine whether to provide an adjustment element in the next layer of substructure based on the warpage, thereby balancing the aforementioned warpage in real time. When the number of substructures of circuit structure 220 is greater than two layers, the risk of excessive warpage of the overall circuit structure 200 due to the accumulation of warpage in multiple substructures can be reduced.

[0103] Step 348 involves providing a plurality of pads CP3 disposed on the second substructure 224. The circuit structure 220 can be electrically connected to the subsequently formed package structure 230 via the pads CP3. In some embodiments, the pads CP3 may be fabricated simultaneously with at least a portion of the conductor layer C224, but are not limited thereto.

[0104] Step 350 involves providing a package structure 230 disposed on the circuit structure 220. The package structure 230 includes an electronic unit 232, a package layer 234, bonding elements CE4, and a filler material UF3. The electronic unit 232 is disposed on the circuit structure 220 and electrically connected to the circuit structure 220 via the bonding elements CE4. The filler material UF3 is disposed in the gaps between the plurality of bonding elements CE1 and the plurality of pads CP3. The package layer 234 covers the electronic unit 232 and the filler material UF3, wherein the package layer 234 covers and surrounds the electronic unit 232 and the filler material UF3, and the package layer 234 covers the surface of the second substructure 224 not covered by the filler material UF3.

[0105] The ratio of the coefficient of thermal expansion of the package structure 230 to the coefficient of thermal expansion of at least one of the first substructure 222 and the second substructure 224 is greater than or equal to 0.8 and less than or equal to 1.5. The coefficient of thermal expansion of the package structure 230 can be jointly determined by the electronic unit 232, the package layer 234, the bonding element CE4, and the filler material UF3. The coefficient of thermal expansion of the first substructure 222 can be jointly determined by the insulating layer I222, the conductor layer C222, and the first adjustment element AE1. The coefficient of thermal expansion of the second substructure 224 can be jointly determined by the insulating layer I224, the conductor layer C224, and the second adjustment element AE2. The coefficient of thermal expansion can be calculated according to the above formula (I), which will not be elaborated here.

[0106] Furthermore, after the circuit structure 220 is fabricated, the coefficients of thermal expansion of the first substructure 222 and / or the second substructure 224 can be calculated based on the components and / or elements contained in the first substructure 222 and / or the second substructure 224. Then, the proportion of each component and / or element in the package structure 230 is determined so that the ratio of the coefficient of thermal expansion of the package structure 230 to the coefficient of thermal expansion of at least one of the first substructure 222 and the second substructure 224 can satisfy the above relationship, which is beneficial to improving the matching degree of the coefficients of thermal expansion between the package structure 230 and the circuit structure 220.

[0107] The manufacturing method 300 for an electronic device can be applied to the manufacture of any one of electronic devices 1A, 1B, 1C, 1D, and 1E. That is, any substructure in the circuit structure of electronic devices 1A, 1B, 1C, 1D, or 1E may selectively include an adjustment element. Taking the manufacturing method 300 for electronic devices as an example of manufacturing electronic device 1A, in step 310, Figure 10 The carrier board 210 can be replaced by the substrate structure 110A, and steps 320 and 330 can be omitted, that is, the substrate structure 110A can be part of the final product (i.e., electronic device 1A). In step 340, the circuit structure 220 can be replaced by the first part P1 of the circuit structure 120A, and in step 350, Figure 10 The encapsulation structure 230 can be replaced with the encapsulation structure 130A. Then, the semi-finished electronic device 1F can be flipped over, and the second part P2 of the circuit structure 220 can be completed. The second part P2 of the circuit structure 120A can also be made using steps 342 to 346.

[0108] As can be seen from the above, in the electronic device according to the present invention, the ratio of the thermal expansion coefficient of the packaging structure to the thermal expansion coefficient of at least one substructure in the circuit structure is greater than or equal to 0.8 and less than or equal to 1.5. This is beneficial for improving the matching degree of the thermal expansion coefficients between the packaging structure and the circuit structure, and thus beneficial for reducing the warpage of the electronic device. The manufacturing method of the electronic device of the present invention can monitor the warpage of the newly completed substructure in real time, and can determine whether to provide an adjustment component in the next layer of substructure based on the warpage, thereby balancing the aforementioned warpage in real time. When the number of substructures in the circuit structure is greater than two layers, it is beneficial for reducing the probability of excessive warpage of the overall circuit structure due to the accumulation of warpage in multiple substructures.

[0109] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electronic device, characterized in that, include: A first substrate structure; A first circuit structure is disposed on a surface of the first substrate structure, wherein the first circuit structure includes a first substructure. as well as An encapsulation structure is disposed on the first circuit structure and electrically connected to the first circuit structure; The first substructure has a first coefficient of thermal expansion, the encapsulation structure has a second coefficient of thermal expansion, and the ratio of the second coefficient of thermal expansion to the first coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.

5.

2. The electronic device according to claim 1, characterized in that, The first substrate structure has a third coefficient of thermal expansion, and the ratio of the second coefficient of thermal expansion to the third coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.

5.

3. The electronic device according to claim 1, characterized in that, At least one of the first substrate structure, the first substructure, and the packaging structure further includes at least one warp adjustment layer.

4. The electronic device according to claim 1, characterized in that, The first substrate structure includes a substrate layer and a conductive element. The substrate layer has a through hole, and the conductive element is disposed in the through hole. The conductive element includes a buffer layer and a conductor layer, and the buffer layer is disposed between the conductor layer and the substrate layer.

5. The electronic device according to claim 1, characterized in that, The first substructure includes a first insulating layer and a first conductor layer disposed in the first insulating layer. In the first substructure, the content of the first conductor layer is from 2% to 55% by volume.

6. The electronic device according to claim 5, characterized in that, The first substructure also includes a first adjustment member disposed in the first insulating layer.

7. The electronic device according to claim 1, characterized in that, The first substrate structure includes a second electronic unit disposed inside the first substrate structure.

8. The electronic device according to claim 1, characterized in that, The first circuit structure further includes a second substructure, which is disposed on opposite sides of the first substructure and the first substructure. The second substructure has a fourth coefficient of thermal expansion, and the ratio of the second coefficient of thermal expansion to the fourth coefficient of thermal expansion is greater than or equal to 0.8 and less than or equal to 1.

5.

9. A method for manufacturing an electronic device, characterized in that, include: Provide a carrier board; as well as A circuit structure is provided on the carrier board, including: A first substructure is provided on the carrier plate, wherein the first substructure includes a first adjustment member; Calculate the degree of warping of the first substructure; and A second substructure is provided on the first substructure, and a second adjustment element is provided in the second substructure depending on the degree of warpage.

10. The method for manufacturing an electronic device according to claim 9, characterized in that, Also includes: A warp adjustment layer is provided on the carrier plate.

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