Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor is provided that yields a high Q value. In the multilayer ceramic capacitor (1), the dielectric layer (40) comprises (Ca) 1－x－y Sr x Ba y ) m (Zr) 1－z－α Ti z At least one of O3 (where x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) and TiO2, when the length of the straight line that will become the boundary line (65) of the inner electrode layer (30) and the dielectric layer (40) is set to S and the length of the actual boundary line (66) of the inner electrode layer (30) and the dielectric layer (40) is set to A, A / S is 1.7 or less, the thickness of the end (33) of the width direction (W) of the inner electrode layer (30) is 1.2 μm or more, the coverage of the end (33) of the width direction (W) of the inner electrode layer (30) is greater than the coverage of the central part (34), and the average particle size of copper contained in the inner electrode layer (30) is 2.2 μm or more.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] For applications in electronic devices with high-frequency circuits, multilayer ceramic capacitors with high Q values ​​in the high-frequency region are required. Patent Document 1 discloses a technique for improving the Q value of multilayer ceramic capacitors in the high-frequency region by thickening the internal electrodes.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2000-306762 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Regarding electrical conduction in the high-frequency region, conduction near the surface of the internal electrodes plays a dominant role. This is due to the skin effect. Therefore, for example, increasing the thickness of the internal electrodes results in a small increase in surface area and a minimal improvement in the Q value. The object of the present invention is to provide a multilayer ceramic capacitor that yields a high Q value.

[0008] Technical solutions for solving the problem

[0009] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor comprising a multilayer of dielectric layers and a multilayer of internal electrode layers, wherein the dielectric layers contain (Ca) 1－x－y Sr x Ba y ) m (Zr) 1－z－α Ti z At least one of O3 (where x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) and TiO2, wherein the length of the straight line that forms the boundary line between the internal electrode layer and the dielectric layer at the end of the internal electrode layer in the width direction in a cross section of the laminate orthogonal to the lamination direction is S, and the actual length of the boundary line between the internal electrode layer and the dielectric layer is A, and A / S is 1.7 or less, the thickness of the end of the internal electrode layer in the width direction is 1.2 μm or more, the coverage of the end of the internal electrode layer in the width direction is greater than the coverage of the central part of the internal electrode layer in the width direction, and the average particle size of copper contained in the internal electrode layer is 2.2 μm or more.

[0010] Invention Effects

[0011] According to the present invention, a multilayer ceramic capacitor with a high Q value can be provided. Attached Figure Description

[0012] Figure 1 This is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0013] Figure 2 yes Figure 1 Sectional view along line 201-201.

[0014] Figure 3 yes Figure 1 Sectional view along line 202-202.

[0015] Figure 4 yes Figure 1 Sectional view along line 203-203.

[0016] Figure 5 It is Figure 4 The first enclosing box 111 shows an enlarged view of the figure.

[0017] Figure 6 This is a diagram showing an LT cross-section of the end of the internal electrode layer in the width direction.

[0018] Figure 7 This is a diagram showing the central LT cross-section in the width direction of the internal electrode layer.

[0019] Figure 8 This is a diagram showing the LW cross-section of a multilayer ceramic capacitor. Detailed Implementation

[0020] (Laminated ceramic capacitor)

[0021] The following is a summary of the multilayer ceramic capacitor 1 according to an embodiment of the present invention. Figure 1 This is a perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present invention. Figure 1 As shown, the multilayer ceramic capacitor 1 includes a multilayer body 2 and an external electrode 50. The external electrode 50 includes a first external electrode 51 and a second external electrode 52.

[0022] (Layered structure)

[0023] Figure 2 yes Figure 1 Sectional view along line 201-201. Figure 3 yes Figure 1 Sectional view along line 202-202. Figure 4 yes Figure 1 The sectional view along line 203-203. (See example.) Figure 2 as well as Figure 3 As shown, the laminate 2 includes an internal electrode layer 30 and a dielectric layer 40. Multiple internal electrode layers 30 and dielectric layers 40 are included in the laminate 2. The internal electrode layers 30 and dielectric layers 40 are stacked sequentially.

[0024] (Direction of the stacked body)

[0025] The general shape of the stack 2 is a cuboid. The stacking direction T is the direction in which the internal electrode layer 30 and the dielectric layer 40 are stacked. The length direction L is one of the directions orthogonal to the stacking direction T. The width direction W is a direction orthogonal to both the stacking direction T and the length direction L.

[0026] (Name of the cross-section)

[0027] The LT section is a section parallel to the length direction L and the stacking direction T. Figure 2 The LT section is shown. The WT section is parallel to the width direction W and the stacking direction T. Figure 3 The WT section is shown. The LW section is a section parallel to the length direction L and the width direction W. Figure 4 The LW profile is shown.

[0028] (Surface of the laminate)

[0029] The first principal surface T1 and the second principal surface T2 are two surfaces of a laminate that are opposite each other in the stacking direction T. The first side surface W1 and the second side surface W2 are two surfaces of a laminate that are opposite each other in the width direction W. The first end surface L1 and the second end surface L2 are two surfaces of a laminate that are opposite each other in the length direction L.

[0030] (Internal electrode layer)

[0031] The internal electrode layer 30 includes a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 is an internal electrode layer 30 that extends to a first end face L1. The second internal electrode layer 32 is an internal electrode layer 30 that extends to a second end face L2. Figure 4 The first internal electrode layer 31 is shown.

[0032] The inner electrode layer 30 contains copper as the main component. The inner electrode layer 30 may also contain metals other than copper.

[0033] The total number of internal electrode layers 30 is the sum of the number of layers in the first internal electrode layer 31 and the number of layers in the second internal electrode layer 32. The preferred total number of layers is 2 or more and 30 or less.

[0034] (Dielectric layer)

[0035] Dielectric layer 40 comprises general formula (Ca)1－x－y Sr x Ba y ) m (Zr) 1－z－α Ti z The main component is at least one of the following: a ceramic material represented by the above general formula (where x is 0 or more and less than 1, y is 0 or more and less than 0.4, m is 1.0 or more and less than 1.1, z is 0 or more and less than 0.2, and α is 0 or more and less than 0.3). Examples of ceramic materials represented by the above general formula include calcium zirconate (CaZrO3). In addition to the main components mentioned above, additives can be added according to the purpose. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, Cr, or V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, Y; oxides of Co, Ni, Li, B, Na, K, and Si; or glass.

[0036] The preferred thickness of the dielectric layer 40, which is sandwiched between the first inner electrode layer 31 and the second inner electrode layer 32 in the stacking direction T, is 0.3 μm or more and 20 μm or less.

[0037] (Size of the stacked body)

[0038] The size of the laminate 2 is not limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 10 mm or less. The preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 5 mm or less. The preferred length of the laminate 2 in the lamination direction T is 0.1 mm or more and 5 mm or less.

[0039] (External electrode)

[0040] The external electrode 50 includes a first external electrode 51 and a second external electrode 52. The first external electrode 51 is an external electrode 50 connected to the first internal electrode layer 31. The second external electrode 52 is an external electrode 50 connected to the second internal electrode layer 32.

[0041] The first external electrode 51 is disposed on the first end face L1, a portion of the first main face T1, a portion of the second main face T2, a portion of the first side face W1, and a portion of the second side face W2. The second external electrode 52 is disposed on the second end face L2, a portion of the first main face T1, a portion of the second main face T2, a portion of the first side face W1, and a portion of the second side face W2.

[0042] The external electrode 50 includes a base electrode layer 53 and a plating layer 55. The plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57. The base electrode layer 53, the nickel plating layer 56, and the tin plating layer 57 are arranged in the order of base electrode layer 53, nickel plating layer 56, and tin plating layer 57, starting from the end face of the laminate 2.

[0043] The substrate electrode layer 53 comprises metal and glass. Examples of metals include copper, nickel, silver, palladium, silver-palladium alloys, and gold. Examples of glass include borosilicate glass and silicon-based glass. The substrate electrode layer 53 is obtained by firing a conductive paste. The conductive paste comprises metal and glass. The conductive paste is fired after being applied to the laminate 2. The preferred thickness of the substrate electrode layer 53 is 3 μm or more and 100 μm or less.

[0044] The nickel plating layer 56 is configured to cover the substrate electrode layer 53. The tin plating layer 57 is configured to cover the nickel plating layer 56.

[0045] The multilayer ceramic capacitor 1 is mounted onto the substrate using solder. A nickel plating layer 56 inhibits the solder from eroding the base electrode layer 53. A tin plating layer 57 improves the wettability of the solder onto the multilayer ceramic capacitor 1. The tin plating layer 57 facilitates the mounting of the multilayer ceramic capacitor 1 onto the substrate.

[0046] (Size of the multilayer ceramic capacitor)

[0047] The size of the multilayer ceramic capacitor 1 is not limited. The preferred length direction L of the multilayer ceramic capacitor 1, including the multilayer body 2 and the external electrode 50, is 0.2 mm or more and 10 mm or less. The preferred stacking direction T of the multilayer ceramic capacitor 1, including the multilayer body 2 and the external electrode 50, is 0.1 mm or more and 5 mm or less. The preferred width direction W of the multilayer ceramic capacitor 1, including the multilayer body 2 and the external electrode 50, is 0.1 mm or more and 10 mm or less.

[0048] (Straightness of the ends of the internal electrode layer)

[0049] The straightness of the end 33 in the width direction W of the internal electrode layer 30 of the multilayer ceramic capacitor 1 in this embodiment is as follows. For example... Figure 4 As shown, the end 33 of the inner electrode layer 30 in the width direction W is the end edge of the inner electrode layer 30 opposite to the first side surface W1 or the second side surface W2. In the stacked ceramic capacitor 1 of this embodiment, the straightness of the end 33 of the inner electrode layer 30 in the width direction W is high.

[0050] Figure 4The length-direction centerline 131 shown is a line drawn at the center of the length direction L of the laminate 2. The width-direction centerline 132 is a line drawn at the center of the width direction W of the laminate 2. The center position 60 is the center position of both the length direction L and the width direction W of the laminate 2. The center position 60 is located at the intersection of the length-direction centerline 131 and the width-direction centerline 132. The first position 71 and the second position 72 are located on the end 33 of the width direction W of the inner electrode layer 30. The midpoint between the first position 71 and the second position 72 is located on the length-direction centerline 131.

[0051] (Length S)

[0052] The first line segment 121 is the line segment connecting the first position 71 and the second position 72. The length S is the length of the first line segment 121. The length S means the following: The shape of the inner electrode layer 30 is considered as a polygon when viewed from the stacking direction T. When the inner electrode layer 30 is a polygon, the boundary line between the inner electrode layer 30 and the dielectric layer 40 becomes a straight line. Figure 4 The shape of the internal electrode layer 30 shown can be considered as a rectangle, which is a type of polygon. The boundary line between the internal electrode layer 30 and the dielectric layer 40 is simulated as a straight line. Figure 5 It is Figure 4 The bounding box 111 is enlarged to show the figure. Figure 5 The dashed line 65 shown represents the boundary line when it is set as a straight line. Length S is the length of dashed line 65. The length of dashed line 65 is related to... Figure 4 The length of the first line segment 121 is the same.

[0053] (Length A)

[0054] Figure 5 The solid line 66 shown is the actual boundary line between the inner electrode layer 30 and the dielectric layer 40. The actual boundary line 66 is not a straight line when viewed from above in the stacking direction T. Length A is the length of the actual boundary line 66.

[0055] (Length A / Length S)

[0056] When the actual boundary line 66 between the inner electrode layer 30 and the dielectric layer 40 is a straight line, length A is equal to length S. Except when the actual boundary line 66 between the inner electrode layer 30 and the dielectric layer 40 is a straight line, length A becomes longer than length S. The ratio of length A to length S is generally greater than 1.0. Length A / length S indicates the straightness of the end 33 of the inner electrode layer 30. If length A / length S is close to 1, the straightness is better. If length A / length S is larger, the straightness is worse. In this embodiment, the length A / length S of the multilayer ceramic capacitor 1 is 1.7 or less.

[0057] When the multilayer ceramic capacitor 1 is used in the high-frequency region, the current mainly flows through the surface of the inner electrode layer 30. This main current flow through the surface of the inner electrode layer 30 is due to the skin effect. The current concentrates at the actual boundary line 66 between the inner electrode layer 30 and the dielectric layer 40. When the length of the actual boundary line 66, i.e., length A, is long, the resistance value is large. With a large resistance value, the ESR per unit inner electrode layer increases. A small length A is preferred. When the length A / length S is 1.7 or less, the ESR per unit electrode layer of the multilayer ceramic capacitor 1 in the high-frequency region decreases.

[0058] For example, in the relationship between length A / length S and the ESR (Ω) of each internal electrode layer at 1 GHz, the ESR when length A / length S is 1.7 is 78% of the ESR when length A / length S is 2.4. In other words, by reducing length A / length S from 2.4 to 1.7, the ESR can be reduced by 28%. Furthermore, these measurements were performed as a multilayer ceramic capacitor 1.

[0059] (Method for determining length A / length S)

[0060] The method for determining length A and length S is as follows. Length A and length S are determined based on the same cross-sectional image. The main surface of the multilayer ceramic capacitor 1 is ground to expose the LW cross-section of the internal electrode layer 30. The end 33 of the internal electrode layer 30, corresponding to the position of the first line segment 121, is magnified and observed using an electron microscope, and length A is measured. The length of the first line segment 121 when measuring length A is 80 μm. Length S is 80 μm. The magnification of the observation is set to 2000x.

[0061] (Thickness of the end of the internal electrode layer in the width direction)

[0062] The thickness of the end 33 of the internal electrode layer 30 in the width direction W of the multilayer ceramic capacitor 1 in this embodiment is as follows. In the multilayer ceramic capacitor 1 of this embodiment, the end 33 of the internal electrode layer 30 in the width direction W is thick. The thickness of the end 33 of the internal electrode layer 30 in the width direction W is 1.4 μm or more.

[0063] As a means to improve the straightness of the end 33 of the internal electrode layer 30, it is possible to increase the thickness of the end 33 in the width direction W of the internal electrode layer 30.

[0064] For example, by setting the thickness of the end 33 in the width direction W of the inner electrode layer 30 to a given thickness or more, it is possible to make the length A / length S less than a given value. In this way, if the thickness of the end 33 in the width direction W of the inner electrode layer 30 increases, the straightness of the end 33 of the inner electrode layer 30 is improved. Specifically, for example, by setting the thickness of the end 33 in the width direction W of the inner electrode layer 30 to 1.4 μm or more, it is possible to make the length A / length S less than 1.7.

[0065] (Method for measuring the thickness of the end of the internal electrode layer in the width direction)

[0066] The method for measuring the thickness of the end 33 of the width direction W of the internal electrode layer 30 is as follows. Figure 4 The end center position 61 is the location where the longitudinal centerline 131 intersects with the end 33 of the internal electrode layer 30. The thickness of the internal electrode layer 30 is measured at the end center position 61. The side surface of the multilayer ceramic capacitor 1 is ground to expose the LT cross-section of the internal electrode layer 30. The end center position 61 is magnified using an electron microscope to measure the thickness of the internal electrode layer 30. The magnification is 2000x.

[0067] Furthermore, the aforementioned measurements of length A / length S (i.e., linearity) and the thickness of the end 33 of the width direction W of the internal electrode layer 30 can be performed, for example, in the order of linearity and thickness. In this case, firstly, the main surface of the multilayer ceramic capacitor 1 is ground. Then, the LW cross-section of the internal electrode layer 30 is exposed, and the length A and length S are measured. Next, the side surface of the multilayer ceramic capacitor 1 is ground. Then, the LT cross-section of the internal electrode layer 30 is exposed, and the thickness of the internal electrode layer 30 is measured.

[0068] (Coverage of the internal electrode layer)

[0069] The coverage of the internal electrode layer 30 of the multilayer ceramic capacitor 1 in this embodiment is as follows. Figure 4 The central portion 34 of the internal electrode layer 30 shown is located on the central line 132 in the width direction. The central portion 34 of the internal electrode layer 30 is located at the center of the width direction W of the internal electrode layer 30. In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the end portion 33 in the width direction W of the internal electrode layer 30 is greater than the coverage of the central portion 34 in the width direction W of the internal electrode layer 30. The coverage includes line coverage and surface coverage. At least one of line coverage and surface coverage, the coverage of the end portion 33 in the width direction W of the internal electrode layer 30 is greater than the coverage of the central portion 34 in the width direction W of the internal electrode layer 30.

[0070] (Line coverage)

[0071] Line coverage is the coverage measured in the LT section of the inner electrode layer 30. The cross-section of the inner electrode layer 30 observed in the LT section can be considered as a line. Line coverage indicates the proportion of metal in the inner electrode layer 30, which is considered as a line. Specifically, it is the proportion of the length other than the break 35 relative to the overall length of a given line segment. The calculated proportion is taken as the line coverage. Figure 6 This is a diagram showing the LT cross-section of the end 33 of the inner electrode layer 30 in the width direction W. Figure 6 The segment 35 shown is the part that divides the internal electrode layer 30. The line coverage of the end 33 in the width direction W of the internal electrode layer 30 is greater than the line coverage of the central portion 34 in the width direction W of the internal electrode layer 30.

[0072] (Line coverage at the end)

[0073] The method for measuring the line coverage of the end 33 of the inner electrode layer 30 in the width direction W is as follows. The side surface of the laminate 2 is ground to expose the LT section of the end 33 of the inner electrode layer 30. In the exposed LT section, the position of the inner electrode layer 30 corresponding to the first line segment 121 is observed using an electron microscope. The position of the first line segment 121 is as follows: Figure 4 As explained, the line coverage is determined in the internal electrode layer 30 at the position corresponding to the first line segment 121.

[0074] (Central Region 34 Line Coverage)

[0075] The method for measuring the line coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is as follows. The line coverage of the end portion 33 in the width direction W of the internal electrode layer 30 is measured at the position corresponding to the first line segment 121. The line coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is measured at the position corresponding to the first line segment 121. Figure 4 The position corresponding to the second line segment 122 shown is measured. The second line segment 122 is the line segment connecting the third position 73 and the fourth position 74. The second line segment 122 is located on the center line 132 in the width direction. The length of the second line segment 122 is the same as that of the first line segment 121. The position of the second line segment 122 in the length direction L is the same as that of the first line segment 121 in the length direction L. The third position 73 and the first position 71 are at the same position in the length direction L. The fourth position 74 and the second position 72 are at the same position in the length direction L. The side surface of the laminate 2 is ground to expose the LT section on the center line 132 in the W direction of the inner electrode layer 30. Figure 7 This is a diagram showing the LT cross-section of the central portion 34 in the width direction W of the internal electrode layer 30. The line coverage is determined by observing the position of the internal electrode layer 30 corresponding to the second line segment 122 using an electron microscope.

[0076] The line coverage of the end 33 of the width direction W of the internal electrode layer 30 is greater than the line coverage of the central part 34 of the width direction W of the internal electrode layer 30.

[0077] (Area coverage)

[0078] The surface coverage is the coverage percentage measured when the internal electrode layer 30 is viewed from above in the stacking direction T. The LW plane is the plane observed when viewed from above in the stacking direction T. The internal electrode layer 30 observed in the LW plane can be considered as a plane. The surface coverage indicates the proportion of metal in the internal electrode layer 30, which is considered as a plane. Figure 8 This is a diagram showing the LW side of the multilayer ceramic capacitor 1. Figure 8 The hole 37 shown is a hole formed in the inner electrode layer 30. The metal material forming the inner electrode layer 30 is not present in the hole 37. Surface coverage is the ratio of the area of ​​the portion of the inner electrode layer 20 excluding the hole 37 to a given area. Surface coverage can be determined based on the number of pixels contained in the image during image processing. Specifically, the surface coverage is the ratio of the number of pixels in the portion excluding the hole 37 to the total number of pixels in the inner electrode layer 20 of the observed object. The surface coverage of the region near the end 33 in the width direction W of the inner electrode layer 30 is greater than the surface coverage of the central portion 34 in the width direction W of the inner electrode layer 30. In surface coverage, the coverage of the end 33 in the width direction W of the inner electrode layer 30 means the coverage within a given range including the end 33. In surface coverage, the coverage of the central portion 34 in the width direction W of the inner electrode layer 30 means the coverage within a given range including the central portion 34.

[0079] (Surface coverage at the end)

[0080] The method for measuring the surface coverage of the end 33 in the width direction W of the internal electrode layer 30 is as follows: The dielectric layer 40 of the laminate 2 is peeled away from the internal electrode layer 30 to expose the internal electrode layer 30. The surface coverage is then calculated in the exposed LW surface.

[0081] The third enclosing frame 113 is square in shape. One side of the third enclosing frame 113 has a length of 10 μm. One side of the third enclosing frame 113 is located at the end 33 of the inner electrode layer 30 in the width direction W. The third enclosing frame 113 is located at the center in the length direction L. Position 5 75 is the location of one vertex on the end 33 of the third enclosing frame 113. Position 6 76 is the location of the other vertices on the end 33 of the third enclosing frame 113. The midpoint between position 5 75 and position 6 76 is located on the centerline 131 in the length direction.

[0082] (Central area 34 coverage rate)

[0083] The method for measuring the surface coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is as follows. The following explanation differs from the method for measuring the surface coverage of the end portion 33. The matters not described below are the same as those for measuring the surface coverage of the end portion 33. The surface coverage of the end portion 33 is measured in the third enclosure frame 113. The surface coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is measured in the second enclosure frame 112.

[0084] The second bounding box 112 is in Figure 4 As shown in the diagram, the second bounding box 112 is square in shape. One side of the second bounding box 112 has a length of 10 μm. Two sides of the second bounding box 112 are parallel to the length direction L. The other two sides of the second bounding box 112 are parallel to the width direction W. The second bounding box 112 is located at the center of the stack 2. The intersection of the two diagonals of the second bounding box 112 is located at the center position 60°.

[0085] In the multilayer ceramic capacitor 1 of this embodiment, the surface coverage of the end portion 33 in the width direction W of the inner electrode layer 30 is greater than the surface coverage of the central portion 34 in the width direction W of the inner electrode layer 30. Figure 8 The region 141 near the end shown is the region near the end 33 of the inner electrode layer 30 in the width direction W. Figure 8 The central region 142 shown is the region near the central portion 34 of the width direction W of the internal electrode layer 30. Figure 8 The distribution of pores 37 in the internal electrode layer 30 is simulated. Figure 8 The hole 37 shown is not an actual hole 37. For example... Figure 8 As shown, the density of the distribution of pores 37 in the region 141 near the end is less than the density of the distribution of pores 37 in the region 142 near the center.

[0086] In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the end portion 33 in the width direction W of the inner electrode layer 30 is greater than the coverage of the central portion 34 in the width direction W of the inner electrode layer 30. The resistance value of the end portion 33 in the width direction W of the inner electrode layer 30 decreases. The multilayer ceramic capacitor 1 of this embodiment can achieve a high Q value.

[0087] (Average grain size of copper)

[0088] The copper particle size contained in the internal electrode layer 30 of the multilayer ceramic capacitor 1 of this embodiment is as follows. In the multilayer ceramic capacitor 1 of this embodiment, the average particle size of the copper contained in the internal electrode layer 30 is 2.2 μm or more. In the multilayer ceramic capacitor 1 of this embodiment, because the average particle size of the copper contained in the internal electrode layer 30 is 2.2 μm or more, the resistance value of the internal electrode layer 30 decreases.

[0089] The average particle size of the copper contained in the inner electrode layer 30 was determined by observing the LT profile of the inner electrode layer 30 using a focused ion beam (FIB)-scanning ion microscope (SIM).

[0090] In the multilayer ceramic capacitor 1 of this embodiment, the straightness, thickness, coverage, and average copper particle size of the end 33 in the width direction W of the internal electrode layer 30 simultaneously possess the aforementioned properties. A high Q value can be obtained in the multilayer ceramic capacitor 1 of this embodiment.

[0091] (Method for manufacturing a multilayer ceramic capacitor according to the embodiment)

[0092] The manufacturing method of the multilayer ceramic capacitor 1 is described.

[0093] (1) Prepare conductive paste for dielectric sheet and internal electrode layer 30. The dielectric sheet and conductive paste contain adhesive and solvent. The adhesive and solvent can be known organic adhesive and organic solvent.

[0094] (2) A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a given pattern. That is, an internal electrode layer pattern is formed on the dielectric sheet. Examples of printing methods are screen printing or gravure printing.

[0095] (3) A given number of dielectric sheets without printed internal electrode layer patterns are stacked. A given number of dielectric sheets with printed internal electrode layer patterns are stacked on top of them. A given number of dielectric sheets without printed internal electrode layer patterns are stacked on top of them.

[0096] (4) Press the stacked sheets in the stacking direction. An example of a pressing method is isostatic pressing. The pressed stacked sheets become a stacked block.

[0097] (5) The laminated block is fired to become a laminate 2. In the laminated ceramic capacitor 1 of this embodiment, the firing temperature is 980°C or higher and 1020°C or lower.

[0098] (6) External electrodes 50 are formed on the two end faces of the laminate 2. The method for forming the external electrodes 50 can also be a known method. For example, a conductive paste with copper or nickel as the main conductive component is applied to the end faces, and then sintered to form the base electrode layer 54. The base electrode layer 54 can also be formed by applying conductive paste to both end faces of the precursor of the laminate 2 before sintering and then performing a sintering process. After the base electrode layer 53 is formed, a nickel plating layer 56 and a tin plating layer 57 are formed on the surface of the base electrode layer 53 by electrolytic plating. Thus, a multilayer ceramic capacitor is manufactured.

[0099] The embodiments of the present invention have been described above, but the present invention is not limited to the aforementioned embodiments and various changes and modifications are possible.

[0100] Explanation of reference numerals in the attached figures

[0101] 1. Multilayer ceramic capacitor

[0102] 2-layered body

[0103] 30 Internal electrode layer

[0104] 31 First Inner Electrode Layer

[0105] 32 Second inner electrode layer

[0106] 33 end

[0107] 34. Central Department

[0108] 35 points

[0109] 37 empty holes

[0110] 40 Dielectric layer

[0111] 50 External Electrode

[0112] 51 First external electrode

[0113] 52 Second external electrode

[0114] 53. Substrate Electrode Layer

[0115] 55 Coating Layer

[0116] 56 Nickel plating

[0117] 57 Tin plating layer

[0118] 60 Central position

[0119] 61. End center position

[0120] 65 Dashed line

[0121] 66. Actual boundary line

[0122] 71. Position 1

[0123] 72, Position 2

[0124] 73, 3rd position

[0125] 74, 4th position

[0126] 75, Position 5

[0127] 76, 6th position

[0128] 111 First bounding box

[0129] 112 Second bounding box

[0130] 113 Third bounding box

[0131] 121. Line segment 1

[0132] 122 Segment 2

[0133] 131. Centerline in length direction

[0134] 132 Centerline in width direction

[0135] 141. Region near the end

[0136] 142 Central Area

[0137] A. Actual length

[0138] S is the length of the straight line.

Claims

1. A multilayer ceramic capacitor comprising a multilayer body consisting of multiple dielectric layers and multiple internal electrode layers, wherein, The dielectric layer contains at least one of (Ca 1－x－y , Sr x , Ba y ) m (Zr 1－z－α , Ti z )O3 and TiO2, wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and a is 0 or more and 0.3 or less, When the length of the straight line that forms the boundary line between the internal electrode layer and the dielectric layer at the end of the internal electrode layer in the width direction of a cross section cut by a plane orthogonal to the stacking direction is defined as S, and the actual length of the boundary line between the internal electrode layer and the dielectric layer is defined as A, and A / S is 1.7 or less, The thickness of the inner electrode layer at its width end is 1.2 μm or more. The coverage at the ends of the internal electrode layer in the width direction is greater than the coverage at the center of the internal electrode layer in the width direction. The average particle size of the copper contained in the internal electrode layer is greater than 2.2 μm.

2. The multilayer ceramic capacitor according to claim 1, wherein, The coverage rate is evaluated by the number of segments that divide the internal electrode layer, given a length, when the internal electrode layer is observed in a cross-section cut in a plane parallel to the stacking direction.

3. The multilayer ceramic capacitor according to claim 1, wherein, The coverage is evaluated by the number of voids contained in the internal electrode layer within a given area when the internal electrode layer is viewed from the stacking direction.

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