Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor capable of suppressing an increase in the DC resistance of an internal electrode layer. The multilayer ceramic capacitor (1) has a laminate (10) and three or more external electrodes (40). The first internal electrode layer (31) has a first opposed electrode portion (31M), a first lead portion (31A), and a second lead portion (31B). The first opposed electrode portion (31M) has a first central portion region (31MM), a first connection portion region (31MA) as a portion connected to the first lead portion (31A), and a second connection portion region (31MB) as a portion connected to the second lead portion (31B). The coverage rates of the first connection portion region (31MA) and the second connection portion region (31MB) with respect to the dielectric layer (20) are higher than the coverage rate of the first central portion region (31MM) with respect to the dielectric layer (20). The coverage rates of the first lead portion (31A) and the second lead portion (31B) with respect to the dielectric layer (20) are higher than the coverage rate of the first central portion region (31MM) with respect to the dielectric layer (20).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor. Background Art

[0002] Conventionally, multilayer ceramic capacitors have been known. For example, as a decoupling capacitor used to stabilize the power supply voltage supplied to an integrated circuit component operating at high speed, a multilayer through-hole ceramic capacitor having a structure as described in Patent Document 1 has been known. The multilayer through-hole ceramic capacitor described in Patent Document 1 includes a ceramic substrate. Inside the ceramic substrate, a plurality of first internal electrodes and a plurality of second internal electrodes are alternately arranged in the stacking direction. Moreover, for the first internal electrode, both ends thereof are led out to both end faces in the length direction of the ceramic substrate, and for the second internal electrode, both ends thereof are led out to both end faces in the width direction of the ceramic substrate.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 2000-58376

[0006] In such a multilayer through-hole ceramic capacitor, with the high performance of the electronic device on which the multilayer through-hole ceramic capacitor is mounted, an increase in capacitance is required. Here, as one of the means for achieving an increase in capacitance, it is conceivable to increase the number of stacked sheets in the effective part by thinning the thickness of the internal electrode. However, when the thickness of the internal electrode is thinned, if the melting point of the metal powder used for the internal electrode is lower than that of the dielectric powder, the internal electrode liquefies during sintering of the dielectric layer, resulting in increased aggregation. In this case, the internal electrode is divided into multiple parts, and the coverage rate of the internal electrode layer on the dielectric layer decreases. As a result, the metal ratio of the internal electrode becomes lower, the area of the current path becomes smaller, the resistance becomes higher, and thus the DC resistance (Rdc) increases. Consequently, it is considered that the characteristics of the multilayer ceramic capacitor deteriorate. In addition, when the above-mentioned problem of the decrease in the coverage rate occurs in the lead-out portion of the internal electrode led out to the end face and side face of the ceramic substrate, the internal electrode is not sufficiently exposed from the end face and side face of the laminate, and the connectivity between the internal electrode and the external electrode decreases. When the connectivity between the internal electrode layer and the external electrode decreases, the DC resistance (Rdc) may increase more significantly. Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing an increase in the DC resistance of the internal electrode layer.

[0009] Technical Means for Solving the Problems

[0010] The multilayer ceramic capacitor according to the present invention has: a laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction and the length direction; and three or more external electrodes. In the multilayer ceramic capacitor, the plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers. The first internal electrode layer has: a first opposed electrode portion opposed to the second internal electrode layer with the dielectric layer interposed therebetween; a first lead portion extending from the first opposed electrode portion and led out to a first surface portion of the laminate; and a second lead portion extending from the first opposed electrode portion and led out to a second surface portion of the laminate. The second internal electrode layer has: a second opposed electrode portion opposed to the first internal electrode layer with the dielectric layer interposed therebetween; and a third lead portion extending from the second opposed electrode portion and led out to a third surface portion of the laminate. The three or more external electrodes have: a first external electrode connected to the first lead portion; a second external electrode connected to the second lead portion; and a third external electrode connected to the third lead portion. The first opposed electrode portion has: a first central portion region including a central portion of the first opposed electrode portion; a first connection portion region which is a portion connected to the first lead portion and has a higher coverage rate of the dielectric layer than the first central portion region; and a second connection portion region which is a portion connected to the second lead portion and has a higher coverage rate of the dielectric layer than the first central portion region. The coverage rate of the first connection portion region and the second connection portion region of the dielectric layer is higher than the coverage rate of the first central portion region of the dielectric layer. The coverage rate of the first lead portion and the second lead portion of the dielectric layer is higher than the coverage rate of the first central portion region of the dielectric layer.

[0011] Advantages of the Invention

[0012] According to the present invention, a multilayer ceramic capacitor capable of suppressing an increase in the DC resistance of the internal electrode layer can be provided. Description of the Drawings

[0013] Figure 1 is an external perspective view of the multilayer ceramic capacitor of the first embodiment.

[0014] Figure 2 is a front view when observing the multilayer ceramic capacitor shown in Figure 1 from the direction of arrow II on the side of the first side surface.

[0015] Figure 3 is a front view when observing the first main surface side of the multilayer ceramic capacitor shown in the direction of arrow III. Figure 2

[0016] Figure 4 is Figure 3 a cross-sectional view of the multilayer ceramic capacitor shown along line IV-IV.

[0017] Figure 5 is Figure 4 a cross-sectional view of the multilayer ceramic capacitor shown along line V-V.

[0018] Figure 6 is Figure 4 a cross-sectional view of the multilayer ceramic capacitor shown along line VI-VI, which is a view showing the first internal electrode layer.

[0019] Figure 7 is Figure 4 a cross-sectional view of the multilayer ceramic capacitor shown along line VII-VII, which is a view showing the second internal electrode layer.

[0020] Figure 8A is a view showing the measurement position of the coverage rate of the first internal electrode layer on the dielectric layer.

[0021] Figure 8B is a view showing the measurement position of the coverage rate of the second internal electrode layer on the dielectric layer.

[0022] Figure 9 is a cross-sectional view showing a modification example of the second internal electrode layer of the multilayer ceramic capacitor of the above-described embodiment, and is a view corresponding to Figure 7

[0023] Figure 10A is an external perspective view of the multilayer ceramic capacitor of the second embodiment.

[0024] Figure 10B is a view showing the first internal electrode layer of the above-described embodiment.

[0025] Figure 10C is a view showing the second internal electrode layer of the above-described embodiment.

[0026] Figure 11A is an external perspective view of the multilayer ceramic capacitor of the third embodiment.

[0027] Figure 11B is a view showing the first internal electrode layer of the above-described embodiment.

[0028] Figure 11C is a view showing the second internal electrode layer of the above-described embodiment.

[0029] Figure 12A It is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor according to the fourth embodiment.

[0030] Figure 12B It is a diagram showing the second internal electrode layer of the above-described embodiment.

[0031] Figure 13A It is a perspective view of the appearance of the multilayer ceramic capacitor according to the fifth embodiment.

[0032] Figure 13B It is a diagram showing the first internal electrode layer of the above-described embodiment.

[0033] Figure 13C It is a diagram showing the second internal electrode layer of the above-described embodiment.

[0034] Figure 14A It is a perspective view of the appearance of the multilayer ceramic capacitor according to the sixth embodiment.

[0035] Figure 14B It is a diagram showing the first internal electrode layer of the above-described embodiment.

[0036] Figure 14C It is a diagram showing the second internal electrode layer of the above-described embodiment.

[0037] Figure 15A It is a perspective view of the appearance of the multilayer ceramic capacitor according to the seventh embodiment.

[0038] Figure 15B It is a diagram showing the first internal electrode layer of the above-described embodiment.

[0039] Figure 15C It is a diagram showing the second internal electrode layer of the above-described embodiment.

[0040] Description of Reference Numerals

[0041] 1, 101, 201, 301: Multilayer ceramic capacitor;

[0042] 10, 310: Stacked body;

[0043] LS1: First end face;

[0044] LS2 Second end face;

[0045] WS1: First side face;

[0046] WS2 Second side face;

[0047] TS1: First main face;

[0048] TS2 Second main face;

[0049] 20: Dielectric layer;

[0050] 30: Inner electrode layer;

[0051] 31, 131, 231, 331: First inner electrode layer;

[0052] 31M, 131M, 231M, 331M: First opposed electrode part;

[0053] 31A, 131A, 231A, 331A: First lead-out part;

[0054] 31B, 131B, 131F1, 231B, 331B: Second lead-out part;

[0055] 31MM, 131MM, 231MM, 331MM: First central part region;

[0056] 31MA, 131MA, 231MA, 331MA: First connection part region;

[0057] 31MB, 131MB, 131MF1, 231MB, 331MB: Second connection part region;

[0058] 32, 132, 232, 332: Second inner electrode layer;

[0059] 32M, 132M, 232M, 332M: Second opposed electrode part;

[0060] 32C, 132C, 132B1, 232C, 332C: Third lead-out part;

[0061] 32D, 132D, 132E1, 232D, 332D: Fourth lead-out part;

[0062] 32MM, 132MM, 232MM, 332MM: Second central part region;

[0063] 32MC, 132MC, 132MB1, 232MC, 332MC: Third connection part region;

[0064] 32MD, 132MD, 132ME1, 232MD, 332MD: Fourth connection part region;

[0065] 40, 140, 240, 340: External electrode;

[0066] 40A, 140A, 240A, 340A: First external electrode;

[0067] 40B, 140B, 140F1, 240B, 340B: Second external electrode;

[0068] 40C, 140C, 140B1, 240C, 340C: The 3rd external electrode;

[0069] 40D, 140D, 140E1, 240D, 340D: The 4th external electrode;

[0070] L: Length direction;

[0071] W: Width direction;

[0072] T: Lamination direction. Detailed implementation mode

[0073] <The 1st implementation mode>

[0074] Hereinafter, the multilayer ceramic capacitor 1 according to the 1st implementation mode of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 of the present implementation mode. Figure 2 It is for Figure 1 The elevation view when observing the 1st side WS1 side of the multilayer ceramic capacitor 1 shown in the direction of arrow II. Figure 3 It is for Figure 2 The elevation view when observing the 1st main surface TS1 side of the multilayer ceramic capacitor 1 shown in the direction of arrow III. Figure 4 It is Figure 3 The cross-sectional view of the multilayer ceramic capacitor 1 shown along the line IV-IV. Figure 5 It is Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 shown along the line V-V. Figure 6 It is Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 shown along the line VI-VI, which is a view showing the 1st internal electrode layer 31. Figure 7 It is Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 shown along the line VII-VII, which is a view showing the 2nd internal electrode layer 32.

[0075] The multilayer ceramic capacitor 1 has a laminate 10 and an external electrode 40.

[0076] In Figures 1 - 7 An XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, Figure 4 The cross-sectional view shown is also called the LT cross-section. Figure 5 The cross-sectional view shown is also called the WT cross-section. Figure 6 And Figure 7 The cross-sectional view shown is also called the LW cross-section.

[0077] As shown Figures 1 - 7 in FIG. 1, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in the length direction L orthogonal to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in the width direction W orthogonal to the stacking direction T and the length direction L.

[0078] As shown Figure 1 in FIG. 2, the laminate 10 has a substantially rectangular parallelepiped shape. In addition, the dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. It is preferable that the corners and ridge lines of the laminate 10 have rounded corners. A corner is a part where three surfaces of the laminate intersect, and a ridge line is a part where two surfaces of the laminate intersect. In addition, unevenness or the like may be formed on a part or all of the surface constituting the laminate 10.

[0079] The dimensions of the laminate 10 are not particularly limited.

[0080] As shown Figure 4 and Figure 5 in FIG. 3, the laminate 10 has an inner layer portion 11, a first main surface side outer layer portion 12, and a second main surface side outer layer portion 13 that are arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0081] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes the internal electrode layer 30 closest to the first main surface TS1 side to the internal electrode layer 30 closest to the second main surface TS2 side in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates capacitance and substantially functions as a capacitor.

[0082] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material in which auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added to these main components.

[0083] The thickness of the dielectric layer 20 is preferably 0.3 μm or more and 1.5 μm or less. The number of sheets of the stacked dielectric layers 20 is preferably 14 sheets or more and 1000 sheets or less. In addition, the number of sheets of the dielectric layer 20 is the total number of the number of sheets of the dielectric layers in the inner layer portion 11 and the number of sheets of the dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0084] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are disposed on the plurality of dielectric layers 20 and are led out to the first side surface WS1 and the second side surface WS2. The plurality of second internal electrode layers 32 are disposed on the plurality of dielectric layers 20 and are led out to the first end surface LS1 and the second end surface LS2. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately disposed with the dielectric layers 20 therebetween in the stacking direction T of the laminate 10. The first internal electrode layer 31 and the second internal electrode layer 32 are disposed so as to sandwich the dielectric layer 20.

[0085] As Figure 6 shown, the first internal electrode layer 31 has: a first opposing electrode portion 31M that opposes the second internal electrode layer 32 with the dielectric layer 20 therebetween; a first lead-out portion 31A that extends from the first opposing electrode portion 31M and is led out to a part of the first side surface WS1 that is the first surface portion; and a second lead-out portion 31B that extends from the first opposing electrode portion 31M and is led out to a part of the second side surface WS2 that is the second surface portion. The first lead-out portion 31A is exposed on the first side surface WS1, and the second lead-out portion 31B is exposed on the second side surface WS2.

[0086] The shape of the first opposing electrode portion 31M is not particularly limited, but a rectangular shape is preferred. However, the corners of the rectangular shape may have rounded corners, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31A and the second lead-out portion 31B are not particularly limited, but a rectangular shape is preferred. However, the corners of the rectangular shape may have rounded corners, or the corners of the rectangular shape may be formed obliquely.

[0087] The dimension L2 in the length direction L of the first lead-out portion 31A is smaller than the dimension L1 in the length direction L of the first opposing electrode portion 31M. The dimension L2 in the length direction L of the second lead-out portion 31B is smaller than the dimension L1 in the length direction L of the first opposing electrode portion 31M. That is, when the lead-out direction of the first lead-out portion 31A (the direction from the second side surface WS2 toward the first side surface WS1) is set as the first lead-out direction, the length L2 in the orthogonal direction (length direction L) of the first lead-out direction of the first lead-out portion 31A is smaller than the length L1 in the orthogonal direction (length direction L) of the first lead-out direction of the first opposing electrode portion 31M. When the lead-out direction of the second lead-out portion 31B (the direction from the first side surface WS1 toward the second side surface WS2) is set as the second lead-out direction, the length L2 in the orthogonal direction (length direction L) of the second lead-out direction of the second lead-out portion 31B is smaller than the length L1 in the orthogonal direction (length direction L) of the second lead-out direction of the first opposing electrode portion 31M. The length L2 is preferably 90% or less of the length L1. The length L2 is more preferably 5% or more and 90% or less of the length L1.

[0088] The first opposed electrode portion 31M has: a first central portion region 31MM, which includes the central portion of the first opposed electrode portion 31M; a first connection portion region 31MA, which is a portion connected to the first lead portion 31A and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 31MM; and a second connection portion region 31MB, which is a portion connected to the second lead portion 31B and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 31MM.

[0089] The length in the width direction W of the first connection portion region 31MA is defined by 5% of the length W1 in the width direction W of the first opposed electrode portion 31M. The length in the length direction L of the first connection portion region 31MA is defined by the same length as the length L2 in the length direction L of the first lead portion 31A. The length in the width direction W of the second connection portion region 31MB of the second connection portion region 31MB is defined by 5% of the length W1 in the width direction W of the first opposed electrode portion 31M. The length in the length direction L of the second connection portion region 31MB is defined by the same length as the length L2 in the length direction L of the first lead portion 31A.

[0090] The coverage rates of the first connection portion region 31MA and the second connection portion region 31MB with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 31MM with respect to the dielectric layer 20. The coverage rates of the first lead portion 31A and the second lead portion 31B with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 31MM with respect to the dielectric layer 20.

[0091] That is, when the coverage rate of the first central portion region 31MM with respect to the dielectric layer 20 is set as A, the coverage rates of the first connection portion region 31MA and the second connection portion region 31MB with respect to the dielectric layer 20 are set as B, and the coverage rates of the first lead portion 31A and the second lead portion 31B with respect to the dielectric layer 20 are set as C, then A < B and A < C.

[0092] As a result, the metal ratios of the first connection portion region 31MA and the second connection portion region 31MB of the first internal electrode layer 31, the first lead portion 31A and the second lead portion 31B become higher. Therefore, the area of the current path connecting the first internal electrode layer 31 and the first external electrode 40A and the second external electrode 40B (to be described later) constituting the external electrode 40 can be increased. As a result, the resistance of the first internal electrode layer 31 becomes lower. Therefore, an increase in the DC resistance (Rdc) can be suppressed, and the characteristics of the multilayer ceramic capacitor 1 can be maintained and improved. In addition, the first internal electrode layer 31 can be prevented from being divided into multiple parts, so that a decrease in the connectivity between the first internal electrode layer 31 and the first external electrode 40A and the second external electrode 40B can be suppressed.

[0093] In this way, by setting the first connection portion region 31MA and the second connection portion region 31MB, and making the coverage rate B of the first connection portion region 31MA and the second connection portion region 31MB with respect to the dielectric layer 20 greater than the coverage rate A of the first central portion region 31MM with respect to the dielectric layer 20, not only does the metal ratio of the first internal electrode layer 31 become higher in the first lead portion 31A and the second lead portion 31B, but also the metal ratio of the first internal electrode layer 31 becomes higher in the first connection portion region 31MA and the second connection portion region 31MB. As a result, the area of the current path can be increased, and accordingly, the resistance can be reduced, and the resistance of the entire first internal electrode layer 31 can be reduced. As a result, the inhibitory effect on the increase in the DC resistance (Rdc) can be made higher.

[0094] Here, the reason for not making the coverage rate A of the first central portion region 31MM the same as the coverage rates B of the first connection portion region 31MA and the second connection portion region 31MB, and the coverage rates C of the first lead portion 31A and the second lead portion 31B in the present embodiment will be described. When the coverage rate A of the first central portion region 31MM is continuously increased to be the same as or higher than the coverage rates B of the first connection portion region 31MA and the second connection portion region 31MB, and the coverage rates C of the first lead portion 31A and the second lead portion 31B, although capacitance can be ensured, the portion of the dielectric layer 20 exposed on the surface of the first internal electrode layer 31 may sometimes become smaller. In this case, it is considered that the contact points between the dielectric layers of the other dielectric layers 20 laminated on the first internal electrode layer 31 will decrease, resulting in a decrease in the adhesion force, and there is a concern that interlayer peeling may occur. For example, when the coverage rate of the internal electrode layer on the dielectric layer is 100%, interlayer peeling is sometimes more likely to occur compared to the case where the coverage rate of the internal electrode layer on the dielectric layer is low. In the present embodiment, by making the coverage rate A of the first central portion region 31MM lower than the coverage rates B of the first connection portion region 31MA and the second connection portion region 31MB, and the coverage rates C of the first lead portion 31A and the second lead portion 31B, a portion of the dielectric layer 20 exposed on the surface of the first internal electrode layer 31 can be ensured, and the contact points between the dielectric layers of the other dielectric layers 20 laminated on the first internal electrode layer 31 can be increased. Thereby, the adhesion force can be ensured, and interlayer peeling can be suppressed. According to the present embodiment, it is possible to achieve both suppression of an increase in the DC resistance (Rdc) of the first internal electrode layer 31 and suppression of interlayer peeling. That is, in the multilayer ceramic capacitor 1 according to the present embodiment, an anchoring effect is generated between the dielectric layer and the internal electrode layer, and the adhesion strength between the dielectric layer and the internal electrode layer can be improved. As a result, it is possible to suppress the intrusion of moisture and the like into the laminate, and to suppress a decrease in the moisture resistance of the multilayer ceramic capacitor 1. Therefore, it is possible to improve the reliability of the multilayer ceramic capacitor 1 while suppressing an increase in the DC resistance (Rdc) of the first internal electrode layer 31.

[0095] In addition, the coverage rate B of the first connection portion region 31MA and the second connection portion region 31MB on the dielectric layer 20 is preferably 72% or more. The coverage rate C of the first lead portion 31A and the second lead portion 31B on the dielectric layer 20 is preferably 72% or more. Furthermore, the coverage rate A of the first central portion region 31MM on the dielectric layer 20 is preferably lower than the coverage rates B and C, and is 52% or more. The coverage rates B and C may also be 5% or more higher than the coverage rate A.

[0096] As Figure 7As shown, the second internal electrode layer 32 has: a second opposed electrode portion 32M that opposes the first internal electrode layer 31 with a dielectric layer 20 therebetween; a third lead portion 32C that extends from the second opposed electrode portion 32M and is led out to a part of the first end surface LS1 as the third surface portion; and a fourth lead portion 32D that extends from the second opposed electrode portion 32M and is led out to a part of the second end surface LS2 as the fourth surface portion. The third lead portion 32C is exposed on the first end surface LS1, and the fourth lead portion 32D is exposed on the second end surface LS2.

[0097] The shape of the second opposed electrode portion 32M is not particularly limited, but a rectangular shape is preferred. However, the corners of the rectangular shape may have rounded corners, or the corners of the rectangular shape may be formed obliquely. The shapes of the third lead portion 32C and the fourth lead portion 32D are not particularly limited, but a rectangular shape is preferred. However, the corners of the rectangular shape may have rounded corners, or the corners of the rectangular shape may be formed obliquely.

[0098] The dimension W2 in the width direction W of the third lead portion 32C is equal to or smaller than the dimension W1 in the width direction W of the second opposed electrode portion 32M. The dimension W2 in the width direction W of the fourth lead portion 32D is equal to or smaller than the dimension W1 in the width direction W of the second opposed electrode portion 32M. In the present embodiment, the dimension W2 in the width direction W of the third lead portion 32C is smaller than the dimension W1 in the width direction W of the second opposed electrode portion 32M. The dimension W2 in the width direction W of the fourth lead portion 32D is smaller than the dimension W1 in the width direction W of the second opposed electrode portion 32M. That is, when the lead-out direction of the third lead portion 32C (the direction from the second end surface LS2 side toward the first end surface LS1 side) is set as the third lead-out direction, the length W2 in the orthogonal direction (width direction W) of the third lead-out direction of the third lead portion 32C is smaller than the length W1 in the orthogonal direction (width direction W) of the third lead-out direction of the second opposed electrode portion 32M. When the lead-out direction of the fourth lead portion 32D (the direction from the first end surface LS1 side toward the second end surface LS2 side) is set as the fourth lead-out direction, the length W2 in the orthogonal direction (width direction W) of the fourth lead-out direction of the fourth lead portion 32D is smaller than the length W1 in the orthogonal direction (width direction W) of the fourth lead-out direction of the second opposed electrode portion 32M. The length W2 is preferably 90% or less of the length W1. The length W2 is more preferably 5% or more and 90% or less of the length W1.

[0099] The second opposing electrode portion 32M preferably has: a second central portion region 32MM, which includes the central portion of the second opposing electrode portion 32M; a third connection portion region 32MC, which is the portion connected to the third lead portion 32C and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 32MM; and a fourth connection portion region 32MD, which is the portion connected to the fourth lead portion 32D and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 32MM.

[0100] The length in the length direction L of the third connection portion region 32MC is defined by 5% of the length L1 in the length direction L of the second opposing electrode portion 32M. The length in the width direction W of the third connection portion region 32MC is defined by the same length as the length W2 in the width direction W of the third lead portion 32C. The length in the length direction L of the fourth connection portion region 32MD is defined by 5% of the length L1 in the length direction L of the second opposing electrode portion 32M. The length in the width direction W of the fourth connection portion region 32MD is defined by the same length as the length W2 in the width direction W of the fourth lead portion 32D.

[0101] The coverage rates of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 are preferably higher than the coverage rate of the second central portion region 32MM with respect to the dielectric layer 20. The coverage rates of the third lead portion 32C and the fourth lead portion 32D with respect to the dielectric layer 20 are preferably higher than the coverage rate of the second central portion region 32MM with respect to the dielectric layer 20.

[0102] That is, when the coverage rate of the second central portion region 32MM with respect to the dielectric layer 20 is set as D, the coverage rates of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 are set as E, and the coverage rates of the third lead portion 32C and the fourth lead portion 32D with respect to the dielectric layer 20 are set as F, it is preferably D < E and D < F.

[0103] As a result, the metal ratios of the third connection portion region 32MC, the fourth connection portion region 32MD, the third lead portion 32C, and the fourth lead portion 32D of the second internal electrode layer 32 become higher, so that the area of the current path connecting the second internal electrode layer 32 and the third external electrode 40C and the fourth external electrode 40D, which will be described later and constitute the external electrode 40, can be increased. As a result, the resistance of the second internal electrode layer 32 becomes lower, so that an increase in the direct current resistance (Rdc) can be suppressed, and the characteristics of the multilayer ceramic capacitor 1 can be maintained and improved. In addition, the second internal electrode layer 32 can be prevented from being divided into multiple parts, so that a decrease in the connectivity between the second internal electrode layer 32 and the third external electrode 40C and the fourth external electrode 40D can be suppressed.

[0104] In this way, by providing the third connection portion region 32MC and the fourth connection portion region 32MD and making the coverage ratio E of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 greater than the coverage ratio D of the second central portion region 32MM with respect to the dielectric layer 20, not only the metal ratio of the second internal electrode layer 32 becomes higher in the third lead portion 32C and the fourth lead portion 32D, but also the metal ratio of the second internal electrode layer 32 becomes higher in the third connection portion region 32MC and the fourth connection portion region 32MD. As a result, the area of the current path can be increased, and accordingly, the resistance can be reduced, and the resistance of the entire second internal electrode layer 32 can be reduced. As a result, the effect of suppressing the increase in the DC resistance (Rdc) can be made higher.

[0105] Here, the reason for not making the coverage rate D of the second central portion region 32MM the same as the coverage rates E of the third connection portion region 32MC and the fourth connection portion region 32MD, and the coverage rates F of the third lead-out portion 32C and the fourth lead-out portion 32D in the present embodiment will be described. When continuously increasing the coverage rate D of the second central portion region 32MM to be the same as or higher than the coverage rates E of the third connection portion region 32MC and the fourth connection portion region 32MD, and the coverage rates F of the third lead-out portion 32C and the fourth lead-out portion 32D, although capacitance can be ensured, the portion of the dielectric layer 20 exposed on the surface of the second internal electrode layer 32 may sometimes become smaller. In this case, it is considered that the contact points between the dielectric layers of the other dielectric layers 20 laminated on the second internal electrode layer 32 will decrease, resulting in a decrease in the adhesion force, and there is a concern that interlayer peeling may occur. For example, when the coverage rate of the internal electrode layer on the dielectric layer is 100%, interlayer peeling is sometimes more likely to occur compared to the case where the coverage rate of the internal electrode layer on the dielectric layer is low. In the present embodiment, by making the coverage rate D of the second central portion region 32MM lower than the coverage rates E of the third connection portion region 32MC and the fourth connection portion region 32MD, and the coverage rates F of the third lead-out portion 32C and the fourth lead-out portion 32D, a portion of the dielectric layer 20 exposed on the surface of the second internal electrode layer 32 can be ensured, and the contact points between the dielectric layers of the other dielectric layers 20 laminated on the first internal electrode layer 31 can be increased. As a result, the adhesion force can be ensured and interlayer peeling can be suppressed. According to the present embodiment, it is possible to achieve both suppression of the increase in the DC resistance (Rdc) of the second internal electrode layer 32 and suppression of interlayer peeling. That is, in the multilayer ceramic capacitor 1 according to the present embodiment, an anchoring effect is generated between the dielectric layer and the internal electrode layer, and the close contact strength between the dielectric layer and the internal electrode layer can be improved. As a result, it is possible to suppress the intrusion of moisture and the like into the laminate, and to suppress the decrease in the moisture resistance of the multilayer ceramic capacitor 1. Therefore, it is possible to improve the reliability of the multilayer ceramic capacitor 1 while suppressing the increase in the DC resistance (Rdc) of the second internal electrode layer 32.

[0106] In addition, the coverage rate E of the third connection portion region 32MC and the fourth connection portion region 32MD on the dielectric layer 20 is preferably 72% or more. The coverage rate F of the third lead-out portion 32C and the fourth lead-out portion 32D on the dielectric layer 20 is preferably 72% or more. Further, the coverage rate D of the second central portion region 32MM on the dielectric layer 20 is preferably lower than the coverage rates E and F and is 52% or more. The coverage rates E and F may be 5% or more higher than the coverage rate D.

[0107] In addition, the first internal electrode layer 31 can also be used as a ground electrode in a stacked via ceramic capacitor. The second internal electrode layer 32 can also be used as a via electrode in a stacked via ceramic capacitor.

[0108] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 can also be made of, for example, an Ag-Pd alloy or the like.

[0109] The total number of sheets of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 14 or more and 1000 or less. The number of the first internal electrode layer 31 is not particularly limited, but is preferably 7 or more and 500 or less, for example. The number of the second internal electrode layer 32 is not particularly limited, but is preferably 7 or more and 500 or less, for example.

[0110] The thickness of the first opposed electrode portion 31M of the first internal electrode layer 31 and the second opposed electrode portion 32M of the second internal electrode layer 32 is not particularly limited, but is preferably on the order of 0.25 μm or more and 0.60 μm or less, for example. In addition, in the present disclosure, a particularly high effect is exhibited in a region where the thickness is particularly thin, such as 0.4 μm or less.

[0111] The thickness of the first lead-out portion 31A, the second lead-out portion 31B of the first internal electrode layer 31, the third lead-out portion 32C, and the fourth lead-out portion 32D of the second internal electrode layer 32 is not particularly limited, but is preferably on the order of 0.25 μm or more and 0.60 μm or less, for example. In addition, in the present disclosure, a particularly high effect is exhibited in a region where the thickness is particularly thin, such as 0.4 μm or less.

[0112] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12 can be the same as the dielectric layer 20 used in the inner layer portion 11.

[0113] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 13 can be the same as the dielectric layer 20 used in the inner layer portion 11.

[0114] In this way, the laminate 10 has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20. That is, the multilayer ceramic capacitor 1 has a laminate 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately stacked.

[0115] In addition, the laminate 10 has an opposing portion 11E. The opposing portion 11E is a portion where the first opposing electrode portion 31M of the first internal electrode layer 31 and the second opposing electrode portion 32M of the second internal electrode layer 32 oppose each other. The opposing portion 11E is configured as a part of the inner layer portion 11. Figure 6 And Figure 7 show the ranges in the width direction W and the length direction L of the opposing portion 11E. In addition, the opposing portion 11E is also referred to as the capacitor effective portion.

[0116] In addition, the laminate 10 has a side surface side outer layer portion. The side surface side outer layer portion has a first side surface side outer layer portion WG1 located on the first side surface WS1 side and a second side surface side outer layer portion WG2 located on the second side surface WS2 side. The first side surface side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing portion 11E and the first side surface WS1 and the first lead portion 31A. That is, the first side surface side outer layer portion WG1 is an aggregate of the portions of the plurality of dielectric layers 20 on the first side surface WS1 side and the plurality of first lead portions 31A. The second side surface side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing portion 11E and the second side surface WS2 and the second lead portion 31B. That is, the second side surface side outer layer portion WG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second side surface WS2 side and the plurality of second lead portions 31B. Figures 5 - 7 show the ranges in the width direction W of the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2. In addition, the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are also referred to as the W interval or the side interval.

[0117] In addition, the laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 located on the first end surface LS1 side and a second end surface side outer layer portion LG2 located on the second end surface LS2 side. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the opposing portion 11E and the first end surface LS1 and the third lead portion 32C. That is, the first end surface side outer layer portion LG1 is an aggregate of the portions of the plurality of dielectric layers 20 on the first end surface LS1 side and the plurality of third lead portions 32C. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the opposing portion 11E and the second end surface LS2 and the fourth lead portion 32D. That is, the second end surface side outer layer portion LG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second end surface LS2 side and the plurality of fourth lead portions 32D. Figure 4 、 Figure 6 AndFigure 7 The range in the length direction L of the first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 is shown. In addition, the first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are also referred to as the L interval or the end interval.

[0118] Here, a method for measuring the coverage rate of the internal electrode layer 30 on the dielectric layer 20 will be described. Figure 8A It is a diagram showing the measurement position of the coverage rate of the first internal electrode layer 31 on the dielectric layer 20. Figure 8B It is a diagram showing the measurement position of the coverage rate of the second internal electrode layer 32 on the dielectric layer 20.

[0119] First, a method for measuring the coverage rate of each part of the first internal electrode layer 31 on the dielectric layer 20 will be described. The coverage rate A of the first central region 31MM on the dielectric layer 20, the coverage rate B of the first connection region 31MA and the second connection region 31MB on the dielectric layer 20, and the coverage rate C of the first lead portion 31A and the second lead portion 31B on the dielectric layer 20 can be measured by the following method.

[0120] First, the multilayer ceramic capacitor 1 is sectionally polished from the first end face LS1 or the second end face LS2 until the position of 1 / 2 of the L dimension, so as to expose a specific WT section. This WT section is the WT section at the central part in the length direction L of the multilayer ceramic capacitor 1.

[0121] Next, as Figure 8A shown, the WT section of the laminate 10 exposed by polishing is divided into a plurality of regions. In addition, in Figure 8A the illustration of the external electrode 40 is omitted.

[0122] An explanation will be given for the region division in the stacking direction T. The inner layer portion 11 is divided into three regions: the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C sandwiched therebetween, so as to be equally divided into three parts in the stacking direction T.

[0123] An explanation will be given for the region division in the width direction W. First, the laminate 10 is divided into three regions: the first side surface side outer layer portion WG1, the second side surface side outer layer portion WG2, and the opposing portion 11E. Next, the opposing portion 11E is divided into five regions: the first side surface side region EWA, the second side surface side region EWB, and three regions EWC1, EWC2, and EWC3 sandwiched therebetween, so as to be equally divided into five parts in the width direction W.

[0124] Here, the first side outer layer portion WG1 is the portion including the first lead-out portion 31A. The second side outer layer portion WG2 is the portion including the second lead-out portion 31B. The first side region EWA is the portion of the first connection portion region 31MA including the first opposed electrode portion 31M. The second side region EWB is the portion of the second connection portion region 31MB including the first opposed electrode portion 31M. The central region EWC composed of three regions EWC1, EWC2, and EWC3 is the region defining the first central portion region 31MM of the first internal electrode layer 31. That is, the first central portion region 31MM of the first internal electrode layer 31 is a region centered on the central portion in the width direction W of the first opposed electrode portion 31M, and is a region defined by a length of 60% of the length W1 in the width direction W of the first opposed electrode portion 31M.

[0125] <Method for Measuring the Coverage Rate A of the First Central Portion Region 31MM with Respect to the Dielectric Layer 20>

[0126] In the three regions EWC1, EWC2, and EWC3 of the laminate 10, the WT cross-sectional images of the first internal electrode layer 31 in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C are observed by a scanning electron microscope (SEM) or a metallurgical microscope, respectively.

[0127] At this time, an observation range R1 is set in the nine observation regions so that any ten first internal electrode layers 31 are respectively determined. Then, the length La in the width direction W of the first internal electrode layer 31 determined within the observation range R1, which is the length to be analyzed (including the length of the gap in the first internal electrode layer 31), and the length Lb in the width direction W of the first internal electrode layer 31 actually existing within the length to be analyzed (the length of the actual first internal electrode layer 31 after removing the gap) are respectively measured, and the coverage rate of the first internal electrode layer 31 in the first central portion region 31MM with respect to the dielectric layer 20 is calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm, and the length to be analyzed is set to 40 μm.

[0128] Coverage Rate (%) = (Length Lb / Length La) × 100…(1)

[0129] Finally, the average value of the coverage rates of the 90 first internal electrode layers 31 calculated in the nine observation regions is calculated as the coverage rate A of the first central portion region 31MM with respect to the dielectric layer 20 in the present embodiment.

[0130] In addition, in Figure 8AIn the figure, only one first internal electrode layer 31 is shown within the observation range R1 in each observation region. However, in the case of the multilayer ceramic capacitor 1 in which many internal electrode layers are stacked, more than 10 first internal electrode layers 31 are observed within each observation range R1. However, for example, when the total number of the first internal electrode layers 31 stacked in the laminate 10 is less than 30, sometimes the number of the first internal electrode layers 31 that can be observed within each observation range R1 is less than 10. In this case, the coverage rate of all the first internal electrode layers 31 that can be observed in each observation region is measured, and the average value thereof is calculated as the coverage rate A. The same applies to the measurement of the coverage rate B and the coverage rate C described later. In addition, the same applies to the measurement of the coverage rates D, E, and F of the second internal electrode layer 32 described later, which will be described by Figure 8B The same applies to the measurement of the coverage rates D, E, and F of the second internal electrode layer 32 described later.

[0131] <Method for Measuring the Coverage Rate B of the First Connection Portion Region 31MA and the Second Connection Portion Region 31MB with Respect to the Dielectric Layer 20>

[0132] The coverage rate of the first connection portion region 31MA with respect to the dielectric layer 20 is measured using the WT cross-section at the central portion in the length direction L of the first lead portion 31A. The coverage rate of the second connection portion region 31MB with respect to the dielectric layer 20 is measured using the WT cross-section at the central portion in the length direction L of the second lead portion 31B. In the case where the first lead portion 31A and the second lead portion 31B are arranged at the central portion in the length direction L of the multilayer ceramic capacitor 1 as in the present embodiment, the WT cross-section used in calculating the coverage rate A of the first central portion region 31MM with respect to the dielectric layer 20 is used to measure the coverage rate B of the first connection portion region 31MA and the second connection portion region 31MB with respect to the dielectric layer 20. The same applies to the measurement of the coverage rate C described later.

[0133] In the first side surface side region EWA, the WT cross-section image of the first connection portion region 31MA in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope. Here, the first connection portion region 31MA is defined by a position starting from the boundary between the first lead portion 31A and the first opposed electrode portion 31M (the boundary between the first side surface side outer layer portion WG1 and the opposed portion 11E) and extending toward the center side in the width direction W of the laminate 10 up to 5% of the length W1 in the width direction W of the first opposed electrode portion 31M (opposed portion 11E).

[0134] In the second side surface side region EWB, a WT cross-sectional image of the second connection portion region 31MB in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope. Here, the second connection portion region 31MB is defined by a position starting from the boundary between the second lead portion 31B and the first opposed electrode portion 31M (the boundary between the second side surface side outer layer portion WG2 and the opposed portion 11E) and extending toward the center side in the width direction W of the laminate 10 up to a length of 5% of the length W1 in the width direction W of the first opposed electrode portion 31M (opposed portion 11E).

[0135] At this time, an observation range R2 is set within the six observation regions such that any ten first internal electrode layers 31 are respectively determined. Then, the length La in the width direction W of the first internal electrode layer 31 determined within the observation range R2, which is the length to be analyzed (including the length of the voids in the first internal electrode layer 31), and the length Lb in the width direction W of the first internal electrode layer 31 actually existing within the length to be analyzed (the length of the actual first internal electrode layer 31 with the voids removed) are respectively measured, and the coverage rate of the first internal electrode layer 31 on the dielectric layer 20 in the first connection portion region 31MA and the second connection portion region 31MB is calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm. In addition, when the lengths of the first connection portion region 31MA and the second connection portion region 31MB are 40 μm or more, the length to be analyzed is set to 40 μm. When the lengths of the first connection portion region 31MA and the second connection portion region 31MB are less than 40 μm, the total lengths of the first connection portion region 31MA and the second connection portion region 31MB are set as the length to be analyzed.

[0136] Coverage rate (%) = (length Lb / length La) × 100…(1)

[0137] Finally, the average value of the coverage rates of the 60 first internal electrode layers 31 calculated within the six observation regions is calculated as the coverage rate B of the first connection portion region 31MA and the second connection portion region 31MB on the dielectric layer 20 in the present embodiment.

[0138] <Method for measuring the coverage rate C of the first lead portion 31A and the second lead portion 31B on the dielectric layer 20>

[0139] In the first side surface side outer layer portion WG1, a WT cross-sectional image of the first lead portion 31A in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope.

[0140] In the outer layer portion WG2 on the second side surface side, a cross-sectional image of the WT of the second lead portion 31B in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope.

[0141] At this time, an observation range R3 is set within the six observation regions such that any ten first internal electrode layers 31 are respectively determined. Then, the length La in the width direction W of the analysis target length of the first internal electrode layer 31 determined within the observation range R3 (the length including the gaps of the first internal electrode layer 31) and the length Lb in the width direction W of the first internal electrode layer 31 actually existing within the analysis target length (the length of the actual first internal electrode layer 31 excluding the gaps) are respectively measured, and the coverage rates of the first internal electrode layer 31 in the first lead portion 31A and the second lead portion 31B with respect to the dielectric layer 20 are calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm. In addition, when the lengths of the first lead portion 31A and the second lead portion 31B are 40 μm or more, the analysis target length is set to 40 μm. When the lengths of the first lead portion 31A and the second lead portion 31B are less than 40 μm, the total lengths of the first lead portion 31A and the second lead portion 31B are set as the analysis target length.

[0142] Coverage rate (%) = (length Lb / length La) × 100…(1)

[0143] Finally, the average value of the coverage rates of the 60 first internal electrode layers 31 calculated in the six observation regions is calculated as the coverage rate C of the first lead portion 31A and the second lead portion 31B with respect to the dielectric layer 20 in the present embodiment.

[0144] Next, a method for measuring the coverage rate of each part of the second internal electrode layer 32 with respect to the dielectric layer 20 will be described. The coverage rate D of the second central portion region 32MM with respect to the dielectric layer 20, the coverage rate E of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20, and the coverage rate F of the third lead portion 32C and the fourth lead portion 32D with respect to the dielectric layer 20 are measured by the following method.

[0145] First, the multilayer ceramic capacitor 1 is polished in cross-section from the first side surface WS1 or the second side surface WS2 until the position of 1 / 2 of the L dimension, so that a specific LT cross-section is exposed. This LT cross-section is the LT cross-section at the central portion in the width direction W of the multilayer ceramic capacitor 1.

[0146] Next, as Figure 8B shown, the LT cross-section of the laminate 10 exposed by polishing is divided into a plurality of regions. In addition, inFigure 8B In the figure, the illustration of the external electrode 40 is omitted.

[0147] The division of the regions in the stacking direction T will be described. The inner layer portion 11 is divided into three regions, namely, the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C sandwiched therebetween, such that they are equally divided into three parts in the stacking direction T.

[0148] The division of the regions in the length direction L will be described. First, the stacked body 10 is divided into three regions, namely, the first end face side outer layer portion LG1, the second end face side outer layer portion LG2, and the opposed portion 11E. Next, the opposed portion 11E is divided into five regions, namely, the first end face side region ELA, the second end face side region ELB, and three regions ELC1, ELC2, and ELC3 sandwiched therebetween, such that they are equally divided into five parts in the length direction L.

[0149] Here, the first end face side outer layer portion LG1 is the portion including the third lead-out portion 32C. The second end face side outer layer portion LG2 is the portion including the fourth lead-out portion 32D. The first end face side region ELA is the portion including the third connection portion region 32MC of the second opposed electrode portion 32M. The second end face side region ELB is the portion including the fourth connection portion region 32MD of the second opposed electrode portion 32M. The central region ELC formed by the three regions ELC1, ELC2, and ELC3 is the region that defines the second central portion region 32MM of the second internal electrode layer 32. That is, the second central portion region 32MM of the second internal electrode layer 32 is the region centered on the central portion in the length direction L of the second opposed electrode portion 32M, and is the region defined by a length of 60% of the length L1 in the length direction L of the second opposed electrode portion 32M.

[0150] <Method for measuring the coverage rate D of the second central portion region 32MM on the dielectric layer 20>

[0151] In the three regions ELC1, ELC2, and ELC3 of the stacked body 10, the LT cross-sectional images of the second internal electrode layer 32 in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C are observed by a scanning electron microscope (SEM) or a metallurgical microscope, respectively.

[0152] At this time, an observation range R4 is set in nine observation regions so that ten arbitrary second internal electrode layers 32 are respectively determined. Then, the length La in the length direction L of the second internal electrode layer 32 determined within the observation range R4, which is the length of the analysis target (including the length of the gap of the second internal electrode layer 32), and the length Lb in the length direction L of the second internal electrode layer 32 actually existing within the analysis target length (the length of the actual second internal electrode layer 32 excluding the gap) are respectively measured, and the coverage rate of the second internal electrode layer 32 in the second central region 32MM with respect to the dielectric layer 20 is calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm, and the analysis target length is set to 40 μm.

[0153] Coverage rate (%) = (length Lb / length La) × 100…(1)

[0154] Finally, the average value of the coverage rates of the 90 second internal electrode layers 32 calculated in the nine observation regions is calculated as the coverage rate D of the second central region 32MM with respect to the dielectric layer 20 in the present embodiment.

[0155] <Method for measuring the coverage rate E of the third connection region 32MC and the fourth connection region 32MD with respect to the dielectric layer 20>

[0156] The coverage rate of the third connection region 32MC with respect to the dielectric layer 20 is measured using the LT cross-section at the center in the width direction W of the third lead portion 32C. The coverage rate of the fourth connection region 32MD with respect to the dielectric layer 20 is measured using the LT cross-section at the center in the width direction W of the fourth lead portion 32D. In the case where the third lead portion 32C and the fourth lead portion 32E are arranged at the center in the width direction W of the multilayer ceramic capacitor 1 as in the present embodiment, the LT cross-section used in the calculation of the coverage rate D of the second central region 32MM with respect to the dielectric layer 20 is used to measure the coverage rate E of the third connection region 32MC and the fourth connection region 32MD with respect to the dielectric layer 20. In addition, the same applies to the measurement of the coverage rate F described later.

[0157] In the first end face side region ELA, the LT cross-sectional image of the third connection region 32MC in the first main face side region 11A, the second main face side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope. Here, the third connection region 32MC is defined by a position from the boundary between the third lead portion 32C and the second opposed electrode portion 32M (the boundary between the first end face side outer layer portion LG1 and the opposed portion 11E) as a starting point to the center side in the length direction L of the laminate 10 up to 5% of the length L1 in the length direction L of the second opposed electrode portion 32M (opposed portion 11E).

[0158] In the second end face side region ELB, an LT cross-sectional image of the fourth connection portion region 32MD in the first main face side region 11A, the second main face side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope. Here, the fourth connection portion region 32MD is defined by a position starting from the boundary between the fourth lead-out portion 32D and the second opposed electrode portion 32M (the boundary between the second end face side outer layer portion LG2 and the opposed portion 11E) and extending toward the center side in the length direction L of the laminate 10 up to 5% of the length L1 in the length direction L of the second opposed electrode portion 32M (opposed portion 11E).

[0159] At this time, an observation range R5 is set within the six observation regions such that any ten second internal electrode layers 32 are respectively determined. Then, the length La in the length direction L of the second internal electrode layer 32 determined within the observation range R5, which is the length to be analyzed (including the length of the voids in the second internal electrode layer 32), and the length Lb in the length direction L of the second internal electrode layer 32 actually existing within the length to be analyzed (the actual length of the second internal electrode layer 32 excluding the voids) are respectively measured, and the coverage rate of the second internal electrode layer 32 with respect to the dielectric layer 20 in the third connection portion region 32MC and the fourth connection portion region 32MD is calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm. In addition, when the lengths of the third connection portion region 32MC and the fourth connection portion region 32MD are 40 μm or more, the length to be analyzed is set to 40 μm. When the lengths of the third connection portion region 32MC and the fourth connection portion region 32MD are less than 40 μm, the total lengths of the third connection portion region 32MC and the fourth connection portion region 32MD are set as the length to be analyzed.

[0160] Coverage rate (%) = (length Lb / length La) × 100... (1)

[0161] Finally, the average value of the coverage rates of the 60 second internal electrode layers 32 calculated within the six observation regions is calculated as the coverage rate E of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 in the present embodiment.

[0162] <Method for measuring the coverage rate F of the third lead-out portion 32C and the fourth lead-out portion 32D with respect to the dielectric layer 20>

[0163] In the first end face side outer layer portion LG1, an LT cross-sectional image of the third lead-out portion 32C in the first main face side region 11A, the second main face side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope.

[0164] In the outer layer portion LG2 on the second end face side, the LT cross-sectional image of the fourth lead portion 32D in the first main surface side region 11A, the second main surface side region 11B, and the intermediate region 11C is observed by a scanning electron microscope (SEM) or a metallurgical microscope.

[0165] At this time, an observation range R6 is set within the six observation regions so that any ten second internal electrode layers 32 are respectively determined. Then, the length La (the length including the voids of the second internal electrode layer 32) in the length direction L of the second internal electrode layer 32 determined within the observation range R6 as the analysis target length, and the length Lb (the length of the actual second internal electrode layer 32 excluding the voids) in the length direction L where the second internal electrode layer 32 actually exists within the analysis target length are respectively measured, and the coverage rate of the second internal electrode layer 32 on the dielectric layer 20 in the third lead portion 32C and the fourth lead portion 32D is calculated by the following formula (1). In addition, the observation range is set to 40 μm × 40 μm. In addition, when the lengths of the third lead portion 32C and the fourth lead portion 32D are 40 μm or more, the analysis target length is set to 40 μm. When the lengths of the third lead portion 32C and the fourth lead portion 32D are less than 40 μm, the total lengths of the third lead portion 32C and the fourth lead portion 32D are set as the analysis target length.

[0166] Coverage rate (%) = (length Lb / length La) × 100…(1)

[0167] Finally, the average value of the coverage rates of the 60 second internal electrode layers 32 calculated in the six observation regions is calculated as the coverage rate F of the third lead portion 32C and the fourth lead portion 32D on the dielectric layer 20 in the present embodiment.

[0168] The external electrode 40 has three or more external electrodes. In the present embodiment, the external electrode 40 has: a first external electrode 40A connected to the first lead portion 31A; a second external electrode 40B connected to the second lead portion 31B; a third external electrode 40C connected to the third lead portion 32C; and a fourth external electrode 40D connected to the fourth lead portion 32D.

[0169] The first external electrode 40A is disposed on the first side surface WS1. The first external electrode 40A is connected to the first lead portion 31A of the first internal electrode layer 31. The first external electrode 40A may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2. In the present embodiment, the first external electrode 40A is formed to extend from the first side surface WS1 to a part of the first main surface TS1 and a part of the second main surface TS2.

[0170] The second external electrode 40B is disposed on the second side surface WS2. The second external electrode 40B is connected to the second lead portion 31B of the first internal electrode layer 31. The second external electrode 40B may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2. In the present embodiment, the second external electrode 40B is formed to extend from the second side surface WS2 to a part of the first main surface TS1 and a part of the second main surface TS2.

[0171] The third external electrode 40C is disposed on the first end surface LS1. The third external electrode 40C is connected to the third lead portion 32C of the second internal electrode layer 32. The third external electrode 40C may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, it is formed to extend from the first end surface LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2.

[0172] The fourth external electrode 40D is disposed on the second end surface LS2. The fourth external electrode 40D is connected to the fourth lead portion 32D of the second internal electrode layer 32. The fourth external electrode 40D may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, it is formed to extend from the second end surface LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, and a part of the first side surface WS1 and a part of the second side surface WS2.

[0173] The first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0174] The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0175] The third external electrode 40C has a third base electrode layer 50C and a third plating layer 60C disposed on the third base electrode layer 50C.

[0176] The fourth external electrode 40D has a fourth base electrode layer 50D and a fourth plating layer 60D disposed on the fourth base electrode layer 50D.

[0177] The first base electrode layer 50A is disposed on the surface of the first side surface WS1 of the laminate 10, and is formed to extend from the first side surface WS1 and cover a part of each of the first main surface TS1 and the second main surface TS2. The first base electrode layer 50A is connected to the first lead-out portion 31A of the first internal electrode layer 31. Alternatively, the first base electrode layer 50A may be disposed only on the surface of the first side surface WS1 of the laminate 10.

[0178] The second base electrode layer 50B is disposed on the surface of the second side surface WS2 of the laminate 10, and is formed to extend from the second side surface WS2 and cover a part of each of the first main surface TS1 and the second main surface TS2. The second base electrode layer 50B is connected to the second lead-out portion 31B of the first internal electrode layer 31. Alternatively, the second base electrode layer 50B may be disposed only on the surface of the second side surface WS2 of the laminate 10.

[0179] The third base electrode layer 50C is disposed on the surface of the first end surface LS1 of the laminate 10, and is formed to extend from the first end surface LS1 and cover a part of each of the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. The third base electrode layer 50C is connected to the third lead-out portion 32C of the second internal electrode layer 32. Alternatively, the third base electrode layer 50C may be disposed only on the surface of the first end surface LS1 of the laminate 10.

[0180] The fourth base electrode layer 50D is disposed on the surface of the second end surface LS2 of the laminate 10, and is formed to extend from the second end surface LS2 and cover a part of each of the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2. The fourth base electrode layer 50D is connected to the fourth lead-out portion 32D of the second internal electrode layer 32. Alternatively, the fourth base electrode layer 50D may be disposed only on the surface of the second end surface LS2 of the laminate 10.

[0181] The first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D (hereinafter, also collectively referred to as the base electrode layer) of the present embodiment are sintered layers. The sintered layer preferably contains a metal component and one of a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the ceramic component, the same type of ceramic material as the dielectric layer 20 may be used, or a different type of ceramic material from the dielectric layer 20 may be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0182] The firing layer is, for example, a firing layer formed by applying a conductive paste containing glass and metal to the laminate and then firing it. The firing layer may be a firing layer obtained by simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or may be a firing layer formed by applying a conductive paste to the laminate after firing a laminated chip having internal electrodes and a dielectric layer to obtain the laminate and then firing it. Further, in the case of simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, the firing layer is preferably formed by firing a material in which a ceramic material is added in place of the glass component. In this case, as the added ceramic material, a ceramic material of the same type as the dielectric layer 20 is particularly preferably used. The firing layer may also be a plurality of layers.

[0183] The thickness in the width direction of the first base electrode layer 50A located on the first side surface WS1 is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the stacking direction T and the length direction L of the first base electrode layer 50A.

[0184] The thickness in the width direction of the second base electrode layer 50B located on the second side surface WS2 is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the stacking direction T and the length direction L of the second base electrode layer 50B.

[0185] In the case where the first base electrode layer 50A is provided on at least a part of one of the first main surface TS1 and the second main surface TS2, the thickness in the stacking direction of the first base electrode layer 50A provided on this part is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on this part.

[0186] In the case where the second base electrode layer 50B is provided on at least a part of one of the first main surface TS1 and the second main surface TS2, the thickness in the stacking direction of the second base electrode layer 50B provided on this part is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on this part.

[0187] The thickness in the length direction of the third base electrode layer 50C located on the first end surface LS1 is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the stacking direction T and the width direction W of the third base electrode layer 50C.

[0188] The thickness in the length direction of the fourth base electrode layer 50D located on the second end surface LS2 is preferably, for example, 3 μm or more and 70 μm or less at the central portion in the stacking direction T and the width direction W of the fourth base electrode layer 50D.

[0189] When a part of at least one of the first main surface TS1 and the second main surface TS2 is also provided with the third base electrode layer 50C, the thickness in the stacking direction of the third base electrode layer 50C provided in this part is preferably, for example, 3 μm or more and 70 μm or less at the central part in the length direction L and the width direction W of the third base electrode layer 50C provided in this part.

[0190] When a part of at least one of the first side surface WS1 and the second side surface WS2 is also provided with the third base electrode layer 50C, the thickness in the width direction of the third base electrode layer 50C provided in this part is preferably, for example, 3 μm or more and 70 μm or less at the central part in the length direction L and the stacking direction T of the third base electrode layer 50C provided in this part.

[0191] When a part of at least one of the first main surface TS1 and the second main surface TS2 is also provided with the fourth base electrode layer 50D, the thickness in the stacking direction of the fourth base electrode layer 50D provided in this part is preferably, for example, 3 μm or more and 70 μm or less at the central part in the length direction L and the width direction W of the fourth base electrode layer 50D provided in this part.

[0192] When a part of at least one of the first side surface WS1 and the second side surface WS2 is also provided with the fourth base electrode layer 50D, the thickness in the width direction of the fourth base electrode layer 50D provided in this part is preferably, for example, 3 μm or more and 70 μm or less at the central part in the length direction L and the stacking direction T of the fourth base electrode layer 50D provided in this part.

[0193] In addition, the base electrode layer is not limited to the firing layer. The base electrode layer includes at least one selected from the firing layer, the conductive resin layer, the thin film layer, etc. For example, the base electrode layer can also be a thin film layer. The thin film layer is formed by a thin film formation method such as sputtering or evaporation. The thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0194] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0195] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0196] The third plating layer 60C is arranged to cover the third base electrode layer 50C.

[0197] The fourth plating layer 60D is arranged to cover the fourth base electrode layer 50D.

[0198] The first plating layer 60A, the second plating layer 60B, the third plating layer 60C, and the fourth plating layer 60D (hereinafter also collectively referred to as the plating layer) may also include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The plating layer may also be formed by a plurality of layers respectively. The plating layer is preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0199] The first plating layer 60A is arranged to cover the first base electrode layer 50A. In the present embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0200] The second plating layer 60B is arranged to cover the second base electrode layer 50B. In the present embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0201] The third plating layer 60C is arranged to cover the third base electrode layer 50C. In the present embodiment, the third plating layer 60C has a third Ni plating layer 61C and a third Sn plating layer 62C located on the third Ni plating layer 61C.

[0202] The fourth plating layer 60D is arranged to cover the fourth base electrode layer 50D. In the present embodiment, the fourth plating layer 60D has a fourth Ni plating layer 61D and a fourth Sn plating layer 62D located on the fourth Ni plating layer 61D.

[0203] The Ni plating layer prevents the base electrode layer from being eroded by the solder when the multilayer ceramic capacitor 1 is mounted. In addition, the Sn plating layer improves the wettability of the solder when the multilayer ceramic capacitor 1 is mounted. Thereby, the mounting of the multilayer ceramic capacitor 1 becomes easy. The thicknesses of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, the second Sn plating layer 62B, the third Ni plating layer 61C, the third Sn plating layer 62C, the fourth Ni plating layer 61D, and the fourth Sn plating layer 62D are each preferably 2 μm or more and 15 μm or less.

[0204] In addition, the external electrode 40 of the present embodiment may also have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. When the conductive resin layer is provided as the base electrode layer, the conductive resin layer may be arranged to cover the sintered layer, or may be directly arranged on the laminate 10 without providing the sintered layer. When the conductive resin layer is arranged to cover the sintered layer, the conductive resin layer is arranged between the sintered layer and the plating layer. The conductive resin layer may completely cover the sintered layer, or may cover a part of the sintered layer.

[0205] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer composed of a plating film or a fired product of a conductive paste. Therefore, even when a physical shock or a shock caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the generation of cracks in the multilayer ceramic capacitor 1.

[0206] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi, or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, metal powders of Ag. Since Ag has the lowest resistivity among metals, it is suitable for electrode materials. In addition, since Ag is a noble metal, it is not easily oxidized and has high weather resistance. Therefore, the metal powder of Ag is suitable as the conductive particles.

[0207] In addition, the conductive particles may also be metal powders coated with Ag on the surface of the metal powder. When using conductive particles coated with Ag on the surface of the metal powder, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to make the base metal inexpensive while maintaining the properties of Ag, it is preferable to use metal powders coated with Ag.

[0208] Furthermore, the conductive particles may also be conductive particles subjected to an oxidation prevention treatment on Cu and Ni. In addition, the conductive particles may also be metal powders coated with Sn, Ni, and Cu on the surface of the metal powder. When using metal powders coated with Sn, Ni, and Cu on the surface of the metal powder, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0209] The shape of the conductive particles is not particularly limited. Conductive particles such as spherical and flat-shaped conductive particles can be used, but it is preferable to use a mixture of spherical metal powders and flat-shaped metal powders.

[0210] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, by the contact of a plurality of conductive particles with each other, a conduction path is formed inside the conductive resin layer.

[0211] The resin constituting the conductive resin layer may, for example, also contain at least one selected from various known thermosetting resins such as epoxy resins, phenolic resins, polyurethane resins, silicone resins, and polyimide resins. Among them, epoxy resins, which are particularly excellent in heat resistance, moisture resistance, adhesion, etc., are one of the most suitable resins. In addition, the resin of the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may also be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide systems.

[0212] In addition, the conductive resin layer may also be formed of multiple layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0213] Alternatively, the structure may be such that the plating layer is directly disposed on the laminate 10 without providing the base electrode layer. That is, the multilayer ceramic capacitor 1 may also be a structure including a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may also be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0214] In this case, the plating layer is also preferably a plurality of layers. The lower plating layer and the upper plating layer preferably each contain at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, etc., or an alloy containing these metals, for example. The lower plating layer is more preferably formed using Ni having solder blocking properties. The upper plating layer is more preferably formed using Sn or Au having good solder wettability. In addition, for example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plating layer may be formed as needed, and the external electrode 40 may also be composed only of the lower plating layer. Furthermore, the plating layer may have the upper plating layer as the outermost layer, or another plating layer may be further formed on the surface of the upper plating layer.

[0215] The thickness of each layer of the plating layer disposed without providing the base electrode layer is preferably 1 μm or more and 15 μm or less. In addition, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0216] In addition, when the plating layer is directly formed on the laminate 10, the thickness of the base electrode layer can be reduced. Thus, correspondingly to the reduction in the thickness of the base electrode layer, the size in the stacking direction T of the multilayer ceramic capacitor 1 can be reduced, and the low profile of the multilayer ceramic capacitor 1 can be achieved. Or, correspondingly to the reduction in the thickness of the base electrode layer, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased, and the increase in the body thickness can be achieved. In this way, by directly forming the plating layer on the laminate 10, the design freedom of the multilayer ceramic capacitor can be increased.

[0217] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrode 40 is defined as the L dimension, the L dimension is preferably 1.0 mm or more and 3.2 mm or less. Further, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is defined as the T dimension, the T dimension is preferably 0.3 mm or more and 2.5 mm or less. Moreover, if the dimension in the width direction of the multilayer ceramic capacitor 1 is defined as the W dimension, the W dimension is preferably 0.5 mm or more and 2.5 mm or less. Additionally, the dimensions of the multilayer ceramic capacitor 1 can be measured by a microscope.

[0218] Hereinafter, a modified example of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are given to the same structures as those in the above-described embodiment, and detailed descriptions thereof are omitted. Figure 9 FIG. is a cross-sectional view showing a modified example of the second internal electrode layer 32 of the multilayer ceramic capacitor 1 of the present embodiment, and is a view corresponding to Figure 7 corresponding figure.

[0219] In this modified example, the shape of the second internal electrode layer 32 is different from Figure 7 the shape of the second internal electrode layer 32 shown. In this modified example, the dimension in the width direction W of the third lead-out portion 32C is the same as the dimension W1 in the width direction W of the second opposed electrode portion 32M. The dimension in the width direction W of the fourth lead-out portion 32D is the same as the dimension W1 in the width direction W of the second opposed electrode portion 32M.

[0220] In this modified example, the second opposed electrode portion 32M also preferably has: a second central portion region 32MM including the central portion of the second opposed electrode portion 32M; a third connection portion region 32MC, which is a portion connected to the third lead-out portion 32C and is a region having a higher coverage ratio of the dielectric layer 20 than the second central portion region 32MM; and a fourth connection portion region 32MD, which is a portion connected to the fourth lead-out portion 32D and is a region having a higher coverage ratio of the dielectric layer 20 than the second central portion region 32MM.

[0221] The coverage ratio of the third connection portion region 32MC and the fourth connection portion region 32MD to the dielectric layer 20 is preferably higher than the coverage ratio of the second central portion region 32MM to the dielectric layer 20. The coverage ratio of the third lead-out portion 32C and the fourth lead-out portion 32D to the dielectric layer 20 is preferably higher than the coverage ratio of the second central portion region 32MM to the dielectric layer 20.

[0222] With such a structure, the effects of the present embodiment can also be obtained.

[0223] Next, a manufacturing method of the multilayer ceramic capacitor 1 of the present embodiment will be described.

[0224] Prepare a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may also be well-known binders and solvents.

[0225] In addition, the structure of the first internal electrode layer 31 including the first lead-out portion 31A, the second lead-out portion 31B, the first connection portion region 31MA, the second connection portion region 31MB, and the first central portion region 31MM in the present embodiment is achieved by separately applying the conductive paste for the internal electrode layer. Similarly, the structure of the second internal electrode layer 32 including the third lead-out portion 32C, the fourth lead-out portion 32D, the third connection portion region 32MC, the fourth connection portion region 32MD, and the second central portion region 32MM in the present embodiment is achieved by separately applying the conductive paste for the internal electrode layer. Therefore, prepare the conductive paste for each internal electrode layer 30.

[0226] Specifically, prepare the internal electrode conductive paste A for the portions that will become the first lead-out portion 31A, the second lead-out portion 31B, the third lead-out portion 32C, the fourth lead-out portion 32D, the first connection portion region 31MA, the second connection portion region 31MB, the third connection portion region 32MC, and the fourth connection portion region 32MD. In addition, prepare the internal electrode conductive paste B, which is used for: the portion of the first opposed electrode portion 31M that includes the first central portion region 31MM except for the portions that become the first connection portion region 31MA and the second connection portion region 31MB; and the portion of the second opposed electrode portion 32M that includes the second central portion region 32MM except for the portions that become the third connection portion region 32MC and the fourth connection portion region 32MD.

[0227] Here, when the average particle diameter of the metal powder contained in the internal electrode conductive paste A is set to D2 and the average particle diameter of the metal powder contained in the internal electrode conductive paste B is set to D1, adjust so that D2 < D1. Thereby, in the region where the internal electrode conductive paste B is applied, the average particle diameter of the metal powder is large, and when particle defects occur, the thickness of the internal electrode layer in this portion becomes very thin. Therefore, this portion is likely to become a defective portion during firing, and the coverage rate of the internal electrode layer in the region where the internal electrode conductive paste B is applied becomes low. On the other hand, in the region where the internal electrode conductive paste A is applied, the average particle diameter of the metal powder is small. When particle defects occur, the influence on the thickness of the internal electrode layer in this portion is small. Therefore, this portion is not likely to become a defective portion during firing, and the coverage rate of the internal electrode layer in the region where the internal electrode conductive paste A is applied becomes high. In addition, by adjusting the sizes of D2 and D1, the value of the coverage rate of the internal electrode layer 30 with respect to the dielectric layer 20 can be adjusted.

[0228] On a dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a given pattern, for example, by screen printing, gravure printing, or the like. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 formed thereon and a dielectric sheet having a pattern of the second internal electrode layer 32 formed thereon are prepared.

[0229] More specifically, a screen mask for printing the first internal electrode layer 31 and a screen mask for printing the second internal electrode layer 32 are prepared respectively. Then, a printing machine can be used, that is, a printing machine capable of printing each internal electrode layer using the two screen masks.

[0230] In order to obtain the structure of the first internal electrode layer 31 of the present embodiment including the first lead portion 31A, the second lead portion 31B, the first connection portion region 31MA, the second connection portion region 31MB, and the first central portion region 31MM, a plurality of conductive pastes for the internal electrode layer are applied on the dielectric sheet respectively.

[0231] First, a conductive paste A for the internal electrode is applied to the portions that become the first lead portion 31A, the second lead portion 31B, the first connection portion region 31MA, and the second connection portion region 31MB. Next, a conductive paste B for the internal electrode is applied to the portion of the first opposed electrode portion 31M that includes the first central portion region 31MM and excludes the portions that become the first connection portion region 31MA and the second connection portion region 31MB. At this time, the conductive paste B may be applied overlapping the conductive paste A for the internal electrode. In this case, it is preferable to control so that the final coating film becomes smooth.

[0232] In order to obtain the structure of the second internal electrode layer 32 of the present embodiment including the third lead portion 32C, the fourth lead portion 32D, the third connection portion region 32MC, the fourth connection portion region 32MD, and the second central portion region 32MM, a plurality of conductive pastes for the internal electrode layer are applied on the dielectric sheet respectively.

[0233] First, a conductive paste A for the internal electrode is applied to the portions that become the third lead portion 32C, the fourth lead portion 32D, the third connection portion region 32MC, and the fourth connection portion region 32MD. Next, a conductive paste B for the internal electrode is applied to the portion of the second opposed electrode portion 32M that includes the second central portion region 32MM and excludes the portions that become the third connection portion region 32MC and the fourth connection portion region 32MD. At this time, the conductive paste B may be applied overlapping the conductive paste A for the internal electrode. In this case, it is preferable to control so that the final coating film becomes smooth.

[0234] By laminating dielectric sheets with the patterns of a given number of unprinted internal electrode layers, a part of the outer layer portion 12 on the first main surface TS1 side is formed. On this, a dielectric sheet printed with the pattern of the first internal electrode layer 31 and a dielectric sheet printed with the pattern of the second internal electrode layer 32 are laminated in sequence, thereby forming a part of the inner layer portion 11. On this part that becomes the inner layer portion 11, dielectric sheets with the patterns of a given number of unprinted internal electrode layers are laminated, thereby forming a part of the outer layer portion 13 on the second main surface TS2 side. Thus, a laminated sheet is fabricated.

[0235] The laminated sheet is pressed in the height direction by means such as isostatic pressing, thereby fabricating a laminated block.

[0236] By cutting the laminated block into a given size, laminated small pieces are cut out. At this time, rounded corners can also be formed at the corner portions and ridge line portions of the laminated small pieces by means such as barrel polishing.

[0237] By firing the laminated small pieces, a laminate 10 is fabricated. Although the firing temperature also depends on the materials of the dielectric layer 20 and the internal electrode layer 30, it is preferably 900 °C or higher and 1400 °C or lower.

[0238] A first base electrode layer 50A and a second base electrode layer 50B are formed on the first side surface WS1 and the second side surface WS2 of the laminate 10 obtained by firing. In the present embodiment, the base electrode layer is a sintered layer. A conductive paste containing a glass component and a metal is applied to the laminate 10. Then, a sintering process is performed to form the base electrode layer. The temperature of the sintering process at this time is preferably 700 °C or higher and 900 °C or lower.

[0239] Here, as a method for forming the sintered layer, various methods can be used. For example, a process method of extruding and applying the conductive paste from a slit can be used. In the case of this process method, by increasing the extrusion amount of the conductive paste, not only can the base electrode layer be formed on the first side surface WS1 and the second side surface WS2, but also the base electrode layer can be formed on a part of the first main surface TS1 and a part of the second main surface TS2.

[0240] In addition, a roll transfer method can be used for formation. In the case where the base electrode layer is formed not only on the first side surface WS1 and the second side surface WS2 but also on a part of the first main surface TS1 and a part of the second main surface TS2 by the roll transfer method, the pressing pressure during roll transfer is increased. Thereby, the base electrode layer can be formed on a part of the first main surface TS1 and a part of the second main surface TS2.

[0241] Next, a third base electrode layer 50C and a fourth base electrode layer 50D are formed on the first end face LS1 and the second end face LS2 of the fired laminate 10. In the present embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10. Then, a baking process is performed to form the base electrode layer. The temperature of the baking process at this time is preferably 700 °C or higher and 900 °C or lower.

[0242] In the present embodiment, the impregnation method is used to form the base electrode layer so that the base electrode layer is formed not only on the first end face, the second end face, but also extends to a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face.

[0243] In addition, regarding the baking process, the first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D can be baked simultaneously, or can be baked separately at different timings on the side face side and the end face side.

[0244] In addition, when the unfired laminate chip and the conductive paste applied to the laminate chip are fired simultaneously, the baked layer is preferably formed by baking a material in which a ceramic material is added instead of the glass component. At this time, as the added ceramic material, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20. In this case, a conductive paste is applied to the unfired laminate chip, and the laminate chip and the conductive paste applied to the laminate chip are baked simultaneously to form the laminate 10, and the laminate 10 forms a baked layer.

[0245] Then, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, as the plating layer, a Ni plating layer and a Sn plating layer are formed. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating has the disadvantage of complicating the process because pretreatment using a catalyst or the like is required to increase the plating deposition rate. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are formed in sequence by barrel plating, for example. In addition, the plating layer can be directly disposed on the exposed portion of the internal electrode layer 30 of the laminate 10 without providing the base electrode layer.

[0246] In addition, in the case where the base electrode layer is formed of a thin film layer, by performing mask setting or the like, a thin film layer serving as the base electrode layer is formed at a portion where an external electrode is desired to be formed. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. The thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0247] In addition, in the case where a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be configured to cover the sintered layer, or may be directly disposed on the laminate 10 without providing the sintered layer. In the case where the conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the sintered layer or the laminate 10, and then heat treatment is performed at a temperature of 250 to 550 °C or higher. As a result, the thermosetting resin is thermally cured to form the conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and to prevent the oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less. Further, as a method of applying the conductive resin paste, similar to the method of forming the base electrode layer through the sintered layer, for example, a process method of extruding and applying the conductive paste from a slit or a roll transfer method can be used.

[0248] Through such a manufacturing process, the multilayer ceramic capacitor 1 is manufactured.

[0249] In addition, in the present embodiment, the internal electrode layer (ground electrode) led out to the first side surface WS1 and the second side surface WS2 is described as the first internal electrode layer, and the internal electrode layer (through electrode) led out to the first end surface LS1 and the second end surface LS2 is described as the second internal electrode layer. However, it is also possible to understand the internal electrode layer (through electrode) led out to the first end surface LS1 and the second end surface LS2 as the first internal electrode layer, and the internal electrode layer (ground electrode) led out to the first side surface WS1 and the second side surface WS2 as the second internal electrode layer. In this case, it is understood that the first internal electrode layer is led out to the first end surface LS1 and the second end surface LS2 which are the first surface portion and the second surface portion, and the second internal electrode layer is led out to the first side surface WS1 and the second side surface WS2 which are the third surface portion and the fourth surface portion. Further, in this case, the external electrodes described as the third external electrode 40C, the fourth external electrode 40D, the first external electrode 40A, and the second external electrode 40B in the present embodiment are respectively understood as the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode.

[0250] The multilayer ceramic capacitor 1 according to the present embodiment achieves the following effects.

[0251] (1) The multilayer ceramic capacitor 1 of the present embodiment has: a laminate 10 having a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite in the stacking direction, a first end surface LS1 and a second end surface LS2 opposite in the length direction orthogonal to the stacking direction, and a first side surface WS1 and a second side surface WS2 opposite in the width direction orthogonal to the stacking direction and the length direction; and three or more external electrodes 40. In the multilayer ceramic capacitor 1, the plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layer 31 has: a first opposed electrode portion 31M opposed to the second internal electrode layer 32 with the dielectric layer 20 interposed therebetween; a first lead portion 31A extending from the first opposed electrode portion 31M and led out to the first surface portion of the laminate 10; and a second lead portion 31B extending from the first opposed electrode portion 31M and led out to the second surface portion of the laminate 10. The second internal electrode layer 32 has: a second opposed electrode portion 32M opposed to the first internal electrode layer 31 with the dielectric layer 20 interposed therebetween; and a third lead portion 32C extending from the second opposed electrode portion 32M and led out to the third surface portion of the laminate 10. The three or more external electrodes 40 have: a first external electrode 40A connected to the first lead portion 31A; a second external electrode 40B connected to the second lead portion 31B; and a third external electrode 40C connected to the third lead portion 32C. The first opposed electrode portion 31M has: a first central region 31MM including the central portion of the first opposed electrode portion 31M; a first connection region 31MA which is a portion connected to the first lead portion 31A and is a region having a higher coverage rate of the dielectric layer 20 than the first central region 31MM; and a second connection region 31MB which is a portion connected to the second lead portion 31B and is a region having a higher coverage rate of the dielectric layer 20 than the first central region 31MM. The coverage rate of the first connection region 31MA and the second connection region 31MB to the dielectric layer 20 is higher than the coverage rate of the first central region 31MM to the dielectric layer 20. The coverage rate of the first lead portion 31A and the second lead portion 31B to the dielectric layer 20 is higher than the coverage rate of the first central region 31MM to the dielectric layer 20. Thus, a multilayer ceramic capacitor 1 capable of suppressing an increase in the DC resistance of the internal electrode layer can be provided.

[0252] (2) At least a part of the first surface portion of the multilayer ceramic capacitor 1 of the present embodiment is a part of the first side surface WS1, and at least a part of the second surface portion is a part of the second side surface WS2. In such a structure, the effects of the present embodiment can also be obtained.

[0253] (3) The length L2 of the first lead-out portion 31A of the multilayer ceramic capacitor 1 according to this embodiment in the length direction L is shorter than the length L1 of the first opposed electrode portion 31M in the length direction L, and the length L2 of the second lead-out portion 31B in the length direction L is shorter than the length L1 of the first opposed electrode portion 31M in the length direction L. When the internal electrode layer is regarded as a path for flowing charges, in the case where the width of the lead-out portion is narrower than that of the opposed electrode portion, the DC resistance of the internal electrode layer is subject to the states of the lead-out portion, the opposed electrode portion, and the connection portion between the lead-out portion and the opposed electrode portion. Therefore, the present disclosure exhibits a particularly high effect in such a structure of the internal electrode layer.

[0254] (4) In the multilayer ceramic capacitor 1 according to this embodiment, the coverage rate of the first connection portion region 31MA and the second connection portion region 31MB with respect to the dielectric layer 20 is 72% or more, and the coverage rate of the first lead-out portion 31A and the second lead-out portion 31B with respect to the dielectric layer 20 is 72% or more. Thereby, an increase in the DC resistance of the internal electrode layer can be more effectively suppressed.

[0255] (5) The second internal electrode layer 32 of the multilayer ceramic capacitor 1 according to this embodiment further includes: a fourth lead-out portion 32D, which extends from the second opposed electrode portion 32M and is led out to the fourth surface portion of the laminate 10, and three or more external electrodes 40 further include a fourth external electrode 40D connected to the fourth lead-out portion 32D. In such a structure, the effects of this embodiment can also be obtained.

[0256] (6) At least a part of the third surface portion of the multilayer ceramic capacitor 1 according to this embodiment is a part of the first end surface LS1, and at least a part of the fourth surface portion is a part of the second end surface LS2. In such a structure, the effects of this embodiment can also be obtained.

[0257] (7) The length W2 of the third lead-out portion 32C of the multilayer ceramic capacitor 1 according to this embodiment in the width direction W is shorter than the length W1 of the second opposed electrode portion 32M in the width direction W, and the length W2 of the fourth lead-out portion 32D in the width direction W is shorter than the length W1 of the second opposed electrode portion 32M in the width direction. In such a structure, the effects of this embodiment can also be obtained.

[0258] (8) The second opposing electrode portion 32M of the multilayer ceramic capacitor 1 according to the present embodiment has: a second central portion region 32MM, which includes the central portion of the second opposing electrode portion 32M; a third connection portion region 32MC, which is a portion connected to the third lead-out portion 32C and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 32MM; and a fourth connection portion region 32MD, which is a portion connected to the fourth lead-out portion 32D and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 32MM. The coverage rates of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 are higher than the coverage rate of the second central portion region 32MM with respect to the dielectric layer 20, and the coverage rates of the third lead-out portion 32C and the fourth lead-out portion 32D with respect to the dielectric layer 20 are higher than the coverage rate of the second central portion region 32MM with respect to the dielectric layer 20. Thus, in addition to suppressing an increase in the DC resistance of the first internal electrode layer 31, an increase in the DC current of the second internal electrode layer 32 can also be suppressed.

[0259] (9) In the multilayer ceramic capacitor 1 according to the present embodiment, the coverage rates of the third connection portion region 32MC and the fourth connection portion region 32MD with respect to the dielectric layer 20 are 72% or more, and the coverage rates of the third lead-out portion 32C and the fourth lead-out portion 32D with respect to the dielectric layer 20 are 72% or more. Thus, an increase in the DC resistance of the internal electrode layer can be suppressed more effectively.

[0260] (10) The thickness of the dielectric layer 20 of the multilayer ceramic capacitor 1 according to the present embodiment is 0.3 μm or more and 1.5 μm or less. In such a structure, the effects of the present embodiment can also be obtained.

[0261] (11) The thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the present embodiment is 0.25 μm or more and 0.6 μm or less. The present disclosure exhibits high effects in a region where the thickness of the internal electrode layer 30 is thin.

[0262] (12) The thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the present embodiment is 0.25 μm or more and 0.4 μm or less. The present disclosure exhibits even higher effects in a region where the thickness of the internal electrode layer 30 is thin.

[0263] (13) In the multilayer ceramic capacitor 1 of the present embodiment, when the lead-out direction of the first lead-out portion 31A is set as the first lead-out direction, the length in the orthogonal direction of the first lead-out direction of the first lead-out portion 31A is shorter than the length in the orthogonal direction of the first lead-out direction of the first opposed electrode portion 31M. When the lead-out direction of the second lead-out portion 31B is set as the second lead-out direction, the length in the orthogonal direction of the second lead-out direction of the second lead-out portion 31B is shorter than the length in the orthogonal direction of the second lead-out direction of the first opposed electrode portion 31M. When the internal electrode layer is regarded as a path through which charges flow, when the width of the lead-out portion is narrower than that of the opposed electrode portion, the DC resistance of the internal electrode layer is subject to the states of the lead-out portion, the opposed electrode portion, and the connecting portion between the lead-out portion and the opposed electrode portion. Therefore, the present disclosure exhibits a particularly high effect in such a structure of the internal electrode layer.

[0264] Alternatively, in the multilayer ceramic capacitor 1 of the present embodiment, at least a part of the first surface portion may be a part of the first side surface WS1, and at least a part of the second surface portion may be a part of the second side surface WS2. Alternatively, in the multilayer ceramic capacitor 1 of the present embodiment, at least a part of the first surface portion may be a part of the first end surface LS1, and at least a part of the second surface portion may be a part of the second end surface.

[0265] In addition, the present disclosure includes the following content.

[0266] The multilayer ceramic capacitor 1 includes: a laminate 10 having a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction orthogonal to the stacking direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction orthogonal to the stacking direction and the length direction; and a plurality of external electrodes 40. The plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers. The first internal electrode layer has: a first opposing electrode portion facing the second internal electrode layer across the dielectric layer; and a first lead portion extending from the first opposing electrode portion and led out to the outer surface of the laminate. The second internal electrode layer has: a second opposing electrode portion facing the first internal electrode layer across the dielectric layer; and another lead portion extending from the second opposing electrode portion and led out to the outer surface of the laminate. When the lead-out direction of the first lead portion is set as the first lead-out direction, the length in the orthogonal direction of the first lead-out direction of the first lead portion is shorter than the length in the orthogonal direction of the first lead-out direction of the first opposing electrode portion. The plurality of external electrodes include: a first external electrode connected to the first lead portion; and another external electrode connected to the other lead portion. The first opposing electrode portion has: a first central portion region including the central portion of the first opposing electrode portion; and a first connection portion region which is the portion connected to the first lead portion and is a region with a higher coverage rate of the dielectric layer than the first central portion region. The coverage rate of the first connection portion region on the dielectric layer is higher than the coverage rate of the first central portion region on the dielectric layer. The coverage rate of the first lead portion on the dielectric layer is higher than the coverage rate of the first central portion region on the dielectric layer. When the internal electrode layer is regarded as a path for flowing charges, when the width of the lead portion is narrower than that of the opposing electrode portion, the resistance of the internal electrode layer is subject to the states of the lead portion, the opposing electrode portion, and the connection portion between the lead portion and the opposing electrode portion. Therefore, the present disclosure exhibits a particularly high effect in such a structure of the internal electrode layer.

[0267] <Second Embodiment>

[0268] Hereinafter, the multilayer ceramic capacitor 101 according to the second embodiment will be described. In addition, in the following description, detailed descriptions of the same structures as those in the first embodiment are omitted. Figure 10A It is an external perspective view of the multilayer ceramic capacitor 101 of the present embodiment. Figure 10B It is an LW cross-sectional view showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of the present embodiment. Figure 10C It is an LW cross-sectional view showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of the present embodiment. In addition, in Figure 10B and Figure 10C the illustration of the external electrode 140 is omitted.

[0269] In the multilayer ceramic capacitor 101 of the present embodiment, the forms of the first internal electrode layer, the second internal electrode layer, and the external electrodes are different from those of the first embodiment.

[0270] As Figure 10B shown, the first internal electrode layer 131 has: a first opposing electrode portion 131M that opposes the second internal electrode layer 132 with the dielectric layer 20 interposed therebetween; a first lead portion 131A that extends from the first opposing electrode portion 131M and is led out to a part on the first end face LS1 side of the first side surface WS1 that is the first surface portion; and a second lead portion 131B that extends from the first opposing electrode portion 131M and is led out to a part on the second end face LS2 side of the first side surface WS1 that is the second surface portion. The first lead portion 131A is exposed at a part on the first end face LS1 side of the first side surface WS1. The second lead portion 131B is exposed at a part on the second end face LS2 side of the first side surface WS1. The second lead portion 131B is exposed at a position different from the exposed portion of the first lead portion 131A in the length direction L of the laminate 10. The first internal electrode layer 131 is substantially "U" shaped (substantially C shaped).

[0271] In the present embodiment, the dimension in the length direction L of the first lead portion 131A is also smaller than the dimension in the length direction L of the first opposing electrode portion 131M. The dimension in the length direction L of the second lead portion 131B is smaller than the dimension in the length direction L of the first opposing electrode portion 131M. That is, when the lead-out direction of the first lead portion 131A (the direction from the second side surface WS2 toward the first side surface WS1) is set as the first lead-out direction, the length in the orthogonal direction (length direction L) of the first lead-out direction of the first lead portion 131A is smaller than the length in the orthogonal direction (length direction L) of the first lead-out direction of the first opposing electrode portion 131M. When the lead-out direction of the second lead portion 131B (the direction from the second side surface WS2 toward the first side surface WS1) is set as the second lead-out direction, the length in the orthogonal direction (length direction L) of the second lead-out direction of the second lead portion 131B is smaller than the length in the orthogonal direction (length direction L) of the second lead-out direction of the first opposing electrode portion 131M.

[0272] The first opposing electrode portion 131M has: a first central portion region 131MM that includes the central portion of the first opposing electrode portion 131M; a first connection portion region 131MA that is a part connected to the first lead portion 131A and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM; and a second connection portion region 131MB that is a part connected to the second lead portion 131B and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM.

[0273] The length in the width direction W of the first connection portion region 131MA is defined by 5% of the length in the width direction W of the first opposed electrode portion 131M. The length in the length direction L of the first connection portion region 131MA is defined by the same length as the length of the first lead-out portion 131A. The length in the width direction W of the second connection portion region 131MB is defined by 5% of the length in the width direction W of the first opposed electrode portion 131M. The length in the length direction L of the second connection portion region 131MB is defined by the same length as the length of the second lead-out portion 131B. Further, in the following embodiments, each connection portion region of the first internal electrode layer is also defined by the same method based on the size of the opposed electrode portion.

[0274] The coverage rate of the first connection portion region 131MA and the second connection portion region 131MB with respect to the dielectric layer 20 is higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20. The coverage rate of the first lead-out portion 131A and the second lead-out portion 131B with respect to the dielectric layer 20 is higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20.

[0275] That is, when the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20 is set as A, the coverage rate of the first connection portion region 131MA and the second connection portion region 131MB with respect to the dielectric layer 20 is set as B, and the coverage rate of the first lead-out portion 131A and the second lead-out portion 131B with respect to the dielectric layer 20 is set as C, A < B and A < C.

[0276] As Figure 10C shown, the second internal electrode layer 132 has: a second opposed electrode portion 132M opposed to the first internal electrode layer 131 with the dielectric layer 20 interposed therebetween; and a third lead-out portion 132C extending from the second opposed electrode portion 132M and led out to a part of the first side surface WS1 as the third surface portion. The third lead-out portion 132C is exposed on the first side surface WS1. The third lead-out portion 132C is exposed at a position different from the exposed portions of the first lead-out portion 131A and the second lead-out portion 132B in the width direction W of the laminate 10. In the present embodiment, the third lead-out portion 132C is exposed at the central portion in the width direction W of the laminate 10.

[0277] The size of the third lead-out portion 132C in the length direction L is smaller than the size of the second opposed electrode portion 132M in the length direction L. That is, when the lead-out direction of the third lead-out portion 132C (the direction from the second side surface WS2 side toward the first side surface WS1 side) is set as the third lead-out direction, the length of the third lead-out portion 132C in the orthogonal direction (length direction L) of the third lead-out direction is smaller than the length of the second opposed electrode portion 132M in the orthogonal direction (length direction L) of the third lead-out direction.

[0278] The second opposing electrode portion 132M preferably has: a second central portion region 132MM, which includes the central portion of the second opposing electrode portion 132M; and a third connection portion region 132MC, which is a portion connected to the third lead portion 132C and is a region with a higher coverage rate of the dielectric layer 20 than that of the second central portion region 132MM.

[0279] The length in the width direction W of the third connection portion region 132MC is defined by 5% of the length in the width direction W of the second opposing electrode portion 132M. In addition, the length in the length direction L of the third connection portion region 132MC is defined by the same length as the length in the length direction L of the third lead portion 132C. In the following embodiments, each connection portion region of the second internal electrode layer is also defined by the same method based on the size of the opposing electrode portion.

[0280] The coverage rate of the third connection portion region 132MC with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20. The coverage rate of the third lead portion 132C with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20.

[0281] That is, when the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20 is set as D, the coverage rate of the third connection portion region 132MC with respect to the dielectric layer 20 is set as E, and the coverage rate of the third lead portion 132C with respect to the dielectric layer 20 is set as F, it is preferably D < E and D < F.

[0282] The external electrode 140 of the present embodiment has, as three or more external electrodes: a first external electrode 140A connected to the first lead portion 131A; a second external electrode 140B connected to the second lead portion 131B; and a third external electrode 140C connected to the third lead portion 132C.

[0283] The first external electrode 140A is disposed on the first side surface WS1 on the first end surface LS1 side. The first external electrode 140A is connected to the first lead portion 131A of the first internal electrode layer 131. The first external electrode 140A may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2. In the present embodiment, the first external electrode 140A is formed to extend from the first side surface WS1 to a part of the first main surface TS1 and a part of the second main surface TS2.

[0284] The second external electrode 140B is disposed on the first side surface WS1 and at a position different from that of the first external electrode 140A. The second external electrode 140B is disposed on the first side surface WS1 on the side of the second end surface LS2. The second external electrode 140B is connected to the second lead-out portion 131B of the first internal electrode layer 131. The second external electrode 140B may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2. In the present embodiment, the second external electrode 140B is formed to extend from the first side surface WS1 to a part of the first main surface TS1 and a part of the second main surface TS2.

[0285] The third external electrode 140C is disposed on the first side surface WS1 and at a position different from that of the first external electrode 140A and the second external electrode 140B. The third external electrode 140C is disposed on the first side surface WS1 at the central portion in the longitudinal direction L of the laminate 10. The third external electrode 140C is connected to the third lead-out portion 132C of the second internal electrode layer 132. The third external electrode 140C may also be disposed on a part of the first main surface TS1 and a part of the second main surface TS2. In the present embodiment, the third external electrode 140C is formed to extend from the first side surface WS1 to a part of the first main surface TS1 and a part of the second main surface TS2.

[0286] In addition, as the layer structure constituting the external electrode 140, the same layer structure as that of the first embodiment can be adopted.

[0287] In the multilayer ceramic capacitor 1 of the present embodiment, at least a part of the first surface portion is a part on the side of the first end surface LS1 of the first side surface WS1, and at least a part of the second surface portion is a part on the side of the second end surface LS2 of the first side surface WS1. In such a structure, the same effect as that of the first embodiment can also be obtained.

[0288] <The Third Embodiment>

[0289] Hereinafter, the multilayer ceramic capacitor 101 according to the third embodiment will be described. In addition, in the following description, detailed description of the same structures as those in the second embodiment will be omitted. Figure 11A is an external perspective view of the multilayer ceramic capacitor 101 of the present embodiment. Figure 11B is an LW cross-sectional view showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of the present embodiment. Figure 11C is an LW cross-sectional view showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of the present embodiment. In addition, in Figure 11B and Figure 11C the illustration of the external electrode 140 is omitted.

[0290] In the multilayer ceramic capacitor 101 of the present embodiment, the forms of the first internal electrode layer, the second internal electrode layer, and the external electrodes are different from those of the second embodiment.

[0291] As Figure 11B shown, the first internal electrode layer 131 of the present embodiment further includes: a fifth lead-out portion 131E that extends from the first opposing electrode portion 131M and is led out to a part on the side of the first end surface LS1 of the second side surface WS2; and a sixth lead-out portion 131F that extends from the first opposing electrode portion 131M and is led out to a part on the side of the second end surface LS2 of the second side surface WS2. The fifth lead-out portion 131E is exposed at a part on the side of the first end surface LS1 of the second side surface WS2, and the sixth lead-out portion 131F is exposed at a part on the side of the second end surface LS2 of the second side surface WS2. The first internal electrode layer 131 is substantially H-shaped.

[0292] The first opposing electrode portion 131M preferably further includes: a fifth connection portion region 131ME, which is a part connected to the fifth lead-out portion 131E and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM; and a sixth connection portion region 131MF, which is a part connected to the sixth lead-out portion 131F and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM.

[0293] The coverage rates of the fifth connection portion region 131ME and the sixth connection portion region 131MF with respect to the dielectric layer 20 are preferably higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20. The coverage rates of the fifth lead-out portion 131E and the sixth lead-out portion 131F with respect to the dielectric layer 20 are preferably higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20.

[0294] As Figure 11C shown, the second internal electrode layer 132 further includes: a fourth lead-out portion 132D that extends from the second opposing electrode portion 132M and is led out to a part of the second side surface WS2. The fourth lead-out portion 132D is exposed on the second side surface WS2. The fourth lead-out portion 132D is exposed at a position different from the exposed portions of the fifth lead-out portion 131E and the sixth lead-out portion 131F in the length direction L of the laminate 10. In the present embodiment, the fourth lead-out portion 132D is exposed at the central portion in the width direction W of the laminate 10.

[0295] The dimension in the length direction L of the fourth lead-out portion 132D is smaller than the dimension in the length direction L of the second opposing electrode portion 132M. That is, when the lead-out direction of the fourth lead-out portion 132D (the direction from the first side surface WS1 side toward the second side surface WS2 side) is set as the fourth lead-out direction, the length in the orthogonal direction (length direction L) of the fourth lead-out direction of the fourth lead-out portion 132D is smaller than the length in the orthogonal direction (length direction L) of the fourth lead-out direction of the second opposing electrode portion 132M.

[0296] The second opposing electrode portion 132M preferably further has: a fourth connection portion region 132MD, which is a portion connected to the fourth lead-out portion 132D and is a region with a higher coverage rate of the dielectric layer 20 than that of the second central portion region 132MM.

[0297] The coverage rate of the fourth connection portion region 132MD with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20. The coverage rate of the fourth lead-out portion 132D with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20.

[0298] The external electrode 140 of the present embodiment has, on the second side surface WS2 side, in a configuration symmetric to that of the first external electrode 140A, the second external electrode 140B, and the third external electrode 140C: a fifth external electrode 140E connected to the fifth lead-out portion 131E; a sixth external electrode 140F connected to the sixth lead-out portion 131F; and a fourth external electrode 140D connected to the fourth lead-out portion 132D.

[0299] In addition, in the present embodiment, as the external electrode, the same external electrode as that of the Figure 1 first embodiment shown can be adopted. In this case, for example, the external electrode disposed on the first end surface LS1 side is understood as the first external electrode, the external electrode disposed on the second end surface LS2 side is understood as the second external electrode, and the external electrode disposed on the first side surface WS1 side is understood as the third external electrode.

[0300] In such a structure, the same effect as that of the first embodiment can also be obtained.

[0301] In addition, in the present embodiment, for example, in the first internal electrode layer 131, one of the two lead-out portions led out to the second side surface WS2 can be understood as the first lead-out portion, and the other lead-out portion led out to the second side surface WS2 can be understood as the second lead-out portion. In addition, in the first internal electrode layer 131, one of the two lead-out portions led out to the first side surface WS1 can be understood as the first lead-out portion, and one of the two lead-out portions led out to the second side surface WS2 can be understood as the second lead-out portion.

[0302] <Fourth Embodiment>

[0303] Hereinafter, the multilayer ceramic capacitor 101 according to the fourth embodiment will be described. In addition, in the following description of the internal electrode layer, the detailed description of the same structure as that of the second embodiment will be omitted. Figure 12A It is an LW cross-sectional view of the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of the present embodiment. Figure 12B It is an LW cross-sectional view of the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of the present embodiment. In addition, in Figure 12A and Figure 12B the illustration of the external electrode 40 is omitted. In addition, the arrangement of the external electrode is the same as that of the third embodiment shown in Figure 11A Therefore, the external appearance three-dimensional view of the multilayer ceramic capacitor 1 and the detailed description of the external electrode 140 are omitted.

[0304] In the multilayer ceramic capacitor 101 of the present embodiment, the first internal electrode layer, the second internal electrode layer, and the external electrode are different from those of the second embodiment.

[0305] As shown in Figure 12A the first internal electrode layer 131 of the present embodiment further has: a seventh lead-out portion 131D, which extends from the first opposed electrode portion 131M and is led out to the central portion in the length direction L of the second side surface WS2. The seventh lead-out portion 131D is exposed at the central portion in the length direction L of the second side surface WS2.

[0306] The first opposed electrode portion 131M preferably further has: a seventh connection portion region 131MD, which is a portion connected to the seventh lead-out portion 131D and is a region with a higher coverage ratio of the dielectric layer 20 than the first central portion region 131MM.

[0307] The coverage ratio of the seventh connection portion region 131MD to the dielectric layer 20 is preferably higher than the coverage ratio of the first central portion region 131MM to the dielectric layer 20. The coverage ratio of the seventh lead-out portion 131D to the dielectric layer 20 is preferably higher than the coverage ratio of the first central portion region 131MM to the dielectric layer 20.

[0308] As shown in Figure 12BAs shown, the second internal electrode layer 132 of the present embodiment further includes: an eighth lead-out portion 132E that extends from the second opposing electrode portion 132M and is led out to a part on the first end face LS1 side of the second side surface WS2; and a ninth lead-out portion 132F that extends from the second opposing electrode portion 132M and is led out to a part on the second end face LS2 side of the second side surface WS2. The eighth lead-out portion 132E is exposed at a part on the first end face LS1 side of the second side surface WS2, and the ninth lead-out portion 132F is exposed at a part on the second end face LS2 side of the second side surface WS2.

[0309] The second opposing electrode portion 132M preferably further includes: an eighth connection portion region 132ME, which is a part connected to the eighth lead-out portion 132E and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 132MM; and a ninth connection portion region 132MF, which is a part connected to the ninth lead-out portion 132F and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 132MM.

[0310] The coverage rate of the eighth connection portion region 132ME and the ninth connection portion region 132MF with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20. The coverage rate of the eighth lead-out portion 132E and the ninth lead-out portion 132F with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20.

[0311] In the present embodiment, the fourth external electrode 140D is connected to the seventh lead-out portion 131D, the fifth external electrode 140E is connected to the eighth lead-out portion 132E, and the sixth external electrode 140F is connected to the ninth lead-out portion 132F.

[0312] In such a structure, the same effect as that of the first embodiment can also be obtained.

[0313] <Fifth Embodiment>

[0314] Hereinafter, the multilayer ceramic capacitor 101 according to the fifth embodiment will be described. In addition, in the following description of the internal electrode layer, detailed description of the same structure as that of the second embodiment will be omitted. Figure 13A It is an external perspective view of the multilayer ceramic capacitor 101 of the present embodiment.

[0315] Figure 13B It is an LW cross-sectional view showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of the present embodiment. Figure 13C It is an LW cross-sectional view showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of the present embodiment. In addition, in Figure 13B and Figure 13CThe illustration of the external electrode 140 is omitted.

[0316] In the multilayer ceramic capacitor 101 of the present embodiment, the forms of the first internal electrode layer, the second internal electrode layer, and the external electrode are different from those of the second embodiment.

[0317] As Figure 13B shown, the first internal electrode layer 131 has: a first opposed electrode portion 131M that opposes the second internal electrode layer 132 with the dielectric layer 20 therebetween; a first lead portion 131A that extends from the first opposed electrode portion 131M and is led out to a part on the first end surface LS1 side of the first side surface WS1 as the first surface portion; and a second lead portion 131F1 that extends from the first opposed electrode portion 131M and is led out to a part on the second end surface LS2 side of the second side surface WS2 as the second surface portion.

[0318] The first opposed electrode portion 131M has: a first central portion region 131MM that includes the central portion of the first opposed electrode portion 131M; a first connection portion region 131MA that is a part connected to the first lead portion 131A and has a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM; and a second connection portion region 131MF1 that is a part connected to the second lead portion 131F1 and has a higher coverage rate of the dielectric layer 20 than the first central portion region 131MM.

[0319] The coverage rates of the first connection portion region 131MA and the second connection portion region 131MF1 with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20. The coverage rates of the first lead portion 131A and the second lead portion 131F1 with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 131MM with respect to the dielectric layer 20.

[0320] As Figure 13C shown, the second internal electrode layer 132 has: a second opposed electrode portion 132M that opposes the first internal electrode layer 131 with the dielectric layer 20 therebetween; a third lead portion 132B1 that extends from the second opposed electrode portion 132M and is led out to a part on the second end surface LS2 side of the first side surface WS1 as the third surface portion; and a fourth lead portion 132E1 that extends from the second opposed electrode portion 132M and is led out to a part on the first end surface LS1 side of the second side surface WS2 as the fourth surface portion.

[0321] The second counter electrode portion 132M preferably has: a second central portion region 132MM, which includes the central portion of the second counter electrode portion 132M; a third connection portion region 132MB1, which is the portion connected to the third lead-out portion 132B1 and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 132MM; and a fourth connection portion region 132ME1, which is the portion connected to the fourth lead-out portion 132E1 and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 132MM.

[0322] The coverage rate of the third connection portion region 132MB1 and the fourth connection portion region 132ME1 with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20. The coverage rate of the third lead-out portion 132B1 and the fourth lead-out portion 132E1 with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 132MM with respect to the dielectric layer 20.

[0323] The external electrode 140 of the present embodiment has, as three or more external electrodes: a first external electrode 140A connected to the first lead-out portion 131A; a second external electrode 140F1 connected to the second lead-out portion 131F1; a third external electrode 140B1 connected to the third lead-out portion 132B1; and a fourth external electrode 140E1 connected to the fourth lead-out portion 132E1.

[0324] In such a structure, the same effects as those of the first embodiment can also be obtained.

[0325] <The Sixth Embodiment>

[0326] Hereinafter, the multilayer ceramic capacitor 201 according to the sixth embodiment will be described. In addition, in the following description of the internal electrode layer, detailed description of the same structure as that of the second embodiment will be omitted. Figure 14A This is a perspective external view of the multilayer ceramic capacitor 201 of the present embodiment.

[0327] Figure 14B This is an LW cross-sectional view showing the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of the present embodiment. Figure 14C This is an LW cross-sectional view showing the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of the present embodiment. In addition, in Figure 14B and Figure 14C the illustration of the external electrode 240 is omitted.

[0328] In the multilayer ceramic capacitor 201 of the present embodiment, the forms of the first internal electrode layer, the second internal electrode layer, and the external electrode are different from those of the second embodiment.

[0329] As Figure 14BAs shown, the first internal electrode layer 231 has: a first opposing electrode portion 231M that opposes the second internal electrode layer 232 across the dielectric layer 20; a first lead-out portion 231A that extends from the first opposing electrode portion 231M and is led out to a part on the first end surface LS1 side of the first side surface WS1 as the first surface portion; and a second lead-out portion 231B that extends from the first opposing electrode portion 231M and is led out to a part on the second end surface LS2 side of the first side surface WS1 as the second surface portion. The first internal electrode layer 231 further has: a tenth lead-out portion 231E that extends from the first opposing electrode portion 231M and is led out to a part on the first end surface LS1 side of the second side surface WS2; and an eleventh lead-out portion 231F that extends from the first opposing electrode portion 231M and is led out to a part on the second end surface LS2 side of the second side surface WS2.

[0330] The first opposing electrode portion 231M has: a first central portion region 231MM that includes the central portion of the first opposing electrode portion 231M; a first connection portion region 231MA that is a part connected to the first lead-out portion 231A and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 231MM; and a second connection portion region 231MB that is a part connected to the second lead-out portion 231B and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 231MM. The first opposing electrode portion 231M further has: a tenth connection portion region 231ME that is a part connected to the tenth lead-out portion 231E and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 231MM; and an eleventh connection portion region 231MF that is a part connected to the eleventh lead-out portion 231F and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 231MM.

[0331] The coverage rates of the first connection portion region 231MA and the second connection portion region 231MB with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 231MM with respect to the dielectric layer 20. The coverage rates of the first lead-out portion 231A and the second lead-out portion 231B with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 231MM with respect to the dielectric layer 20. In addition, the coverage rates of the tenth connection portion region 231ME and the eleventh connection portion region 231MF with respect to the dielectric layer 20 are preferably higher than the coverage rate of the first central portion region 231MM with respect to the dielectric layer 20. The coverage rates of the tenth lead-out portion 231E and the eleventh lead-out portion 231F with respect to the dielectric layer 20 are preferably higher than the coverage rate of the first central portion region 231MM with respect to the dielectric layer 20.

[0332] As Figure 14CAs shown, the second internal electrode layer 232 has: a second opposed electrode portion 232M that opposes the first internal electrode layer 231 with a dielectric layer 20 interposed therebetween; a third lead portion 232C that extends from the second opposed electrode portion 232M and is led out to a part on the second end face LS2 side of the first side face WS1 that is the third surface portion; and a fourth lead portion 232D that extends from the second opposed electrode portion 232M and is led out to a part on the first end face LS1 side of the second side face WS2 that is the fourth surface portion. The second internal electrode layer 232 further has: a twelfth lead portion 232G that extends from the second opposed electrode portion 232M and is led out to a part on the first end face LS1 side of the first side face WS1; and a thirteenth lead portion 232H that extends from the second opposed electrode portion 232M and is led out to a part on the second end face LS2 side of the second side face WS2.

[0333] The second opposed electrode portion 232M preferably has: a second central portion region 232MM that includes the central portion of the second opposed electrode portion 232M; a third connection portion region 232MC that is a part connected to the third lead portion 232C and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 232MM; and a fourth connection portion region 232MD that is a part connected to the fourth lead portion 232D and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 232MM. The second opposed electrode portion 232M preferably further has: a twelfth connection portion region 232MG that is a part connected to the twelfth lead portion 232G and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 232MM; and a thirteenth connection portion region 232MH that is a part connected to the thirteenth lead portion 232H and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 232MM.

[0334] The coverage rate of the third connection portion region 232MC and the fourth connection portion region 232MD with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 232MM with respect to the dielectric layer 20. The coverage rate of the third lead portion 232C and the fourth lead portion 232D with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 232MM with respect to the dielectric layer 20. In addition, the coverage rate of the twelfth connection portion region 232MG and the thirteenth connection portion region 232MH with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 232MM with respect to the dielectric layer 20. The coverage rate of the twelfth lead portion 232G and the thirteenth lead portion 232H with respect to the dielectric layer 20 is preferably higher than the coverage rate of the second central portion region 232MM with respect to the dielectric layer 20.

[0335] The external electrodes 240 of the present embodiment have, as three or more external electrodes: a first external electrode 240A connected to the first lead portion 231A; a second external electrode 240B connected to the second lead portion 231B; a third external electrode 240C connected to the third lead portion 232C; and a fourth external electrode 240D connected to the fourth lead portion 232D. The external electrodes 240 of the present embodiment further have: a fifth external electrode 240E connected to the tenth lead portion 231E; a sixth external electrode 240F connected to the eleventh lead portion 231F; a seventh external electrode 240G connected to the twelfth lead portion 232G; and an eighth external electrode 240H connected to the thirteenth lead portion 232H.

[0336] In such a structure, the same effects as those of the first embodiment can also be obtained.

[0337] <The Seventh Embodiment>

[0338] Hereinafter, the multilayer ceramic capacitor 301 according to the seventh embodiment will be described. In addition, in the following description of the internal electrode layers, detailed descriptions of the same structures as those of the first embodiment will be omitted. Figure 15A It is an external perspective view of the multilayer ceramic capacitor 301 of the present embodiment.

[0339] Figure 15B It is an LW cross-sectional view showing the first internal electrode layer 331 of the multilayer ceramic capacitor 301 of the present embodiment. Figure 15C It is an LW cross-sectional view showing the second internal electrode layer 332 of the multilayer ceramic capacitor 301 of the present embodiment. In addition, in Figure 15B and Figure 15C the illustration of the external electrodes 340 is omitted.

[0340] In the multilayer ceramic capacitor 1 of the present embodiment, the ways of the laminate, the first internal electrode layer, the second internal electrode layer, and the external electrodes are different from those of the first embodiment.

[0341] The multilayer ceramic capacitor 301 of the present embodiment has a laminate 310 and external electrodes 340. The laminate 310 of the present embodiment is a thin type with a small thickness in the stacking direction, and its shape is square when viewed from the stacking direction.

[0342] As Figure 15BAs shown, the first internal electrode layer 331 has: a first opposing electrode portion 331M that opposes the second internal electrode layer 332 with the dielectric layer 20 therebetween; a first lead portion 331A that extends from the first opposing electrode portion 331M and is led out to the first side surface WS1 and the first end surface LS1 that are the first surface portions; and a second lead portion 331B that extends from the first opposing electrode portion 331M and is led out to the second side surface WS2 and the second end surface LS2 that are the second surface portions.

[0343] The first opposing electrode portion 331M has: a first central portion region 331MM that includes the central portion of the first opposing electrode portion 331M; a first connection portion region 331MA that is the portion connected to the first lead portion 331A and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 331MM; and a second connection portion region 331MB that is the portion connected to the second lead portion 331B and is a region with a higher coverage rate of the dielectric layer 20 than the first central portion region 331MM.

[0344] The coverage rates of the first connection portion region 331MA and the second connection portion region 331MB with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 331MM with respect to the dielectric layer 20. The coverage rates of the first lead portion 331A and the second lead portion 331B with respect to the dielectric layer 20 are higher than the coverage rate of the first central portion region 331MM with respect to the dielectric layer 20.

[0345] As Figure 15C shown, the second internal electrode layer 332 has: a second opposing electrode portion 332M that opposes the first internal electrode layer 331 with the dielectric layer 20 therebetween; a third lead portion 332C that extends from the second opposing electrode portion 332M and is led out to the first side surface WS1 and the second end surface LS2 that are the third surface portions; and a fourth lead portion 332D that extends from the second opposing electrode portion 332M and is led out to the second side surface WS2 and the first end surface LS1 that are the fourth surface portions.

[0346] The second opposing electrode portion 332M preferably has: a second central portion region 332MM that includes the central portion of the second opposing electrode portion 332M; a third connection portion region 332MC that is the portion connected to the third lead portion 332C and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 332MM; and a fourth connection portion region 332MD that is the portion connected to the fourth lead portion 332D and is a region with a higher coverage rate of the dielectric layer 20 than the second central portion region 332MM.

[0347] The coverage rate of the dielectric layer 20 by the third connection portion region 332MC and the fourth connection portion region 332MD is preferably higher than the coverage rate of the dielectric layer 20 by the second central portion region 332MM. The coverage rate of the dielectric layer 20 by the third lead portion 332C and the fourth lead portion 332D is preferably higher than the coverage rate of the dielectric layer 20 by the second central portion region 332MM.

[0348] The external electrode 340 of the present embodiment has, as three or more external electrodes: a first external electrode 340A connected to the first lead portion 331A; a second external electrode 340B connected to the second lead portion 331B; a third external electrode 340C connected to the third lead portion 332C; and a fourth external electrode 340D connected to the fourth lead portion 332D.

[0349] In such a structure, the same effects as those of the first embodiment can also be obtained.

[0350] <Experimental Example>

[0351] According to the above manufacturing method, a multilayer ceramic capacitor was fabricated as a sample of the experimental example, and the value of the DC resistance (Rdc) of the multilayer ceramic capacitor was measured.

[0352] 1. Fabrication of Multilayer Ceramic Capacitor

[0353] As a sample of the experimental example, using the manufacturing method according to the embodiment, a multilayer ceramic capacitor with the following specifications and adjusted coverage rate of the internal electrode layer on the dielectric layer was fabricated in the Figures 1 - 7 shown structure.

[0354] · Dimensions of the multilayer ceramic capacitor: L×W×T = 1.0 mm × 0.5 mm × 0.5 mm

[0355] · Material (main component) of the dielectric layer: BaTiP3

[0356] · Capacitance: 10 μF

[0357] · Rated voltage: 4 V

[0358] · Thickness of the dielectric layer: 0.5 μm

[0359] · First internal electrode layer

[0360] · Material: Ni

[0361] · Shape: Figure 6 shown shape

[0362] · Thickness: 0.4 μm

[0363] · Coverage rate A of the first opposing electrode portion on the dielectric layer: Refer to the table

[0364] · Coating rate B of the dielectric layer by the first connection portion region and the second connection portion region: Refer to the table

[0365] · Coating rate C of the dielectric layer by the first lead portion and the second lead portion: Refer to the table

[0366] · Second internal electrode layer: Ni

[0367] · Material: Ni

[0368] · Shape: Figure 7 The shape shown

[0369] · Thickness: 0.4 μm

[0370] · Coating rate D of the dielectric layer by the second opposed electrode portion: Refer to the table

[0371] · Coating rate E of the dielectric layer by the third connection portion region and the fourth connection portion region: Refer to the table

[0372] · Coating rate F of the dielectric layer by the third lead portion and the fourth lead portion: Refer to the table

[0373] · Structure of the external electrode

[0374] · Structure of the first external electrode and the second external electrode

[0375] · Base electrode layer: A fired layer containing a conductive metal (Cu) and a glass component

[0376] · Thickness of the central portion on the side: Approximately 30 μm

[0377] · Plating layer: Two layers of Ni plating layer and Sn plating layer are formed

[0378] · Thickness of the Ni plating layer: 4 μm

[0379] · Thickness of the Sn plating layer: 4 μm

[0380] · The third external electrode and the fourth external electrode

[0381] · Base electrode layer: A fired layer containing a conductive metal (Cu) and a glass component

[0382] · Thickness of the central portion on the end face: Approximately 45 μm

[0383] · Plating layer: Two layers of Ni plating layer and Sn plating layer are formed

[0384] · Thickness of the Ni plating layer: 4 μm

[0385] · Thickness of the Sn plating layer: 4 μm

[0386] 2. Evaluation

[0387] Next, the fabricated samples were evaluated according to the following measurement methods.

[0388] <Measurement of the DC resistance (Rdc) value of the multilayer ceramic capacitor>

[0389] For Experimental Examples 1a to 8a, while passing a current of I = 100 mA between the first external electrode and the second external electrode, the potential difference V between the first external electrode and the second external electrode was measured, and the DC resistance Rdc1 was calculated by computing Rdc1 = V / I (potential difference / 100 mA). Then, the coverage rates A, B, and C were measured. For Experimental Examples 1b to 8b, while passing a current of I = 100 mA between the third external electrode and the fourth external electrode, the potential difference V between the third external electrode and the fourth external electrode was measured, and Rdc2 = V / I (potential difference / 100 mA) was calculated, thereby obtaining the DC resistance Rdc2. Then, the coverage rates D, E, and F were measured.

[0390] 3. Measurement Results

[0391] The measurement results of Rdc1 and the coverage rates A, B, and C are shown in Table 1. The measurement results of Rdc2 and the coverage rates D, E, and F are shown in Table 2.

[0392] [Table 1]

[0393] Coating rate A Coating rate B Coating rate C DC resistance Rdc1 Experimental example 1a 58％ 42％ 41％ 20 mΩ Experimental example 2a 53％ 71％ 73％ 14 mΩ Experimental example 3a 52％ 44％ 46％ 19 mΩ Experimental example 4a 52％ 74％ 72％ 14 mΩ Experimental example 5a 65％ 56％ 55％ 17 mΩ Experimental example 6a 60％ 80％ 79％ 10 mΩ Experimental example 7a 80％ 98％ 95％ 4 mΩ Experimental example 8a 95％ 100％ 100％ 3 mΩ

[0394] [Table 2]

[0395] Coating rate D Coating rate E Coating rate F DC resistance Rdc2 Experimental example 1b 58％ 44％ 43％ 19 mΩ Experimental example 2b 53％ 49％ 47％ 17 mΩ Experimental example 3b 52％ 73％ 75％ 13 mΩ Experimental example 4b 52％ 76％ 74％ 12 mΩ Experimental example 5b 65％ 51％ 54％ 16 mΩ Experimental example 6b 60％ 78％ 80％ 9 mΩ Experimental example 7b 78％ 97％ 98％ 3 mΩ Experimental example 8b 95％ 100％ 100％ 2 mΩ

[0396] Comparing Experimental Example 3a with Experimental Example 2a and Experimental Example 4a, it can be seen that when the coverage rate A is approximately the same value, if the coverage rates B and C are higher than the coverage rate A (Experimental Example 2a, Experimental Example 4a), the DC resistance Rdc1 can be reduced. In addition, when observing Experimental Example 5a with respect to Experimental Example 2a and Experimental Example 4a, it can be confirmed that even if the coverage rate A is increased, when the coverage rates B and C are low, the DC resistance Rdc1 will become higher. In Experimental Example 8a, by making the coverage rate A lower than the coverage rates B and C, it is possible to reduce the DC resistance Rdc1 while improving the adhesion between dielectric layers.

[0397] Comparing Experimental Example 2b, Experimental Example 3b, and Experimental Example 4b, it can be seen that when the coverage rate D is at approximately the same value, if the coverage rate E and the coverage rate F are higher than the coverage rate D (Experimental Example 3b, Experimental Example 4b), the DC resistance Rdc2 can be reduced. In addition, when observing Experimental Example 5b with respect to Experimental Example 3b and Experimental Example 4b, it can be confirmed that even if the coverage rate D is increased, when the coverage rate E and the coverage rate F are low, the DC resistance Rdc2 will increase. In Experimental Example 8b, by making the coverage rate D lower than the coverage rate E and the coverage rate F, the DC resistance Rdc2 can be reduced while improving the adhesion between the dielectric layers.

[0398] As shown in Experimental Examples 2a, 4a, 6a, 7a, and 8a, by setting the coverage rate A < the coverage rate B and the coverage rate A < the coverage rate C, the DC resistance Rdc1 can be reduced. In addition, as shown in Experimental Examples 3b, 4b, 6b, 7b, and 8b, by setting the coverage rate D < the coverage rate E and the coverage rate D < the coverage rate F, the DC resistance Rdc2 can be reduced. Additionally, the coverage rates B, C, E, and F are preferably 72% or more. The coverage rates A and D are preferably 52% or more. The coverage rates B and C may be 5% or more higher than the coverage rate A. The coverage rates E and F may be 5% or more higher than the coverage rate D.

[0399] Thereby, the adhesion force between the dielectric layers is also increased, the increase in the DC resistance (Rdc) can be suppressed while suppressing delamination between layers, and the characteristics as a multilayer ceramic capacitor can be maintained and improved.

[0400] The present invention is not limited to the structure of the above-described embodiments, and can be appropriately modified and applied within the scope without changing the gist of the present invention. In addition, a structure in which two or more of the various preferred structures described in the above embodiments are combined is also the present invention.

Claims

1. A multilayer ceramic capacitor having: A laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction, and a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction and the length direction; and Three or more external electrodes, In the multilayer ceramic capacitor, The plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers, The first internal electrode layer has: A first opposed electrode portion opposed to the second internal electrode layer with the dielectric layer interposed therebetween; A first lead-out portion extending from the first opposed electrode portion and led out to a first surface portion of the laminate; and A second lead-out portion extending from the first opposed electrode portion and led out to a second surface portion of the laminate, The second internal electrode layer has: A second opposed electrode portion opposed to the first internal electrode layer with the dielectric layer interposed therebetween; and A third lead-out portion extending from the second opposed electrode portion and led out to a third surface portion of the laminate, The three or more external electrodes have: A first external electrode connected to the first lead-out portion; A second external electrode connected to the second lead-out portion; and A third external electrode connected to the third lead-out portion, The first opposed electrode portion has: A first central region including the central portion of the first opposed electrode portion; A first connection region which is a portion connected to the first lead-out portion and is a region having a higher coverage rate of the dielectric layer than the first central region; and A second connection region which is a portion connected to the second lead-out portion and is a region having a higher coverage rate of the dielectric layer than the first central region, The coverage rate of the first connection region and the second connection region to the dielectric layer is higher than the coverage rate of the first central region to the dielectric layer, The coverage rate of the first lead-out portion and the second lead-out portion to the dielectric layer is higher than the coverage rate of the first central region to the dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein At least a part of the first surface portion is a part of the first side surface, At least a part of the second surface portion is a part of the second side surface.

3. The multilayer ceramic capacitor according to claim 2, wherein The length of the first lead-out portion in the length direction is shorter than the length of the first opposed electrode portion in the length direction, The length of the second lead-out portion in the length direction is shorter than the length of the first opposed electrode portion in the length direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The coverage rate of the first connection region and the second connection region to the dielectric layer is 72% or more, The coverage rate of the first lead-out portion and the second lead-out portion to the dielectric layer is 72% or more.

5. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, the second internal electrode layer further has: a fourth lead-out portion that extends from the second opposing electrode portion and is led out to a fourth surface portion of the laminate, the three or more external electrodes further have: a fourth external electrode connected to the fourth lead-out portion.

6. The multilayer ceramic capacitor according to claim 5, wherein, at least a part of the third surface portion is a part of the first end face, at least a part of the fourth surface portion is a part of the second end face.

7. The multilayer ceramic capacitor according to claim 6, wherein, the length of the third lead-out portion in the width direction is shorter than the length of the second opposing electrode portion in the width direction, the length of the fourth lead-out portion in the width direction is shorter than the length of the second opposing electrode portion in the width direction.

8. The multilayer ceramic capacitor according to claim 5, wherein, the second opposing electrode portion has: a second central portion region including the central portion of the second opposing electrode portion; a third connection portion region that is a portion connected to the third lead-out portion and is a region having a higher coverage rate of the dielectric layer than the second central portion region; and a fourth connection portion region that is a portion connected to the fourth lead-out portion and is a region having a higher coverage rate of the dielectric layer than the second central portion region, the coverage rates of the third connection portion region and the fourth connection portion region with respect to the dielectric layer are higher than the coverage rate of the second central portion region with respect to the dielectric layer, the coverage rates of the third lead-out portion and the fourth lead-out portion with respect to the dielectric layer are higher than the coverage rate of the second central portion region with respect to the dielectric layer.

9. The multilayer ceramic capacitor according to claim 8, wherein, the coverage rates of the third connection portion region and the fourth connection portion region with respect to the dielectric layer are 72% or more, the coverage rates of the third lead-out portion and the fourth lead-out portion with respect to the dielectric layer are 72% or more.

10. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, the thickness of the dielectric layer is 0.3 μm or more and 1.5 μm or less.

11. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, the thickness of the internal electrode layer is 0.25 μm or more and 0.6 μm or less.

12. The multilayer ceramic capacitor according to claim 11, wherein, the thickness of the internal electrode layer is 0.25 μm or more and 0.4 μm or less.

13. The multilayer ceramic capacitor according to claim 1, wherein, when the lead-out direction of the first lead-out portion is set as the first lead-out direction, the length of the first lead-out portion in the direction orthogonal to the first lead-out direction is shorter than the length of the first opposing electrode portion in the direction orthogonal to the first lead-out direction, when the lead-out direction of the second lead-out portion is set as the second lead-out direction, The length in the direction orthogonal to the second lead-out direction of the second lead-out portion is shorter than the length in the direction orthogonal to the second lead-out direction of the first opposing electrode portion.

14. The multilayer ceramic capacitor according to claim 13, wherein At least a part of the first surface portion is a part of the first side surface, At least a part of the second surface portion is a part of the second side surface.

15. The multilayer ceramic capacitor according to claim 13, wherein At least a part of the first surface portion is a part of the first end surface, At least a part of the second surface portion is a part of the second end surface.

16. The multilayer ceramic capacitor according to claim 13, wherein At least a part of the first surface portion is a part of the first side surface on the first end surface side, At least a part of the second surface portion is a part of the first side surface on the second end surface side.

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