Image sensor and method of manufacturing the same, electronic device

Abstract

The application provides an image sensor and a preparation method thereof and an electronic device, and the preparation method comprises the following steps: providing a semiconductor substrate, forming a first groove and a first filling layer on a second surface, forming a second groove in the first filling layer, and preparing a second filling layer comprising a first structure layer and a second structure layer. Based on the design, the first groove and the first filling layer are formed first, the second groove is prepared in the first filling layer, and the second filling layer with the first structure layer and the second structure layer is formed based on the second groove. The signal matching modulation structure and the crosstalk improvement structure can be formed based on the second filling layer. Based on the design of the second filling layer, the problem of matching difference between different pixels in the pixel array can be optimized while improving the crosstalk, and the imaging quality is improved.

Description

Technical Field

[0001] This invention belongs to the field of image acquisition technology, and in particular relates to an image sensor, its preparation method, and corresponding electronic equipment. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on the different components, they can be divided into two main categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor).

[0003] With the continuous development of CMOS integrated circuit manufacturing processes, especially the design and manufacturing processes of CMOS image sensors (CIS), CMOS image sensors have gradually replaced CCD image sensors as the mainstream. Compared with CCD, CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application value in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.

[0004] However, crosstalk between imaging signals often exists during the imaging process of image sensors, affecting the final imaging effect. In some applications, such as high-resolution, low-pixel CIS products with 100-megapixel or 200-megapixel resolutions, there is often a need to fuse multiple high-resolution pixels into a low-resolution image to suit different application scenarios. A 4x4 color filter arrangement becomes one option. However, the 4x4 arrangement causes differences in the physical environment surrounding the same color. These differences in the physical environment lead to variations in signal crosstalk at different locations of the same color, resulting in color noise in the image and affecting the imaging effect. In addition, the fabrication processes for structures that mitigate crosstalk and differences in existing technologies are often quite complex.

[0005] Therefore, it is necessary to provide an image sensor and its fabrication method, as well as an electronic device, to solve the problems of crosstalk between imaging signals and the differences in crosstalk between different pixels in the existing technology. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an image sensor and its manufacturing method and electronic device, which solves the problems of crosstalk between imaging signals of pixels in pixel arrays, the difficulty in effectively solving the crosstalk differences between different pixels, and the complexity of the corresponding manufacturing process in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an image sensor, the method comprising:

[0008] A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces;

[0009] A first trench is formed in the semiconductor substrate from the second surface of the semiconductor substrate;

[0010] A first filling layer is prepared in the first trench, the first filling layer fills the first trench and extends to cover the semiconductor substrate surrounding the first trench;

[0011] A second trench is formed in the first filling layer, the second trench corresponding to the first trench and extending from the second surface of the semiconductor substrate into the corresponding first trench;

[0012] A second filling layer is prepared in the second trench, wherein:

[0013] The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on a second surface of the semiconductor substrate to form a crosstalk improvement structure.

[0014] The present invention also provides an image sensor, which can be prepared by the preparation method described above, or by other methods. The image sensor includes:

[0015] A semiconductor substrate having opposing first and second surfaces;

[0016] A first trench extends from a second surface of the semiconductor substrate into the semiconductor substrate;

[0017] The first filling layer fills the first trench;

[0018] The second trench is located in the first filling layer, and the second trench extends from the second surface of the semiconductor substrate to the corresponding first trench;

[0019] A second filling layer, located at least within the second trench, wherein:

[0020] The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the surface of the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on the second surface of the semiconductor substrate to form a crosstalk improvement structure.

[0021] The present invention also provides an electronic device including an image sensor as described in any of the above embodiments.

[0022] As described above, the image sensor and its fabrication method and electronic device of this application first form a first trench and a first filling layer during the fabrication process, then form a second trench in the first filling layer, and form a second filling layer with a first structural layer and a second structural layer based on the second trench. A signal matching modulation structure and a crosstalk improvement structure can be formed based on the second filling layer. Based on the design of the second filling layer, the problem of matching differences between different pixels in the pixel array can be optimized while improving crosstalk, thereby improving the imaging quality. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 The diagram shows the basic structure of an image sensor system.

[0025] Figure 2 The diagram shows a pixel circuit made of an image sensor.

[0026] Figure 3 The flowchart shown is a process for preparing the image sensor in an embodiment of this application.

[0027] Figure 4 The diagram shows a semiconductor substrate provided in the fabrication of the image sensor of this application.

[0028] Figure 5 This is a schematic diagram showing the front-side process after fabrication of the image sensor in this application.

[0029] Figure 6 The diagram shown is a schematic of the back side after thinning during the fabrication of the image sensor in this application.

[0030] Figures 7-12 The diagram shows the formation of a first trench, a surface cover layer, a first filling layer, a thinned structure of the first filling layer, a second trench, and a second filling material layer in the fabrication of the image sensor of this application.

[0031] Figures 13-16 This is shown as a first example of forming a second filling layer in the fabrication of the image sensor of this application.

[0032] Figure 17 The diagram shows a lens formed in the fabrication of the real-image sensor of this application, corresponding to the first example described above.

[0033] Figures 18-22This is shown as a second example of forming a second filling layer in the fabrication of the image sensor of this application.

[0034] Figure 23 The diagram shows a lens formed in the fabrication of the real-image sensor of this application, corresponding to the first example described above.

[0035] Figure 24 and Figure 25 The image sensor shown is configured to correspond to the second groove.

[0036] Figure 26 and Figure 27 The diagram shown is a pixel unit pixel circuit and layout schematic of an image sensor according to this application. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0039] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. For ease of explanation in the detailed description of embodiments of the invention, cross-sectional views illustrating device structures may be partially enlarged and not to scale; these schematic diagrams are merely examples and should not limit the scope of protection of the invention. In actual fabrication, three-dimensional spatial dimensions of length, width, and depth should be included.

[0040] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "above" may be used herein to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. The described structure of a first feature "above" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] Figure 1 The diagram shows a basic block structure of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. A functional logic unit is connected to the readout circuit, and the readout circuit and control circuit are connected to a status register to control the pixel array. The pixel array includes multiple pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In specific implementations, the readout circuit may include an analog-to-digital converter (ADC) and other circuits. In some applications, after the pixels acquire image data, they are read out using the readout mode specified by the status register and then transmitted to the functional logic unit.

[0042] In some applications, the status register may contain a programmed selection system to determine whether the readout system uses rolling shutter or global shutter exposure. The functional logic unit may store raw image data or image data after image processing. In some implementations, the readout circuitry may read one row of image data at a time along the readout column lines; other methods may also be used. The operation of the control circuitry can be determined by the current settings in the status register. For example, the control circuitry generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global shutter signal, allowing all pixels in the pixel array to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal may be a rolling shutter signal, allowing pixels in each row of the pixel array to be continuously exposed and read through the acquisition window.

[0043] Figure 2This diagram illustrates a pixel unit in an image sensor. As shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and pixel circuitry (shown as a transistor within the dashed box). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one application example, the pixel circuitry includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS), connected to, for example... Figure 2 The diagram shows a transfer transistor (TX) and a photodiode. In some applications, the pixel circuitry is stacked, including a reset transistor, a source follower transistor, and a pixel select transistor on a first circuit chip, and a transfer transistor on a second circuit chip, where the photodiode is connected to other transistors on the first circuit chip via the transfer transistor. In further applications, the pixel circuitry may also include a gain control transistor (DCG) connected between the floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photocharge in response to incident light during exposure. The transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer the accumulated charge in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and in response to a reset signal, resets the sensor pixel circuitry (e.g., discharges or charges the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor, which is connected between the power supply voltage and the pixel select transistor, responding to and outputting the potential of the floating diffusion region. The pixel select transistor is connected to the source follower transistor and the bit line, and in response to a pixel select control signal, performs pixel selection readout and outputs it to the readout column.

[0044] However, crosstalk between imaging signals often exists during the imaging process of image sensors, affecting the final imaging effect. In some applications, such as high-resolution, low-pixel CIS products (e.g., 100-megapixel or 200-megapixel), multiple high-resolution pixels are often fused into a low-resolution image to suit different application scenarios. A 4x4 color arrangement becomes a common choice. However, this 4x4 arrangement causes differences in the physical environment surrounding the same color, leading to variations in signal crosstalk at different locations of the same color. This results in color noise in the image, affecting the imaging effect. Existing technologies often employ complex fabrication processes to mitigate crosstalk and differences. This invention, through the design of the image sensor's structure and manufacturing process, effectively improves the aforementioned problems related to crosstalk, differences, and process design.

[0045] The following will describe the process in detail with reference to the embodiments.

[0046] Example 1:

[0047] Please see Figure 3 As shown, this embodiment provides a method for fabricating an image sensor. Figure 3 The flowchart shown is for the preparation method, which includes the following steps:

[0048] S1: Provide a semiconductor substrate having opposing first and second surfaces;

[0049] S2: A first trench is formed in the semiconductor substrate from the second surface of the semiconductor substrate;

[0050] S3: A first filling layer is prepared in the first trench, the first filling layer fills the first trench and extends to cover the semiconductor substrate surrounding the first trench;

[0051] S4: A second trench is prepared in the first filling layer, the second trench corresponding to the first trench and extending from the second surface of the semiconductor substrate to the corresponding first trench;

[0052] S5: A second filling layer is prepared in the second trench, wherein:

[0053] The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the surface of the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on a second surface of the semiconductor substrate to form a crosstalk improvement structure.

[0054] In the image sensor and its fabrication in this embodiment, a first trench and a first filling layer are first formed, then a second trench is fabricated in the first filling layer. A second filling layer, including a first structural layer and a second structural layer, is formed based on the second trench. A signal matching modulation structure and a crosstalk reduction structure can be formed based on the second filling layer. Through the design of the second filling layer, the matching differences between different pixels in the pixel array can be optimized while improving crosstalk, thereby improving image quality. It should be noted that the fabrication sequence in the above steps, corresponding to existing processes, can be changed according to actual needs without affecting the beneficial effects of this application.

[0055] The fabrication of the image sensor of this application will be described in detail below with reference to specific embodiments.

[0056] First, such as Figure 4 As shown, in step S1, a semiconductor substrate 101 is provided, the semiconductor substrate 101 having a first surface 101a (upper surface) and a second surface 101b (lower surface) opposite each other.

[0057] Specifically, the semiconductor substrate 101 can be a structure composed of a single material layer, including but not limited to a silicon substrate. The material can be monocrystalline silicon, monocrystalline germanium, polycrystalline silicon, amorphous silicon, or silicon-germanium compounds, etc. Of course, the semiconductor substrate 101 can also be silicon-on-insulator (SOI), etc. Furthermore, the semiconductor substrate 101 can also have N-type doped or P-type doped regions to meet practical requirements.

[0058] Furthermore, the semiconductor substrate 101, serving as the substrate for the image sensor, can also be a multilayer structure, such as including a semiconductor substrate and an epitaxial layer formed on the surface of the semiconductor substrate. The epitaxial layer serves as a functional layer for the device, enabling the fabrication of the image sensor device. In other embodiments, the semiconductor substrate 101 can be any structure used in the field of image sensors for fabricating the functional areas of the image sensor. The photosensitive elements, individual transistors, and interconnections of a CMOS image sensor can be fabricated based on the semiconductor substrate 101.

[0059] In one example, the device functional layer can be part of the semiconductor substrate 101. For example, it can be an epitaxial layer (EPI) formed on a semiconductor substrate (such as a silicon substrate). The epitaxial layer serves as the device functional layer and can be a P-type silicon epitaxial layer. It can be formed directly using an epitaxial process or using other methods of existing processes. In this case, the semiconductor substrate and the epitaxial layer constitute the semiconductor substrate 101. Figure 4 The first surface 101a can be considered the upper surface of the epitaxial layer, and the second surface 101b can be considered the lower surface of the epitaxial layer. Furthermore, Figure 6 Surface 101c is obtained by thinning the back side after flipping, and is still referred to as the second surface.

[0060] In some applications, the functional regions (including semiconductor devices) of the image sensor are fabricated within the device functional layer. In other applications, the semiconductor substrate 101 can be considered as a doped substrate as a whole, including the device functional layer of the first doping type (P-type). In this case, the functional regions of the image sensor can be fabricated within the semiconductor substrate 101, including the photoelectric conversion doped regions of the second doping type (N-type). Of course, if needed, the required structure of the image sensor can also be fabricated within the semiconductor substrate or other material layers. A back-illuminated image sensor can be fabricated based on this semiconductor substrate and device functional layer.

[0061] Next, as Figures 5-7 As shown, in step S2, a first trench 108 is formed in the semiconductor substrate 101 from the second surface 101b.

[0062] Please see Figure 5 and Figure 6 As an example, before forming the first trench 108, the following steps are also included:

[0063] A shallow trench isolation structure 103 is formed on the first surface 101a side of the semiconductor substrate 101. The material includes, but is not limited to, silicon oxide. When forming the shallow trench isolation structure 103, a surface dielectric layer 102 is also prepared on the trench surface, which can be a silicon oxide layer formed by thermal oxidation. Furthermore, the method also includes the step of forming a photoelectric conversion doped region 104 and an isolation region 105 with different doping types from the first surface 101a side, such as the isolation region 105 having a first doping type P-type and the photoelectric conversion doped region 104 having a second doping type N-type.

[0064] The image sensor fabrication process also includes forming various semiconductor devices, such as transmission transistors 106, from the first surface layer. Furthermore, an interconnect layer 107 for electrical connection and routing of the transistors is formed, such as... Figure 5 As shown. In other examples, a support substrate may be further formed on the interconnect layer 107 to facilitate subsequent processes. Furthermore, before performing the second-side process, a process of flipping the aforementioned structure is included. After flipping, the structure can be further thinned to obtain the second surface 101c for subsequent processes, such as... Figure 6 As shown.

[0065] Specifically, the semiconductor device (not shown in the figure) may include photoelectric conversion elements and the corresponding transistors of the pixel circuit of the image sensor. The photoelectric conversion elements realize the conversion of photoelectricity, and the photoelectric conversion doped region is a component of the photoelectric conversion elements. Of course, it may also include other CIS pixel circuit devices in the prior art to realize the functions of image acquisition and subsequent imaging. For example, the pixel circuit may include transmission transistors TX, etc. See [reference needed]. Figure 26 As shown, it may also include a reset transistor RST, an output transistor SF, a pixel selection transistor RS, and a gain adjustment transistor DCG, etc.

[0066] As an example, the isolation region 105 can be ion-doped to achieve isolation. In one example, the semiconductor substrate 101 includes a semiconductor substrate and an epitaxial layer, with the epitaxial layer serving as the device functional layer. The isolation region 105 can penetrate the device functional layer. Of course, in some implementations, the depth of the isolation region 105 can be set according to the location of the photoelectric conversion element or actual needs to achieve isolation. Figure 5 In the example shown, the bottom of the isolation region 105 is closer to the first surface 101a than the photoelectric conversion doped region 104.

[0067] In an optional example, the shallow trench isolation structure 103 and the subsequent first trench and second trench are all formed at positions corresponding to the isolation region 105, and the device isolation function can be achieved based on the structure formed by each part according to the requirements. For example, the position of the first trench 108 corresponding to the isolation region 105 can mean that the first trench 108 is completely located within the projection range of the isolation region 105, that is, the periphery of the first trench corresponds to the isolation region 105, or the edge of the first trench 108 is aligned with the edge of the isolation region 105.

[0068] Please see Figure 7 As shown, in one example, the method for forming the first trench 108 may be:

[0069] First, a first mask layer (not shown in the figure) is formed on the second surface 101c of the semiconductor substrate 101; then, the semiconductor substrate 101 is etched based on the first mask layer to form a first trench 108. Optionally, the first mask layer includes, but is not limited to, a hard mask layer, such as a silicon nitride mask layer.

[0070] In one example, this step involves fabricating a deep trench isolation structure on the back side (photosensitive surface) of a back-illuminated image sensor. First, the first isolation structure on the back side is patterned using a photolithography process, and then an etching process is performed to fabricate the trench structure in the area of ​​the first isolation structure on the back side defined by the photolithography process.

[0071] Optionally, the depth of the first trench 108 is greater than 0.5 μm and less than or equal to the thickness of the semiconductor substrate. Further, the depth of the first trench 108 is less than or equal to the thickness of the device functional layer (such as an epitaxial layer); wherein, the thickness of the semiconductor substrate (such as a silicon substrate) can be distributed between 1 μm and 15 μm.

[0072] Next, as Figures 8-10 As shown, in step S3, a first filling layer 110 is prepared in the first trench 108. The first filling layer 110 fills the first trench 108 and extends to cover the semiconductor substrate 10 surrounding the first trench 108.

[0073] Please see Figure 8 As shown, as an example, before the first filling layer 110 is prepared in the first trench 108, the method further includes the step of forming a surface capping layer 109 on the inner wall and surrounding surface of the semiconductor substrate 101 of the first trench 108. Subsequently, the first filling layer 110 is formed on the surface capping layer 109 and forms a stacked barrier structure with the surface capping layer. The stacked barrier structure formed by the surface capping layer 109 and the first filling layer 110 forms the basis for subsequent processes and improves process stability. The specific details will be further explained in the subsequent corresponding processes.

[0074] As an example, the surface capping layer 109 includes at least one of an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, and a tantalum oxide layer. That is, the material of the surface capping layer 109 can be a common oxide or nitride material, including aluminum oxide, silicon oxide, silicon nitride, hafnium oxide, tantalum oxide, etc.

[0075] In addition, the number of surface cover layers 109 is at least one, that is, it can be a single layer or multiple layers. When the surface cover layer 109 is multiple layers, it is a combination of the above material layers. The thickness of a single surface cover layer 109 is between 1nm and 200nm, such as 2nm, 10nm, 50nm, 100nm, etc.

[0076] Specifically, the surface coating can be prepared using one or a combination of ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition) technologies.

[0077] Please see Figure 9 and Figure 10 As shown, in one example, after forming the surface cover layer 109, the step includes: forming a filler material layer in the first trench 108 to obtain the first filler layer 110.

[0078] The specific steps may include: depositing an initial material layer on the first trench 108 and the surrounding semiconductor substrate 101, such as... Figure 9 As shown, the initial material layer is then subjected to chemical mechanical polishing (CMP) to obtain the first filling layer 110, as shown. Figure 10 As shown in the figure, the numbers 110 are used to indicate the areas before and after polishing.

[0079] Specifically, the first filling layer 110 can be prepared using one or a combination of ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), and PVD (Physical Vapor Deposition) techniques. Furthermore, the material of the first filling layer 110 can be a transparent material with a refractive index different from that of the semiconductor substrate (such as silicon), which helps prevent crosstalk of optical signals. For example, the material of the first filling layer 110 can be a non-metallic material, such as silicon oxide, aluminum oxide, or silicon nitride.

[0080] Specifically, the first filler layer 110 completely or partially fills the first trench 108 on the back side, so that the entire surface of the first trench 108 on the back side is covered with the material of the first filler layer. The portion of the first filler layer on the silicon surface can be planarized by CMP process, so that the remaining material of the first filler layer on the silicon surface is planarized.

[0081] Next, as Figure 11As shown, step S4 is performed: a second trench 111 is prepared in the first filling layer 110. The second trench 111 corresponds to the first trench 108 and extends from the second surface 101c of the semiconductor substrate 101 to the corresponding first trench 108 for subsequent preparation of the second filling layer.

[0082] Specifically, in this step, the fabrication of the second trench 111 on the back side can be achieved by first patterning the second trench 111 on the back side using a photolithography process, and then using an etching process to fabricate the trench structure in the area of ​​the second trench on the back side defined by the photolithography process.

[0083] As an example, the depth of the second trench 111 is greater than 0.1 μm and less than the depth of the first trench 108. For example, the depth of the second trench 111 can be set to 0.2 μm, 0.3 μm, 0.4 μm, etc.

[0084] Finally, as Figures 12-23 As shown, step S5 is performed: a second filling layer is prepared in the second trench 111, wherein: the second filling layer includes a first structural layer and a second structural layer, the first structural layer fills the second trench and covers the surface of the first filling layer 110 exposed in the second trench to form a signal matching modulation structure, and the second structural layer is located on the second surface 101c of the semiconductor substrate 101 to form a crosstalk improvement structure.

[0085] Please see Figure 12-17 As shown, in one implementation, the step of preparing the second filling layer includes:

[0086] First, a second filling material layer 112 is formed on the inner wall of the second trench 108 and the surface of the surrounding first filling layer 110, such as... Figure 12 As shown; in this step, the preparation of the second filling material layer 112 can be carried out by one or more of the following techniques: ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition).

[0087] The second filling layer is made of a light-absorbing material (a material with low transmittance of visible light), such as a metallic material like tungsten, aluminum, or copper. The second filling layer can completely or partially fill the second trench 108, and the entire surface of the second trench 108 is covered by the first filling layer.

[0088] Next, the second filling material layer 112 is etched to obtain the second filling layer, wherein:

[0089] In one example, such as Figure 13As shown, the second filling layer includes a first structure 113 and a second structure 114 in contact with each other, and a first modified structure group is formed based on the first structure and the second structure; wherein, in this example, the first structure 113 constitutes the first structural layer and the second structure 114 constitutes the second structural layer.

[0090] In another example, such as Figure 14 As shown, the second filling layer includes a first structure 113 and a second structure 114 in contact with each other, and the second filling layer also includes a third structure 115 located on the first filling layer. Based on the third structure 115 at this location, a second modified structure group is also formed, such as... Figure 14 As shown in the square dashed box, the first modified structure group is as follows: Figure 14 The elliptical dashed box is shown in the figure. In this example, the first structure 113 constitutes the first structural layer, and the second structure 114 and the third structure 115 constitute the second structural layer.

[0091] The first structure 13 and the second structure 14, which are in contact, are formed in the semiconductor substrate and extend into the material layer above the semiconductor substrate. This effectively reduces the mutual interference between signals. The first modified structure group can perform matched modulation to improve the inconsistency of signal interference between pixels and obtain uniform image information. In addition, the second modified structure group, formed on the semiconductor substrate, can serve as a grid structure above to prevent incident light crosstalk, thereby improving crosstalk. Furthermore, the first and second modified structure groups can be fabricated using the same process, simplifying the process and saving costs.

[0092] As an example, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench 108. When the second modified structure group is present, see [reference needed]. Figure 14 As shown, the number of combinations of the two corresponds to the first groove, that is, each first groove is provided with a first modified structure group or a second modified structure group.

[0093] Please see Figure 15 As shown, in one example, in the first modified structure group, the second filling layer includes the first structure 113 and the second structure 114 in contact with each other, and the width of the second structure 114 is greater than the width of the first structure 113. In this example, the second structure with the larger width is still indicated by the reference numeral 114.

[0094] In another example, the second filling layer also includes a third structure 115 located on the first filling layer. In this example, the width of the third structure 115 can be the same as the width of the first structure 113, such as... Figure 15 As shown; of course, in other further examples, the width of the third structure 115 can also be designed to be consistent with the width of the second structure 114, such as the third structure 115 and the second structure 114 having the same width, such as... Figure 16 As shown.

[0095] Please see Figure 16 As shown, as an example, at least the second structure 114 has an extension extending toward the center of the pixel array, and the widths of the extensions at different locations from the center of the pixel array may be the same or different. When the third structure 115 is present, the third structure may also have an extension extending toward the center of the pixel array.

[0096] Specifically, the extension refers to the area on the side facing the center of the pixel array where the second structure 114 extends beyond the first structure 113, such as... Figure 16 As shown in the elliptical dashed box, for ease of understanding, the width of the extension can be considered as the distance between the edge of the second structure 114 and the center line of the first groove on the side facing the center of the pixel array. Furthermore, the third structure 115 also has a corresponding extension, so that the second structure 114 and the third structure 115 constitute a structural group with extensions. They are designed as a whole. In this structural group, the widths of the extensions at different locations from the center of the pixel array may be the same or different. When the widths are different, the width of the extension at the corresponding position can be adjusted based on the principal ray angle CRA.

[0097] Please see Figure 12 and 18 As shown in Figure 22, in another implementation, the preparation of the second filling layer includes:

[0098] First, a second filling material 112 is formed on the inner wall of the second trench 111 and the surface of the surrounding first filling layer 110, such as... Figure 12 As shown, the preparation and structure of the second filler material 112 are described above.

[0099] Next, the second filler layer and the first filler layer are etched to obtain the first structure 121, such as... Figure 18 As shown, in this example, the second filling layer material layer on the surface can be etched away by a direct etching process (without photolithography). Since part of the second filling layer material is located in the second trench, the surface etching process will cause part of the second filling material layer to remain in the second filling layer to form the first structure 121.

[0100] Next, an intermediate spacer layer 122 is formed on the etched surface of the structure, such as... Figure 19As shown, the material of the intermediate spacer layer 122 can be the same as the material of the first filling layer 110. In this step, it is equivalent to preparing the first filling layer again. The thin film layer can be prepared by one or more of the following techniques: ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition). In addition, the intermediate spacer layer 122 can be further polished on the silicon surface by CMP (chemical mechanical polishing) process, so that the intermediate spacer layer material residue on the silicon surface is planarized.

[0101] Continuing, a third filling material layer 123 is formed on the surface of the intermediate spacer layer 122, such as... Figure 20 As shown; wherein, the material of the third filler layer 123 is the same as the material of the second filler layer 112. In this step, it is equivalent to performing a second filler layer. The thin film layer can be prepared by one or more of the following techniques: ALD (atomic layer deposition), CVD (chemical vapor deposition), and PVD (physical vapor deposition).

[0102] Finally, the third filler material 123 is etched to obtain the second structural layer 124, wherein:

[0103] Please see Figure 21 As shown, in one example, the second filling layer includes a first structure 121 and a second structure 124 corresponding to the intermediate spacer layer 122, and a third modified structure group is formed based on the first structure 122 and the second structure 124. (See also: [link to third modified structure group]). Figure 21 The elliptical dashed box in the figure is shown; in this example, the first structure 121 constitutes the first structural layer, and the second structure 124 constitutes the second structural layer.

[0104] In another example, see [link to example]. Figure 21 As shown, the second filling layer includes corresponding first structure 121 and second structure 124, and a third modified structure group is formed based on the first structure 121 and the second structure 124. The second filling layer also includes a third structural layer 125 located on the intermediate spacer layer 122, and a fourth modified structure group is formed based on the third structure 125. The third modified structure group is as follows: Figure 21 As shown in the elliptical dashed box, the fourth modified structure group is as follows: Figure 21 The square dashed box in the figure is shown. In this example, the first structure 121 constitutes the first structural layer, and the second structure 124 and the third structure 125 constitute the second structural layer.

[0105] As an example, the second filling layer includes corresponding first structure 121 and second structure 124, and the width of the second structure 124 is greater than the width of the first structure 121; furthermore, the second structure 124 may also be provided with an extension; in addition, when a third structure 125 is included, the second structure 124 and the third structure 125 can be designed as a structural group as a whole. As an example, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench 108. Similar structural descriptions in this embodiment can be found in the above implementation details and will not be repeated here.

[0106] Please see Figure 22 As shown, as an example, at least the second structure 124 has an offset distance d relative to the corresponding first groove, and the offset distance d at different positions from the center of the pixel array may be the same or different. When a third structure 125 is present, the third structure 125 may also have an offset distance d relative to the first groove. The second structure 124 and the third structure 125 can constitute a structure group with an offset distance d, designed as a whole. In this structure group, the widths of the offset distances d at different positions from the center of the pixel array may be the same or different. When the widths are different, they can be adjusted based on the principal ray angle CRA.

[0107] As an example, the depth of the first trench 108 is greater than 0.5 μm; the thickness of the semiconductor substrate 101 is between 1 μm and 15 μm; and the depth of the second trench 111 is greater than 0.1 μm and less than the depth of the first trench.

[0108] As an example, the number of second trenches 111 is less than the number of first trenches 108.

[0109] Specifically, in this example, a matched modulation structure can be formed based on the second trench 111, and a crosstalk improvement structure can be obtained based on the first trench 108. The design of this application can be flexibly configured.

[0110] As an example, the first filling layer 110 includes a light-transmitting material layer and has a different refractive index than the semiconductor substrate 101, and the second filling layer (such as including the first structure, the second structure and the third structure) includes a light-absorbing material layer.

[0111] As an example, the position of the second trench 111 is determined based on simulation.

[0112] Specifically, the second trench 111 can be set at the position where the simulation results show that the isolation strength needs to be enhanced. The pixels that receive inconsistent crosstalk can be obtained through simulation, and then a second communication can be prepared at the corresponding position. Matching modulation can be achieved through the second filling layer filled in the second trench to improve the uniformity of the interference.

[0113] Additionally, please see Figure 17 and Figure 23 As shown, after forming the second filling layer, the process also includes the steps of fabricating a color filter and microlens for the image sensor, both of which can be achieved using existing CIS processes and structures.

[0114] Please see Figures 24 to 27 As shown, as an example, the semiconductor substrate 101 includes a plurality of pixel blocks arranged in an array, wherein each pixel block is arranged periodically in a Bayer array and each pixel block corresponds to a color filter of the same color, and each pixel block has at least a first sub-pixel and a second sub-pixel with different environments.

[0115] Specifically, with Figure 24 Taking a 4x4 arrangement as an example, sub-pixels B1-4 and B4-4 are the first and second sub-pixels with different environments. Both sub-pixels B1-4 and B4-4 are blue, but their physical structures differ. Specifically, B1-4 is surrounded by blue material, while B4-4 is surrounded by blue, green (or yellow), and some red material. When light shines on the sensor surface, in addition to the light signals directly received by B1-4 and B4-4 themselves (assuming the amount of this light signal is the same), B1-4 will mainly receive crosstalk signals from B1-1, B1-2, B2-1, B2-3, B4-1, B3-2, B3-1, and B1-3, while B4-4 will mainly receive crosstalk signals from B4-1, B4-2, G3-1, G3-3, R1-1, G2-2, and G2-1. The crosstalk signal of B4-3 can be considered as follows: the physical environment of the same color is the same, so the amount of crosstalk signal generated is also the same. However, compared with B1-4, since G3-1, G3-3, R1-1, G2-2, and G2-1 are not blue, the main source of crosstalk in B4-4 is the signal of the four green (or yellow) colors (G3-1, G3-3, G2-2, and G2-1). Green (or yellow) colors have higher sensitivity and contribute more crosstalk signal, thus causing a difference in the signal amount between B1-4 and B4-4, affecting the imaging effect. That is, the 4*4 arrangement will cause the physical environment around the same color to be different. This difference in physical environment will cause the signal crosstalk of the same color at different positions to be different, which will be reflected in the image as color noise, thus affecting the imaging effect.

[0116] Specifically, the periodic arrangement of the Bayer array can be RGGB, RYYB, or RGBW, RGBIR, etc., which are color arrangements based on a pixel block to obtain the information of the corresponding pixel point. That is, it is similar to the periodic structure of the traditional Bayer array for obtaining image signal information.

[0117] As an example, such as Figure 24As shown, the first trench 108 is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, wherein the second trench 111 is formed between adjacent pixel blocks and also between adjacent pixel units, corresponding to the light-gathering center of the pixel unit.

[0118] Specifically, based on the example design, a second trench and a corresponding second filling layer are arranged around sub-pixels in different environments, i.e., including a first modified structure group or a third modified structure group. This facilitates matching adjustments. For example, in the example above, it can reduce the amount of crosstalk signal from green (or yellow) color, thereby improving the non-uniformity of the sub-pixel affected by surrounding sub-pixels and improving image quality. Furthermore, in this example, selecting the configuration position of the second trench corresponding to the center of the microlens is beneficial for optimizing near-light performance.

[0119] Furthermore, in this example, one pixel block corresponds to four pixel units, one pixel unit has four sub-pixels, a first groove is formed between each sub-pixel, and a second groove is formed between pixel units. Furthermore, one microlens is set to correspond to one pixel unit.

[0120] In another example, such as Figure 25 As shown, the first trench 108 is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, and the second trench 111 is formed between adjacent pixel blocks.

[0121] Furthermore, in this example, one pixel block corresponds to four pixel units, one pixel unit has four sub-pixels, a first groove is formed between each sub-pixel, and a second groove is formed between pixel blocks. Furthermore, one microlens is set to correspond to one pixel unit.

[0122] Please see Figures 24 to 27 As shown, as an example, each pixel block includes multiple pixel units to obtain focus information of different phases based on at least one pixel unit.

[0123] As an example, each pixel block includes four pixel units, and each pixel unit includes four sub-pixels, wherein each pixel unit corresponds one-to-one with a microlens to form phase focusing information with the corresponding microlens.

[0124] Specifically, phase information of different phases can be obtained from different sub-pixels under the same microlens, and phase focusing can be achieved by calculating based on this phase information. For example, the signals of the two left sub-pixels in a pixel unit under a microlens are combined to obtain the left phase information, and the signals of the two right sub-pixels are combined to obtain the right phase information. Phase focusing can be achieved based on the left and right phase information. Similarly, the upper and lower phase information can be obtained from the sub-pixels under a microlens. Based on the design of this example, full-pixel phase focusing of the entire pixel array can be achieved, improving focusing accuracy.

[0125] In practice, the signals of sub-pixels within a single pixel unit or pixel block can be merged and read to obtain the merged information, thereby improving the readout frame rate. Alternatively, the information of each sub-pixel in the pixel array can be read out separately to create an image based on the information of each sub-pixel, thus improving the resolution.

[0126] like Figure 26 and Figure 27 As shown in the figure, as an example, the pixel unit includes four photoelectric conversion doped regions (corresponding to PD1 to PD4) and four transfer control gates (corresponding to Tx1 to Tx4) corresponding to the photoelectric conversion doped regions. Figure 26 Displayed as a pixel circuit diagram Figure 27 For the corresponding map structure, where,

[0127] The transmission control gates are arranged facing each other to form a central opening area, and the pixel unit also includes:

[0128] The output transistor SF is located at the center of the central opening region;

[0129] The floating diffusion region includes a first floating diffusion node FD1 and a second floating diffusion node FD2 located on both sides of the output transistor SF and connected to the corresponding transmission control gates TX1 to TX4; and,

[0130] The device gate is connected to at least one floating diffusion node; wherein, the device gate can be the gate of other transistors in the pixel circuit, such as the gate of the reset transistor RST. In this example, it is connected to the first floating diffusion point FD1. Of course, it can also be the gate of the gain control transistor DCG, depending on the actual setting.

[0131] Specifically, the second trench 111 is disposed in the first trench surrounding the pixel unit, as shown by the square dashed box in the figure. That is, the first modified structure group or the third modified structure group is disposed around the pixel unit. In this example, the center of the second trench is configured to correspond to the center of each photoelectric conversion doped region in the pixel unit, so that the crosstalk between adjacent photoelectric conversion doped regions is effectively improved, thereby effectively improving the influence between pixels at the corresponding positions, which is beneficial for mismatched modulation and can also improve pixel sensitivity.

[0132] Example 2:

[0133] Please see Figures 13 to 17 and Figures 21 to 27 As shown, this application also provides an image sensor. The image sensor in this embodiment is prepared using the image sensor preparation method described in Embodiment 1. The relevant structure and corresponding features can be found in the description of the preparation method, and will not be repeated here. Of course, in other embodiments, it can also be obtained based on other preparation methods, wherein the image sensor includes:

[0134] Semiconductor substrate 101, the semiconductor substrate having a first surface 101a and a second surface 101c opposite to each other;

[0135] The first trench 108 extends from the second surface 101c of the semiconductor substrate into the semiconductor substrate 101;

[0136] A first filling layer 110 is filled in the first trench 108, and the first filling layer 110 also extends to cover the semiconductor substrate 101 surrounding the first trench 108.

[0137] The second trench 111 is located in the first filling layer 110, and the second trench 111 extends from the second surface 101c of the semiconductor substrate 101 to the corresponding first trench 108.

[0138] The second filling layer is located at least in the second trench 111, wherein:

[0139] The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench 111 and covers the surface of the first filling layer 110 exposed by the second trench 111 to form a signal matching modulation structure. The second structural layer is located on the second surface 101c of the semiconductor substrate 101 to form a crosstalk improvement structure.

[0140] As an example, the image sensor also includes a surface cover layer 109 located on the surface of the semiconductor substrate 101 on and around the inner wall of the first trench 108, and a first fill layer 110 formed on the surface cover layer 109 and forming a stacked barrier structure with the surface cover layer 109.

[0141] As an example, the second filling layer includes a first structural layer 113 and a second structural layer 114 in contact with each other, the first structure 113 and the second structure 114 in contact with each other constituting a first modified structure group. Alternatively, the second filling layer also includes a third structure 115 located on the first filling layer 110, the third structure 115 located on the first filling layer 110 also constituting a second modified structure group.

[0142] As an example, the image sensor also includes an intermediate spacer layer 122 located on the semiconductor substrate 101, and a second filling layer includes a first structure 121 and a second structure 124 corresponding to the intermediate spacer layer, and a third modified structure group is formed based on the first structure 121 and the second structure 124. Alternatively, the second filling layer also includes a third structure 125 located on the intermediate spacer layer 122, and a fourth modified structure group is formed based on the third structure layer 125.

[0143] As an example, the second filling layer includes a first structure 113 and a second structure 114 in contact with each other, wherein: in the first modified structure group, the width of the second structure layer is greater than the width of the first structure layer; and / or, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench; and / or, at least each second structure has an extension extending toward the center of the pixel array, and the widths of the extensions at different locations from the center of the pixel array are the same or different.

[0144] As an example, the second filling layer includes corresponding first structure 121 and second structure 124, wherein: in the third modified structure group, the width of the second structure layer is greater than the width of the first structure layer; and / or, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench; and / or, at least the second structure has an offset distance relative to the corresponding first trench, and the offset distance from different positions of the pixel array center is the same or different.

[0145] As an example, the semiconductor substrate includes a plurality of pixel blocks arranged in an array, each pixel block being arranged in a Bayer base structure, each pixel block corresponding to the same color filter and having at least a first sub-pixel and a second sub-pixel with different environments.

[0146] As an example, the semiconductor substrate includes a plurality of pixel blocks arranged in an array, the pixel blocks being arranged in a Bayer array, and the pixel blocks including a plurality of pixel units to obtain phase focusing information at least based on the pixel units.

[0147] As an example, each pixel block includes four pixel units, and each pixel unit includes four sub-pixels, wherein each pixel unit corresponds one-to-one with a microlens to form phase focusing information with the corresponding microlens.

[0148] As an example, the first trench is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, and the second trench is formed between adjacent pixel blocks, such as... Figure 25 As shown; or, a second trench may also be formed between adjacent pixel units to correspond to the light-gathering center of the pixel unit, such as... Figure 24 As shown.

[0149] like Figure 26 and Figure 27 As shown, as an example, the pixel unit includes four photoelectric conversion doped regions and four transfer control gates corresponding to the photoelectric conversion doped regions. The transfer control gates are arranged facing each other to form a central opening region. The pixel unit also includes:

[0150] The output transistor is located at the center of the central opening region;

[0151] The floating diffusion region includes a first floating diffusion node and a second floating diffusion node located on both sides of the output transistor and connected to the corresponding transmission control gates; and,

[0152] The device gate is connected to at least one floating diffusion node; wherein:

[0153] The second trench is correspondingly disposed in the first trench surrounding the pixel unit.

[0154] Example 3:

[0155] The present invention also provides an electronic device, including an image sensor as described in any of the above embodiments. The electronic device can be a security monitoring device, an in-vehicle electronics device, a mobile phone camera, a machine vision device, etc. The image sensor based on the present invention can acquire high-quality image information and can be used in infrared utilization devices.

[0156] In summary, the image sensor and its fabrication method, as well as the electronic device of this application, first form a first trench and a first filling layer during the fabrication process. A second trench is then fabricated within the first filling layer. Based on the second trench, a second filling layer with a first structural layer and a second structural layer is formed. Signal matching modulation structures and crosstalk improvement structures can be formed based on the second filling layer. Furthermore, the design of the second filling layer can improve crosstalk while optimizing the matching differences between different pixels in the pixel array, thereby improving image quality. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. All equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an image sensor, characterized in that, The preparation method includes: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces; A first trench is formed in the semiconductor substrate from the second surface of the semiconductor substrate; A first filling layer is prepared in the first trench, the first filling layer fills the first trench and extends to cover the semiconductor substrate surrounding the first trench; A second trench is formed in the first filling layer, the second trench corresponding to the first trench and extending from the second surface of the semiconductor substrate into the corresponding first trench; A second filling layer is prepared in the second trench, wherein: The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on a second surface of the semiconductor substrate to form a crosstalk improvement structure.

2. The method for fabricating an image sensor as described in claim 1, characterized in that, Before preparing the first filling layer in the first trench, the method further includes the following steps: A surface capping layer is formed on the inner wall of the first trench and the surface of the semiconductor substrate, and a first filling layer is formed on the surface capping layer and forms a stacked barrier structure with the surface capping layer.

3. The method for fabricating an image sensor as described in claim 2, characterized in that, The surface coating layer includes at least one of an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, and a tantalum oxide layer; and / or, the thickness of a single surface coating layer is between 1 and 200 nm; and / or, the number of surface coating layers is at least one; and / or, the surface coating layer is at least one of an oxide layer and a nitride layer.

4. The method for fabricating an image sensor as described in claim 1, characterized in that, The step of preparing the second filling layer in the second trench includes: A second filling material is formed on the inner wall of the second trench and the surface of the first filling layer around it; The second filler layer is obtained by etching the second filler material layer, wherein: The second filling layer includes a first structure and a second structure in contact, wherein the first structure is located in the second trench and forms a first modified structure group based on the first structure and the second structure, or... The second filling layer further includes a third structure located on a second surface of the semiconductor substrate, and a second modified structure group different from the first modified structure group is formed based on the third structure.

5. The method for fabricating an image sensor as described in claim 4, characterized in that, In the first modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench; and / or, the second structure or the second structure and the third structure have an extension extending toward the center of the pixel array, and the width of the extension at different positions from the center of the pixel array is the same or different.

6. The method for fabricating an image sensor as described in claim 1, characterized in that, The step of preparing the second filling layer in the second trench includes: A second filling material is formed on the inner wall of the second trench and the surface of the first filling layer around it; The second filler material layer and the first filler layer are etched to obtain the first structural layer; An intermediate spacer layer is formed on the etched surface of the structure. A third filler material is formed on the surface of the intermediate spacer layer; The third filler material is etched to obtain the second structural layer, wherein: The second filling layer includes corresponding first and second structures, wherein the first structure is located in the second trench and forms a third modified structure group based on the first and second structures, or, The second filling layer also includes a third structure located on the intermediate spacer layer, and a fourth modified structure group, different from the third modified structure group, is formed based on the third structure.

7. The method for fabricating an image sensor as described in claim 6, characterized in that, In the third modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the third modified structure group and the fourth modified structure group corresponds one-to-one with the first groove; And / or, at least the second structure has an offset distance relative to the corresponding first trench, the offset distance being the same or different at different positions from the center of the pixel array.

8. The method for fabricating an image sensor according to any one of claims 1-7, characterized in that, The depth of the first trench is greater than 0.5 μm and less than or equal to the thickness of the semiconductor substrate; and / or, the thickness of the semiconductor substrate is between 1 μm and 15 μm; and / or, the depth of the second trench is greater than 0.1 μm and less than the depth of the first trench; and / or, the number of the second trenches is less than the number of the first trenches; and / or, the first filling layer includes a light-transmitting material layer and has a different refractive index from the surrounding semiconductor substrate, and the second filling layer includes a light-absorbing material layer; and / or, the positions of the second trenches are arranged based on simulation.

9. An image sensor, characterized in that, The image sensor includes: A semiconductor substrate having opposing first and second surfaces; A first trench extends from a second surface of the semiconductor substrate into the semiconductor substrate; The first filling layer fills at least the first trench; The second trench is located in the first filling layer, and the second trench extends from the second surface of the semiconductor substrate to the corresponding first trench; A second filling layer, located at least within the second trench, wherein: The second filling layer includes a first structural layer and a second structural layer. The first structural layer fills the second trench and covers the surface of the first filling layer exposed by the second trench to form a signal matching modulation structure. The second structural layer is located on the second surface of the semiconductor substrate to form a crosstalk improvement structure.

10. The image sensor as claimed in claim 9, characterized in that, The image sensor also includes a surface cover layer located on the inner wall of the first trench and the surrounding surface of the semiconductor substrate.

11. The image sensor as claimed in claim 9, characterized in that, The second filling layer includes a first structure and a second structure in contact, the first structure being located in the second trench and forming a first modified structure group based on the first and second structures; or, the second filling layer further includes a third structure located on a second surface of the semiconductor substrate, and forming a second modified structure group different from the first modified structure group based on the third structure; or, The image sensor includes an intermediate spacer layer located between the first structural layer and the second structural layer. The second filling layer includes corresponding first and second structures. The first structure is located in a second trench and forms a third modified structure group based on the first and second structures. Alternatively, the second filling layer also includes a third structure located on the intermediate spacer layer, and forms a fourth modified structure group different from the third modified structure group based on the third structure.

12. The image sensor as claimed in claim 11, characterized in that, When the second filling layer comprises the first and second structures in contact with each other, wherein: In the first modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the first modified structure group and the second modified structure group corresponds one-to-one with the first trench; and / or, at least the second structure has an extension extending toward the center of the pixel array, and the width of the extension at different positions from the center of the pixel array may be the same or different; or... When the second filling layer includes the corresponding first and second structures, wherein: In the third modified structure group, the width of the second structure is greater than the width of the first structure; and / or, the combination of the third modified structure group and the fourth modified structure group corresponds one-to-one with the first trench; and / or, at least the second structure has an offset distance relative to the corresponding first trench, and the offset distance is the same or different at different positions from the center of the pixel array.

13. The image sensor as described in any one of claims 9-12, characterized in that, The semiconductor substrate includes a plurality of pixel blocks arranged in an array, each pixel block being arranged in a Bayer array, each pixel block corresponding to the same color filter and having at least a first sub-pixel and a second sub-pixel with different environments.

14. The image sensor as claimed in claim 13, characterized in that, The pixel block includes multiple pixel units to obtain different phase focusing information based on at least each pixel unit, wherein each pixel unit corresponds one-to-one with a microlens to form the phase focusing information corresponding to the microlens.

15. The image sensor as claimed in claim 14, characterized in that, Each pixel block includes four pixel units, each pixel unit includes four sub-pixels, and each sub-pixel includes a photoelectric conversion doped region and a transmission control gate corresponding to the photoelectric conversion doped region. The transmission control gates are arranged facing each other to form a central opening region. The pixel unit further includes: The output transistor is located at the center of the central opening region; The floating diffusion region includes a first floating diffusion node and a second floating diffusion node located on both sides of the output transistor and connected to the corresponding transmission control gate; and, The device gate is connected to at least one floating diffusion node; The second groove is disposed in the first groove surrounding the pixel unit.

16. The image sensor as claimed in claim 13, characterized in that, The first trench is formed between adjacent pixel blocks, adjacent pixel units, and adjacent sub-pixels, wherein the second trench is formed between adjacent pixel blocks, or the second trench is also formed between adjacent pixel units to correspond to the light-gathering center of the pixel unit.

17. An electronic device, characterized in that, The electronic device includes an image sensor as described in any one of claims 9-16.

Images