A method and apparatus for multi-channel data binding and clock compensation based on soft logic

Abstract

This disclosure relates to the field of high-speed serial communication technology, and discloses a method and apparatus for multi-channel data binding and clock compensation based on soft logic. By dynamically configuring a corresponding number of independent buffer units according to the number of transmission channels, and using a recovery clock as the write clock and a unified synchronization clock as the read clock, the output data of each buffer unit is merged into a centralized buffer module. This allows the buffer configuration to automatically match the actual number of access channels, eliminating clock phase deviations between channels and avoiding configuration mismatch problems when the fixed-number buffer scheme expands the channel scale. When a binding code is detected on each transmission channel, the data reading of the corresponding buffer unit is paused and locked at the binding code. Reading is resumed uniformly after all channels have completed locking. This achieves decoupling of multi-channel binding code detection and frame alignment in timing, enabling the soft logic to be compatible with short-interval binding code processing and solving the problems of missed detection and synchronization timeout caused by the fixed processing cycle of native hardware.

Description

Technical Field

[0001] This disclosure relates to the field of high-speed serial communication technology, specifically to a method and apparatus for multi-channel data binding and clock compensation based on soft logic. Background Technology

[0002] In high-speed serial communication systems, multi-channel parallel transmission architecture is the mainstream solution for achieving high-bandwidth data interaction, among which channel bonding and clock compensation are the core mechanisms to ensure synchronous transmission of multi-channel data.

[0003] However, the channel binding logic of the native hardware in related technologies only supports fixed-interval binding code processing. When the upper-layer protocol adopts short-interval or random-interval binding codes, the hardware may experience missed detections or synchronization timeouts due to the fixed processing clock, resulting in channel binding failure. At the same time, existing clock compensation schemes rely on a fixed number of cache units and static compensation thresholds. They cannot adaptively adjust the cache configuration and compensation strategy with the dynamic changes in the number of channels, and they also lack the ability to collaboratively perceive clock deviations of multiple channels, which significantly increases the risk of cache overflow and data loss when the channel scale expands.

[0004] Therefore, there is an urgent need for a software logic method that can be compatible with short-interval binding codes, dynamically adjust the cache configuration according to the number of channels, and support multi-channel clock collaborative compensation, so as to break through the functional limitations of native hardware and achieve reliable binding and accurate clock compensation for multi-channel data transmission. Summary of the Invention

[0005] In view of this, this disclosure provides a method and apparatus for multi-channel data binding and clock compensation based on soft logic, in order to solve the problem of achieving a soft logic method that is compatible with short-interval binding codes, dynamically adjusts the buffer configuration according to the number of channels, and supports multi-channel clock collaborative compensation, thereby overcoming the functional limitations of native hardware and realizing reliable binding and accurate clock compensation for multi-channel data transmission.

[0006] On the one hand, this disclosure provides a multi-channel data binding and clock compensation method based on soft logic, the method including: The number of independent buffer units is dynamically configured according to the number of transmission channels. The recovery clock of each transmission channel is used as the write clock and the unified synchronization clock is used as the read clock. The output data of each buffer unit is merged into a centralized buffer module to eliminate the clock phase deviation between each transmission channel. Data is read from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, the data reading of that transmission channel is paused and locked at the binding code. After all transmission channels are locked at the binding code, the data reading of each transmission channel is resumed in a unified manner to achieve multi-channel data frame alignment and complete channel binding. The system monitors the data volume of the centralized cache module. When the data volume is lower than the preset lower threshold, clock compensation codes are inserted; when the data volume is higher than the preset upper threshold, clock compensation codes are deleted. The lower and upper thresholds are dynamically adjusted according to the number of transmission channels.

[0007] On the other hand, this disclosure also provides a multi-channel data binding and clock compensation device based on soft logic, the device comprising: The cache configuration module is used to dynamically configure the corresponding number of independent cache units according to the number of transmission channels. It uses the recovery clock of each transmission channel as the write clock and the unified synchronization clock as the read clock to merge the output data of each cache unit into a centralized cache module, thereby eliminating the clock phase deviation between each transmission channel. The binding detection module is used to read data from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, the data reading of that transmission channel is paused and locked at the binding code. After all transmission channels are locked at the binding code, the data reading of each transmission channel is resumed in a unified manner to achieve multi-channel data frame alignment and complete channel binding. The clock compensation module is used to monitor the data volume of the centralized cache module. When the data volume is lower than the preset lower threshold, a clock compensation code is inserted; when the data volume is higher than the preset upper threshold, the clock compensation code is deleted. The lower and upper thresholds are dynamically adjusted according to the number of transmission channels.

[0008] On the other hand, this disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described soft logic-based multichannel data binding and clock compensation methods when executing the computer program.

[0009] On the other hand, this disclosure also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described soft logic-based multichannel data binding and clock compensation methods.

[0010] On the other hand, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described soft logic-based multichannel data binding and clock compensation methods.

[0011] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, firstly, by dynamically configuring a corresponding number of independent buffer units according to the number of transmission channels, and using the recovery clock of each channel as the write clock and the unified synchronization clock as the read clock, the output data of each buffer unit is merged into the centralized buffer module, so that the buffer configuration automatically matches the actual number of access channels, eliminating the clock phase deviation between each transmission channel and avoiding the configuration mismatch problem of the fixed number of buffer schemes when the channel scale expands. Secondly, by pausing the data reading of the corresponding buffer unit and locking it at the binding code when the binding code is detected in each transmission channel, and resuming reading uniformly after all channels have completed locking, the timing decoupling of multi-channel binding code detection and frame alignment is realized, so that the soft logic can be compatible with the processing of short-interval binding codes, and the problems of missed detection and synchronization timeout caused by the fixed processing time of the native hardware are solved. Finally, by monitoring the data volume of the centralized cache module in real time and dynamically inserting or deleting clock compensation codes based on the upper and lower watermark thresholds, and by adjusting the upper and lower watermark thresholds synchronously with the number of transmission channels, the compensation strategy is automatically adapted to the channel scale, thus avoiding the risk of cache overflow and data loss caused by static thresholds in multi-channel concurrent scenarios. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating a multi-channel data binding and clock compensation method based on soft logic provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a multi-channel data binding and clock compensation device based on soft logic provided in an embodiment of this disclosure; Figure 3 A schematic diagram of another multi-channel data binding and clock compensation device based on soft logic provided in this disclosure embodiment; Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0014] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0015] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0016] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] Please refer to Figure 1 , Figure 1 A flowchart illustrating a multi-channel data binding and clock compensation method based on soft logic, as provided in this disclosure embodiment, is shown below. Figure 1 As shown, the method may include the following steps: Step S101: Dynamically configure the corresponding number of independent buffer units according to the number of transmission channels, use the recovery clock of each transmission channel as the write clock and the unified synchronization clock as the read clock, and merge the output data of each buffer unit into a centralized buffer module to eliminate the clock phase deviation between each transmission channel.

[0018] In this embodiment, the transmission channel (hereinafter referred to as the channel) can refer to multiple high-speed serial data channels that work in parallel in the system. Each channel operates independently in physical terms, and its recovery clock can be extracted from the received data by its respective clock recovery circuit. Therefore, there is often a phase deviation between the recovery clocks of different channels, which cannot be directly used for the synchronous processing of multi-channel data.

[0019] As a specific implementation, the transmission channel can be a high-speed serial transceiver (GT) channel within a Field Programmable Gate Array (FPGA). The GT channel has a built-in independent clock recovery circuit, whose recovery clock is directly extracted from the received data by the channel's phase-locked loop circuit. Due to the limitations of the GT's native hardware channel bonding logic, when the upper-layer protocol uses short-interval bonding codes, the GT hardware may experience missed detections or synchronization timeouts due to its fixed processing clock, leading to channel bonding failure. This embodiment can implement the above steps using FPGA software logic, compensating for the functional deficiencies of the native GT hardware in short-interval bonding code scenarios without modifying the GT hardware.

[0020] Specifically, the cache unit uses the recovery clock of the corresponding channel as the write clock to write the data of that channel into the cache; and uses the unified synchronization clock as the read clock to read the data from the cache and output it to the next stage.

[0021] By separating the write clock and the read clock, each cache unit independently completes the asynchronous caching of single-channel data, realizing the conversion from the recovery clock domain of each channel to the unified synchronous clock domain.

[0022] Furthermore, the output data of each buffer unit is merged into a centralized buffer module, which uniformly receives synchronization data from all channels. Since each buffer unit uses a unified synchronization clock as its read clock, the multiple data streams merged into the centralized buffer module are all in the same clock domain, thereby eliminating clock phase deviations caused by different recovery clock phases between channels and providing a unified synchronization data basis for subsequent channel bonding and clock compensation.

[0023] It should be noted that the number of cache units is dynamically configured according to the actual number of channels accessed. When the number of channels changes, the system adjusts the number of cache units accordingly to ensure that the cache configuration always matches the channel scale.

[0024] Step S102: Read data from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, pause the data reading of that transmission channel and lock it at the binding code. After all transmission channels are locked at the binding code, resume the data reading of each transmission channel in a unified manner to achieve multi-channel data frame alignment and complete channel binding.

[0025] In this embodiment, the binding code can be a special codeword that appears periodically in each channel's data stream to identify the alignment reference point of each channel's data frame. Since the physical transmission paths and clock phases of each channel are different, the arrival times of the binding codes of each channel at the receiving side differ. Direct merging may result in misalignment of multi-channel data frames.

[0026] Specifically, data is read from the corresponding cache unit of each channel and the binding code is detected in real time. When a binding code appears in the data of a certain channel, the data reading of that channel is paused and the reading position is locked at the binding code. At the same time, the other channels continue to read and detect their respective data until all channels are locked.

[0027] Here, the binding code detection and reading control for each channel are performed independently. Each channel does not need to complete the detection simultaneously; instead, each pauses and waits after detecting a binding code. This decouples the multi-channel binding code detection process from the timing constraints of frame alignment. Once all channels are locked at the binding code, data reading from each channel resumes uniformly. At this point, the data output of all channels begins from the same frame start position after the binding code, achieving precise alignment of multi-channel data frames and completing channel binding.

[0028] Step S103: Monitor the data volume of the centralized cache module. When the data volume is lower than the preset lower threshold, insert the clock compensation code. When the data volume is higher than the preset upper threshold, delete the clock compensation code. The lower threshold and upper threshold are dynamically adjusted according to the number of transmission channels.

[0029] In this embodiment, a slight frequency deviation generally exists between the recovery clock of each channel and the system's local operating clock. This deviation accumulates over time, causing the data volume of the centralized cache module to remain consistently high or low, thereby triggering buffer overflow or empty reads. Clock compensation codes are predefined special codewords. By dynamically inserting or deleting clock compensation codes in the data stream, the output rhythm of effective data can be adjusted, thereby compensating for the frequency deviation between the recovery clock and the local clock and maintaining the data volume of the centralized cache module within a reasonable range.

[0030] Specifically, the data volume of the centralized cache module is monitored in real time and compared with preset lower and upper thresholds: when the data volume is lower than the lower threshold, it indicates that the data consumption rate is continuously higher than the write rate. At this time, clock compensation code is inserted to supplement the data flow and prevent downstream modules from losing data due to empty reads; when the data volume is higher than the upper threshold, it indicates that the data write rate is continuously higher than the consumption rate. At this time, the previously inserted clock compensation code is deleted to smooth the data flow and prevent the centralized cache module from overflowing.

[0031] Furthermore, the upper and lower watermark thresholds are dynamically adjusted based on the number of channels. As the number of channels increases, multiple data streams concurrently flow into the centralized buffer module, leading to greater fluctuations in data volume. Therefore, the range of the upper and lower watermark thresholds needs to be appropriately expanded to maintain the effectiveness of the compensation strategy. Conversely, as the number of channels decreases, the threshold range narrows accordingly to avoid unnecessary clock compensation code insertion. By linking the compensation thresholds to the number of channels, the clock compensation strategy can automatically adapt to changes in channel size.

[0032] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, firstly, by dynamically configuring a corresponding number of independent cache units according to the number of channels, and using the recovery clock of each channel as the write clock and the unified synchronization clock as the read clock, the output data of each cache unit is merged into the centralized cache module. This allows the cache configuration to automatically match the actual number of access channels, eliminating clock phase deviations between channels and avoiding configuration mismatch problems when the fixed number of cache schemes expands the channel scale. Secondly, by pausing the data reading of the corresponding cache unit and locking it at the binding code when a binding code is detected in each channel, and then resuming reading uniformly after all channels have completed locking, the timing decoupling of multi-channel binding code detection and frame alignment is achieved. This enables the soft logic to be compatible with the processing of short-interval binding codes and solves the problems of missed detection and synchronization timeout caused by the fixed processing cycle of native hardware. Finally, by monitoring the data volume of the centralized cache module in real time and dynamically inserting or deleting clock compensation codes according to the upper and lower watermark thresholds, and with the upper and lower watermark thresholds adjusted synchronously with the number of channels, the compensation strategy automatically adapts to the channel scale, avoiding the risk of buffer overflow and data loss caused by static thresholds in multi-channel concurrent scenarios.

[0033] In one possible implementation of step S101 above, the number of independent buffer units is dynamically configured according to the number of transmission channels, including: A number of buffer units, no less than the maximum number of transmission channels, are pre-established. The corresponding number of buffer units are activated sequentially according to the number of access transmission channels, while the remaining buffer units remain dormant. The unified synchronization clock is the recovery clock of the preset reference transmission channel in each transmission channel.

[0034] In this embodiment, considering that the number of channels may change dynamically with system configuration, temporarily creating cache units when a channel is accessed would introduce runtime resource allocation delays and uncertainties, which would be detrimental to the system's real-time response. Therefore, this embodiment adopts a pre-established, on-demand activated cache resource management strategy.

[0035] Specifically, during the initialization phase, the system pre-establishes a corresponding number of cache units based on the maximum number of supported channels. These cache units are configured at the hardware level but are in a dormant state, not participating in data transmission or reception operations, to reduce resource consumption during non-working periods. When a channel is connected, the system sequentially activates a corresponding number of cache units from the established cache units according to the number of currently connected channels. Each cache unit establishes a fixed mapping relationship with its corresponding channel; the remaining inactive cache units remain in a dormant state until a new channel is connected and activated.

[0036] Furthermore, regarding the source of the unified synchronization clock, this embodiment adopts the scheme of using the recovery clock of the preset reference channel in the system as the unified synchronization clock.

[0037] Specifically, the reference transmission channel (which can be simply referred to as the reference channel) is a channel pre-specified during the system configuration phase. The recovery clock of this channel is selected as the unified read clock for all buffer units. Since all channels operate under the same protocol architecture, their nominal recovery clock frequencies are the same. The recovery clock of the reference channel can serve as an effective reference for the read side of each buffer unit, achieving uniformity of the read clock for each buffer unit without introducing an additional external clock source.

[0038] It should be noted that the recovery clock of the reference channel also has a slight frequency deviation relative to the local clock, but this deviation is uniformly handled by the clock compensation mechanism in the subsequent step S103, and does not affect the goal of eliminating the clock phase deviation between channels by uniformly reading the clock in this step.

[0039] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, by pre-establishing a cache unit with no less than the maximum number of channels and activating it sequentially as needed, the overhead of dynamically allocating cache resources at runtime is avoided, enabling the cache configuration to be completed with low latency when the channel is accessed; by using the recovery clock of the reference channel as a unified synchronization clock, the clock on the read side of each cache unit is unified without introducing an additional clock source, providing a reliable clock reference for the multi-channel data aggregation and synchronization of the centralized cache module.

[0040] In one possible implementation of step S102 above, multi-channel data frame alignment and channel binding are achieved, including: Data is read from the cache unit corresponding to each transmission channel, and a preliminary detection of the binding code is performed on each transmission channel. After the preliminary detection is completed, the data is output to the centralized cache module. The centralized cache module compares and verifies the multi-channel binding code of the synchronization data of each transmission channel. After the verification is passed, the channel binding is confirmed to be complete.

[0041] In this embodiment, step S102 describes the overall mechanism of channel binding, which involves pausing data reading of each channel and locking it at the binding code, then resuming uniformly after all channels are locked to achieve frame alignment. Based on this, this embodiment further clarifies the layered implementation of channel binding detection, constructing a dual detection mechanism by setting different levels of binding code processing logic on the cache unit side and the centralized cache module side.

[0042] Specifically, on the cache unit side, that is, in the preliminary detection stage, data is read from the cache unit corresponding to each channel, and the data stream of each channel is compared and detected character by character with the binding code. When the data of a certain channel is consistent with the preset binding code feature value, the reading of the data of the cache unit corresponding to that channel is stopped and the current position is maintained, while the other channels continue their respective detections until all channels have completed the preliminary detection.

[0043] After the initial test is completed, a recovery read command is sent synchronously to all cache units to restore the data output of each channel and merge the data into the centralized cache module.

[0044] Furthermore, on the centralized caching module side, that is, in the comparison and verification stage, the centralized caching module performs multi-channel binding code comparison and verification on the imported channel synchronization data, checks whether the data of each channel is aligned at the binding code, and whether the relative position of the binding codes of each channel meets the expected binding format; after the verification is passed, it is confirmed that the multi-channel data frames have achieved precise alignment and the channel binding is completed.

[0045] Here, the layered design of the preliminary detection and comparison verification mentioned above can have a clear division of responsibilities. That is, the preliminary detection is carried out independently in each channel, which solves the problem of asynchronous arrival time of the binding codes in each channel; the comparison verification is carried out uniformly in the centralized cache module, which solves the problem of whether the binding codes in each channel are truly aligned.

[0046] It is understandable that the two layers in the above layered design work together to enable the soft logic to compensate for the limitations of the fixed hardware processing cycle by using a cache buffer, thereby achieving reliable detection of short-interval binding codes.

[0047] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, by setting up a dual detection mechanism of preliminary detection and comparison verification on the cache unit side and the centralized cache module side respectively, the independent detection of each channel binding code and the centralized verification of multi-channel binding results are decoupled. This enables the soft logic to complete the reliable detection of short-interval binding codes without relying on a fixed processing cycle, effectively reducing the risk of missed detection and false judgment, and shortening the binding response time.

[0048] In one possible implementation of the above embodiments, the method further includes: If the comparison and verification fails, reset all the cache units and centralized cache modules corresponding to the transmission channels, discard the residual data, and re-perform the preliminary test. After the comparison and verification are passed, the binding code is removed from the output data of the centralized cache module, and the synchronization status of the binding code of each transmission channel is continuously monitored. When the binding code is detected to be out of sync, the preliminary test is re-executed.

[0049] In this embodiment, the channel binding process may not be able to be completed successfully on the first attempt. When the channel quality is unstable or the binding code is abnormal, the comparison and verification of the centralized cache module may fail. In this case, a reset and retry mechanism is needed to ensure the final completion of the binding.

[0050] Specifically, when the comparison verification result of the centralized cache module fails, all cache units corresponding to the channels and the centralized cache module can be reset, clearing the data left over from this binding attempt and restoring the system state to the initial state of the binding detection. Here, discarding residual data is to prevent data from the previous failed attempt from interfering with the next binding detection, ensuring that each re-detection is based on a clean initial state.

[0051] After the reset is complete, the preliminary testing process is repeated until the comparison and verification pass, confirming that the channel binding is complete.

[0052] Furthermore, after successful channel binding, the output data can be processed. Here, the binding code is a special codeword used specifically for frame alignment. Its purpose is complete after channel binding; continuing to transmit the binding code to downstream modules would consume effective data bandwidth and potentially interfere with downstream logic. Therefore, after channel binding is complete, the binding code is removed from the output data of the centralized buffer module, and only valid service data is transmitted downstream.

[0053] It should be noted that after the channel binding is completed, the binding code may still become out of sync due to channel fluctuations or external interference during the operation of the transmission link. If this is not addressed, the multi-channel data frames will lose alignment again.

[0054] Therefore, after binding is completed, the synchronization status of the binding codes of each transmission channel is continuously monitored; once the binding codes are not synchronized, the preliminary detection process is immediately re-executed to restore the multi-channel frame alignment status.

[0055] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, the reliable completion of the channel binding process is ensured by resetting and discarding residual data and re-initiating detection when the comparison verification fails; the binding code is removed after successful binding to avoid redundant codewords occupying downstream effective data bandwidth; and the continuous monitoring of the binding code synchronization status and abnormal triggering rebinding ensure the continuous effectiveness of multi-channel frame alignment during link operation.

[0056] In one possible implementation of step S103 above, the waterline threshold is determined according to... Confirmed, the upper water line threshold is set according to... Determined; among them, and For preset coefficients, The number of transmission channels; The method also includes: increasing the insertion frequency of clock compensation codes when the amount of data in the centralized cache module is continuously below the bottom line threshold and its rate of decline exceeds the preset rate threshold; Once the amount of data in the centralized cache module recovers to between the lower and upper thresholds, the default insertion frequency will be restored. The preset baseline buffer occupancy is dynamically calibrated during link idle periods by sending and receiving training codes, and recalibration is triggered when the number of received error codes exceeds a preset threshold.

[0057] In this embodiment, the threshold values ​​of the upper and lower water lines in step S103 are dynamically adjusted according to the number of transmission channels. This embodiment specifies the adjustment rule, establishes a quantitative linkage between the threshold value and the number of channels through a clear calculation relationship, and further improves the clock compensation code insertion frequency adjustment mechanism and the dynamic calibration mechanism of the water line reference value.

[0058] Specifically, the waterline threshold is based on Confirmed, the upper water line threshold is set according to... Determined; among them, and For preset coefficients, The number of transmission channels is set, and the preset baseline cache occupancy is the target data volume of the centralized cache module under ideal working conditions.

[0059] With the number of transmission channels With the increase in data volume, multiple data streams are concurrently written to the centralized cache module, leading to a greater fluctuation in the amount of data per unit time. This is addressed by adjusting the upper limit threshold. Incremental upward movement, lower waterline threshold The incremental shift allows the compensation trigger range to expand synchronously with the channel size, ensuring the effectiveness of the compensation strategy at each scale.

[0060] Furthermore, regarding the insertion frequency of the clock compensation code, this embodiment can employ a multi-level response mechanism. When the data volume of the centralized cache module is lower than the lower threshold, the clock compensation code is inserted according to the default cycle. When the data volume remains below the lower threshold and the rate of decline exceeds the preset rate threshold, it indicates that the frequency deviation between the recovery clock and the local clock has exceeded the default compensation capability. At this time, the insertion frequency of the clock compensation code is increased to accelerate the compensation rhythm and prevent the cache from continuously running out of data. When the data volume rises back to between the lower and upper thresholds, the default insertion frequency is restored to avoid overcompensation causing the data volume to be excessively high.

[0061] Furthermore, the preset baseline buffer occupancy is not a fixed static parameter. Due to changes in ambient temperature causing thermal expansion and contraction of physical transmission lines, the actual transmission delay of each channel shifts with changes in external conditions, and the actual required baseline occupancy also changes accordingly.

[0062] Therefore, the preset baseline buffer occupancy can be dynamically calibrated during link idle periods by sending and receiving training codes, including: The system sends a known training code sequence within the link idle window and recalculates the actual transmission deviation of each channel based on the measurement results of the transmit and receive delays, and updates the preset baseline buffer occupancy. At the same time, when the number of received error codes exceeds the preset threshold, it indicates that the current baseline value is no longer accurate, triggering a recalibration process, so that the upper and lower watermark thresholds are continuously updated according to the measured link status.

[0063] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, by establishing a quantitative linkage relationship between the upper and lower watermark thresholds and the number of transmission channels, the compensation trigger range automatically expands with the channel scale, avoiding compensation failure caused by range mismatch in multi-channel scenarios when the threshold is fixed; by using a multi-level clock compensation code insertion frequency mechanism, differentiated responses to different degrees of deviation are achieved, reducing the occurrence of overcompensation and undercompensation; by dynamically calibrating the preset reference buffer occupancy through training codes, the compensation strategy can be continuously updated with the actual link status, improving the long-term compensation accuracy of the system under environmental change conditions.

[0064] In one possible implementation of the above embodiments, after the channel binding is completed, the method further includes: Real-time monitoring of the operating status of each transmission channel; If a failure is detected in a transmission channel, the buffer unit corresponding to the failure transmission channel is put into a dormant state, and channel binding is re-initiated for the remaining transmission channels.

[0065] In this embodiment, during long-term operation, a multi-channel transmission system may malfunction due to hardware aging, signal integrity deterioration, or external interference, causing one of the transmission channels to fail. If the faulty channel is not isolated, its abnormal data will continue to affect the normal operation of the centralized buffer module and may block the channel binding recovery process, ultimately leading to the interruption of the entire transmission link. Therefore, this embodiment provides a mechanism for single-channel fault isolation and rebinding of remaining channels.

[0066] Specifically, after channel binding is completed, the operating status of each transmission channel is monitored in real time. The monitoring includes, but is not limited to, abnormal characteristics such as the channel's signal lock-in status, continuous bit error rate, and data stream interruption. Once a fault is detected in a transmission channel, the corresponding buffer unit is immediately put into a dormant state, stopping data writing and reading operations, and cutting off the data input of the faulty channel to the centralized buffer module. This limits the impact of the fault to a single channel and prevents it from spreading to other transmission channels.

[0067] After putting the buffer unit of the faulty transmission channel into sleep mode, the channel binding process is restarted with the remaining normally functioning transmission channels as the target. This allows the remaining channels to complete a new round of frame alignment with a smaller number of channels, ensuring that multi-channel data transmission can continue even after the faulty channel is removed.

[0068] The rebinding process for the remaining transmission channels reuses the aforementioned dual detection mechanism, with only the number of channels participating in the binding reduced accordingly, while the rest of the process remains unchanged; the buffer unit of the faulty transmission channel remains dormant and does not participate in the rebinding until the upper-layer system completes the repair of the channel and reconnects.

[0069] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, by continuously detecting the operating status of each transmission channel after the channel binding is completed, the buffer unit of the faulty channel is put into sleep mode in time to isolate the impact of the fault, and the channel binding is re-initiated for the remaining channels, the fault tolerance capability of the entire transmission link is realized without interruption of a single channel failure, thereby improving the reliability of the multi-channel system in long-term operation.

[0070] In one possible implementation of the above embodiments, the method further includes a dynamic switching step between native hardware mode and software logic mode: In the initial training phase of the transmission link composed of various transmission channels, the underlying native hardware logic is used by default for channel binding; Real-time monitoring of the binding status of the native hardware logic. When the interval between receiving the binding code in the transmission channel is less than the minimum synchronization interval of the native hardware logic, causing the verification state machine of the native hardware logic to output a verification failure signal, a switch to soft logic mode is triggered. During the switch to soft logic mode, the existing logic code remains unchanged, the corresponding independent cache unit is activated according to the number of transmission channels, and the centralized cache module is cleared. During the switchover process, only the training data generated during the initial training phase is discarded, while the transmission of normal business communication data is maintained.

[0071] In this embodiment, in the application scenario of this disclosure, the communication system often first attempts to complete channel binding using the underlying native hardware logic, because native hardware logic has lower processing latency and less resource consumption. However, when the upper-layer protocol uses short-interval binding codes, the native hardware logic cannot respond in time due to its fixed processing rhythm. At this time, it is necessary to switch to the soft logic mode provided by this method to take over. Based on this, this embodiment provides a dynamic switching mechanism between the native hardware mode and the soft logic mode.

[0072] During the initial training phase of the transmission link, the underlying native hardware logic can be used by default for channel binding. The native hardware logic is responsible for handling binding code detection and channel alignment operations. At the same time, the binding status of the native hardware logic is monitored in real time to determine whether it can successfully complete the channel binding under the current protocol.

[0073] When the interval between receiving binding codes in the transmission channel is less than the minimum synchronization interval of the native hardware logic, the native hardware logic will miss a detection because it cannot complete the processing between adjacent binding codes. At this time, the verification state machine inside the native hardware logic detects that the verification code does not match the expectation and outputs a verification failure signal. After the system detects this failure signal, it uses it as a trigger condition to start the switching process to soft logic mode.

[0074] During the switching process, the existing logic code remains unchanged, meaning that no modifications or recompilations are required to the deployed logic design. The mode conversion can be completed through configuration-level state switching. The corresponding number of independent cache units are activated according to the number of current transmission channels, and independent cache paths for each channel's data are established. At the same time, a zeroing operation is performed on the centralized cache module to clear any historical data that may have been left over from the native hardware mode, ensuring that the soft logic mode starts from a clean state.

[0075] It should be noted that the mode switch occurs during the initial training phase of the transmission link. During this phase, the sender and receiver exchange training data used to establish communication parameters, rather than normal business communication data.

[0076] Therefore, only the training data generated during the initial training phase is discarded during the switching process, while normal business communication data remains unaffected; when the upper-layer application detects that training has been restarted, it can regard this as a normal link initialization process.

[0077] In the multi-channel data binding and clock compensation method and apparatus based on soft logic in the above embodiments of this disclosure, by defaulting to native hardware logic in the initial training phase and triggering a switch to soft logic mode when the native hardware logic outputs a verification failure signal, an organic combination of efficient utilization of hardware resources and flexible supplementation of soft logic functions is achieved; by maintaining the existing logic code unchanged during the switching method, the intrusive modification of the deployed logic by the mode conversion is avoided; by limiting the switching to the initial training phase and discarding only the training data, the continuity of normal business data transmission is ensured to be unaffected by the switching process.

[0078] In one embodiment, a schematic diagram of the architecture of a multi-channel data binding and clock compensation device based on soft logic is provided, such as... Figure 2As shown, the device includes: a mode detection unit 21, a buffer configuration unit 22, a channel binding module 23, a clock compensation binding module 24, N GT channels 25, N buffer units 26, and a centralized buffer module 27, wherein: The mode detection unit 21 is connected to the cache configuration unit 22 and the channel binding module 23. It is used to monitor the binding status of the underlying native hardware logic in real time during the initial training phase of the transmission link composed of each GT channel 25. When it is detected that the receiving interval of the binding code in the GT channel 25 is less than the minimum synchronization interval of the native hardware logic, causing the verification state machine to output a verification failure signal, a switching command is sent to the cache configuration unit 22 to trigger the switching to the soft logic mode.

[0079] The cache configuration unit 22 is connected to the mode detection unit 21 and N cache units 26 respectively. It is used to respond to the switching command of the mode detection unit 21, activate the corresponding number of cache units 26 in sequence according to the number of currently connected GT channels 25, and keep the remaining cache units 26 in a dormant state. At the same time, it determines the reference transmission channel and uses the recovery clock of the reference transmission channel as the unified synchronization clock of each cache unit 26.

[0080] N GT channels 25 are connected to corresponding cache units 26 respectively. Each GT channel 25 provides its serial data stream and recovery clock to the corresponding cache unit 26. Since the recovery clock of each GT channel 25 is extracted independently by its own clock recovery circuit, there is generally a clock phase deviation between channels.

[0081] N cache units 26 are connected to the corresponding GT channel 25, channel binding module 23 and centralized cache module 27 respectively. Each cache unit 26 uses the recovery clock of the corresponding GT channel 25 as the write clock and the unified synchronous clock as the read clock to complete the asynchronous caching and clock domain conversion of single channel data. Under the control of the channel binding module 23, the output data of the cache unit 26 is uniformly output to the centralized cache module 27 after the initial detection of the binding code is completed.

[0082] The centralized caching module 27 is connected to N caching units 26, the channel binding module 23, and the clock compensation binding module 24. It is used to uniformly receive the synchronization data output by each caching unit 26, eliminate the clock phase deviation between each transmission channel, provide multi-channel synchronization data to the channel binding module 23 to perform comparison verification, and provide real-time data volume information to the clock compensation binding module 24 to perform clock compensation.

[0083] The channel binding module 23 is connected to N buffer units 26 and a centralized buffer module 27. It is used to read data from each buffer unit 26 and perform preliminary detection of the binding code for each transmission channel. When a binding code appears in the output data of any buffer unit 26, the data reading of that buffer unit 26 is paused and locked at the binding code. After all buffer units 26 are locked at the binding code, a recovery reading command is sent to each buffer unit 26 synchronously to restore the data output. Subsequently, the centralized buffer module 27 performs multi-channel binding code comparison and verification on the synchronous data of each transmission channel. If the verification is successful, the channel binding is confirmed to be complete. If the comparison and verification fails, all buffer units 26 and the centralized buffer module 27 are reset, residual data is discarded, and the preliminary detection is re-executed.

[0084] The clock compensation binding module 24 is connected to the centralized cache module 27 and is used to monitor the data volume of the centralized cache module 27 in real time: when the data volume is lower than the preset lower threshold, the clock compensation code is inserted; when the data volume is higher than the preset upper threshold, the clock compensation code is deleted. The lower threshold and upper threshold are dynamically adjusted according to the number of GT channels 25 to adapt to the fluctuation range of the data volume of the centralized cache module 27 under different channel scales.

[0085] In one embodiment, please participate Figure 3 This invention provides a multi-channel data binding and clock compensation device based on soft logic, which corresponds one-to-one with the multi-channel data binding and clock compensation method based on soft logic described in the above embodiments. For example... Figure 3 As shown, the device includes: The cache configuration module 31 is used to dynamically configure the corresponding number of independent cache units according to the number of transmission channels. The recovery clock of each transmission channel is used as the write clock and the unified synchronization clock is used as the read clock. The output data of each cache unit is merged into a centralized cache module to eliminate the clock phase deviation between each transmission channel. The binding detection module 32 is used to read data from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, the data reading of that transmission channel is paused and locked at the binding code. After all transmission channels are locked at the binding code, the data reading of each transmission channel is resumed in a unified manner to realize the alignment of multi-channel data frames and complete the channel binding. The clock compensation module 33 is used to monitor the data volume of the centralized cache module. When the data volume is lower than the preset lower threshold, a clock compensation code is inserted; when the data volume is higher than the preset upper threshold, the clock compensation code is deleted. The lower threshold and the upper threshold are dynamically adjusted according to the number of transmission channels.

[0086] In one embodiment, the cache configuration module 31 is specifically used to pre-establish a cache unit with no less than the maximum number of transmission channels, activate the corresponding number of cache units in sequence according to the number of access transmission channels, and keep the remaining cache units dormant; wherein, the unified synchronization clock is the recovery clock of the preset reference transmission channel in each transmission channel.

[0087] In one embodiment, the binding detection module 32 is specifically used to read data from the cache unit corresponding to each transmission channel, perform preliminary detection of the binding code of each transmission channel, and output data to the centralized cache module after the preliminary detection is completed; the centralized cache module performs multi-channel binding code comparison and verification on the synchronization data of each transmission channel, and confirms that the channel binding is completed after the verification is passed.

[0088] In one embodiment, the binding detection module 32 is also used to reset the cache units and centralized cache modules corresponding to all transmission channels if the comparison verification fails, discard the residual data, and re-perform the preliminary detection. After the comparison and verification are passed, the binding code is removed from the output data of the centralized cache module, and the synchronization status of the binding code of each transmission channel is continuously monitored. When the binding code is detected to be out of sync, the preliminary test is re-executed.

[0089] In one embodiment, the clock compensation module 33 is specifically used for... Determine the waterline threshold, according to Determine the water level threshold; where, and For preset coefficients, The number of transmission channels; when the data volume of the centralized buffer module is continuously lower than the bottom line threshold and its rate of decline exceeds the preset rate threshold, the insertion frequency of the clock compensation code is increased; Once the amount of data in the centralized cache module recovers to between the lower and upper thresholds, the default insertion frequency will be restored. The preset baseline buffer occupancy is dynamically calibrated during link idle periods by sending and receiving training codes, and recalibration is triggered when the number of received error codes exceeds a preset threshold.

[0090] In one embodiment, after the channel binding is completed, the binding detection module 32 is also used to detect the operating status of each transmission channel in real time; if a fault is detected in a certain transmission channel, the cache unit corresponding to the faulty transmission channel is put into a dormant state, and the channel binding is re-initiated for the remaining transmission channels.

[0091] In one embodiment, the device further includes: a mode switching module, configured to dynamically switch between native hardware mode and soft logic mode. In the initial training phase of the transmission link composed of various transmission channels, the underlying native hardware logic is used by default for channel binding; Real-time monitoring of the binding status of the native hardware logic. When the interval between receiving the binding code in the transmission channel is less than the minimum synchronization interval of the native hardware logic, causing the verification state machine of the native hardware logic to output a verification failure signal, a switch to soft logic mode is triggered. During the switch to soft logic mode, the existing logic code remains unchanged, the corresponding independent cache unit is activated according to the number of transmission channels, and the centralized cache module is cleared. During the switchover process, only the training data generated during the initial training phase is discarded, while the transmission of normal business communication data is maintained.

[0092] It should be noted that the multi-channel data binding and clock compensation device based on soft logic provided in the above embodiments is only illustrated by the division of the above program modules when implementing the corresponding multi-channel data binding and clock compensation method based on soft logic. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above system can be divided into different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the corresponding Figure 1 The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0093] This disclosure also provides an electronic device having the above-described features. Figure 2 or Figure 3 The device shown is a multi-channel data binding and clock compensation device based on soft logic.

[0094] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.

[0095] The following is a detailed reference. Figure 4 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present disclosure. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 401, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 402 or a program loaded from memory 408 into random access memory (RAM) 403. RAM 403 also stores various programs and data required for the operation of the electronic device. The processor 401, ROM 402, and RAM 403 are interconnected via bus 404. Input / output (I / O) interface 405 is also connected to bus 404.

[0096] Typically, the following devices can be connected to I / O interface 405: input devices 406 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 407 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 408 including, for example, magnetic tapes, hard disks, etc.; and communication devices 409. Communication device 409 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 4 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0097] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 409, or installed from memory 408, or installed from ROM 402. When the computer program is executed by processor 401, it performs the functions defined in the soft logic-based multichannel data binding and clock compensation method of embodiments of this disclosure.

[0098] Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0099] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the soft logic-based multi-channel data binding and clock compensation method shown in the above embodiments is implemented.

[0100] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0101] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A multi-channel data binding and clock compensation method based on soft logic, characterized in that, The method includes: The number of independent buffer units is dynamically configured according to the number of transmission channels. The recovery clock of each transmission channel is used as the write clock and the unified synchronization clock is used as the read clock. The output data of each buffer unit is merged into a centralized buffer module to eliminate the clock phase deviation between each transmission channel. Data is read from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, the data reading of that transmission channel is paused and locked at the binding code. After all transmission channels are locked at the binding code, the data reading of each transmission channel is resumed in a unified manner to achieve multi-channel data frame alignment and complete channel binding. The data volume of the centralized cache module is monitored. When the data volume is lower than a preset lower threshold, a clock compensation code is inserted. When the data volume is higher than a preset upper threshold, the clock compensation code is deleted. The lower threshold and upper threshold are dynamically adjusted according to the number of transmission channels.

2. The method according to claim 1, characterized in that, The method of dynamically configuring a corresponding number of independent buffer units based on the number of transmission channels includes: A number of buffer units, no less than the maximum number of transmission channels, are pre-established. The corresponding number of buffer units are activated sequentially according to the number of accessed transmission channels, while the remaining buffer units remain dormant. The unified synchronization clock is the recovery clock of the preset reference transmission channel in each transmission channel.

3. The method according to claim 1, characterized in that, The process of aligning multi-channel data frames and completing channel binding includes: Data is read from the cache unit corresponding to each transmission channel, and a preliminary detection of the binding code is performed on each transmission channel. After the preliminary detection is completed, the data is output to the centralized cache module. The centralized cache module compares and verifies the multi-channel binding code of the synchronization data of each transmission channel. After the verification is passed, the channel binding is confirmed to be complete.

4. The method according to claim 3, characterized in that, The method further includes: If the comparison verification fails, reset all the cache units corresponding to the transmission channels and the centralized cache module, discard the residual data, and re-execute the preliminary detection. After the comparison and verification is passed, the binding code is removed from the output data of the centralized cache module, and the synchronization status of the binding codes of each transmission channel is continuously monitored. When the binding codes are detected to be out of sync, the preliminary detection is re-executed.

5. The method according to claim 1, characterized in that, The waterline threshold is based on It is determined that the upper waterline threshold is based on... Determined; among them, and For preset coefficients, The number of transmission channels; The method further includes: when the amount of data in the centralized cache module is continuously lower than the bottom line threshold and its rate of decline exceeds a preset rate threshold, increasing the insertion frequency of the clock compensation code; Once the data volume of the centralized cache module recovers to between the lower threshold and the upper threshold, the default insertion frequency is restored. The preset baseline buffer occupancy is dynamically calibrated during link idle periods by sending and receiving training codes, and recalibration is triggered when the number of received error codes exceeds a preset threshold.

6. The method according to claim 1, characterized in that, After completing the channel binding, the method further includes: Real-time monitoring of the operating status of each transmission channel; If a failure is detected in a transmission channel, the buffer unit corresponding to the failure transmission channel is put into a dormant state, and channel binding is re-initiated for the remaining transmission channels.

7. The method according to any one of claims 1-6, characterized in that, The method also includes a dynamic switching step between native hardware mode and software logic mode: During the initial training phase of the transmission link composed of each of the aforementioned transmission channels, the underlying native hardware logic is used by default for channel binding. The binding status of the native hardware logic is monitored in real time. When the receiving interval of the binding code in the transmission channel is less than the minimum synchronization interval of the native hardware logic, causing the verification state machine of the native hardware logic to output a verification failure signal, the switch to the soft logic mode is triggered. During the switch to the soft logic mode, the existing logic code remains unchanged, the corresponding independent cache unit is activated according to the number of transmission channels, and the centralized cache module is cleared. During the switching process, only the training data generated in the initial training phase is discarded, while the transmission of normal business communication data is maintained.

8. A multi-channel data binding and clock compensation device based on soft logic, characterized in that, The device includes: The cache configuration module is used to dynamically configure the corresponding number of independent cache units according to the number of transmission channels. It uses the recovery clock of each transmission channel as the write clock and the unified synchronization clock as the read clock to merge the output data of each cache unit into a centralized cache module, thereby eliminating the clock phase deviation between each transmission channel. The binding detection module is used to read data from the buffer unit corresponding to each transmission channel. When a binding code appears in the data of any transmission channel, the data reading of that transmission channel is paused and locked at the binding code. After all transmission channels are locked at the binding code, the data reading of each transmission channel is resumed in a unified manner to achieve multi-channel data frame alignment and complete channel binding. The clock compensation module is used to monitor the data volume of the centralized cache module. When the data volume is lower than a preset lower threshold, a clock compensation code is inserted; when the data volume is higher than a preset upper threshold, the clock compensation code is deleted. The lower threshold and upper threshold are dynamically adjusted according to the number of transmission channels.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the soft logic-based multichannel data binding and clock compensation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the soft logic-based multichannel data binding and clock compensation method according to any one of claims 1-7.

11. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the soft logic-based multichannel data binding and clock compensation method according to any one of claims 1-7.

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