A clock signal processing method, system, storage medium and electronic device

Abstract

The application relates to a clock signal processing method, a system, a storage medium and an electronic device, and relates to the technical field of signal processing. The method comprises the following steps: performing direct current bias removal processing on a discretized clock input signal sequence to obtain a preprocessed signal; obtaining a signal amplitude peak value in a single clock cycle in the preprocessed signal, combining a target output amplitude, determining an adaptive gain coefficient corresponding to the single clock cycle, and determining a gain amplified signal based on the adaptive gain coefficient corresponding to the single clock cycle and the preprocessed signal; performing forward linear filtering and reverse linear filtering on the gain amplified signal through a target FIR filter to obtain a filtered signal; performing duty cycle closed loop correction processing on the filtered signal to obtain an initial output signal with stable duty cycle; and performing waveform edge optimization on the initial output signal based on the target output amplitude to obtain a final output signal. The application can improve the processing effect of the clock signal.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, specifically to a clock signal processing method, system, storage medium, and electronic device. Background Technology

[0002] A clock signal is a periodic digital signal that alternates between high and low levels at a fixed frequency, providing a unified time reference and synchronization for digital circuits and timing systems. Its core function is to ensure that all modules in a circuit operate synchronously according to the same "beat," avoiding timing discrepancies. Clock signal processing involves adjusting and optimizing the raw clock signal output from the clock source to make it cleaner, more stable, and better suited to system requirements. The core significance of clock signal processing lies in eliminating noise, harmonics, and phase shifts in the raw clock signal, stabilizing its timing characteristics, ensuring clear clock edges and controllable duty cycle errors, thereby providing a high-precision, high-reliability timing synchronization reference for digital circuit systems. This prevents timing errors, data transmission failures, or system malfunctions caused by clock jitter, phase deviations, or duty cycle imbalances, ensuring the stable operation and performance targets of digital devices.

[0003] Currently, the common approach to processing clock signals is as follows: signal amplification and filtering are usually performed independently. While the preamplifier increases the signal amplitude, it also amplifies noise and harmonic components. However, the subsequent fixed-parameter filtering stage cannot dynamically adjust the filtering parameters according to the actual noise level after signal amplification, resulting in poor processing performance of clock signals. Summary of the Invention

[0004] To improve the processing performance of clock signals, this application provides a clock signal processing method, system, storage medium, and electronic device.

[0005] The first aspect of this application provides a clock signal processing method, specifically including: The original analog clock signal output from the target clock source is sampled by analog-to-digital conversion to obtain a discretized clock input signal sequence; The discretized clock input signal sequence is subjected to DC bias removal processing to obtain the preprocessed signal; The peak value of the signal amplitude within a single clock cycle in the preprocessed signal is obtained. Based on the peak value of the signal amplitude and the preset target output amplitude, the adaptive gain coefficient corresponding to a single clock cycle is determined. Based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal, the signal after gain amplification is determined. A zero-phase-shift target FIR filter is constructed, and the amplified signal is subjected to forward linear filtering and reverse linear filtering through the target FIR filter to obtain the filtered signal. The filtered signal is subjected to duty cycle closed-loop correction processing to obtain an initial output signal with a stable duty cycle; Based on the target output amplitude, the waveform edge of the initial output signal is optimized to obtain the final output signal.

[0006] By employing the above technical solution, the original analog clock signal output from the target clock source is sampled digitally to obtain a discretized clock input signal sequence. This sequence is then subjected to DC bias removal processing, effectively eliminating the fixed DC component introduced during sampling and removing the interference of overall signal voltage offset on subsequent amplitude and phase calculations, providing a stable pre-processed signal for subsequent processing. Subsequently, by obtaining the peak signal amplitude within a single clock cycle of the pre-processed signal and combining it with the preset target output amplitude, a single-cycle adaptive gain coefficient is determined. Based on this, the pre-processed signal is amplified accordingly, solving the problem of inconsistent waveform amplitude caused by amplitude fluctuations in different cycles, ensuring uniform and controllable signal amplitudes in each cycle, and improving the consistency of subsequent filtering and correction processing. Furthermore, a zero-phase-shift target FIR filter is constructed. By sequentially performing forward and reverse linear filtering on the amplified signal, utilizing the phase delay cancellation characteristics of the two filters, high-frequency noise and glitches are filtered out while completely preserving the original timing characteristics of the clock signal, avoiding the limitations of ordinary FIR filters. The phase shift caused by filtering is addressed to ensure the timing accuracy of clock signal transition edges and period peaks. Next, the filtered signal undergoes duty cycle closed-loop correction processing. Based on feedback control logic, the duration of high and low signal levels is dynamically adjusted to effectively correct duty cycle deviations caused by circuit non-ideal characteristics and noise interference, resulting in a stable initial output signal. Finally, based on the target output amplitude, the initial output signal undergoes waveform edge optimization, finely adjusting the transition characteristics of the rising and falling edges to suppress edge jitter and overshoot, resulting in a final output signal with steep edges and a regular waveform. This invention systematically solves problems such as DC offset, amplitude fluctuation, phase distortion, noise interference, unstable duty cycle, and edge jitter in clock signal processing through a multi-stage collaborative processing mechanism including DC bias removal, single-cycle adaptive gain amplification, zero-phase-shift FIR filtering, duty cycle closed-loop correction, and waveform edge optimization, thereby improving the processing effect of clock signals.

[0007] In one implementation, determining the adaptive gain coefficient corresponding to a single clock cycle based on the peak value of the signal amplitude and a preset target output amplitude, and determining the amplified signal based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal, specifically includes: Substitute the peak value of the signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula to obtain the adaptive gain coefficient corresponding to a single clock cycle; The adaptive gain coefficient corresponding to a single clock cycle is multiplied by the preprocessed signal to obtain the amplified signal. Based on the target output amplitude, the amplified signal is subjected to soft limiting clamping to obtain the corrected signal. Obtain the peak value of the signal amplitude in the next clock cycle of the corrected signal, use the corrected signal as the preprocessed signal, and repeatedly perform the step of substituting the peak value of the signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula to obtain the adaptive gain coefficient corresponding to a single clock cycle. When traversing all clock cycles, the obtained corrected signal is determined as the signal after gain amplification.

[0008] In one embodiment, the gain coefficient is calculated using the following formula: G(k) = Vtarget / Vpeak(k) × β; In the formula, Vtarget represents the target output amplitude, Vpeak(k) represents the peak signal amplitude within a single clock cycle, β represents the gain safety factor, k represents the sequence number of a single clock cycle, and G(k) represents the adaptive gain factor.

[0009] In one embodiment, performing duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle specifically includes: The filtered signal is subjected to level period detection to obtain the high level duration and the total clock cycle within a single clock cycle. The high level duration is then divided by the total clock cycle to obtain the target real-time duty cycle. The comparison threshold corresponding to a single clock cycle is determined as the comparison threshold to be corrected. The comparison threshold to be corrected is corrected according to the target real-time duty cycle to obtain the corrected comparison threshold. The filtered signal is binarized based on the corrected comparison threshold to obtain the converted signal. The comparison threshold is a reference voltage value used to distinguish the high and low levels of the clock signal. The duty cycle error of the converted signal is determined, and when the duty cycle error is within a preset normal error range, the converted signal is determined as the initial output signal with a stable duty cycle. When the duty cycle error is not within the preset normal error range, the corrected comparison threshold is determined as the comparison threshold to be corrected, and the real-time duty cycle corresponding to the next clock cycle is determined as the target real-time duty cycle. The step of correcting the comparison threshold to be corrected and obtaining the corrected comparison threshold is repeated until the duty cycle error of the determined converted signal is within the preset normal error range, and an initial output signal with a stable duty cycle is obtained.

[0010] In one implementation, the step of correcting the comparison threshold to be corrected based on the target real-time duty cycle to obtain the corrected comparison threshold specifically includes: Substituting the target real-time duty cycle and the comparison threshold to be corrected into a preset correction formula, the corrected comparison threshold is obtained; the correction formula is: Vth(k+1)=Vth(k)+Kp×(0.5-D); In the formula, Kp represents the proportional correction coefficient, Vth(k) represents the comparison threshold to be corrected, Vth(k+1) represents the comparison threshold after correction, and D represents the target real-time duty cycle.

[0011] In one implementation, the step of optimizing the waveform edges of the initial output signal based on the target output amplitude to obtain the final output signal specifically includes: The initial output signal is optimized for waveform edges based on the target output amplitude using a preset optimization formula to obtain the final output signal. The optimization formula is as follows: yout(n)=Vtarget / (1+e^(-α×y3(n))); In the formula, yout(n) represents the final output signal, Vtarget represents the target output amplitude, α represents the edge sharpening coefficient, y3(n) represents the initial output signal, and n represents the sampling point number.

[0012] In one embodiment, the passband center frequency of the target FIR filter is set to the clock base frequency corresponding to the target clock source, the transition band bandwidth of the target FIR filter is set to 5% of the clock base frequency, and the stopband attenuation of the target FIR filter is greater than or equal to 40dB.

[0013] A second aspect of this application provides a clock signal processing system, specifically comprising: The signal sampling module (11) is used to perform analog-to-digital sampling on the original analog clock signal output by the target clock source to obtain a discrete clock input signal sequence; The signal processing module (12) is used to perform DC bias removal processing on the discretized clock input signal sequence to obtain the preprocessed signal; The gain processing module (13) is used to obtain the peak value of the signal amplitude in a single clock cycle in the preprocessed signal, determine the adaptive gain coefficient corresponding to a single clock cycle based on the peak value of the signal amplitude and the preset target output amplitude, and determine the signal after gain amplification based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal. The signal filtering module (14) is used to construct a zero-phase-shift target FIR filter, and to perform forward linear filtering and reverse linear filtering on the gain-amplified signal through the target FIR filter to obtain the filtered signal. The signal correction module (15) is used to perform duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle. The signal optimization module (16) is used to optimize the waveform edge of the initial output signal based on the target output amplitude to obtain the final output signal.

[0014] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when loaded and executed by a processor, performs the steps of the method described in any one of the first aspects.

[0015] A fourth aspect of this application provides an electronic device, specifically comprising: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, the processor being configured to load and execute the computer program stored in the memory to cause the electronic device to perform the method as described in any one of the first aspects.

[0016] In summary, this application includes at least one of the following beneficial technical effects: The original analog clock signal output from the target clock source is sampled digitally to obtain a discretized clock input signal sequence. This sequence is then subjected to DC bias removal processing to effectively eliminate the fixed DC component introduced during sampling, thus eliminating the interference of overall signal voltage offset on subsequent amplitude and phase calculations. This provides a stable pre-processed signal for subsequent processing. Subsequently, by obtaining the peak signal amplitude within a single clock cycle of the pre-processed signal and combining it with the preset target output amplitude, a single-cycle adaptive gain coefficient is determined. Based on this, the pre-processed signal is amplified accordingly, solving the problem of inconsistent waveform amplitude caused by amplitude fluctuations in different cycles. This ensures that the signal amplitude in each cycle is uniform and controllable, improving the consistency of subsequent filtering and correction processing. Furthermore, a zero-phase-shift target FIR filter is constructed. By sequentially performing forward and reverse linear filtering on the amplified signal, the phase delays of the two filters cancel each other out. This removes high-frequency noise and glitches while completely preserving the original timing characteristics of the clock signal, avoiding the limitations of ordinary FIR filters. The phase shift caused by filtering is addressed to ensure the timing accuracy of clock signal transition edges and period peaks. Next, the filtered signal undergoes duty cycle closed-loop correction processing. Based on feedback control logic, the duration of high and low signal levels is dynamically adjusted to effectively correct duty cycle deviations caused by circuit non-ideal characteristics and noise interference, resulting in a stable initial output signal. Finally, based on the target output amplitude, the initial output signal undergoes waveform edge optimization, finely adjusting the transition characteristics of the rising and falling edges to suppress edge jitter and overshoot, resulting in a final output signal with steep edges and a regular waveform. This invention systematically solves problems such as DC offset, amplitude fluctuation, phase distortion, noise interference, unstable duty cycle, and edge jitter in clock signal processing through a multi-stage collaborative processing mechanism including DC bias removal, single-cycle adaptive gain amplification, zero-phase-shift FIR filtering, duty cycle closed-loop correction, and waveform edge optimization, thereby improving the processing effect of clock signals. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a clock signal processing method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the process of determining a signal after gain amplification, as provided in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of a clock signal processing system provided in an embodiment of this application.

[0018] Explanation of reference numerals in the attached diagram: 11. Signal sampling module; 12. Signal processing module; 13. Gain processing module; 14. Signal filtering module; 15. Signal correction module; 16. Signal optimization module. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] In the description of the embodiments of this application, words such as "exemplarily," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0021] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0022] See Figure 1 This application discloses a flowchart of a clock signal processing method, applied to a clock signal processing system, and capable of running on a clock signal processing system based on the von Neumann architecture. This computer program can be integrated into an application or run as a standalone utility application, specifically including: S101: Perform analog-to-digital sampling on the original analog clock signal output from the target clock source to obtain a discretized clock input signal sequence.

[0023] Specifically, in this step, the target clock source is the source of the clock signal to be processed, including but not limited to a crystal oscillator, a phase-locked loop output, or an external clock input interface, whose output is a continuous-time domain analog clock signal. The specific process of performing analog-to-digital sampling on the original analog clock signal is as follows: First, according to the Nyquist sampling theorem, the sampling frequency fs is determined to be no less than twice the clock base frequency fclk. To ensure the accuracy of signal waveform restoration, in this embodiment, the sampling frequency is set to 10 times the clock base frequency, i.e., fs = 10 × fclk. For example, when the clock base frequency fclk of the target clock source is 50MHz, the sampling frequency is set to fs = 500MHz. The specific method for determining the sampling frequency is as follows: obtain the clock base frequency value fclk according to the nominal frequency parameter of the target clock source or through the frequency pre-detection circuit, and then multiply the base frequency value by the oversampling factor (10 times in this embodiment) to obtain the sampling frequency fs. The principle for selecting the oversampling factor is to improve the waveform restoration accuracy as much as possible while meeting the hardware processing capabilities, and it is generally taken as 8 to 16 times.

[0024] In other embodiments, based on pre-cached sampling noise statistics, multiple clock source types with a signal-to-noise ratio (SNR) less than a preset threshold after analog-to-digital sampling are obtained. The occurrence count of a single clock source type is counted among these multiple clock source types. A preset number of clock source types are selected from all different clock source types in descending order of occurrence count and identified as important clock source types—that is, clock source types whose sampled signal noise is prone to be strong. In this embodiment, the preset number is the quotient of the total number of all different clock source types divided by 2. The sampling noise statistics include the SNR of historical clock source samples of different clock source types within a preset time period, and the corresponding historical sampling frequency, etc. The preset time period is the past two years. It should be noted that a lower SNR indicates stronger signal noise. The preset threshold is a critical value for measuring the degree of SNR; in this embodiment, the preset threshold can be 40 dB.

[0025] Furthermore, based on the aforementioned sampling noise statistics, multiple historical sampling frequencies are obtained where the signal-to-noise ratio (SNR) of the sampled signal from a single important clock source type is less than a preset threshold. Then, a preset K-Means algorithm is used to perform cluster analysis on these historical sampling frequencies, dividing them into multiple frequency intervals covering all historical sampling frequencies. The specific process of cluster analysis is as follows: a preset number of clusters, K, is used as the expected number of frequency intervals. Within the range of historical sampling frequencies (from the minimum to the maximum historical sampling frequency), K cluster centers are selected at equal intervals. For each historical sampling frequency, its Euclidean distance to each cluster center is calculated, and the historical sampling frequency is assigned to the cluster with the smallest distance. Subsequently, for each cluster, its cluster center is recalculated as the mean of all samples within that cluster. This sample allocation and cluster center update process is repeated until a preset maximum number of iterations is reached. In this embodiment, the maximum number of iterations can be 50. After clustering convergence, the K clusters are sorted in ascending order of their cluster centers. The boundary between two adjacent clusters is taken as the midpoint between their cluster centers, thus obtaining multiple frequency intervals. The number of clusters K is determined using the elbow rule: clustering is performed with K = 2, 3, ..., K_max, and the sum of squares (SSE) within each cluster corresponding to each K value is calculated. The K value corresponding to a significant slowdown in the rate of SSE decrease is selected as the number of clusters. This clustering analysis process is existing technology and will not be elaborated further here.

[0026] The number of historical sampling frequencies contained in each frequency interval is counted. A predetermined number of frequency intervals are selected from all frequency intervals in descending order of the number of historical sampling frequencies to determine the important frequency intervals corresponding to a single important clock source type. Based on the frequency intervals where sampling results in high noise, in this embodiment, the predetermined number is the result of multiplying the total number of all different frequency intervals by three-fifths and then rounding down. Next, the weight of a single important clock source type is determined. The weight is the ratio of the occurrence count of a single important clock source type to the sum of the occurrence counts of all important clock source types, representing the probability that the clock source of that important clock source type will have high noise after sampling. Then, the weight of each important frequency interval corresponding to a single important clock source type is determined. The weight is the ratio of the number of historical sampling frequencies contained in a single important frequency interval to the sum of the number of historical sampling frequencies contained in all important frequency intervals, representing the probability that sampling at frequencies within that important frequency interval will result in high signal noise.

[0027] Furthermore, when the actual clock source type of the target clock source is an important clock source type, if the important frequency interval corresponding to the actual clock source type contains the sampling frequency, then this important frequency interval is determined as the actual frequency interval. The weight of the actual clock source type is multiplied by the weight of the actual frequency interval to obtain the multiplication result. The multiplication result represents the probability that the sampled signal from the target clock source will be too noisy when sampled at the sampling frequency. If the multiplication result does not exceed the preset result threshold, it indicates that the probability of the sampled signal being too noisy when sampled at the sampling frequency is relatively small, and the sampling frequency is reasonable; therefore, the sampling frequency verification is passed. The result threshold is a critical value for measuring the magnitude of the multiplication result. If the multiplication result exceeds the result threshold, it indicates that the probability of the sampled signal being too noisy is relatively large, and the sampling frequency needs to be re-determined. The product of the weight of the important clock source type and the weight of each corresponding important frequency interval is calculated, and the smallest product is selected from multiple products. A value is then randomly selected from the important frequency interval corresponding to the smallest product as the new sampling frequency. The smaller the product, the lower the probability of noise being too strong when sampling the target clock source at a frequency within the corresponding important frequency interval.

[0028] The original analog clock signal is sampled at equal time intervals using an analog-to-digital converter (ADC) at a sampling frequency fs. The ADC has a quantization bit depth of at least 12 bits to ensure amplitude resolution. Each sample yields a digital quantized value, which, when arranged in chronological order, constitutes the discretized clock input signal sequence x(n), where n is the sampling point number (n = 0, 1, 2, ..., N-1), and N is the total number of sampling points, determined by the product of the sampling duration and the sampling frequency. The number of sampling points M per clock cycle is determined as follows: M = fs / fclk, i.e., the sampling frequency divided by the clock base frequency. When fs = 500MHz and fclk = 50MHz, M = 10, indicating 10 sampling points per clock cycle. This high-multiplication oversampling provides sufficient waveform detail information, offering a high-resolution data foundation for subsequent signal processing and avoiding signal aliasing and waveform distortion caused by insufficient sampling.

[0029] In this step, "discretized clock input signal sequence" refers to the ordered set of digitized signal values ​​arranged in time sequence obtained by converting the analog clock signal in the continuous time domain through equal-interval analog-to-digital conversion, with each element corresponding to the signal amplitude quantization result at a sampling time; "analog-to-digital sampling" refers to the process of converting continuously changing analog voltage signals into discrete digital quantities using an analog-to-digital converter.

[0030] S102: Perform DC bias removal processing on the discretized clock input signal sequence to obtain the preprocessed signal.

[0031] Specifically, the discrete clock input signal sequence x(n) obtained in step S101 is subjected to DC bias removal processing. The purpose is to eliminate the fixed DC bias voltage introduced by factors such as ADC reference voltage offset during the analog-to-digital conversion process and DC component superposition in the signal coupling link, so as to make the signal zero-line symmetrically distributed and provide an accurate amplitude reference for subsequent gain amplification processing. The specific processing process is as follows: The sliding window mean method is used to calculate and subtract the DC bias component. The calculation formula is: x0(n) = x(n) - 1 / M × ∑(i=n-M+1→n)x(i), where x0(n) is the preprocessed signal, x(n) is the value of the nth sampling point in the discrete clock input signal sequence, M is the number of sampling points within a single clock cycle (its value is determined by fs / fclk in step S101, and in this embodiment, M = 10), ∑(i=n-M+1→n)x(i) represents the cumulative sum of M sampling values from the (n-M+1)th sampling point to the nth sampling point, and 1 / M × ∑(i=n-M+1→n)x(i) is the arithmetic mean of the signal within the sliding window with the current sampling point as the end point and a length of one clock cycle. This arithmetic mean is the DC bias estimate value at the current moment. The reason for selecting the sliding window length as the number of sampling points M within a single clock cycle is that the clock signal is a periodic signal, and the mean value of the symmetric waveform within a complete cycle is its DC component. Using a single cycle as the window length can accurately estimate the DC bias without introducing low-frequency signal distortion. For the first M-1 sampling points at the beginning of the signal sequence, since a complete cycle window cannot be formed, the available number of sampling points is used as the window length for mean value calculation. That is, when n < M, x0(n) = x(n) - 1 / (n+1) × ∑(i=0→n)x(i). After the DC bias removal processing, the preprocessed signal x0(n) is symmetrically distributed centered on the zero level, and the peak value in the positive half cycle is approximately equal to the valley value in the negative half cycle. It should be noted that after eliminating the DC bias in this step, the signal is symmetric centered on zero, so that unilateral clipping or amplitude judgment deviation will not occur due to DC component superposition during subsequent gain amplification, improving the accuracy of adaptive gain calculation.

[0032] S103: Obtain the signal amplitude peak within a single clock cycle of the preprocessed signal, determine the adaptive gain coefficient corresponding to a single clock cycle based on the signal amplitude peak and the preset target output amplitude, and determine the gain-amplified signal based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal.

[0033] Specifically, after the preprocessed signal is determined, it needs to undergo adaptive gain amplification processing clock cycle by clock cycle. The specific implementation process is as follows: First, within the range of M sampling points corresponding to each clock cycle, traverse the absolute values ​​of all sampling points and take the maximum value as the peak signal amplitude Vpeak(k) of that clock cycle, where k is the index of the clock cycle, k=0,1,2,… The clock cycle is the total time length occupied by the clock signal to complete one complete high-low level alternation, and it is also the smallest basic time unit in digital circuits and timing systems.

[0034] Then, based on the peak signal amplitude Vpeak(k) and the preset target output amplitude Vtarget, the adaptive gain coefficient G(k) corresponding to a single clock cycle is calculated according to the gain coefficient calculation formula: G(k) = Vtarget / Vpeak(k) × β, where Vtarget is the target output amplitude, which is the expected peak signal output voltage preset according to the voltage specifications of the subsequent circuit. For example, when the subsequent circuit is a 3.3V CMOS level standard, Vtarget is set to 3.3V, and when the subsequent circuit is 2.5V... When using the LVDS level standard, Vtarget is set to 2.5V. Its specific value is determined by the system designer based on the actual level standard and configured as an algorithm input parameter. Vpeak(k) is the peak signal amplitude detected in the current k-th clock cycle. β is the gain safety factor. In this embodiment, β is set to 0.92. This factor allows for a margin in gain calculation, ensuring the amplified signal peak is slightly lower than the target output amplitude, thus avoiding hard clipping distortion caused by signal transient fluctuations exceeding Vtarget. In other embodiments, β can also be set to 0.95. In the formula, Vtarget / Vpeak(k) physically means: the theoretical gain factor required to amplify the peak signal amplitude in the current clock cycle to the target output amplitude; multiplying by β for margin reduction yields the actual gain factor. After calculating the adaptive gain factor G(k), it is multiplied point-by-point with the preprocessed signal in the current clock cycle to complete signal amplification. Then, soft-limiting clamping is applied to the amplified signal. The rules for soft-limiting clamping are: When x0(n)×G(k)>Vtarget, the output is limited to Vtarget; when x0(n)×G(k)<-Vtarget, the output is limited to -Vtarget; in other cases, the output is x0(n)×G(k). That is, the complete expression of the amplified signal y1(n) is a piecewise function: y1(n)=Vtarget (when x0(n)×G(k)>Vtarget), y1(n)=-Vtarget (when x0(n)×G(k)<-Vtarget), y1(n)=x0(n)×G(k) (other cases). This soft limiting process ensures that the amplitude of the output signal is always constrained within the range of [-Vtarget, Vtarget], preventing amplitude overflow caused by excessive gain or signal abrupt changes.

[0035] After amplification and soft-limiting processing for the current clock cycle, the corrected signal is used as the input signal for peak signal amplitude detection in the next clock cycle. That is, the peak signal amplitude of the corrected signal in the next clock cycle is reacquired. Then, the corrected signal is used as the preprocessed signal, and the step of substituting the peak signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula is repeated to obtain the adaptive gain coefficient corresponding to a single clock cycle. That is, the adaptive gain coefficient corresponding to the next clock cycle is calculated again, and then this adaptive gain coefficient is multiplied by the newly determined preprocessed signal to complete signal amplification and soft-limiting clamping, forming a cycle-by-cycle iterative closed-loop feedback mechanism. This feedback mechanism allows the gain coefficient to be dynamically adjusted according to the real-time changes in signal amplitude. The gain automatically increases when the input signal amplitude gradually decreases and automatically decreases when the input signal amplitude increases, thus achieving adaptive tracking of input amplitude drift. After traversing all clock cycles and completing the above iterative processing, the final corrected signal is determined as the amplified signal. For details, please refer to [link to relevant documentation]. Figure 2 .

[0036] It should be noted that "peak signal amplitude" refers to the maximum absolute value among all sampling points within a complete clock cycle, reflecting the maximum amplitude of the signal in that cycle; "adaptive gain coefficient" refers to the amplification factor calculated in real time based on the peak signal amplitude and target output amplitude within the current clock cycle, and its value is automatically adjusted as the input signal amplitude changes; "target output amplitude" refers to the desired peak output voltage of the signal pre-set according to the level specifications of the subsequent circuit; "gain safety factor" refers to a scaling factor less than 1 introduced in the gain calculation to reserve amplitude margin and prevent hard clipping distortion; "soft limiting clamping" refers to the operation of smoothly limiting the signal amplitude to the boundary value when it exceeds the set boundary, which is different from hard limiting by direct truncation and can reduce high-frequency harmonics caused by waveform abrupt changes. In addition, through the synergistic effect of cycle-by-cycle adaptive gain calculation and soft limiting clamping, it ensures that the signal is accurately amplified to near the target amplitude, and avoids the signal clipping or insufficient amplification problems that occur when the input amplitude drifts in the fixed gain scheme, realizing real-time adaptive tracking of dynamic amplitude changes.

[0037] S104: Construct a zero-phase-shift target FIR filter, and use the target FIR filter to perform forward and reverse linear filtering on the amplified signal to obtain the filtered signal.

[0038] Specifically, the signal amplified by the gain obtained in step S103 is subjected to zero-phase-shift narrowband FIR filtering to filter out random noise and high-order harmonic components in the signal, while ensuring that the filtering process does not introduce any phase shift. The specific implementation process is as follows: First, construct the target FIR filter, which is a finite-length unit impulse response (FIR) digital filter. Its design parameters are determined according to the following rules: The passband center frequency is set to the fundamental frequency fclk corresponding to the target clock source, that is, the center of the filter's passband is consistent with the fundamental frequency of the clock signal, ensuring that the fundamental frequency component of the clock passes through without attenuation; the transition band bandwidth is set to 5% of the fundamental frequency of the clock, that is, Δf=0.05×fclk. For example, when fclk=50MHz, the transition band bandwidth is 2.5MHz. The transition band bandwidth determines the transition speed of the filter from the passband to the stopband. Taking 5% of the fundamental frequency of the clock is to achieve a balance between effectively suppressing near-frequency noise and maintaining a reasonable filter order; the stopband attenuation is set to be greater than or equal to 40dB, that is, the signal component in the stopband is attenuated by at least 40dB (i.e., the amplitude is attenuated to less than 1 / 100), ensuring that noise and harmonics are fully suppressed. The filter order N is estimated and determined using the Kaiser window design formula based on the required transition band width and stopband attenuation index: N≈(A-8) / (2.285×2π×Δf / fs), where A is the stopband attenuation in decibels (A=40dB in this embodiment), Δf is the transition band width, and fs is the sampling frequency. After calculating the value of N, an even number not less than this value is taken as the actual filter order. In this embodiment, N is 16. The filter coefficients h(i) (i=0,1,…,N-1) are designed using the window function method. Specifically, the impulse response of the ideal bandpass filter is first determined, and then a window is added for truncation. The window function is either the Hamming window or the Kaiser window to meet the stopband attenuation requirements.

[0039] Furthermore, the principle of zero phase shift is based on forward-backward filtering: The first step is forward filtering, where the amplified signal is input into the target FIR filter in forward time order and linear convolution is performed. The forward filtering formula is: yf(n)=∑(i=0→N-1)h(i)×y1(ni), where h(i) is the i-th filter coefficient, y1(ni) is the value of the input signal after a delay of i sampling points, and N is the filter order. This forward filtering introduces a fixed phase delay equal to the group delay of the filters. The second step is backward filtering, where the output signal of the forward filter is... After time reversal, yf(n) is convolved again through the same target FIR filter. The inverse filtering formula is: yfr(n)=∑(i=0→N-1)h(i)×yf(N-1-n+i), where yf(N-1-n+i) represents the filtering process after reversing the forward filtering output in the time dimension. The phase delay introduced by the inverse filtering is equal in magnitude and opposite in direction to the phase delay introduced by the forward filtering. The phase delays of the two filters cancel each other out, ultimately achieving zero phase offset. The output signal (yfr(n)) after inverse filtering is time-reversed again to restore the normal timing sequence, and the resulting signal is the filtered signal. This filtered signal retains only the effective signal components near the clock fundamental frequency. High-frequency random noise and high-order harmonics are effectively suppressed, and the time position (phase) of the signal is completely consistent with that before filtering, without introducing any timing offset or clock edge position drift.

[0040] It should be noted that "zero phase shift" means that the filtered signal has no delay or lead over the unfiltered signal in time, that is, the phase characteristics of the output signal are completely consistent with the input signal; "forward linear filtering" refers to the filtering operation of linearly convolving the input signal with the filter coefficients in the forward time sequence of the signal; "reverse linear filtering" refers to the operation of linearly convolving the output signal of the forward filter in reverse time sequence and then filtering it again; "transition band bandwidth" refers to the frequency range that the filter's frequency response attenuates from the edge of the passband to the edge of the stopband; "stopband attenuation" refers to the degree of suppression of signal components by the filter within the stopband frequency range, expressed in decibels. Furthermore, the zero phase shift characteristic achieved through forward-reverse bidirectional filtering effectively filters out noise and harmonics while completely maintaining the timing edge position of the clock signal, avoiding the clock jitter and edge distortion problems caused by the phase delay introduced by traditional unidirectional filtering, achieving a noise suppression effect of over 20dB.

[0041] S105: Perform duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle.

[0042] Specifically, in this embodiment, the filtered signal is subjected to level period detection. That is, within a single clock cycle (containing M sampling points), the number of sampling points with signal amplitude greater than Vth(k) is counted based on the comparison threshold Vth(k) corresponding to the current clock cycle. This number is multiplied by the sampling interval (1 / fs) to obtain the high-level duration TH. The total clock cycle Tclk=M / fs=1 / fclk. The high-level duration is divided by the total clock cycle to obtain the target real-time duty cycle D=TH / Tclk. The comparison threshold is determined by taking the midpoint value of the range of the filtered signal amplitude.

[0043] The comparison threshold corresponding to a single clock cycle (clock cycle with sequence number 0) is determined as the comparison threshold to be corrected. Then, based on the target real-time duty cycle, the comparison threshold to be corrected is corrected to obtain the corrected comparison threshold. One feasible correction method is to substitute the target real-time duty cycle and the comparison threshold to be corrected into a preset correction formula to obtain the corrected comparison threshold. The correction formula is as follows: Vth(k+1)=Vth(k)+Kp×(0.5-D); In the formula, Kp represents the proportional correction coefficient, Vth(k) represents the comparison threshold to be corrected, Vth(k+1) represents the corrected comparison threshold used for the comparison threshold corresponding to the next clock cycle, and D represents the target real-time duty cycle. The target value is set at a standard duty cycle of 50% (i.e., 0.5). The comparison threshold is adjusted in real-time based on the deviation between the currently detected target real-time duty cycle D and the target value of 0.5. It should be noted that the value of Kp ranges from 0.05 to 0.2; in this embodiment, Kp = 0.1.

[0044] Furthermore, the physical meaning of this correction formula is as follows: When the target real-time duty cycle D is less than 0.5, it indicates that the high-level time is too short, and the comparison threshold needs to be reduced so that more sampling points are judged as high level. At this time, (0.5-D)>0, and the direction of Vth(k) increase is positive adjustment (the logic of reducing the comparison threshold to increase the high level is: for a sinusoidal filtered signal, reducing the comparison threshold is equivalent to increasing the high-level time. Therefore, when D<0.5, the comparison threshold actually needs to be reduced. In the formula, Kp×(0.5-D) is a positive value added to Vth(k). The corresponding physical meaning needs to be understood in conjunction with the signal polarity. When the signal is symmetrical with zero as the center, the increase of the threshold, that is, the shift in the positive direction, is equivalent to increasing the proportion of the negative half-cycle judged as low level. The specific direction is determined by the signal shape. In this embodiment, for the symmetrical signal after DC bias removal, the positive increase of the comparison threshold Vth corresponds to the correction direction of increasing the high-level time).

[0045] Perform binary conversion on the filtered signal based on the corrected comparison threshold Vth(k + 1). The conversion rule is as follows: when the filtered signal y2(n) ≥ Vth(k + 1), output the high-level value Vtarget; when y2(n) < Vth(k + 1), output the low-level value 0 to obtain the converted signal. Subsequently, perform duty cycle detection on the converted signal. That is, within each clock cycle, calculate the ratio of the high-level duration to the total duration of the clock cycle, and record this ratio as the actual duty cycle. Then calculate the duty cycle error for each clock cycle. The duty cycle error is defined as |measured duty cycle - 0.5| × 100%. The preset normal error range is that the duty cycle error does not exceed ±1%, that is, |measured duty cycle - 0.5| ≤ 0.01. This ±1% error range is determined according to the typical technical requirements of high-precision digital systems for the clock duty cycle. In the field of communication and digital chips, a duty cycle deviation exceeding ±1% may cause setup time and hold time violations. If the duty cycle errors are all within ±1%, the currently converted signal is determined as the initial output signal y3(n) with a stable duty cycle. If the duty cycle errors are not within ±1%, use the corrected comparison threshold Vth(k + 1) as the new comparison threshold to be corrected, continue to detect the real-time duty cycle for the next clock cycle, and repeat the execution of the correction formula to iteratively adjust the threshold until the duty cycle error of the converted signal converges within ±1%. At this time, the converted signal obtained is the initial output signal y3(n) with a stable duty cycle.

[0046] It should be noted that the comparison threshold is the reference voltage value used to distinguish the high and low levels of the clock signal. In addition, the proportional correction coefficient is the proportional gain parameter that controls the adjustment step of the comparison threshold in the correction formula and determines the correction convergence speed. The beneficial effect of this step is that: by using the correction formula to correct the duty cycle deviation in real time, the duty cycle of the output clock signal is accurately stabilized within the range of 50% ± 1%, meeting the strict requirements of high-precision timing systems for clock symmetry, and the closed-loop mechanism has an automatic tracking ability and can adapt to the duty cycle drift caused by signal condition changes.

[0047] S106: Optimize the waveform edges of the initial output signal based on the target output amplitude to obtain the final output signal.

[0048] Specifically, the initial output signal y3(n) with a stable duty cycle obtained in step S105 undergoes waveform edge optimization processing to eliminate potential overshoot and ringing phenomena at the signal transition edges. Simultaneously, the rising and falling edges of the clock are sharpened to make the edge transitions steeper and smoother. The specific implementation process is as follows: A nonlinear transformation based on the Sigmoid function is used to shape the waveform of the initial output signal. The optimization formula is: yout(n) = Vtarget / (1 + e^(-α × y3(n))), where yout(n) is the amplitude of the final output signal at the nth sampling point, Vtarget is the target output amplitude (same as in step S103, determined by the level specification of the subsequent circuit; in this embodiment, Vtarget = 3.3V), α is the edge sharpening coefficient, y3(n) is the amplitude of the initial output signal at the nth sampling point, and n is the sampling point number. The edge sharpening coefficient ranges from 2 to 5; in this embodiment, the edge sharpening coefficient is 3.

[0049] The physical meaning of this optimization formula is as follows: The Sigmoid function 1 / (1+e^(-α×y3(n))) is an S-shaped nonlinear mapping function with an output range of (0,1). After multiplying by Vtarget, the output range becomes (0,Vtarget). When y3(n) is a large positive value, e^(-α×y3(n)) approaches 0, and the output approaches Vtarget, corresponding to a high clock level. When y3(n) is a large negative value, e^(-α×y3(n)) approaches infinity, and the output approaches 0, corresponding to a low clock level. When y3(n) transitions near zero (i.e., in the clock edge transition region), the S-shaped characteristic of the Sigmoid function allows the output to switch quickly from low to high (or inversely) in a smooth and monotonic manner, without overshoot or ringing.

[0050] After this nonlinear transformation, the final output signal yout(n) has the following characteristics: the high-level region is stable near Vtarget, the low-level region is stable near 0, the transition region between the rising and falling edges is smooth and without overshoot or ringing, and the steepness of the edge is controlled by the α parameter. In this step, "waveform edge optimization" refers to signal shaping processing that makes the transition region between the rising and falling edges of the clock signal steeper and smoother without ringing through nonlinear function transformation; "edge sharpening coefficient" refers to the parameter in the Sigmoid transformation function that controls the steepness of the output edge, the larger the value, the steeper the edge; the beneficial effect of this step is that, by utilizing the natural smooth and bounded characteristics of the Sigmoid function, while sharpening the clock edge to shorten the transition time, it mathematically eliminates the generation of overshoot and ringing (because the Sigmoid function is monotonically bounded, the output cannot exceed Vtarget or fall below 0), achieving a unity of edge steepness and waveform stability, and the final output meets the comprehensive requirements of high-precision digital systems for clock signal amplitude stability, timing accuracy, duty cycle symmetry, and edge quality.

[0051] The implementation principle of the clock signal processing method in this application is as follows: The original analog clock signal output from the target clock source is sampled digitally to obtain a discretized clock input signal sequence. Then, DC bias removal processing is performed on this sequence to effectively eliminate the fixed DC component introduced during sampling, thus eliminating the interference of the overall signal voltage offset on subsequent amplitude and phase calculations, providing a stable pre-processed signal for subsequent processing. Subsequently, by obtaining the peak signal amplitude within a single clock cycle in the pre-processed signal, and combining it with the preset target output amplitude, a single-cycle adaptive gain coefficient is determined. Based on this, the pre-processed signal is amplified accordingly, solving the problem of inconsistent waveform amplitude caused by fluctuations in signal amplitude across different cycles, ensuring that the signal amplitude of each cycle is uniform and controllable, and improving the consistency of subsequent filtering and correction processing. Furthermore, a zero-phase-shift target FIR filter is constructed. By sequentially performing forward and reverse linear filtering on the amplified signal, the phase delays of the two filters cancel each other out, filtering out high-frequency noise and glitches while completely preserving the original timing characteristics of the clock signal, avoiding the problems associated with ordinary FIR filters. The phase shift caused by filtering is addressed to ensure the timing accuracy of clock signal transition edges and period peaks. Next, the filtered signal undergoes duty cycle closed-loop correction processing. Based on feedback control logic, the duration of high and low signal levels is dynamically adjusted to effectively correct duty cycle deviations caused by circuit non-ideal characteristics and noise interference, resulting in a stable initial output signal. Finally, based on the target output amplitude, the initial output signal undergoes waveform edge optimization, finely adjusting the transition characteristics of the rising and falling edges to suppress edge jitter and overshoot, resulting in a final output signal with steep edges and a regular waveform. This invention systematically solves problems such as DC offset, amplitude fluctuation, phase distortion, noise interference, unstable duty cycle, and edge jitter in clock signal processing through a multi-stage collaborative processing mechanism including DC bias removal, single-cycle adaptive gain amplification, zero-phase-shift FIR filtering, duty cycle closed-loop correction, and waveform edge optimization, thereby improving the processing effect of clock signals.

[0052] The following are system embodiments of this application, which can be used to execute the method embodiments of this application. For details not disclosed in the system embodiments of this application, please refer to the method embodiments of this application.

[0053] Please see Figure 3 This is a schematic diagram of the clock signal processing system provided in an embodiment of this application. This clock signal processing system can be implemented as all or part of a system through software, hardware, or a combination of both. The system includes a signal sampling module 11, a signal processing module 12, a gain processing module 13, a signal filtering module 14, a signal correction module 15, and a signal optimization module 16.

[0054] The signal sampling module 11 is used to perform analog-to-digital sampling on the original analog clock signal output by the target clock source to obtain a discretized clock input signal sequence; Signal processing module 12 is used to perform DC bias removal processing on the discretized clock input signal sequence to obtain a preprocessed signal; The gain processing module 13 is used to obtain the peak value of the signal amplitude in a single clock cycle in the preprocessed signal, determine the adaptive gain coefficient corresponding to a single clock cycle based on the peak value of the signal amplitude and the preset target output amplitude, and determine the signal after gain amplification based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal. Signal filtering module 14 is used to construct a zero-phase-shift target FIR filter. The target FIR filter is used to perform forward linear filtering and reverse linear filtering on the amplified signal to obtain the filtered signal. Signal correction module 15 is used to perform duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle. The signal optimization module 16 is used to optimize the waveform edges of the initial output signal based on the target output amplitude to obtain the final output signal.

[0055] Optional, gain processing module 13, specifically used for: Substitute the peak signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula to obtain the adaptive gain coefficient corresponding to a single clock cycle. The adaptive gain coefficient corresponding to a single clock cycle is multiplied by the preprocessed signal to obtain the amplified signal. Based on the target output amplitude, the amplified signal is subjected to soft limiting clamping to obtain the corrected signal. The peak value of the signal amplitude in the next clock cycle is obtained from the corrected signal. The corrected signal is used as the preprocessed signal. The steps of substituting the peak value of the signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula are repeated to obtain the adaptive gain coefficient corresponding to a single clock cycle. When traversing all clock cycles, the obtained corrected signal is determined as the signal after gain amplification.

[0056] Optional, signal correction module 15, specifically used for: The filtered signal is subjected to level period detection to obtain the high level duration and the total clock cycle within a single clock cycle. The high level duration is then divided by the total clock cycle to obtain the target real-time duty cycle. The comparison threshold corresponding to a single clock cycle is determined as the comparison threshold to be corrected. According to the target real-time duty cycle, the comparison threshold to be corrected is corrected to obtain the corrected comparison threshold. The filtered signal is binarized based on the corrected comparison threshold to obtain the converted signal. The comparison threshold is a reference voltage value used to distinguish the high and low levels of the clock signal. The duty cycle error of the converted signal is determined. When the duty cycle error is within the preset normal error range, the converted signal is determined as the initial output signal with a stable duty cycle. When the duty cycle error is not within the preset normal error range, the corrected comparison threshold is determined as the comparison threshold to be corrected, and the real-time duty cycle corresponding to the next clock cycle is determined as the target real-time duty cycle. The steps of correcting the comparison threshold to be corrected and obtaining the corrected comparison threshold are repeated until the duty cycle error of the determined converted signal is within the preset normal error range, and an initial output signal with a stable duty cycle is obtained.

[0057] Optionally, the signal correction module 15 is also used for: Substituting the target real-time duty cycle and the comparison threshold to be corrected into the preset correction formula, the corrected comparison threshold is obtained; the correction formula is: Vth(k+1)=Vth(k)+Kp×(0.5-D); In the formula, Kp represents the proportional correction coefficient, Vth(k) represents the comparison threshold to be corrected, Vth(k+1) represents the comparison threshold after correction, and D represents the target real-time duty cycle.

[0058] Optional, signal optimization module 16, specifically used for: The initial output signal is optimized for waveform edges based on the target output amplitude using a preset optimization formula to obtain the final output signal. The optimization formula is as follows: yout(n)=Vtarget / (1+e^(-α×y3(n))); In the formula, yout(n) represents the final output signal, Vtarget represents the target output amplitude, α represents the edge sharpening coefficient, y3(n) represents the initial output signal, and n represents the sampling point number.

[0059] It should be noted that the clock signal processing system provided in the above embodiments is only illustrated by the division of the above functional modules when executing the clock signal processing method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the clock signal processing system and the clock signal processing method embodiment provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiment, which will not be repeated here.

[0060] This application also discloses a computer-readable storage medium, which stores a computer program, wherein when the computer program is executed by a processor, it implements a clock signal processing method of the above embodiments.

[0061] The computer program can be stored in a computer-readable medium. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or certain middleware. The computer-readable medium includes any entity or system capable of carrying computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the computer-readable medium includes, but is not limited to, the above-mentioned components.

[0062] The clock signal processing method of the above embodiment is stored in the computer-readable storage medium and loaded and executed on the processor to facilitate the storage and application of the above method.

[0063] This application also discloses an electronic device, which can be a desktop computer, a laptop computer, or a cloud server, etc. The electronic device includes, but is not limited to, a processor and a memory. For example, the electronic device may also include input / output devices, network access devices, and buses.

[0064] The processor can be a central processing unit (CPU). Of course, depending on the actual use, it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc., and this application does not limit it.

[0065] The memory can be an internal storage unit of an electronic device, such as a hard disk or RAM, or an external storage device, such as a plug-in hard disk, smart memory card (SMC), secure digital card (SD), or flash memory card (FC) equipped on the electronic device. Furthermore, the memory can be a combination of an internal storage unit and an external storage device. The memory is used to store computer programs and other programs and data required by the electronic device. The memory can also be used to temporarily store data that has been output or will be output. This application does not limit this.

[0066] In this electronic device, a clock signal processing method according to the above embodiment is stored in the memory of the electronic device and loaded and executed on the processor of the electronic device for convenient use.

[0067] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A clock signal processing method, characterized in that, The method includes: The original analog clock signal output from the target clock source is sampled by analog-to-digital conversion to obtain a discretized clock input signal sequence; The discretized clock input signal sequence is subjected to DC bias removal processing to obtain the preprocessed signal; The peak value of the signal amplitude within a single clock cycle in the preprocessed signal is obtained. Based on the peak value of the signal amplitude and the preset target output amplitude, the adaptive gain coefficient corresponding to a single clock cycle is determined. Based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal, the signal after gain amplification is determined. A zero-phase-shift target FIR filter is constructed, and the amplified signal is subjected to forward linear filtering and reverse linear filtering through the target FIR filter to obtain the filtered signal. The filtered signal is subjected to duty cycle closed-loop correction processing to obtain an initial output signal with a stable duty cycle; Based on the target output amplitude, the waveform edge of the initial output signal is optimized to obtain the final output signal.

2. The clock signal processing method according to claim 1, characterized in that, The process of determining the adaptive gain coefficient for a single clock cycle based on the peak value of the signal and the preset target output amplitude, and determining the amplified signal based on the adaptive gain coefficient for a single clock cycle and the preprocessed signal, specifically includes: Substitute the peak value of the signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula to obtain the adaptive gain coefficient corresponding to a single clock cycle; The adaptive gain coefficient corresponding to a single clock cycle is multiplied by the preprocessed signal to obtain the amplified signal. Based on the target output amplitude, the amplified signal is subjected to soft limiting clamping to obtain the corrected signal. Obtain the peak value of the signal amplitude in the next clock cycle of the corrected signal, use the corrected signal as the preprocessed signal, and repeatedly perform the step of substituting the peak value of the signal amplitude and the preset target output amplitude into the preset gain coefficient calculation formula to obtain the adaptive gain coefficient corresponding to a single clock cycle. When traversing all clock cycles, the obtained corrected signal is determined as the signal after gain amplification.

3. The clock signal processing method according to claim 2, characterized in that, The formula for calculating the gain coefficient is as follows: G(k) = Vtarget / Vpeak(k) × β; In the formula, Vtarget represents the target output amplitude, Vpeak(k) represents the peak signal amplitude within a single clock cycle, β represents the gain safety factor, k represents the sequence number of a single clock cycle, and G(k) represents the adaptive gain factor.

4. The clock signal processing method according to claim 1, characterized in that, The step of performing duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle specifically includes: The filtered signal is subjected to level period detection to obtain the high level duration and the total clock cycle within a single clock cycle. The high level duration is then divided by the total clock cycle to obtain the target real-time duty cycle. The comparison threshold corresponding to a single clock cycle is determined as the comparison threshold to be corrected. The comparison threshold to be corrected is corrected according to the target real-time duty cycle to obtain the corrected comparison threshold. The filtered signal is binarized based on the corrected comparison threshold to obtain the converted signal. The comparison threshold is a reference voltage value used to distinguish the high and low levels of the clock signal. The duty cycle error of the converted signal is determined, and when the duty cycle error is within a preset normal error range, the converted signal is determined as the initial output signal with a stable duty cycle. When the duty cycle error is not within the preset normal error range, the corrected comparison threshold is determined as the comparison threshold to be corrected, and the real-time duty cycle corresponding to the next clock cycle is determined as the target real-time duty cycle. The step of correcting the comparison threshold to be corrected and obtaining the corrected comparison threshold is repeated until the duty cycle error of the determined converted signal is within the preset normal error range, and an initial output signal with a stable duty cycle is obtained.

5. The clock signal processing method according to claim 4, characterized in that, The step of correcting the comparison threshold to be corrected based on the target real-time duty cycle to obtain the corrected comparison threshold specifically includes: Substituting the target real-time duty cycle and the comparison threshold to be corrected into a preset correction formula, the corrected comparison threshold is obtained; the correction formula is: Vth(k+1)=Vth(k)+Kp×(0.5-D); In the formula, Kp represents the proportional correction coefficient, Vth(k) represents the comparison threshold to be corrected, Vth(k+1) represents the comparison threshold after correction, and D represents the target real-time duty cycle.

6. The clock signal processing method according to claim 1, characterized in that, The step of optimizing the waveform edges of the initial output signal based on the target output amplitude to obtain the final output signal specifically includes: The initial output signal is optimized for waveform edges based on the target output amplitude using a preset optimization formula to obtain the final output signal. The optimization formula is as follows: yout(n)=Vtarget / (1+e^(-α×y3(n))); In the formula, yout(n) represents the final output signal, Vtarget represents the target output amplitude, α represents the edge sharpening coefficient, y3(n) represents the initial output signal, and n represents the sampling point number.

7. The clock signal processing method according to claim 1, characterized in that, The passband center frequency of the target FIR filter is set to the clock base frequency corresponding to the target clock source, the filter bandwidth of the target FIR filter is set to 5% of the clock base frequency, and the stopband attenuation of the target FIR filter is greater than or equal to 40dB.

8. A clock signal processing system, characterized in that, include: The signal sampling module (11) is used to perform analog-to-digital sampling on the original analog clock signal output by the target clock source to obtain a discretized clock input signal sequence; The signal processing module (12) is used to perform DC bias removal processing on the discretized clock input signal sequence to obtain the preprocessed signal; The gain processing module (13) is used to obtain the peak value of the signal amplitude in a single clock cycle in the preprocessed signal, determine the adaptive gain coefficient corresponding to a single clock cycle based on the peak value of the signal amplitude and the preset target output amplitude, and determine the signal after gain amplification based on the adaptive gain coefficient corresponding to a single clock cycle and the preprocessed signal. The signal filtering module (14) is used to construct a zero-phase-shift target FIR filter, and to perform forward linear filtering and reverse linear filtering on the gain-amplified signal through the target FIR filter to obtain the filtered signal. The signal correction module (15) is used to perform duty cycle closed-loop correction processing on the filtered signal to obtain an initial output signal with a stable duty cycle. The signal optimization module (16) is used to optimize the waveform edge of the initial output signal based on the target output amplitude to obtain the final output signal.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is loaded and executed by the processor, it implements the method of any one of claims 1-7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that, When the processor loads and executes the computer program, it implements the method of any one of claims 1-7.

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