Mim capacitors and methods of manufacturing the same

Abstract

The application discloses a MIM capacitor, and a capacitor main body structure comprises: a lower plate, a plate dielectric layer and an upper plate which are stacked in sequence. The lower plate is formed on the top surface of a first dielectric layer. The bottom metal interconnection pattern at the bottom of the lower plate comprises a lower plate connecting pattern. The lower plate is connected to the lower plate connecting pattern through a lower plate through hole penetrating through the first dielectric layer. A first top interlayer film covers the capacitor main body structure and extends out of the capacitor main body structure. A plurality of through holes are formed in the stacked structure of the first top interlayer film and the first dielectric layer, and the through holes comprise an upper plate through hole located at the top of the upper plate. A top metal interconnection pattern is formed in a second top interlayer film at the top of the first top interlayer film, and the top metal interconnection pattern comprises an upper plate connecting pattern, and the top of the upper plate through hole is in contact with the upper plate connecting pattern. The application can save capacitor area, improve capacitor density, and is particularly suitable for a CIS adopting a small pixel lofic.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a MIM capacitor. This invention also relates to a method for manufacturing a MIM capacitor. Background Technology

[0002] A CMOS image sensor (CIS) is a photoelectric conversion device that converts a light image on a photosensitive surface into an electrical signal proportional to the light image. Full-well capacity (FWC) is an important indicator for evaluating the performance of a CIS device, and it is mainly affected by the size of the photodiode (PD). However, as the size shrinks, the FWC decreases, and premature saturation of the electrical signal leads to a deterioration in dynamic performance. Therefore, improving FWC and dynamic range performance is urgently needed for small pixels.

[0003] Lateral overflow integral capacitance (Lofic) technology designs a high-density capacitor next to the photodiode (PD) to collect photoelectrons overflowing from the PD under high light, freeing the field of view (FWC) from the limitations of PD size, avoiding the loss of high light information, and improving the imaging dynamic range. The core component of Lofic technology is the high-density capacitor, typically a micro-molecular-weighted (MIM) capacitor. In existing MIM capacitors, the main structure consists of a TiN-based lower electrode, a dielectric layer such as alumina, and a TiN-based upper electrode stacked together. The upper electrode is led out through a via at the top, while the lower electrode needs to extend outside the upper electrode and form a via at the top of the extension. However, when miniaturizing existing MIM capacitors, the dimensions between the vias of the upper and lower electrodes must meet the requirements of photolithography and overlay, limiting further reduction in capacitance density. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a MIM capacitor that can save capacitor area and increase capacitor density, and is particularly suitable for CIS using small pixel lofic.

[0005] To solve the above-mentioned technical problems, the main structure of the MIM capacitor provided by the present invention includes: a lower electrode plate, an electrode plate dielectric layer and an upper electrode plate stacked in sequence.

[0006] The lower electrode is formed on the top surface of the first dielectric layer.

[0007] The bottom of the first dielectric layer has a bottom interlayer film and a bottom metal interconnect pattern, the bottom metal interconnect pattern including a lower electrode connection pattern.

[0008] The lower electrode plate is connected to the lower electrode plate connection pattern through a lower electrode plate through-hole passing through the first dielectric layer.

[0009] A first top interlayer film covers the capacitor body structure and extends outside the capacitor body structure.

[0010] A plurality of through holes are formed in the superimposed structure of the first top interlayer membrane and the first dielectric layer, including an upper electrode plate through hole located on the top of the upper electrode plate and passing only through the first top interlayer membrane.

[0011] A second top interlayer membrane is formed on top of the first top interlayer membrane, and a top metal interconnect pattern is formed in the second top interlayer membrane. The top metal interconnect pattern includes an upper electrode plate connection pattern, and the top of the upper electrode plate through hole is in contact with the upper electrode plate connection pattern.

[0012] A further improvement is that the upper electrode plate is made of TiN and the lower electrode plate is made of TiN.

[0013] A further improvement is that the material of the electrode dielectric layer includes aluminum oxide.

[0014] A further improvement is that the material of the bottom metal interconnect pattern includes copper, and the material of the top metal interconnect pattern also includes copper.

[0015] A further improvement is that the material of the through hole in the lower electrode plate includes tungsten; and the material of the through hole in the upper electrode plate includes copper.

[0016] A further improvement is that the top metal interconnect pattern is the topmost metal interconnect pattern.

[0017] A further improvement is that the centers of the upper electrode and the lower electrode are aligned, and the peripheral side of the lower electrode extends beyond the peripheral side of the upper electrode.

[0018] To solve the above-mentioned technical problems, the manufacturing method of MIM capacitor provided by the present invention includes the following steps: A semiconductor substrate is provided in which a bottom interlayer film and a bottom metal interconnect pattern are formed, the top surface of the bottom interlayer film and the top surface of the bottom metal interconnect pattern being flush, the bottom metal interconnect pattern including a lower electrode connection pattern.

[0019] A first dielectric layer is formed on the top surface of the bottom interlayer film and the top surface of the bottom metal interconnect pattern.

[0020] A lower electrode through-hole is formed through the first dielectric layer. The lower electrode through-hole is located in the area covered by the subsequent lower electrode, and the bottom of the lower electrode through-hole is in contact with the lower electrode connection pattern.

[0021] A lower electrode, an electrode dielectric layer, and an upper electrode are sequentially formed on the top surface of the first dielectric layer in which the lower electrode through hole is formed.

[0022] The upper electrode, the electrode dielectric layer, and the lower electrode are patterned and etched to form a capacitor body structure by stacking the patterned lower electrode, the electrode dielectric layer, and the upper electrode.

[0023] A first top interlayer film is formed, which covers the capacitor body structure and extends outside the capacitor body structure.

[0024] Multiple through-holes are formed in the superimposed structure of the first top interlayer membrane and the first dielectric layer, including an upper electrode plate through-hole located on the top of the upper electrode plate and passing only through the first top interlayer membrane.

[0025] A second top interlayer membrane is formed on top of the first top interlayer membrane.

[0026] A top metal interconnect pattern is formed in the second top interlayer film, the top metal interconnect pattern including an upper electrode connection pattern, the top of the upper electrode through hole and the upper electrode connection pattern being in contact.

[0027] A further improvement is that the upper electrode plate is made of TiN and the lower electrode plate is made of TiN.

[0028] A further improvement is that the material of the electrode dielectric layer includes aluminum oxide.

[0029] A further improvement is that the material of the bottom metal interconnect pattern includes copper, and the material of the top metal interconnect pattern also includes copper.

[0030] A further improvement is that the material of the through hole in the lower electrode plate includes tungsten; and the material of the through hole in the upper electrode plate includes copper.

[0031] A further improvement is that the top metal interconnect pattern is the topmost metal interconnect pattern.

[0032] A further improvement is that the first dielectric layer is composed of a first nitrogen-doped silicon carbide (NDC) layer and a first PEOX layer. The PEOX layer represents an oxide (OX) layer formed using a PECVD process.

[0033] A further improvement is that the centers of the upper electrode and the lower electrode are aligned, and the peripheral side surface of the lower electrode extends beyond the peripheral side surface of the upper electrode; the patterning etching includes the following sub-steps: A first hard mask layer is formed and the formation area of ​​the upper electrode is defined by photolithography.

[0034] The first hard mask layer and the first upper electrode plate are etched sequentially.

[0035] A second hard mask layer is formed and the formation area of ​​the lower electrode is defined by photolithography.

[0036] The second hard mask layer, the electrode dielectric layer, and the lower electrode are etched sequentially.

[0037] A further improvement is that a second NDC layer is formed on the top surface of the first top interlayer film, and the second top interlayer film is formed on the top surface of the second NDC layer.

[0038] This invention sets a lower electrode plate connection pattern in the bottom metal interconnect pattern at the bottom of the lower electrode plate, so that the lower electrode plate through hole is located at the bottom of the lower electrode plate, while the upper electrode plate through hole remains at the top of the upper electrode plate. Compared with the existing structure where both the upper and lower electrode plate through holes are at the top, this invention can save capacitor area to the maximum extent, thereby increasing capacitor density, and is particularly suitable for CIS using small pixel lofic. Attached Figure Description

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of the MIM capacitor according to an embodiment of the present invention; Figures 2-10 This is a schematic diagram of the device structure in each step of the manufacturing method of the MIM capacitor according to an embodiment of the present invention. Detailed Implementation

[0040] like Figure 1 The diagram shown is a schematic diagram of the structure of a MIM capacitor according to an embodiment of the present invention. The main structure of the MIM capacitor according to an embodiment of the present invention includes: a lower electrode 108, an electrode dielectric layer 109, and an upper electrode 110 stacked sequentially.

[0041] In this embodiment of the invention, the centers of the upper electrode plate 110 and the lower electrode plate 108 are aligned, and the peripheral side surface of the lower electrode plate 108 extends beyond the peripheral side surface of the upper electrode plate 110. Figure 1 In this process, a first hard mask layer 111 is formed on the top surface of the upper electrode 110, defining the formation region of the upper electrode 110. In some embodiments, the material of the first hard mask layer 111 includes silicon nitride. The formation region of the lower electrode 108 is defined by a second hard mask layer. Figure 1 In this configuration, the second hard mask layer is formed by stacking dielectric layer 112 and dielectric layer 113. For example, dielectric layer 112 is an oxide layer, and dielectric layer 113 is silicon nitride.

[0042] In some embodiments, the upper electrode 110 is made of TiN, and the lower electrode 108 is made of TiN. The electrode dielectric layer 109 is made of aluminum oxide.

[0043] The lower electrode 108 is formed on the top surface of the first dielectric layer. In this embodiment of the invention, the first dielectric layer is formed by stacking a first NDC layer 105 and a first PEOX layer 106.

[0044] A bottom interlayer film 102 and a bottom metal interconnect pattern 104 are formed at the bottom of the first dielectric layer, and the bottom metal interconnect pattern 104 includes a lower electrode connection pattern 104a. Figure 1 In this design, the bottom interlayer film 102 is formed on a semiconductor substrate (not shown), and a bottom NDC layer 101 is also formed at the bottom of the bottom interlayer film 102. Semiconductor devices are typically formed on the semiconductor substrate. The semiconductor substrate and the bottom NDC layer 101 also include further underlying metal layer patterns and corresponding underlying interlayer films; structures below the bottom NDC layer 101 are omitted. Figure 1 In the bottom of the bottom metal interconnect pattern 104, a bottom through hole 103 is also formed.

[0045] In this embodiment of the invention, the lower electrode connection pattern 104a is set entirely according to the actual connection requirements of the MIM capacitor, and will not be described in detail in this application.

[0046] The lower electrode 108 is connected to the lower electrode connection pattern 104a through the lower electrode through hole 107 passing through the first dielectric layer.

[0047] In this embodiment of the invention, the material of the lower electrode through hole 107 includes tungsten.

[0048] The first top interlayer membrane 114 covers the capacitor body structure and extends outside the capacitor body structure.

[0049] A plurality of through holes 115 are formed in the superimposed structure of the first top interlayer membrane 114 and the first dielectric layer. The through holes 115 include an upper electrode through hole 115a located on the top of the upper electrode 110 and passing only through the first top interlayer membrane 114. Figure 1 In the process, each of the through holes 115, except for the upper electrode through hole 115a, passes through the first top interlayer film 114 and the first dielectric layer and contacts the bottom metal interconnect pattern 104 corresponding to the bottom.

[0050] A second top interlayer membrane 117 is formed on top of the first top interlayer membrane 114, and a top metal interconnect pattern 118 is formed in the second top interlayer membrane 117. The top metal interconnect pattern 118 includes an upper electrode plate connection pattern 118a, and the top of the upper electrode plate through hole 115a is in contact with the upper electrode plate connection pattern 118a.

[0051] In this embodiment of the invention, the bottom metal interconnect pattern 104 is made of copper, the top metal interconnect pattern 118 is made of copper, and the upper electrode through-hole 115a is made of copper.

[0052] A second NDC layer 116 is also formed on the top surface of the first top interlayer film 114, and a second top interlayer film 117 is formed on the top surface of the second NDC layer 116.

[0053] In this embodiment of the invention, the top metal interconnect pattern 118 is the topmost metal interconnect pattern. A passivation protective layer 119 is also formed on top of the second top interlayer film 117. The material of the passivation protective layer 119 includes silicon nitride.

[0054] In this embodiment of the invention, a lower electrode plate connection pattern 104a is provided in the bottom metal interconnect pattern 104 at the bottom of the lower electrode plate 108, so that the lower electrode plate through hole 107 is located at the bottom of the lower electrode plate 108, while the upper electrode plate through hole 115a remains at the top of the upper electrode plate 110. Compared with the existing structure where both the upper electrode plate through hole 115a and the lower electrode plate through hole 107 are at the top, this embodiment of the invention can save capacitor area to the maximum extent, thereby improving capacitor density, and is particularly suitable for CIS using small pixel lofic.

[0055] like Figures 2 to 10 The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the MIM capacitor according to an embodiment of the present invention. The manufacturing method of the MIM capacitor according to an embodiment of the present invention includes the following steps: Step 1, such as Figure 2 As shown, a semiconductor substrate (not shown) is provided in which a bottom interlayer film 102 and a bottom metal interconnect pattern 104 are formed. The top surface of the bottom interlayer film 102 and the top surface of the bottom metal interconnect pattern 104 are flush. The bottom metal interconnect pattern 104 includes a lower electrode connection pattern 104a.

[0056] Figure 2 In this process, a bottom NDC layer 101 is also formed at the bottom of the bottom interlayer film 102. A semiconductor device is typically formed on the semiconductor substrate, and the semiconductor substrate and the bottom NDC layer 101 also include more underlying metal layer patterns and corresponding underlying interlayer films. The structures below the bottom NDC layer 101 are omitted. Figure 1 In the bottom of the bottom metal interconnect pattern 104, a bottom through hole 103 is also formed.

[0057] In the method of this embodiment, the lower electrode connection pattern 104a is set entirely according to the actual connection needs of the MIM capacitor, and will not be described in detail in this application.

[0058] In the method of this embodiment of the invention, the material of the bottom metal interconnect pattern 104 includes copper. The bottom metal interconnect pattern 104 is formed using a damascus process, or the bottom metal interconnect pattern 104 and the bottom through-hole 103 are formed using a double damascus process.

[0059] Step Two, as follows Figure 2 As shown, a first dielectric layer is formed on the top surface of the bottom interlayer film 102 and the top surface of the bottom metal interconnect pattern 104.

[0060] In the method of this embodiment of the invention, the first dielectric layer is formed by stacking a first NDC layer 105 and a first PEOX layer 106.

[0061] Step 3, as follows Figure 3 As shown, a lower electrode through-hole 107 is formed through the first dielectric layer. The lower electrode through-hole 107 is located in the area covered by the subsequent lower electrode 108. The bottom of the lower electrode through-hole 107 is in contact with the lower electrode connection pattern 104a.

[0062] In the method of this embodiment of the invention, the steps of forming the through hole 107 in the lower electrode plate include: DARC layer 201 and photoresist 202 are formed sequentially.

[0063] Photolithography is performed to define the formation area of ​​the lower electrode through-hole 107.

[0064] Then, the DARC layer 201 and the first dielectric layer are etched sequentially to form the opening 203 of the lower electrode via 107.

[0065] like Figure 3 As shown, a deposited metal layer completely fills the opening 203 and extends to the outside of the opening 203. CMP is then performed to remove the metal layer outside the opening 203, leaving the metal layer remaining in the opening 203 to form the lower electrode through-hole 107. In this embodiment of the invention, the material of the lower electrode through-hole 107 includes tungsten.

[0066] Step 4, as Figure 4 As shown, a lower electrode 108, an electrode dielectric layer 109, and an upper electrode 110 are sequentially formed on the top surface of the first dielectric layer where the lower electrode through hole 107 is formed.

[0067] In the method of this embodiment of the invention, the upper electrode plate 110 is made of TiN, and the lower electrode plate 108 is made of TiN.

[0068] The material of the electrode dielectric layer 109 includes aluminum oxide.

[0069] Step 5, as follows Figure 7 As shown, the upper electrode 110, the electrode dielectric layer 109, and the lower electrode 108 are patterned and etched to form the main capacitor structure, which is formed by stacking the patterned lower electrode 108, the electrode dielectric layer 109, and the upper electrode 110.

[0070] In the method of this embodiment, the centers of the upper electrode plate 110 and the lower electrode plate 108 are aligned, and the peripheral side surface of the lower electrode plate 108 extends beyond the peripheral side surface of the upper electrode plate 110; the patterning etching includes the following steps: like Figure 4 As shown, a first hard mask layer 111 is formed; the pattern of photoresist 204 formed by photolithography defines the formation area of ​​the upper electrode 110.

[0071] like Figure 5 As shown, the first hard mask layer 111 and the first upper electrode plate 110 are etched sequentially. Figure 5 In the process, the electrode dielectric layer 109 outside the first upper electrode 110 is also partially lost.

[0072] like Figure 6 As shown, a second hard mask layer is formed. The second hard mask layer is formed by stacking dielectric layer 112 and dielectric layer 113. For example, dielectric layer 112 is an oxide layer, and dielectric layer 113 is silicon nitride.

[0073] Photolithography processes include: Figure 6 As shown, photoresist 205 is coated; then the photoresist 205 is exposed and developed to form a pattern of photoresist 205, defining the formation area of ​​the lower electrode 108.

[0074] like Figure 7 As shown, the second hard mask layer, the electrode dielectric layer 109, and the lower electrode 108 are etched sequentially.

[0075] Step Six, as Figure 8 As shown, a first top interlayer film 114 is formed, which covers the capacitor body structure and extends outside the capacitor body structure.

[0076] Step 7, as follows Figure 9As shown, a plurality of through holes 115 are formed in the superimposed structure of the first top interlayer membrane 114 and the first dielectric layer. The through holes 115 include an upper electrode through hole 115a located on the top of the upper electrode 110 and passing only through the first top interlayer membrane 114. Figure 9 In the process, each of the through holes 115, except for the upper electrode through hole 115a, passes through the first top interlayer film 114 and the first dielectric layer and contacts the bottom metal interconnect pattern 104 corresponding to the bottom.

[0077] In some embodiments, the formation process of the first top interlayer film 114 includes: performing HDP CVD deposition of an oxide layer, followed by performing a PETEOS process to form an oxide layer, and then performing CMP on the superimposed oxide layer.

[0078] The material of the through hole 115a in the upper electrode plate includes copper. The through hole 115 is formed using the damascus steel process.

[0079] Step 8, as Figure 10 As shown, a second top interlayer membrane 117 is formed on top of the first top interlayer membrane 114.

[0080] In the method of this embodiment of the invention, a second NDC layer 116 is also formed on the top surface of the first top interlayer film 114, and a second top interlayer film 117 is formed on the top surface of the second NDC layer 116.

[0081] Step Nine, Return Figure 1 As shown, a top metal interconnect pattern 118 is formed in the second top interlayer film 117, the top metal interconnect pattern 118 including an upper electrode connection pattern 118a, the top of the upper electrode through hole 115a and the upper electrode connection pattern 118a are in contact.

[0082] In the method of this embodiment of the invention, the top metal interconnect pattern 118 is the topmost metal interconnect pattern.

[0083] The top metal interconnect pattern 118 is made of copper; it is formed using a damascus process, including the following steps: like Figure 10 As shown, after forming the top interlayer film 117, the process also includes forming multiple layers of films required for the photolithography process, including: film layers 206, 207 and 208 and photoresist 209.

[0084] Photolithography exposure and development are performed to form the pattern of photoresist 209, defining the formation area of ​​the top metal interconnect pattern 118. Then, films 206, 207, and 208 and the second top interlayer film 117 are etched sequentially to achieve downward pattern transfer. Films 206, 207, and 208 and the photoresist 209 are consumed during etching or further removed by the etching process. Films 206, 207, and 208 are, for example, DARC layers, SOC layers, and BARC layers, respectively, specifically configured according to the actual needs of the damascus process.

[0085] This invention provides a method for fabricating MIM capacitors that saves layout area, enabling the production of MIM capacitors that meet the requirements of small pixel LOFIC technology. The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A MIM capacitor, characterized in that, The main structure of the capacitor includes: a lower electrode, an electrode dielectric layer, and an upper electrode stacked sequentially; The lower electrode plate is formed on the top surface of the first dielectric layer; A bottom interlayer film and a bottom metal interconnect pattern are formed at the bottom of the first dielectric layer, and the bottom metal interconnect pattern includes a lower electrode connection pattern. The lower electrode plate is connected to the lower electrode plate connection pattern through a lower electrode plate through-hole passing through the first dielectric layer; A first top interlayer film covers the capacitor body structure and extends outside the capacitor body structure; Multiple through holes are formed in the superimposed structure of the first top interlayer membrane and the first dielectric layer. The through holes include an upper electrode plate through hole located on the top of the upper electrode plate and passing only through the first top interlayer membrane. A second top interlayer membrane is formed on top of the first top interlayer membrane, and a top metal interconnect pattern is formed in the second top interlayer membrane. The top metal interconnect pattern includes an upper electrode plate connection pattern, and the top of the upper electrode plate through hole is in contact with the upper electrode plate connection pattern.

2. The MIM capacitor as described in claim 1, characterized in that: The upper electrode plate is made of TiN, and the lower electrode plate is made of TiN.

3. The MIM capacitor as described in claim 1, characterized in that: The material of the dielectric layer of the electrode plate includes aluminum oxide.

4. The MIM capacitor as described in claim 1, characterized in that: The bottom metal interconnect pattern is made of copper, and the top metal interconnect pattern is made of copper.

5. The MIM capacitor as described in claim 4, characterized in that: The material of the through hole in the lower electrode plate includes tungsten; the material of the through hole in the upper electrode plate includes copper.

6. The MIM capacitor as described in claim 4, characterized in that: The top metal interconnect pattern is the topmost metal interconnect pattern.

7. The MIM capacitor as described in claim 1, characterized in that: The upper electrode and the lower electrode are aligned at their centers, and the peripheral side of the lower electrode extends beyond the peripheral side of the upper electrode.

8. A method for manufacturing a MIM capacitor, characterized in that, Includes the following steps: A semiconductor substrate is provided in which a bottom interlayer film and a bottom metal interconnect pattern are formed, wherein the top surface of the bottom interlayer film and the top surface of the bottom metal interconnect pattern are flush, and the bottom metal interconnect pattern includes a lower electrode connection pattern. A first dielectric layer is formed on the top surface of the bottom interlayer film and the top surface of the bottom metal interconnect pattern; A lower electrode through-hole is formed through the first dielectric layer. The lower electrode through-hole is located in the area covered by the subsequent lower electrode. The bottom of the lower electrode through-hole is in contact with the lower electrode connection pattern. A lower electrode plate, an electrode dielectric layer, and an upper electrode plate are sequentially formed on the top surface of the first dielectric layer in which the lower electrode plate through hole is formed. The upper electrode plate, the electrode plate dielectric layer, and the lower electrode plate are patterned and etched to form a capacitor body structure by stacking the patterned lower electrode plate, the electrode plate dielectric layer, and the upper electrode plate. A first top interlayer film is formed, which covers the capacitor body structure and extends outside the capacitor body structure; Multiple through holes are formed in the superimposed structure of the first top interlayer membrane and the first dielectric layer, including an upper electrode plate through hole located on the top of the upper electrode plate and passing only through the first top interlayer membrane; A second top interlayer membrane is formed on top of the first top interlayer membrane; A top metal interconnect pattern is formed in the second top interlayer film, the top metal interconnect pattern including an upper electrode connection pattern, the top of the upper electrode through hole and the upper electrode connection pattern being in contact.

9. The method for manufacturing a MIM capacitor as described in claim 8, characterized in that: The upper electrode plate is made of TiN, and the lower electrode plate is made of TiN.

10. The method for manufacturing a MIM capacitor as described in claim 8, characterized in that: The material of the dielectric layer of the electrode plate includes aluminum oxide.

11. The method for manufacturing a MIM capacitor as described in claim 8, characterized in that: The bottom metal interconnect pattern is made of copper, and the top metal interconnect pattern is made of copper.

12. The method for manufacturing a MIM capacitor as described in claim 11, characterized in that: The material of the through hole in the lower electrode plate includes tungsten; the material of the through hole in the upper electrode plate includes copper.

13. The method for manufacturing a MIM capacitor as described in claim 11, characterized in that: The top metal interconnect pattern is the topmost metal interconnect pattern.

14. The method for manufacturing a MIM capacitor as described in claim 11, characterized in that: The first dielectric layer is composed of a first NDC layer and a first PEOX layer stacked together.

15. The method for manufacturing a MIM capacitor as described in claim 8, characterized in that: The upper electrode and the lower electrode are aligned at their centers, and the peripheral side surface of the lower electrode extends beyond the peripheral side surface of the upper electrode; the patterning etching includes the following steps: A first hard mask layer is formed and the formation area of ​​the upper electrode is defined by photolithography; The first hard mask layer and the first upper electrode plate are etched sequentially. A second hard mask layer is formed and the formation area of ​​the lower electrode is defined by photolithography; The second hard mask layer, the electrode dielectric layer, and the lower electrode are etched sequentially.

16. The method for manufacturing a MIM capacitor as described in claim 11, characterized in that: A second NDC layer is also formed on the top surface of the first top interlayer film, and the second top interlayer film is formed on the top surface of the second NDC layer.

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