Graphene / silicon array-based visible-near-infrared image sensor and its fabrication process

Abstract

This invention belongs to the field of optoelectronic device technology, specifically relating to a row-and-column visible-near-infrared image sensor based on a graphene / silicon array and its fabrication process. The detector comprises silicon on an insulating layer, graphene, silicon dioxide, and electrodes. This detector achieves detection in the visible to near-infrared band by constructing a graphene / silicon Schottky junction. Through array structure design, row and column readouts are achieved via circuitry between the electrodes and graphene. This invention helps to overcome the technical bottlenecks of two-dimensional materials in wide-band, high-sensitivity image sensing.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic device technology, specifically relating to a matrix visible-near-infrared image sensor based on graphene / silicon array and its fabrication process. Background Technology

[0002] Image sensors, as a crucial component of optoelectronic devices, have a broad and urgent market demand in national economic and defense sectors such as military reconnaissance, security monitoring, industrial inspection, remote sensing mapping, biomedical imaging, and consumer electronics. Based on differences in photosensitive materials and working principles, existing image sensors are mainly divided into two categories: charge-coupled devices (CCDs) and complementary metal-oxide-semiconductor (CMOS). They each have advantages in pixel size, readout speed, power consumption, and integration density, and have already achieved high-resolution imaging in the visible light band. However, with the continuous expansion of application scenarios, the demand for wide spectral coverage (such as from ultraviolet to short-wave infrared and even mid-wave infrared) and high-sensitivity detection is becoming increasingly urgent. For example, in night vision reconnaissance, traditional silicon-based sensors are limited by material band gaps, resulting in extremely low response to near-infrared light with wavelengths exceeding 1.1 μm, making passive night vision difficult to achieve. While short-wave infrared sensors using materials such as InGaAs can extend the wavelength range, their high cost and poor compatibility with standard silicon-based CMOS processes limit their large-scale application. Furthermore, in low-light environments, existing sensors often require image intensifiers or cooling methods to improve sensitivity, but these methods are bulky, power-intensive, and difficult to simultaneously achieve wide-band response. Therefore, how to achieve wide-band detection while maintaining high sensitivity remains a critical technical challenge that needs to be overcome in this field. Summary of the Invention

[0003] To address the technical challenges of traditional image sensors in terms of wide spectral range and high sensitivity, this invention provides a matrix-based visible-near-infrared image sensor based on a graphene / silicon array and its fabrication process. This invention combines two-dimensional materials with silicon to fabricate an image sensor based on a low-dimensional heterojunction array. By utilizing the excellent photoelectric properties of two-dimensional materials, the response spectral range is broadened to the near-infrared band, and the sensor exhibits high sensitivity.

[0004] Graphene, an emerging two-dimensional material, possesses a unique band structure. This invention utilizes graphene and combines it with silicon to construct a graphene / silicon Schottky junction, exhibiting high-sensitivity detection performance in the visible to near-infrared bands, effectively overcoming the application bottlenecks of traditional silicon-based image sensors. Furthermore, the graphene / silicon image sensor fabricated using micro-nano processes in this invention meets the lightweight design requirements of novel optoelectronic devices, possessing excellent portability, array compatibility, and high scalability, thus powerfully promoting the future development of the optoelectronic device field.

[0005] The present invention specifically adopts the following technical solution: The first objective of this invention is to provide a matrix-based visible-near-infrared image sensor based on a graphene / silicon array, comprising silicon on an insulating layer, wherein the silicon on the insulating layer is etched into an array structure composed of rectangular top silicon islands, and multiple vertical electrodes are distributed in the array structure. One end of each rectangular top silicon island in the same column is connected to the same vertical electrode for conduction, and one end of each of the multiple vertical electrodes extends to the outside of the array structure for conduction with the outside.

[0006] Graphene is disposed above silicon on an insulating layer having an array structure and vertical electrodes, and a silicon dioxide layer is disposed between the graphene and the vertical electrodes. The graphene contacts the rectangular top silicon island to form a Schottky junction. The graphene extends laterally along the array structure to the outside of the array structure and is connected to the corresponding lateral electrode for external conduction.

[0007] Preferably, the graphene includes graphene in a first functional region and graphene in a second functional region, and the graphene in the first functional region and the graphene in the second functional region are interconnected.

[0008] In the array structure, a silicon dioxide layer is deposited between two adjacent rows of rectangular top silicon islands. The silicon dioxide layer is located above the vertical electrode, and graphene of the first functional region is disposed on the silicon dioxide layer. The silicon dioxide layer serves as an insulating layer between the vertical electrode and the graphene of the first functional region. The continuous strip-shaped silicon dioxide layer allows the graphene to be flatly covered on it, reducing the presence of gaps, wrinkles, or even damage to the graphene.

[0009] The graphene in the second functional region is used to form a Schottky junction with the rectangular top silicon island, and the generated signal is transmitted to the lateral electrode through the graphene in the first functional region.

[0010] Preferably, both the longitudinal and transverse electrodes are made of 10nm~20nm chromium as a transition layer and 80nm~200nm gold as electrodes, and the longitudinal electrode forms an ohmic contact with the graphene and silicon on the insulating layer.

[0011] Preferably, the silicon dioxide layer is used as an insulating layer between the longitudinal electrode and the graphene, and the thickness of the silicon dioxide layer is 150nm~250nm.

[0012] Preferably, the silicon on the insulating layer is inductively coupled plasma etched according to the designed pattern to form an array structure composed of rectangular top silicon islands. The surface of the rectangular top silicon islands is a rectangular structure with a length of 25μm±(1~2μm) and a width of 10μm±(1~2μm), preferably with a size of 25μm×10μm.

[0013] Preferably, graphene is transferred onto silicon on an insulating layer via a wet process, and a serrated pattern is defined by photolithography. The serrated pattern is then formed by oxygen plasma etching.

[0014] A rectangular array of top-mounted silicon islands is etched onto the insulating layer. One end is connected to the vertical electrode and is conductive to the outside; the other end is connected to the lateral, toothed graphene to form a Schottky junction and is also conductive. A layer of silicon dioxide is sputtered between the vertical electrode (i.e., the aforementioned vertical electrode) and the lateral graphene to isolate them. The lateral electrode (i.e., the aforementioned lateral electrode) is connected to the graphene and is conductive to the outside.

[0015] A second objective of this invention is to provide a fabrication process for the above-mentioned graphene / silicon array-based visible-near-infrared image sensor, comprising the following steps: S1. Prepare a clean insulating layer of silicone, clean it with acetone, ethanol and deionized water, and blow it dry; S2. On the silicon surface of the insulating layer, an array structure composed of rectangular top silicon islands is obtained by ultraviolet lithography and inductively coupled plasma etching. S3. Using ultraviolet lithography and electron beam evaporation technology, longitudinally arranged and transverse electrodes are prepared on the silicon-on-insulator layer with array structure, so that one end of the rectangular top silicon islands in the same column is connected to the same longitudinal electrode and conducts through, and one end of multiple sets of longitudinal electrodes extends to the outside of the array structure. S4. Using ultraviolet lithography and magnetron sputtering technology, a silicon dioxide layer is sputtered on the horizontally arranged rectangular top silicon islands and the corresponding vertical electrodes. S5. Graphene is transferred onto silicon on an insulating layer sputtered with a silicon dioxide layer by wet transfer. S6. Graphene is etched into a designed serrated graphene array using ultraviolet lithography and oxygen plasma etching techniques.

[0016] Preferably, S2 specifically includes the following steps: a photoresist masking layer is prepared on the silicon surface of the insulating layer by spin coating, pre-baking, exposure, development and post-baking to obtain the masking of the pattern, ensuring that the rectangular island parts that need to be retained are covered by photoresist to form protection; the exposed top silicon is etched in an inductively coupled plasma etching machine to obtain the desired pattern.

[0017] Preferably, step S3 specifically includes the following steps: a photoresist masking layer is prepared on the silicon surface of the etched insulating layer by spin coating, pre-baking, exposure, development, and post-baking, exposing the areas where metal electrodes need to be deposited, while the remaining areas are covered with photoresist; chromium and gold electrodes are deposited in electron beam evaporation, wherein chromium serves as a transition layer to form a dense chromium layer, enhancing the adhesion between gold and the substrate, and gold, with its excellent conductivity, corrosion resistance, and oxidation resistance, is used as the electrode material; finally, excess photoresist and the metal deposited on top of it are stripped away.

[0018] Preferably, step S4 specifically includes the following steps: preparing a photoresist masking layer by spin coating, pre-baking, exposure, development, and post-baking, exposing the portion of silicon dioxide to be sputtered, while covering the remaining portion with photoresist; sputtering the silicon dioxide layer in a magnetron sputtering machine as an insulating layer between the longitudinal electrode and the graphene; and finally peeling off the excess photoresist and the sputtered silicon dioxide on top.

[0019] Preferably, in S5, a polymethyl methacrylate-assisted wet transfer method is used to transfer graphene onto the insulating silicon layer.

[0020] Preferably, step S6 specifically includes the following steps: preparing a photoresist masking layer by spin coating, pre-baking, exposure, development, and post-baking, whereby the graphene portion to be retained is covered by photoresist to form a protective layer, and the etched portion of the graphene is exposed; in oxygen plasma etching, the exposed portion of the graphene is etched to obtain the desired pattern; and finally, the remaining photoresist is removed.

[0021] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a matrix-based visible-near-infrared image sensor based on a graphene / silicon array. A graphene / silicon Schottky junction is formed by stacking single layers of graphene and silicon. Due to graphene's absorption capabilities in the visible-near-infrared range, the device can absorb near-infrared wavelengths that silicon cannot normally detect, thus broadening the device's spectral response range. Specifically:

[0022] This invention achieves highly efficient pixel row and column addressing and signal readout capabilities through a unique silicon island structure design on a silicon-based insulating layer and a serrated graphene electrode layout. Compared with traditional technologies, this invention has the following significant advantages: First, unlike traditional CMOS image sensor readout circuits, this invention does not rely on complex polysilicon processes, such as high-temperature doping steps like ion implantation, thus simplifying the manufacturing process and reducing costs. Second, compared with existing devices based on two-dimensional materials such as graphene, traditional designs typically require a separate control circuit for each pixel, resulting in extremely redundant peripheral driving circuits that are difficult to meet the demands of high-pixel counts and large-scale array integration. This invention, through its innovative row and column addressing design, optimizes the number of circuit control lines to a level comparable to existing CMOS image sensors, effectively solving the bottleneck problem of excessive circuit complexity in array applications of two-dimensional material devices.

[0023] In summary, this invention not only employs a novel material system and structural design to achieve low-cost pixel addressing, but also provides a new technical path and approach for the future development of image sensors towards higher integration. Furthermore, the graphene / silicon-based matrix visible-near-infrared array image sensor proposed in this invention can achieve visible-near-infrared imaging, improving device sensitivity and broadening the response spectral range to the near-infrared band. The method of this invention is highly reliable, and the fabrication process is simple to operate, helping to overcome the technical bottlenecks in the application of two-dimensional materials in the field of wide-band, high-sensitivity image sensors. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the fabrication process of a graphene / silicon-based matrix array image sensor.

[0025] Figure 2 This is a single-pixel exploded view of a graphene / silicon-based matrix array image sensor.

[0026] Figure 3 yes Figure 2 Cross-sectional view along the AB direction.

[0027] Figure 4 This is an image of the letter "T" formed by a graphene / silicon-based matrix array image sensor.

[0028] Explanation of reference numerals in the attached figures: 1. Silicon on insulating layer, 1-1. Rectangular top silicon island, 2. Graphene, 2-1. Graphene in the first functional region, 2-2. Graphene in the second functional region, 3. Silicon dioxide, 4. Vertical electrode, 5. Transverse electrode. Detailed Implementation

[0029] To enable those skilled in the art to better understand and implement the technical solutions of the present invention, the present invention will be further described below with reference to specific embodiments and accompanying drawings. However, the embodiments described are not intended to limit the present invention. Unless otherwise specified, the experimental methods and detection methods described in the following embodiments are conventional methods; unless otherwise specified, the reagents and materials described are commercially available.

[0030] This invention provides a matrix-based visible-near-infrared image sensor based on a graphene / silicon array, such as... Figure 1 As shown, it includes silicon on insulating layer 1, which is etched into an array structure composed of rectangular top silicon islands 1-1. Multiple vertical electrodes 4 are distributed in the array structure. One end of each rectangular top silicon island 1-1 in the same column is connected to the same vertical electrode 4 for conduction. One end of each of the multiple vertical electrodes 4 extends to the outside of the array structure for conduction with the outside.

[0031] Graphene 2 is disposed above silicon 1 on an insulating layer having an array structure and a vertical electrode 4, and a silicon dioxide layer 3 is disposed between graphene 2 and the vertical electrode 4. Graphene 2 contacts the rectangular top silicon island 1-1 to form a Schottky junction. Graphene 2 extends laterally along the array structure to the outside of the array structure and is connected to the corresponding lateral electrode 5 for external conduction.

[0032] It should be noted that this invention employs a novel material system and structural design, achieving low-cost pixel addressing. Through a unique silicon island structure design on a silicon-based insulating layer and a serrated graphene electrode layout, this invention achieves efficient pixel row and column addressing and signal readout capabilities. Compared with traditional technologies, this invention has the following significant advantages: First, unlike traditional CMOS image sensor readout circuits, this invention does not rely on complex polysilicon processes, such as high-temperature doping steps like ion implantation, thus simplifying the manufacturing process and reducing costs. Second, compared to existing devices based on two-dimensional materials such as graphene, traditional designs typically require a separate control circuit for each pixel, resulting in extremely redundant peripheral driving circuits that are difficult to meet the demands of high-pixel counts and large-scale array integration. This invention, through its innovative row and column addressing design, optimizes the number of circuit control lines to a level comparable to existing CMOS image sensors, effectively solving the bottleneck problem of excessive circuit complexity in array applications of two-dimensional material devices.

[0033] Specifically, to achieve row and column reading, as well as visible-near-infrared response, this invention is based on the graphene / silicon Schottky junction theory method, and its working principle is as follows: Pixel definition: Figure 1 Each rectangular top silicon island and the graphene it contacts above constitute an independent pixel.

[0034] Photogenerated signal: When light shines on a pixel, photogenerated carriers are generated at the graphene / silicon Schottky junction.

[0035] Signal collection: One type of photogenerated carrier (e.g., electrons) is collected by the longitudinal electrode (because the longitudinal electrode is connected to one end of the silicon island). The other type of photogenerated carrier (e.g., holes) is collected by the graphene.

[0036] Row and column addressing: The signal collected by the graphene electrode is read out through the lateral electrode (row gating). The signal collected by the vertical electrode is read out directly through its own leads (column gating).

[0037] By selecting specific row X (horizontal electrode) and column Y (vertical electrode), the pixel signal located at coordinates (X, Y) can be uniquely identified and read, thereby constructing the entire image.

[0038] In a preferred embodiment of the present invention, such as Figure 2 and Figure 3 As shown, graphene 2 includes graphene 2-1 in the first functional region and graphene 2-2 in the second functional region, and the graphene 2-1 in the first functional region and the graphene 2-2 in the second functional region are interconnected.

[0039] In the array structure, a silicon dioxide layer 3 is deposited between two adjacent rows of rectangular top silicon islands 1-1. The silicon dioxide layer 3 is located above the vertical electrode 4 in the row. Graphene 2-1 of the first functional region is disposed on the silicon dioxide layer 3. The silicon dioxide layer 3 serves as an insulating layer between the vertical electrode 4 and the graphene 2-1 of the first functional region.

[0040] The graphene 2-2 in the second functional region is used to form a Schottky junction by contacting the rectangular top silicon island 1-1, and the generated signal is transmitted to the lateral electrode 5 through the graphene 2-1 in the first functional region.

[0041] It should be noted that the graphene 2-2 in the second functional region is used to form a Schottky junction with the rectangular top silicon island 1-1. Due to graphene's absorption capability for visible and near-infrared light, the device can absorb near-infrared wavelengths that silicon cannot detect, thus broadening the device's spectral response range. When light shines on this junction region, photon energy is absorbed, exciting electron-hole pairs. Under the influence of the electric field inside the junction region, electrons and holes are rapidly separated and collected by the electrodes at both ends (vertical electrode 4 and transverse electrode 5), forming a photocurrent. The graphene 2-1 in the first functional region is used to conduct the signal generated in this row to the transverse electrode. The vertical electrode 4 and the graphene 2-1 in the corresponding region of the first functional region are isolated by a silicon dioxide layer.

[0042] This invention utilizes the absorption characteristics of graphene for visible to near-infrared photons, extending the spectral response range of the image sensor to the near-infrared band, thus breaking through the response limit of traditional silicon-based image sensors. When a light source illuminates the sensor surface, charge carriers are generated in the graphene / silicon Schottky junction. Current is then sequentially applied to the electrodes to scan the photocurrent at each pixel. Based on the obtained results, the image can be obtained through algorithmic calculation.

[0043] To achieve a simple and efficient realization of the aforementioned graphene / silicon-based matrix visible-near-infrared array image sensor, this invention provides a reliable fabrication process, such as... Figure 1 As shown, it includes the following steps: S1. Prepare a clean insulating layer of silicone, clean it with acetone, ethanol and deionized water, and blow it dry; It should be noted that the cleaning method in S1 is a commonly used method well known to those skilled in the art, and will not be described in detail here.

[0044] S2. A rectangular top silicon array is obtained by ultraviolet lithography and inductively coupled plasma etching, with each rectangle measuring 25μm×10μm.

[0045] Specifically, photolithography and inductively coupled plasma (ICP) technology are used to fabricate rectangular top silicon islands: a photoresist masking layer is prepared on the silicon surface of the insulating layer by spin coating, pre-baking, exposure, development, and post-baking to mask the pattern, ensuring that the rectangular island portion to be retained is covered by photoresist for protection; in an ICP etching machine, the exposed top silicon is etched to obtain the desired pattern.

[0046] The detailed photolithography steps are as follows: First, spin-coat the photoresist using EPG535. Set the spin-coating parameters as follows: first at a low speed of 500 rpm for 10 seconds, then at a high speed of 3000 rpm for 40 seconds. Next, place the substrate on a heated stage and preheat it to 95°C for 5 minutes to cure the photoresist. Then, use the photolithography machine and the designed and fabricated photomask for alignment and exposure. Finally, develop the substrate by immersing it in a prepared 0.5% sodium hydroxide developer solution and agitating it for 15 seconds to reveal the pattern. Rinse with deionized water and dry with nitrogen gas.

[0047] The detailed steps of inductively coupled plasma etching are as follows: First, place the silicon wafer with the photolithographically defined pattern on the insulating layer into the equipment chamber. Then, set the parameters, as shown in Table 1.

[0048] Table 1 Inductively Coupled Plasma Process Parameters During the etching process, multiple etching cycles with fewer iterations can be used, and the etching effect should be observed after each etching cycle. The etching is complete when the silicon dioxide layer under the top silicon is completely exposed, exhibiting a distinct purple color. Finally, excess photoresist is removed by cleaning.

[0049] S3. Metal electrodes (vertical electrodes and transverse electrodes) are fabricated on silicon on an insulating layer using ultraviolet lithography and electron beam evaporation technology. Specifically, photolithography and electron beam evaporation techniques are used to fabricate the metal electrodes: a photoresist masking layer is prepared on the silicon surface of the etched insulating layer by spin coating, pre-baking, exposure, development, and post-baking, exposing the areas where metal electrodes need to be deposited, while the remaining areas are covered with photoresist; in electron beam evaporation, electrodes with a thickness of 10 nm of chromium and 100 nm of gold are deposited, with specific parameters shown in Table 2, where chromium serves as an intermediate layer to form a dense chromium layer, enhancing the adhesion between gold and the substrate, and gold, with its excellent conductivity, corrosion resistance, and oxidation resistance, is used as the electrode material; finally, excess photoresist and the metal deposited on top are stripped away.

[0050] Table 2 Electron beam evaporation process parameters The detailed steps of photolithography are as follows: First, spin-coating with photoresist, using EPG535, was performed. The spin-coating parameters were set as follows: first at a low speed of 500 rpm for 10 seconds, then at a high speed of 3000 rpm for 40 seconds. Next, the substrate was placed on a heated stage and pre-baked at 95°C for 5 minutes to cure the photoresist. Then, alignment and exposure were performed using a photolithography machine and the designed and fabricated photomask. Finally, development was performed by immersing the substrate in a prepared 0.5% sodium hydroxide developer solution and agitating it for 15 seconds to reveal the pattern. The substrate was then rinsed with deionized water and dried with nitrogen.

[0051] S4. A silicon dioxide layer is sputtered onto the electrode using ultraviolet lithography and magnetron sputtering techniques; Specifically, silicon dioxide is prepared using photolithography and magnetron sputtering techniques: a photoresist masking layer is prepared by spin coating, pre-baking, exposure, development, and post-baking, exposing the parts where silicon dioxide needs to be sputtered, while the rest are covered with photoresist; in a magnetron sputtering machine, a 200 nm thick layer of silicon dioxide is sputtered (specific sputtering parameters are shown in Table 3) as an insulating layer between the electrode and the graphene; finally, the excess photoresist and the sputtered silicon dioxide on top are stripped away.

[0052] Table 3 Magnetron sputtering process parameters The detailed steps of photolithography are as follows: First, spin-coat the photoresist using EPG535. The spin-coating parameters are set as follows: spin-coat at a low speed of 500 rpm for 10 seconds, then at a high speed of 3000 rpm for 40 seconds. Next, place the substrate on a heated stage and pre-bake at 95°C for 5 minutes to cure the photoresist. Then, use a photolithography machine and the designed and fabricated photomask for alignment and exposure. Finally, develop the substrate by immersing it in a prepared 0.5% sodium hydroxide developer solution and agitating it for 15 seconds to reveal the pattern. Rinse with deionized water and dry with nitrogen gas.

[0053] S5. Transfer graphene onto silicon on the insulating layer using a wet transfer process; Specifically, a polymethyl methacrylate-assisted wet transfer method is used to transfer graphene onto an insulating silicon layer. The detailed steps of the monolayer graphene transfer method are as follows:

[0054] First, polymethyl methacrylate (PMMA) is spin-coated onto the graphene on the prepared copper foil substrate. The viscosity of the PMMA adhesive should not be too high; 950A2 is suitable. The spin coater speed is set to low speed 500 rpm for 10 seconds and high speed 3000 rpm for 40 seconds. PMMA is then drop-coated onto the graphene surface, ensuring complete coverage. After spin coating, the substrate is placed on a heating stage and heated at 120°C for 5 minutes to form a PMMA film.

[0055] Next, the copper foil substrate is etched clean. The copper foil is gently placed into 0.5 mL of ammonium persulfate etching solution, ensuring that the copper foil floats flat on the surface of the etching solution. Wait for the copper foil to be completely etched, which takes about 4 hours, until no copper residue is visible to the naked eye.

[0056] The graphene was then transferred to the target substrate. First, the graphene was removed from the etching solution using a clean PET substrate. Next, the removed graphene was placed in deionized water and soaked for 30 minutes. Then, the deionized water was replaced, and the process was repeated twice to remove the etching solution. After that, it was placed in the air for 30 minutes. Finally, it was placed on a 90°C hot plate and heated for 30 minutes to remove the moisture between the graphene and the substrate.

[0057] Finally, to remove the polymethyl methacrylate (PMMA) from the graphene surface, first place the graphene in an acetone solution and soak for 20 minutes; then replace with a clean acetone solution and soak for 20 minutes; then replace with a clean acetone solution again and soak for 30 minutes to ensure complete removal of PMMA; finally, clean the graphene with anhydrous ethanol to remove any remaining acetone, rinse with deionized water, and dry.

[0058] S6. Using ultraviolet lithography and oxygen plasma etching technology, the graphene in S5 is etched into the designed sawtooth graphene array.

[0059] Specifically, the graphene is patterned using photolithography and oxygen plasma etching processes: a photoresist mask layer is prepared by spin coating, pre-baking, exposure, development, and post-baking. The graphene portion that needs to be preserved is covered by the photoresist to form a protective layer, while the etched portion of the graphene is exposed. In oxygen plasma etching, the exposed portion of the graphene is etched to obtain the desired pattern. Finally, the remaining photoresist is removed.

[0060] The detailed photolithography steps are as follows: First, spin-coat the photoresist using EPG535. Set the spin-coating parameters as follows: spin-coat at a low speed of 500 rpm for 10 seconds, then spin-coat at a high speed of 3000 rpm for 40 seconds. Next, place the substrate on a heated stage and pre-bake at 95°C for 5 minutes to cure the photoresist. Then, use the photolithography machine and the designed and fabricated photomask for alignment and exposure. Finally, develop the substrate by immersing it in a prepared 0.5% sodium hydroxide developer solution and agitating it for 15 seconds to reveal the pattern. Rinse with deionized water and dry with nitrogen gas.

[0061] Figure 4 This is an image of the letter "T" formed by the graphene / silicon matrix array image sensor based on the present invention.

[0062] It should be noted that in traditional silicon-based CMOS image sensors, taking 4T active pixels as an example, each pixel typically consists of 4-6 transistors, including a photodiode, reset transistor, transfer transistor, source follower, and row selector. This architecture results in a complex pixel unit structure and a low fill factor (typically only 20%~30%), requiring additional microlenses to improve light utilization.

[0063] This invention employs a unique silicon island design and a serrated graphene electrode layout, eliminating the need for complex transistor amplification circuits within each pixel and achieving a fill factor of 50%. It also eliminates the need for high-temperature steps such as polycrystalline silicon processing and ion implantation, simplifying the manufacturing process and reducing costs.

[0064] In this invention, when graphene and silicon come into contact, a Schottky barrier forms at the interface due to the difference in their work functions. This barrier is crucial for photoelectric detection; the Schottky barrier separates photogenerated electron-hole pairs, forming a photocurrent. If an effective Schottky junction cannot be formed, the device exhibits ohmic contact characteristics, photogenerated carriers cannot be effectively separated, and the photoresponsivity is only on the order of μA / W, 2-3 orders of magnitude lower than devices with a Schottky junction. The barrier height of a typical graphene-silicon Schottky junction is approximately 0.6-0.8 eV. If the barrier is too high (>1 eV), photogenerated electrons cannot easily cross the barrier, resulting in a decrease in responsivity; if the barrier is too low (<0.2 eV), the dark current increases exponentially, degrading the signal-to-noise ratio. The barrier height of a typical graphene-silicon Schottky junction is approximately 0.8 eV.

[0065] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, it is intended to include any modifications and variations that fall within the scope of the claims and their equivalents.

Claims

1. A matrix-based visible-near-infrared image sensor based on a graphene / silicon array, characterized in that, The structure includes silicon on insulating layer (1), which is etched into an array structure composed of rectangular top silicon islands (1-1). Multiple vertical electrodes (4) are distributed in the array structure. One end of each rectangular top silicon island (1-1) in the same column is connected to the same vertical electrode (4) for conduction. One end of each of the multiple vertical electrodes (4) extends to the outside of the array structure for conduction with the outside. Graphene (2) is disposed above silicon (1) on an insulating layer having an array structure and a longitudinal electrode (4), and a silicon dioxide layer (3) is disposed between the graphene (2) and the longitudinal electrode (4). The graphene (2) forms a Schottky junction by contacting the rectangular top silicon island (1-1). The graphene (2) extends laterally along the array structure to the outside of the array structure and is connected to the corresponding lateral electrode (5) for external conduction.

2. The matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 1, characterized in that, Graphene (2) includes graphene (2-1) in a first functional region and graphene (2-2) in a second functional region, and the graphene (2-1) in the first functional region and the graphene (2-2) in the second functional region are interconnected. In the array structure, a silicon dioxide layer (3) is deposited between two adjacent rows of rectangular top silicon islands (1-1). The silicon dioxide layer (3) is located above the vertical electrode (4). Graphene (2-1) of the first functional region is disposed on the silicon dioxide layer (3). The silicon dioxide layer (3) serves as an insulating layer between the vertical electrode (4) and the graphene (2-1) of the first functional region. The graphene in the second functional region (2-2) is used to form a Schottky junction by contacting the rectangular top silicon island (1-1), and the signal generated by the Schottky junction is transmitted to the lateral electrode (5) through the graphene in the first functional region (2-1).

3. The matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 1, characterized in that, The materials of both the longitudinal electrode (4) and the transverse electrode (5) are 10nm~20nm chromium as the transition layer and 80nm~200nm gold as the electrode layer.

4. The matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 1, characterized in that, The thickness of the silicon dioxide layer (3) is 150nm~250nm; The rectangular top silicon island (1-1) has a rectangular structure with a length of 25μm ± (1~2μm) and a width of 10μm ± (1~2μm).

5. A fabrication process for a matrix-based visible-near-infrared image sensor based on a graphene / silicon array as described in claim 1, characterized in that, Includes the following steps: On the silicon surface of the cleaned insulating layer, an array structure composed of rectangular top silicon islands is obtained by ultraviolet lithography and inductively coupled plasma etching. Using ultraviolet lithography and electron beam evaporation technology, vertical and horizontal electrodes are fabricated on silicon-on-insulator layers with array structures, so that one end of each rectangular top silicon island in the same column is connected to the same vertical electrode and conducts through it, and one end of multiple vertical electrodes extends to the outside of the array structure. A silicon dioxide layer is sputtered onto the vertical electrode using ultraviolet lithography and magnetron sputtering techniques. Graphene is transferred onto silicon on an insulating layer sputtered with a silicon dioxide layer using a wet transfer process. Graphene was etched into a designed serrated graphene array using ultraviolet lithography and oxygen plasma etching techniques.

6. The fabrication process of the matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 5, characterized in that, The specific steps for fabricating the array structure include: a photoresist masking layer is prepared on the silicon surface of the insulating layer by spin coating, pre-baking, exposure, development and post-baking to obtain the masking of the pattern, so that the rectangular island parts that need to be retained are covered by photoresist to form protection; the exposed top silicon is etched in an inductively coupled plasma etching machine to obtain the desired pattern.

7. The fabrication process of the matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 5, characterized in that, The fabrication of longitudinal and lateral electrodes includes the following steps: a photoresist masking layer is prepared on the silicon surface of the etched insulating layer by spin coating, pre-baking, exposure, development, and post-baking, exposing the area where metal electrodes need to be deposited, while the rest is covered with photoresist; in electron beam evaporation, a chromium transition layer and a gold electrode layer are deposited, and finally, excess photoresist and the metal deposited on top are stripped away.

8. The fabrication process of the matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 5, characterized in that, The process of sputtering a silicon dioxide layer includes the following steps: preparing a photoresist mask layer by spin coating, pre-baking, exposure, development, and post-baking, exposing the portion of silicon dioxide to be sputtered and covering the remaining portion with photoresist; sputtering a 200nm thick silicon dioxide layer in a magnetron sputtering machine as an insulating layer between the vertical electrode and the graphene; and finally peeling off the excess photoresist and the sputtered silicon dioxide on top.

9. The fabrication process of the matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 5, characterized in that, Graphene was transferred onto silicon on an insulating layer using a polymethyl methacrylate-assisted wet transfer method.

10. The fabrication process of the matrix-based visible-near-infrared image sensor based on graphene / silicon array according to claim 5, characterized in that, The etching process for graphene includes the following steps: a photoresist masking layer is prepared by spin coating, pre-baking, exposure, development, and post-baking. The graphene portion that needs to be preserved is covered by the photoresist to form a protective layer, while the etched portion of the graphene is exposed. In oxygen plasma etching, the exposed portion of the graphene is etched to obtain the desired graphene pattern. Finally, the remaining photoresist is removed.

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